CN111405770B - Circuit board and manufacturing method thereof - Google Patents

Abstract

The invention relates to a circuit board manufacturing method, which comprises the following steps: providing a substrate, wherein the substrate comprises an organic layer and a metal layer; forming a circuit layer on the substrate; protective film pressing, namely performing protective film pressing on the circuit layer; stripping the organic layer, namely stripping the organic layer of the substrate; and etching the metal layer to obtain mutually independent circuits. The substrate comprises the organic layer and the metal layer which are easy to strip, and only the organic layer is stripped during stripping, so that the problems that the metal layer of the substrate is difficult to strip from the electroplating circuit and the electroplating circuit is easy to drop are solved; in addition, when the method is used for etching, the line width is not influenced due to the existence of the protective film, so that the line width compensation design is not needed. Meanwhile, the method of the invention can also manufacture independent circuits with different thicknesses on the same circuit board, thereby meeting the requirements of customers.

Description

Circuit board and manufacturing method thereof

Technical Field

The invention relates to the field of circuit board manufacturing, in particular to a circuit board manufacturing method and a circuit board manufactured by the method.

Background

The circuit board is widely applied to various fields of life, and almost all electronic equipment comprises the corresponding circuit board, so the circuit board has a very important position in the electronic equipment. With the development of the board manufacturing process, a relatively mature board manufacturing process is formed, the board manufacturing process can be divided into an addition method, a semi-addition method and a subtraction method, and different methods are generally selected to manufacture the circuit board according to different requirements of the circuit board.

The semi-additive method requires that a metal layer on a substrate is removed by rapid etching to form an independent circuit, and the metal layer is etched while the metal layer is etched, so that the line width of the circuit is reduced. Therefore, in order to obtain a target line width, line width compensation design needs to be carried out on the line, line spacing is reduced due to the line width compensation design, and the line with small line spacing has higher requirements on the performance of the barrier layer, so that the process cost is increased; on the other hand, if fine lines with smaller line pitches/line widths need to be manufactured, it is difficult to find a satisfactory barrier material.

In order to solve the problem caused by compensating the line width design, in the prior art, after a required line layer is obtained, a protective film is directly laminated on the formed line layer, then the substrate is completely peeled off to obtain the required line, and the etching is not needed in the process, so that the line width compensation design is not needed, and meanwhile, the required line is also obtained. However, since the entire substrate is peeled off, if the metal layer of the substrate has a high bonding force with the plated wiring, the plated wiring is peeled off together during the peeling process; when the bonding force between the metal layer and the electroplated circuit is reduced, the electroplated circuit is easy to drop in the stripping stage of the barrier layer, and the finished product rate of the manufactured circuit is low.

Disclosure of Invention

In order to overcome the problem of low yield caused by the need of line width compensation design on a line and direct stripping of a substrate in the prior art, the invention provides a manufacturing method of a circuit board and the circuit board manufactured by the method, which improve the yield and can form lines with different thicknesses.

Based on the purpose, the technical scheme of the invention is as follows:

a method of manufacturing a wiring board, the method comprising: providing a substrate, wherein the substrate comprises an organic layer and a metal layer; forming a circuit layer on the metal layer of the substrate; performing protective film pressing, and performing protective film pressing on the circuit layer; stripping the organic layer of the substrate; and etching the metal layer to obtain mutually independent circuits.

The invention also provides two methods for forming the circuit layer, wherein the first method for forming the circuit layer on the metal layer of the substrate specifically comprises the following steps: forming a first barrier layer on a substrate, the first barrier layer having a first window; first electroplating, wherein a first circuit layer is formed in the first window; forming an overlying barrier layer covering a portion of the first fenestration; performing superposition electroplating, and forming a superposed circuit layer in the uncovered first window; and repeating the steps of forming the superposed barrier layer and the superposed electroplating until the required circuit layers with various thicknesses are obtained.

The second method for forming the circuit layer on the metal layer of the substrate specifically comprises the following steps: forming a first barrier layer on a substrate, the first barrier layer having a first window; first electroplating, wherein a first circuit layer is formed in the first window; stripping the first barrier layer; forming a second barrier layer having a second window; second electroplating, wherein a second circuit layer is formed in the second windowing; stripping the second barrier layer; and repeating the steps of forming the second barrier layer, the second electroplating and the second barrier layer stripping until the required circuit layers with various thicknesses are obtained. When the second barrier layer is formed, the windowing of the current barrier layer is a part of all the windowing in the front, or the windowing of the current barrier layer is not overlapped with all the windowing in the front, or the windowing of the current barrier layer is overlapped with all the windowing in the front.

And after the circuit layer is formed and before the protective film is pressed, electroplating the substrate again to form a secondary electroplated layer, wherein the metal layer etching of the circuit layer comprises substrate metal layer etching and the secondary electroplated layer exposed after the substrate metal layer etching.

The barrier layer is formed by using a dry film or photoresist, the circuit layer is formed by copper, copper alloy, gold alloy, nickel alloy, aluminum or aluminum alloy, and the organic layer is made of PI, PET, PE, PVC, PP, LCP or PTFE. The metal layer and the organic layer are combined in a pressing, coating or sputtering mode, and the metal layer and the organic layer are combined by the method, so that lower binding force can be obtained, and the organic layer can be conveniently stripped.

The invention also provides a circuit board which is manufactured by the method.

The invention has the following beneficial effects:

the substrate comprises the organic layer and the metal layer which are easy to strip, and only the organic layer is stripped during stripping, so that the problems that the metal layer of the substrate is difficult to strip from the electroplating circuit and the electroplating circuit is easy to drop are solved; although the invention carries out the substrate etching, the line width compensation design of the line is not needed because of the existence of the protective film. Meanwhile, the invention also provides a method for manufacturing circuits with different thicknesses on the same circuit board, which meets the requirements of customers.

The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments thereof, which is to be read in connection with the accompanying drawings.

Drawings

Some specific embodiments of the invention will hereinafter be described in detail by way of example and not by way of limitation, with reference to the accompanying drawings, in which like reference numerals identify the same or similar parts or features, and it will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the drawings:

FIG. 1 is a schematic cross-sectional view of a circuit board manufacturing method of the present invention;

FIGS. 2 and 3 are schematic cross-sectional views of different thickness line layers formed by one method;

FIGS. 4-8 are schematic cross-sectional views of alternative methods for forming line layers of different thicknesses;

fig. 9 is a schematic cross-sectional view of the re-plating process after the different thickness wiring layers of fig. 2 are formed.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in many ways different from those described herein, and it will be apparent to those skilled in the art that similar modifications may be made without departing from the spirit of the invention, and the invention is therefore not limited to the specific embodiments disclosed below.

The invention provides a circuit board manufacturing method without line width compensation design, which comprises the following steps: providing a substrate, wherein the substrate comprises an organic layer and a metal layer; forming a circuit layer on the substrate; and then sequentially carrying out protective film lamination, organic layer stripping and metal layer etching to finally obtain mutually independent circuits.

Fig. 1 shows a specific embodiment of a method for manufacturing a circuit board without a line width compensation design according to the present invention.

As shown in fig. 1(a), a substrate is provided, which includes anorganic layer 11 and ametal layer 12, and is convenient for subsequent stripping of the organic layer because of low bonding force between the organic layer and the metal layer.

As shown in fig. 1(b), awiring layer 13 is formed on the substrate.

As shown in fig. 1(c), theprotective film 14 is laminated, and exemplarily, theprotective film 14 includes aglue layer 141 and aninsulating layer 142, and theinsulating layer 142 is attached to thecircuit layer 13 through theglue layer 141.

As shown in fig. 1(d), theorganic layer 11 is peeled off, because theorganic layer 11 and themetal layer 12 have low bonding force, theorganic layer 11 is easily peeled off from themetal layer 12, and the organic layer is not affected by the high or low bonding force of the metal layer and the wiring layer, and the problem that the metal layer falls off when the wiring is peeled off together or the barrier layer is peeled off does not occur.

As shown in fig. 1(e), since themetal layer 12 is protected by theprotective film 14, theline layer 13 is not affected during etching, so that the line width compensation design is not required, thereby solving the problems of high requirements for the barrier layer due to the line compensation design, and making it possible to manufacture a finer circuit using the same barrier layer material.

The invention also provides a method for forming circuit layers with different thicknesses on the same circuit board. Wherein, the first method comprises the following steps: forming a first barrier layer on the substrate, wherein the first barrier layer is provided with a first window; forming a first circuit layer in the first window through electroplating; then forming an overlapped barrier layer, wherein the overlapped barrier layer covers a part of the first window; electroplating in the uncovered first window to form a superposed circuit layer; and repeating the steps of forming the superposed barrier layer and the superposed electroplating until the required circuit layers with various thicknesses are obtained.

Specifically, as shown in fig. 2, a schematic flow chart of a first method for manufacturing a circuit layer with two thicknesses is shown.

As shown in fig. 2(a), a substrate is provided, which includes anorganic layer 21 and ametal layer 22.

As shown in fig. 2(b), afirst barrier layer 23 is formed on the substrate, thefirst barrier layer 23 having afirst window 24 in which a wiring is formed later;

as shown in fig. 2(c), thefirst window 24 is subjected to first plating to obtain afirst wiring layer 25.

As shown in fig. 2(d), anoverlying barrier layer 26 is formed on the substrate, theoverlying barrier layer 26 covering a portion of thefirst window 24, whereby a desired first thickness of the wiring layer has been achieved within the coveredfirst window 24.

As shown in fig. 2(e), thesuperimposed wiring layer 27 is formed by electroplating in the uncoveredfirst windows 24, so that thefirst wiring layer 25 and thesuperimposed wiring layer 27 together form a wiring layer of a desired second thickness.

As shown in fig. 2(f), thebarrier layers 23 and 26 are peeled off to obtain wiring layers of two thicknesses.

On the basis of the flow shown in fig. 2, if a circuit with three thicknesses is to be obtained, the steps in fig. 3 may be further added.

After the step of fig. 2(e), as shown in fig. 3(a), anotheroverlying barrier layer 28 is formed, theoverlying barrier layer 28 further covers part of thefirst window 24, and then theoverlying wiring layer 29 is formed by electroplating in the remaining uncoveredfirst window 24, i.e., the steps of forming the overlying barrier layer and overlying electroplating are repeated once.

Thereafter, as shown in fig. 3(b), the barrier layer was peeled off in the same manner, and wiring layers of three thicknesses were obtained.

Similarly, if four or more circuit layers are desired, the steps of forming the overlying barrier layer and overlying electroplating are repeated until the desired circuit layers of different thicknesses are obtained.

The second method for forming circuit layers with different thicknesses on the same circuit board comprises the following steps: forming a first barrier layer on the substrate, wherein the first barrier layer is provided with a first window; electroplating in the first window to form a first circuit layer; stripping the first barrier layer; then forming a second barrier layer, wherein the second barrier layer is provided with a second window; electroplating in the second window to form a second circuit layer; stripping the second barrier layer; and repeating the steps of forming the second barrier layer, the second electroplating and the second barrier layer stripping until the required circuit layers with various thicknesses are obtained.

When the second barrier layer is formed, the windowing of the current barrier layer is a part of all previous windowing, or the windowing of the current barrier layer is not overlapped with all previous windowing, or the windowing of the current barrier layer is overlapped with all previous windowing.

As shown in fig. 4 and 5, two embodiments of forming wiring layers of various thicknesses on the same wiring board by the second method for forming wiring layers of the present invention are shown.

In fig. 4, the lines with two thicknesses are finally formed, and the specific flow is as follows:

as shown in fig. 4(a), the substrate includes anorganic layer 31 and ametal layer 32.

As shown in fig. 4(b), afirst barrier layer 33 is formed on the substrate, thefirst barrier layer 33 having afirst window 34.

As shown in fig. 4(c), first electroplating is performed to form afirst wiring layer 35 in thefirst window 34.

As shown in fig. 4(d), thefirst barrier layer 33 is peeled off.

As shown in fig. 4(e), asecond barrier layer 36 is formed on the substrate, thesecond barrier layer 36 having asecond window 37, and it can be seen that thesecond window 37 is part of thefirst window 34.

As shown in fig. 4(f), the second plating is performed to form thesecond wiring layer 38 in thesecond window 37, and since thesecond window 37 is a part of thefirst window 34, thesecond wiring layer 38 is completely superimposed on thefirst wiring layer 35.

As shown in fig. 4(g), thesecond barrier layer 36 is peeled off to obtain wiring layers of two thicknesses.

In fig. 5, the lines with four thicknesses are finally formed, and the specific flow is as follows:

in addition to fig. 4(g), as shown in fig. 5(a), anothersecond barrier layer 39 is formed on the substrate, thesecond barrier layer 39 has asecond window 310, thesecond window 310 is a part of thefirst window 34 and thesecond window 37, then the second electroplating is performed, anothersecond circuit layer 311 is formed in thesecond window 310, and since thesecond window 310 is a part of thefirst window 34 and thesecond window 37, thesecond circuit layer 311 is superimposed on thefirst circuit layer 35 or thesecond circuit layer 38.

As shown in fig. 5(b), thesecond barrier layer 39 is peeled off to obtain four kinds of wiring layers with different thicknesses.

Therefore, in the two embodiments, when the second barrier layer is formed, the windowing of the current barrier layer is part of all the windowing in the front (namely, the circuit layer in the back is overlapped on the circuit layer in the front), and different circuit layers can be overlapped through the design of different windowing, so that circuits with different thicknesses can be obtained. For example, in fig. 5(a), thesecond window 310 may be formed only as a part of thefirst window 34 or thesecond window 37, and then the electroplating, the barrier layer stripping, and the substrate metal layer etching are performed, so that the independent wiring of three thicknesses can be obtained. And repeating the steps of forming the second barrier layer, the second electroplating and the second barrier layer stripping to obtain more circuits with different thicknesses.

In the two embodiments of the second method, because the circuit layers are electroplated in an overlapping manner, the contact surfaces of the two circuit layers may be not firmly attached, and the position of the barrier layer may deviate due to process problems, so that the circuit layers are misaligned and in a staggered state. In order to solve the problem, as shown in fig. 6 and 7, when the second barrier layer is formed, the windowing of the current barrier layer is not overlapped with all previous windowing.

In fig. 6, the lines with two thicknesses are finally formed, and the specific flow is as follows:

as shown in fig. 6(a), the substrate includes anorganic layer 41 and ametal layer 42, and afirst barrier layer 43 is formed on the substrate, thefirst barrier layer 43 having afirst window 44.

As shown in fig. 6(b), first plating is performed to form afirst wiring layer 45 in thefirst window 44.

As shown in fig. 6(c), thefirst barrier layer 43 is peeled off.

As shown in fig. 6(d), asecond barrier layer 46 is formed on the substrate, thesecond barrier layer 46 having asecond window 47, thesecond window 47 not overlapping with thefirst window 44.

As shown in fig. 6(e), second plating is performed to form asecond wiring layer 48 in thesecond window 47, and since thesecond window 47 does not overlap with thefirst window 44, thesecond wiring layer 48 does not overlap with thefirst wiring layer 45.

As shown in fig. 6(f), thefirst barrier layer 46 is peeled off to obtain two wiring layers of different thicknesses.

In fig. 7, a circuit layer with three thicknesses is formed, and the specific flow is as follows:

on the basis of fig. 6(f), as shown in fig. 7(a), anothersecond barrier layer 49 is formed, thesecond barrier layer 49 has asecond window 410, thesecond window 410 is not overlapped with thefirst window 44 and thesecond window 47, and then electroplating is performed in thesecond window 410 to obtain anothersecond circuit layer 411, wherein thesecond circuit layer 411 is not overlapped with thesecond circuit layer 48 and thefirst circuit layer 45.

As shown in fig. 7(b), thesecond barrier layer 49 is peeled off, and wiring layers of three thicknesses are obtained.

In fig. 6 and 7, since the circuit layers are plated independently each time, there are no problems of unstable contact surface adhesion and circuit layer interleaving due to overlay plating. In addition, generally, the thinner the barrier layer, the smaller the line width/line spacing that can be formed; in this embodiment, each circuit layer is independently electroplated, so that different barrier layer thicknesses can be adopted for different circuit layer thicknesses, and further different line spacing/line width limits can be realized.

In another embodiment of the second method, when the second barrier layer is formed, the opening of the current barrier layer may be overlapped with all the previous opening portions, in which case, some circuit layers are formed by overlapping, and some circuit layers are formed independently.

As shown in fig. 8, the four-thickness circuit is finally formed in this way, and the specific flow is as follows:

on the basis of fig. 6(f), as shown in fig. 8(a), anothersecond barrier layer 49 is formed, thesecond barrier layer 49 has asecond window 410, a part of thesecond window 410 is overlapped with thefirst window 44, and another part of the second window is formed at a position different from thefirst window 44 and thesecond window 47, and then electroplating is performed again to obtain anothersecond wiring layer 411; it can be seen that thesecond circuit layer 411 is partially superimposed on the previous circuit and partially formed directly on the new location of the substrate.

As shown in fig. 8(b), thesecond barrier layer 49 is peeled off, and four kinds of wiring layers of different thicknesses are obtained.

In fig. 8(a), a part of thesecond window 410 may overlap thesecond window 47, or may overlap both thefirst window 44 and thesecond window 47.

In the second method for forming the circuit layer, when the second barrier layer is formed, the windowing of the current barrier layer may be a part of all the previous windowing, or the windowing of the current barrier layer is not overlapped with all the previous windowing, or the windowing of the current barrier layer is overlapped with all the previous windowing, one of the three modes is selected for forming the second barrier layer each time, and when the second barrier layer is formed for multiple times, the three modes can also be combined for use, and finally, a plurality of circuit layers with different thicknesses are formed.

If a finer circuit is desired, a second plating may be performed after the formation of the wiring layer and before the lamination of the protective film. Taking the first method of the present invention to obtain two circuit layers with different thicknesses as an example, as shown in fig. 9(a), a re-plating process is performed on the circuit layers in fig. 2(f) to form are-plated layer 210.

As shown in fig. 9(b) to (c), the wiring layer subjected to the re-plating is subjected to the press-fitting of theprotective film 211, exemplarily, theprotective film 211 includes aglue layer 2111 and an insulatinglayer 2112, and thereafter theorganic layer 21 is peeled off. As shown in fig. 9(d), when the metal layer is etched, not only the substrate metal layer but also there-plating layer 210 exposed by the substrate metal layer after etching needs to be further etched, so that an independent circuit layer is obtained.

The barrier layer is formed by a dry film or a photoresist, taking the dry film as an example, dry film bonding, dry film exposure and dry film development are carried out on the substrate, and the exposed dry film is left on the substrate to form the barrier layer with a window. The dry film exposure is to selectively polymerize and crosslink the dry film through ultraviolet irradiation, and the exposed dry film is continuously remained on the metal layer during subsequent development; dry film development is the removal of the unexposed portions of the dry film. In addition, the shape of the cross-section barrier layer in the figure is only a schematic shape, because the flow deformation is generated in the process of laminating the dry film and the photoresist, the cross section of the barrier layer after laminating the barrier layer is not as flat as that in the figure, and if the thickness of the window is larger than that of the barrier layer, the cross section of the barrier layer is still wavy.

In addition, the material of the organic layer and the insulating layer is PI (Polyimide), PET (Polyethylene terephthalate), PE (Polyethylene), PVC (Polyvinyl chloride), PP (polypropylene), LCP (LIQUID CRYSTAL POLYMER), PTFE (Polytetrafluoroethylene), or the like; the metal layer and the plating layer are made of copper, nickel, gold, aluminum, copper alloy, nickel alloy, gold alloy, aluminum alloy or the like.

The organic layer and the metal layer of the substrate are formed in a pressing, coating or sputtering mode, and the bonding force between the organic layer and the metal layer of the substrate formed by the method is low, so that the organic layer is conveniently stripped.

The invention also provides a circuit board manufactured by the method, and when the circuit board is manufactured by the method, fine circuit boards with different circuit thicknesses can be obtained. Specifically, the following experimental results are provided to verify the feasibility of the method and its effects.

The method of fig. 2 for forming a circuit layer using the present invention:

the thickness of the first barrier layer is 30 micrometers, the thickness of the first electroplating layer is 12 micrometers, the thickness of the superposed barrier layer is 20 micrometers, the thickness of the superposed electroplating layer is 18 micrometers, two line thicknesses of 12 micrometers and 30 micrometers can be obtained before electroplating again, the line width \ line distance reaches 15 micrometers \15 micrometers, the thickness of the electroplated copper is 2.5 micrometers, the line width \ line distance reaches 20 micrometers \10 micrometers, and the line thickness is increased to 14.5 micrometers and 32.5 micrometers.

The thickness of the first barrier layer is 40 micrometers, the thickness of the first electroplating layer is 12 micrometers, the thickness of the superposed barrier layer is 25 micrometers, the thickness of the superposed electroplating layer is 28 micrometers, two line thicknesses of 12 micrometers and 40 micrometers can be obtained before electroplating again, the line width/line distance reaches 15 micrometers/15 micrometers, the thickness of electroplating again is 3 micrometers, finally the line width/line distance reaches 21 micrometers/9 micrometers, and the line thickness is increased to 15 micrometers and 43 micrometers.

The method of fig. 6 for forming a circuit using the present invention:

the thickness of the first barrier layer is 15 micrometers, the thickness of the first electroplating layer is 12 micrometers, the thickness of the second barrier layer is 60 micrometers, the thickness of the second electroplating layer is 60 micrometers, the line thickness of 12 micrometers and 60 micrometers can be obtained before electroplating again, the line width \ line distance of 12 micrometers line thickness is 10 micrometers \10 micrometers, the line width \ line distance of 60 micrometers copper thickness is 20micrometers \25 micrometers, the thickness of electroplating again is 2 micrometers, the line width \ line distance after electroplating respectively reaches 14 micrometers \6 micrometers and 24micrometers \21 micrometers, and the line thickness is increased to 14 micrometers and 62 micrometers.

Thus, it should be appreciated by those skilled in the art that while a number of exemplary embodiments of the invention have been illustrated and described in detail herein, many other variations or modifications consistent with the principles of the invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be understood and interpreted to cover all such other variations or modifications.

Claims (7)

1. A method of manufacturing a wiring board, the method comprising:

providing a substrate, wherein the substrate comprises an organic layer and a metal layer;

forming a circuit layer on the metal layer of the substrate;

protective film pressing, namely performing protective film pressing on the circuit layer;

stripping the organic layer, namely stripping the organic layer of the substrate;

etching the metal layer to obtain mutually independent circuits;

the metal layer and the organic layer are combined in a pressing, coating or sputtering mode;

the method for forming the circuit layer on the metal layer of the substrate specifically comprises the following steps:

forming a first barrier layer on a substrate, the first barrier layer having a first window;

first electroplating, wherein a first circuit layer is formed in the first window;

stripping the first barrier layer;

forming a second barrier layer having a second window;

second electroplating, wherein a second circuit layer is formed in the second windowing;

stripping the second barrier layer;

repeating the steps of forming the second barrier layer, the second electroplating and the second barrier layer stripping until the required circuit layers with various thicknesses are obtained;

and the windowing of the current barrier layer is not superposed with all the windowing in the front, or partial windowing of the current barrier layer is superposed with part of all the windowing in the front.

2. The method of manufacturing of claim 1, further comprising: and after the circuit layer is formed and before the protective film is pressed, electroplating the substrate again to form a secondary electroplating layer.

3. The manufacturing method according to claim 2, wherein the metal layer etching includes substrate metal layer etching and re-plating layer etching exposed after the substrate metal layer etching.

4. The manufacturing method according to claim 1, wherein the barrier layer is formed using a dry film or a photoresist.

5. The manufacturing method according to claim 1, wherein the wiring layer is formed of copper, a copper alloy, gold, a gold alloy, nickel, a nickel alloy, aluminum, or an aluminum alloy.

6. The manufacturing method according to claim 1, wherein the organic layer material is PI, PET, PE, PVC, PP, LCP or PTFE.

7. A wiring board, characterized in that it is manufactured using the method according to any one of claims 1-6.

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