CN111371658A - EtherCAT bus control system - Google Patents

Abstract

The invention provides an EtherCAT bus control system which comprises a main chip, a power supply circuit, a network interface circuit, a data storage circuit, a crystal oscillator circuit and an optical coupling isolation circuit, wherein the main chip is respectively connected with the power supply circuit, the network interface circuit, the data storage circuit, the crystal oscillator circuit and the optical coupling isolation circuit, and is provided with a PHY chip which is connected with the network interface circuit. The invention has the beneficial effects that: the number of the slave stations can be expanded to 256, and the number of the IO stations can reach 256X32=8192, or even more.

Description

EtherCAT bus control system

Technical Field

The invention relates to a bus control system, in particular to an EtherCAT bus control system.

Background

In the field automation process, because sensor signals needing to be acquired or transmitted on the field have many points, hundreds or thousands, and the requirement on real-time performance is high, the expansion of IO by using the traditional PCI (or PCIe) plug-in card is troublesome, and the expansion is influenced by computer slots or spaces or limited by the number of IO plug-in of the PLC.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides an EtherCAT bus control system.

The invention provides an EtherCAT bus control system which comprises a main chip, a power supply circuit, a network interface circuit, a data storage circuit, a crystal oscillator circuit and an optical coupling isolation circuit, wherein the main chip is respectively connected with the power supply circuit, the network interface circuit, the data storage circuit, the crystal oscillator circuit and the optical coupling isolation circuit, and is provided with a PHY chip which is connected with the network interface circuit.

As a further improvement of the invention, the main chip is connected with a watchdog circuit.

As a further improvement of the invention, the main chip is connected with a reset circuit.

As a further development of the invention, the data storage circuit comprises an EEPROM circuit.

As a further improvement of the invention, the crystal oscillator circuit is a 25MHZ crystal oscillator circuit.

As a further improvement of the present invention, the power supply circuit is an analog-digital power supply circuit.

The invention has the beneficial effects that: through the scheme, the number of the IO slave stations can be flexibly increased or reduced, the number of the slave stations can be expanded to 256, and the number of the IO slave stations can reach 256X32=8192, or even more.

Drawings

Fig. 1 is a schematic diagram of an EtherCAT bus control system according to the present invention.

Fig. 2 is a circuit diagram of a master chip of an EtherCAT bus control system according to the present invention.

Fig. 3 is a circuit diagram of a network interface circuit of an EtherCAT bus control system according to the present invention.

Fig. 4 is a circuit diagram of a data storage circuit of a network interface circuit of the EtherCAT bus control system according to the present invention.

Fig. 5 is a circuit diagram of a 25MHZ crystal oscillator circuit of a network interface circuit of the EtherCAT bus control system according to the present invention.

Fig. 6 is a bypass capacitance wiring diagram of a network interface circuit of the EtherCAT bus control system according to the present invention.

Fig. 7 is a circuit diagram of an input portion of an optical coupling isolation circuit of a network interface circuit of an EtherCAT bus control system according to the present invention.

Fig. 8 is a circuit diagram of an output portion of the optical coupling isolation circuit of the network interface circuit of the EtherCAT bus control system according to the present invention.

Fig. 9 is a circuit diagram of a power supply circuit of a network interface circuit of the EtherCAT bus control system according to the present invention.

Detailed Description

The invention is further described with reference to the following description and embodiments in conjunction with the accompanying drawings.

The terms are explained as follows:

1, EtherCAT: the abbreviation of Ethernet Control Automation Technology. Ethernet control automation technology. Was first developed by Beffy, Germany.

2, ESC: EtherCAT Slave Controller, EtherCAT Slave Controller.

3, ESM: EtherCAT State Machine, EtherCAT State Machine.

4, CoE CANopen OF EtherCAT, based on CAN bus on EtherCAT basis. The real-time properties of EtherCAT and CANopen were combined.

SDO is Service Data Object. The data object is served.

6, DC: distributed Clock. A distributed clock. And the master station acquires clocks sharing the same reference according to the DC to realize master-slave station synchronization.

As shown in fig. 1, an EtherCAT bus control system includes amain chip 1, a GPIO input/output circuit, a power supply circuit, anetwork interface circuit 3, a data storage circuit, acrystal oscillator circuit 6, and an opticalcoupling isolation circuit 8, where themain chip 1 is connected to the power supply circuit, thenetwork interface circuit 3, the data storage circuit, thecrystal oscillator circuit 6, and the opticalcoupling isolation circuit 8, themain chip 1 has a PHY chip, the PHY chip is connected to thenetwork interface circuit 3, themain chip 1 is connected to awatchdog circuit 5, themain chip 1 is connected to areset circuit 7, the data storage circuit includes anEEPROM circuit 4, thecrystal oscillator circuit 6 is a 25MHZ crystal oscillator circuit, and the power supply circuit is aclassification circuit 2.

The invention provides a design scheme of an EtherCAT slave station circuit, which is a multi-port EtherCAT slave station controller (ESC) and supports at most 3 100Mbps full-duplex operation and self-adaptive fast Ethernet PHY. The invention supports standard EtherCAT protocols such as CoE, FoE, VoE and the like, and can be used for GPIO control, SPI serial control, shaft control, mechanical arm people, industrial field digital-to-analog and analog-to-digital conversion and the like. The present invention provides 32 digitally controlled I/Os suitable for industrial real-time I/O control applications, and one I/O Watchdog provides monitoring of I/O status for proper handling to ensure safety of product functions.

As shown in fig. 1 to fig. 9, theEEPROM circuit 4 supports an I2C Master interface, supports two specifications of the EEROM chip, i.e., 16Kbits and 4Mbits, and facilitates different configurations.

As shown in fig. 1 to 9, thecrystal oscillator circuit 6 is a 25MHZ crystal oscillator, and is proposed to be arranged close to the main chip, C2 and C3=18PF, resonance capacitance, and stable center frequency.

As shown in fig. 1 to 9, the optical coupler andisolator circuit 8 optically couples and isolates the input part DI-n (in the figures, DI-0 and DI-1, other inputs are the same, and the low level is active). Signals are input from DI-0, noise reduction and filtering processing is carried out through a capacitor C11 and an inductor L7, signals of a resistor R14 are limited in current, the capacitor C9 is DC24V in decoupling mode, and a resistor R11 and a resistor R14 form voltage division with a sensor, so that the functions of an optical coupler and the sensor are protected. The input signal is coupled to a 3-pin output low level through an optical coupler LTV-356T and is sent to themain chip 1. The optical coupler isolation output part DOn (DO 0 and DO1 in the figure, other outputs are the same, and the low level is effective). The signal is output from DO0, and is limited by a resistor R88 signal, and an optical coupler LTV-356T is coupled to apin 3. Resistance R92 is opto-coupler output current-limiting resistance, and resistance R89 is field effect switch tube IRF7103 gate resistance, and switch tube IRF7103 adopts OCL output, can improve and take load capacity. After the circuit is isolated by the optical coupler, an external power supply and an internal power supply can be separated, the anti-jamming capability of the circuit is improved, and a core circuit is effectively protected.

As shown in fig. 1 to fig. 9, in the circuit design, the EtherCAT command signal of the master station is accessed from an RJ45 port J3, a network socket HY951180A of HanRun electronics is adopted, a network transformer and LINK and RUN indicator lamps are carried by themaster chip 1, themaster chip 1 is directly connected to a slave station controller, 2 PHY chips are carried by themaster chip 1, and the circuit design between the network transformer and the PHY is omitted. Under the guidance of EEPROM, the Slave controller receives and sends different signals including GPIO, Local Bus, SPI Slave, SPI Master, PWM, ENCA, ENCB and ENCZ according to register address through PDI interface circuit and internal Bus.

As shown in fig. 1 to 9, an I/O watch dog function is added to thewatchdog circuit 5, and themain chip 1 is used to monitor the I/O status for proper handling, so as to ensure the IO status monitoring function and ensure the security of the device.

As shown in fig. 1 to 9, a reset control function is added by thereset circuit 7 for externally accessing a reset button to themain chip 1 and outputting a reset signal, a hardware reset function. The PLL clock generator is used for connecting themain chip 1 to an external crystal oscillator circuit.

As shown in fig. 1 to 9, themain chip 1 has 32 pins as IO functions. The 32 IO pins marked on the chip diagram are IO functions, namely GPIO (0) -GPIO (31). The device can be configured into 3 working modes of 32-bit output, 32-bit input or 16-bit output and 16-bit input according to requirements. The main on-chip LED _ ERR, LED _ RUN, P0_ ACT, P0_ RXIP, P0_ RXIN, P0_ TXOP, P0_ TXON are connected to RJ45 of J3. The P1_ ACT, P1_ RXIP, P1_ RXIN, P1_ TXOP, P1_ TXON on the master chip are connected to the RJ45 of J2. The I2C _ SDA and I2C _ SCL on the master chip are serial bus data and clock lines, which are connected to the EEPROM24LC16B (16K), and EEP _ DONE is an EEPROM write success flag bit. And XSCI and XSCO on the main chip are connected toPINs 1 and 4 of a 25MHZ crystal oscillator circuit. RESET _ BG on the main chip. The A3V3 on themain chip 1 is analog power supply, the 3V3 is digital power supply, and the 1V2 nuclear power supply is respectively connected to the A3V3 and A1V2 of the power supply part.

As shown in fig. 1 to 9, thenetwork interface circuit 3 adopts a standard RJ45, a HanRun electronic HY951180A with transformer and LED, and an EtherCAT portal input part is input through an RJ45 and output to a next node through another interface. The RJ45 plug HY951180A is provided with a network transformer and Link and ACT LED lamps, taking an input J2 as an example, a network signal is sent from TX +/TX-, received from RX +/RX-, and the network condition ACT/Link is sent from the master, passes through a network transformer through a resistor R28, and is displayed on an RJ 45. RUN is sent from the main through a network transformer via resistor R30, also shown on RJ 45. The resistor R16 and the capacitor C19 are used for isolating the signal ground and the ground and preventing the action of surge lightning strike. Resistor R20 and resistor R21 are network matched resistors.

As shown in fig. 1 to 9, the data storage circuit is an EEPROM chip, and the EEPROM chip 24LC16B is 16K in size and stores a configuration file of themain chip 1. Pin8 is connected to 3V3 power supply, and Pin4 is GND. The capacitor C1 is a power supply decoupling capacitor, the resistor R2 and the resistor R3 are pull-up resistors of bus data and a clock, and the PIN7 is grounded through the resistor R8, so that the read-write effect is realized.

As shown in fig. 1 to 9, the crystal oscillator chip NXK25.000AE12F-KAB6-12 is a passive crystal oscillator of 25MHZ, and the crystal oscillator chips PIN1 andPIN 3 are crystal oscillator input and output respectively connected to XSCI/XSCO PINs of themain chip 1. The starting capacitance of the capacitor C2 and the capacitor C3 is 18 PF. The resistor R12 is an input-output coupling resistor, so that the reliable operation of the crystal oscillator is ensured.

As shown in fig. 1 to 9, the power supply circuit adopts an analog-digital power supply circuit, and is used for supplying 3.3V of DIO digital power supply of a main chip, A3.3V of working power supply, 1.2V of digital nuclear power supply and A1.2V of phase-locked loop power supply. The DC5V is converted into 3.3V rectification filter output A3.3V by the power supply adjusting chip, and the other path is converted into 1.2V rectification filter output A1.2V by the power supply adjusting chip, so that a power supply circuit is completed and is used by themain chip 1. A3.3V output. S _5V is input through the left, the capacitor C26 is a filter capacitor, and the capacitor C28 is a decoupling capacitor. The power is input from pin4 of chip XC6220B331PR, pin1 of the chip is high level output valid, and 3.3V is output frompin 5 of the chip, is filtered by capacitor C25 and capacitor C27, is de-rippled by inductor FB1, and is filtered again by capacitor C29 and capacitor C30 to be output A3.3V. A1.2V output, in principle, the power supply chip XC6220B121MR is a dedicated 1.2V output, which is filtered for multiple times to output A1.2V.

As shown in fig. 1 to 9, the power supply bypasses the capacitor portion. The peripheral C4-C18 of the main chip and the access power supplies A3V3, 3V3, A1V2 and 1V2 are all bypass 0.1UF decoupling capacitors, so that the access power supplies are ensured to be free of interference and noise.

Depending on the use of the chip, the invention can support 4 functions:

and 1, GPIO digital IO function.

2, 8-bit SPI Slave function.

3, 8 bit asynchronous local bus.

A 4, 16 bit asynchronous local bus.

The following takes GPIO digital IO functionality as an example.

When the hardware is configured as a GPIO function, themain chip 1 has 32 pins as IO functions. The 32 IO pins marked on the chip diagram are IO functions, namely GPIO (0) -GPIO (31). The device can be configured into 3 working modes of 32-bit output, 32-bit input or 16-bit output and 16-bit input according to requirements.

The LED _ ERR, the LED _ RUN, the P0_ ACT, the P0_ RXIP, the P0_ RXIN, the P0_ TXOP and the P0_ TXON on themain chip 1 are connected to the RJ45 of the J3.

P1_ ACT, P1_ RXIP, P1_ RXIN, P1_ TXOP and P1_ TXON on themain chip 1 are connected to RJ45 of J2.

I2C _ SDA and I2C _ SCL on themain chip 1 are serial bus data and clock lines and are connected to the EEPROM24LC16B (16K), and EEP _ DONE is an EEPROM write success flag bit.

And XSCI and XSCO on themain chip 1 are connected toPINs 1 and 4 of a 25MHZ crystal oscillator circuit.

A3V3 on themain chip 1 is an analog power supply, 3V3 is a digital power supply, and 1V2 is a nuclear working power supply. Connected to power supply sections A3V3, A1V2, respectively.

The invention adopts the EtherCAT bus control technology and is used for reading the digital sensor signal and outputting the digital signal. The digital cascade control circuit is suitable for being applied to more IO occasions, convenient for increasing and reducing digital quantity and suitable for cascading a plurality of IO modules, and the interface can be TTL level and photoelectric coupling.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. An EtherCAT bus control system, its characterized in that: including main chip, power supply circuit, network interface circuit, data storage circuit, crystal oscillator circuit, opto-coupler isolation circuit, main chip respectively with power supply circuit, network interface circuit, data storage circuit, crystal oscillator circuit, opto-coupler isolation circuit connect, main chip has the PHY chip, the PHY chip with network interface circuit connects.

2. The EtherCAT bus control system according to claim 1, wherein: the main chip is connected with a watchdog circuit.

3. The EtherCAT bus control system according to claim 1, wherein: the main chip is connected with a reset circuit.

4. The EtherCAT bus control system according to claim 1, wherein: the data storage circuit includes an EEPROM circuit.

5. The EtherCAT bus control system according to claim 1, wherein: the crystal oscillator circuit is a 25MHZ crystal oscillator circuit.

6. The EtherCAT bus control system according to claim 1, wherein: the power supply circuit is an analog-digital power supply circuit.

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