Disclosure of Invention
Aiming at the defects that the existing optical fiber synchronization mechanism not only occupies a physical channel of a system, but also is easy to cause the condition that a synchronization signal is lost due to the broken optical fiber, and the later on-site control and protection miniaturized platform does not have enough physical space to realize the external synchronization signal network of each terminal, the invention provides a high-speed serial bus data synchronization method, which comprises the following specific steps:
constructing a rapidIO high-speed communication protocol bus based on an FPGA chip;
transmitting a data packet and a synchronous control instruction of the rapidIO high-speed communication protocol bus to a plurality of cascade devices through a switch;
and the cascade devices execute the synchronous control instruction to realize clock synchronization.
Preferably, the plurality of cascaded devices execute the synchronization control instruction to realize clock synchronization, including:
After receiving the synchronous control instruction, each stage of equipment firstly transmits the synchronous control instruction to the subordinate equipment, and then synchronizes the inside of the subordinate equipment.
Preferably, the performing synchronization inside the present-stage device includes:
According to the number of specific devices, after receiving the synchronous control instruction, each stage of device makes time delay in a grading way and then multicasts to each terminal in the device so as to ensure the data synchronization in each device of the whole system.
Preferably, the delay is determined by the time of transmission of the synchronization control instruction and the internal processing time of the switch.
Preferably, the issuing, by the switch, the data packet and the synchronization control instruction of the RapidIO high-speed communication protocol bus to a plurality of cascade devices includes:
Transmitting the data packet of the rapidIO high-speed communication protocol bus and the synchronous control instruction to a plurality of cascade devices through a switch according to the priority order;
Wherein the priority is from high to low in turn:
data transmitted at the idle time of the Rapid IO high-speed communication protocol bus data packet channel or data transmitted in the channel in an inserted manner;
the data packet of the rapidIO high-speed communication protocol bus;
Non-timing data not controlled by the synchronization control instruction.
Preferably, the data transmission of the rapidIO high-speed communication protocol bus comprises a logic transmission layer, a serial protocol layer, a PCS layer, a PMA layer and an electric layer;
The logic transmission layer transmits character streams in the data packets to a serial protocol layer among the rapidIO high-speed communication protocol bus, the switch and the cascade equipment;
the serial protocol layer realizes the real-time transmission of the synchronous control instruction based on the character stream in the data packet transmitted by the logic transmission layer;
the PCS layer segments the data packet channel of the rapidIO high-speed communication protocol bus, generates idle time and executes character flow in the data packet;
The PMA layer is properly aligned with each of the channels and engaged with the electrical layer;
the electrical layer establishes electrical connections for the plurality of cascaded devices.
Preferably, the synchronous control instruction comprises a synchronous control instruction in a data packet of the rapidIO high-speed communication protocol bus and a synchronous control instruction converted from a synchronous signal transmitted by external equipment.
Preferably, the synchronous control instruction comprises a long format synchronous control instruction and a short format synchronous control instruction;
The long format synchronous control instruction is transmitted to the multistage equipment, and the synchronous control instruction comprises state information in the process of transmitting the synchronous control instruction, a delimiter for transmitting a data packet and a receiving port request of the multistage equipment, provides an expanding function and enhances the error detection capability of burst errors;
The short format synchronous control instruction is transmitted to the multistage equipment, and the synchronous control instruction comprises state information in the process of transmitting the synchronous control instruction, a delimiter of a transmission data packet and a receiving port request of the multistage equipment;
Using the long format synchronization control instruction when the serial link transmitting data is higher than 5.5Gbps, and using the short format synchronization control instruction when the serial link transmitting data is lower than 5.5 Gbps;
wherein a synchronization control instruction without the delimiter is allowed to be embedded in a data packet of the RapidIO high-speed communication protocol bus.
Preferably, when the serial link is the RapidIO high-speed communication protocol bus, the speed of data transmitted by the RapidIO high-speed communication protocol bus is lower than 5.5Gbps, and the short-format synchronous control command is used.
Based on the same conception, the invention provides a system for synchronizing high-speed serial bus data, which comprises an FPGA, a switch and a plurality of cascade devices;
the FPGA is used for building a rapidIO high-speed communication protocol bus;
The switch is used for transmitting the data packet of the rapidIO high-speed communication protocol bus and the synchronous control instruction to a plurality of cascade devices through the switch;
the cascade devices are used for executing the synchronous control instruction to realize clock synchronization.
Compared with the prior art, the invention has the beneficial effects that:
1. The invention provides a method for synchronizing high-speed serial bus data, which comprises the steps of constructing a rapidIO high-speed communication protocol bus based on an FPGA chip, transmitting a data packet of the rapidIO high-speed communication protocol bus and a synchronous control instruction to a plurality of cascade devices through a switch, executing the synchronous control instruction by the cascade devices to realize clock synchronization, adopting multistage device synchronization to realize the synchronization of all terminals in the devices, and having smaller synchronization error;
2. The invention provides a system for synchronizing high-speed serial bus data, which adopts a parameter control delay mode in the system to realize the system synchronization of high-speed serial bus communication;
3. The invention provides a method and a system for synchronizing high-speed serial bus data, which have higher priority of synchronous control instructions, can be inserted into a data frame in real time, and improve the real-time performance of synchronous signals. The external hardware synchronization is changed into the internal software data bus protocol type synchronization, so that the external synchronization interfaces of all terminals in all devices in the system are reduced, and the device volume and the hardware cost are reduced.
Detailed Description
Embodiments of the present invention are further described below with reference to the accompanying drawings.
Example 1:
the invention relates to a method for realizing synchronization of all terminals in a system by a switch in the system based on a high-speed serial bus communication platform, which is introduced by combining a flow chart of the method in FIG. 1, and comprises the following specific steps:
step 1, constructing a rapidIO high-speed communication protocol bus based on an FPGA chip;
Step 2, transmitting the data packet of the rapidIO high-speed communication protocol bus and a synchronous control instruction to a plurality of cascade devices through a switch;
step 3, the cascade devices execute synchronous control instructions to realize clock synchronization;
step 1, constructing a rapidIO high-speed communication protocol bus based on an FPGA chip:
The method is applied to a high-speed serial bus communication platform built by using a rapidIO protocol through an FPGA, and a synchronous control instruction is inserted into a data packet or communication idle time in real time through a switch on a data communication bus so as to realize clock synchronization of all units in the system.
Step 2, transmitting the data packet and the synchronous control instruction of the rapidIO high-speed communication protocol bus to a plurality of cascade devices through a switch:
The synchronization Control instruction is implemented by a Control symbol multicast event in the RapidIO protocol. The data communication packet adopts NWRTE format, wherein the data communication is only realized in logic and transmission layers in the RapidIO endpoint structure, and the specific transmission rate and the number of communication ports can be configured by a development engineer according to the project requirements.
The high-speed communication bus also comprises data frames executed in a synchronous period, the data frames are sent and received according to a synchronous control instruction in each period, the data frames belong to second priority data, and the data frames are normally transmitted after each time of receiving the synchronous control instruction. The third type of data is non-real-time data, the data packet is not controlled by a synchronous control instruction, an external command or a fixed period is possibly needed to control the sending and receiving, the size of the data packet is also possibly large, the data priority is the lowest, and the synchronous control instruction is adopted to prevent the data from occupying a bus channel and being unable to synchronize the system in real time, so that the synchronous control instruction can interrupt the transmission of the non-real-time data at any time to synchronize the system clock.
The serial RapidIO packet is delimited by Control symbol at the time of transmission. Since the packet length is variable, both the packet start and end delimiters are required. The Control symbol marking the end of the packet follows the end of the packet or is embedded behind the Control symbol. For a packet, the Control symbol instruction belongs to a lower level instruction to indicate the status of the packet. The synchronous Control instruction is transmitted by embedding the synchronous information carried by the Control symbol into the data packet or the idle time of the channel, and the specific embodiment takes the data flow on the 1x serial RapidIO link as an example.
The 1x serial RapidIO port encodes the boundary control symbol (which belongs to the instruction in the serial protocol layer, represents the communication state, can carry other information, can also be inserted into the data packet, and is equivalent to the interrupt instruction in communication) and the character stream of the data packet, wherein the boundary control symbol is sequentially transmitted from the uppermost logic transmission layer through an 8B/10B encoder, and when the synchronous control instruction and the data packet are not available, the idle sequence is sent to the 8B/10B encoder for encoding and transmitting, so that the whole transceiving link is ensured to be in the synchronous state. Appendix figure 4 shows an example of transmitting synchronization control commands, packets and idle sequences over a 1x serial link. wherein/SC/indicates the start of Control symbol,/PD/indicates packet delimitation Control symbol,/I/indicates idle sequence.
1) The first byte sent represents the Control symbol start/SC/, followed by three data bytes containing 24 bits of Control symbol information, which is not shown, and may be link state information.
2) Control symbol is followed by a four byte idle character.
3) The idle character is followed by a packet-delimited/PD/byte, and the Control symbol information contained in the following three bytes represents packet-delimited symbol information, the Control symbol indicating that the RapidIO data packet follows the Control symbol, and the packet length is 16 bytes.
4) And when the data is transmitted to the fourth byte, receiving a synchronous control instruction, and after the fourth byte is transmitted, inserting the synchronous control instruction into the data packet.
5) And after the synchronous control instruction is sent, continuing to send the data packet which is not sent until 16 bytes are sent.
6) After the data transmission is completed, the data is a PD/byte of the delimited packet, and the three latter bytes contain Control symbol information to indicate the end of the packet.
1) Followed by four bytes of idle characters.
2) After the idle character is sent, a synchronous control instruction is inserted.
Step 3, the cascade devices execute the synchronous control instruction to realize clock synchronization:
The data communication among all terminals in the module is carried out through the switch, the synchronous control instruction initiating terminal is initiated by the switch, and the functions of all terminals comprise the functions of data collection and summarization, control strategy algorithm realization, control instruction sending, data wave recording and the like. The function of the exchanger comprises the receiving of external synchronous signals, the issuing of synchronous control instructions, the parameter configuration of the exchanger and the construction of data interaction channels of all terminals.
The key function of the switch to be realized is to build a multicast module for realizing the transmission of the synchronous control instruction in the module, wherein the priority of the synchronous control instruction is highest in the high-speed serial bus in the module, and the synchronous control instruction can be inserted into the data packet in the data transmission process, and the data packet is continuously transmitted after the synchronous control instruction is transmitted. The synchronous control instruction is inserted into the data packet to wait for the completion of the current data transmission which is being transmitted, the internal synchronous control instruction of the switch transmits the data length after 8B/10B coding, the maximum delay is the data transmission time of 10 bits, the specific delay time is related to the transmission rate of the high-speed serial bus, the SRIO minimum transmission rate is 1.25G in the 1x mode, the maximum delay is 8ns, the delay time is required to be within the synchronous error range allowed by the system, and the delay time can be shortened by adopting the 2x or 4x mode, and the transmission rate can be improved.
The system frame is shown in an annex figure 3, a plurality of cases or modules (cascade devices) can be arranged in the system, wherein one main module is connected with a synchronous signal outside the system, the slave modules are connected to the synchronous expansion interface of the main module in a grading manner, one-level slave module is connected to the synchronous expansion interface of the main module, two-level slave modules are connected to the synchronous expansion interface of the one-level slave module, and the like, and the number of the specific modules is determined by specific project requirements.
Because the module is synchronized in a module cascading mode, after each stage of module receives the external synchronization control instruction, the synchronization control instruction is sent to the next stage of module, and then the synchronization inside the module is performed. The receiving time of the synchronous control instructions of all modules is inconsistent, the higher the number of slave modules is, the later the time of receiving the synchronous signals is, so that each stage of module is delayed in a grading way and multicast to all terminals in the module after receiving the synchronous control instructions according to the specific number of the modules, and the data synchronization in each module of the whole system is ensured. The hierarchical delay is configured according to the number of modules through a parameter configuration port, and the delay time of each stage is the transmission time of a synchronous control instruction and the internal processing time of the switch, and the specific time, the communication speed of a high-speed serial communication interface and the internal FPGA system clock of the switch are determined.
Example 2:
The synchronization method is based on a Control symbol instruction in the RapidIO protocol, is introduced by combining with the RapidIO end point structure diagram of fig. 2, realizes the real-time insertion of a synchronization signal in the data transmission process, and transmits the instruction to all lower-level terminal devices (each cascade device (namely a functional module) externally connected with the switch) through the switch, wherein the functional module comprises a Control or acquisition processing or communication module and the like.
The synchronization method is referred to herein as a synchronization control instruction. The switch receives the external synchronous signal through the external interface, and the switch sends a synchronous control instruction to each terminal in the system through the multicast mode. All control and data acquisition processing modules in the system start to execute through synchronous control instructions.
The synchronous control instruction sending and receiving functions of the exchanger and each terminal are realized through an FPGA, and the high-speed serial communication platform is realized based on the rapidIO protocol. The rapidIO protocol endpoint structure comprises five layers of links from top to bottom, namely a logic layer and a transmission layer, a serial protocol layer, a 3.PCS layer, a 4.PMA layer and an electric layer, wherein specific functions of the layers are shown in an annex 1 block diagram.
The development engineer realizes the rapidIO high-speed serial bus platform by calling the high-speed communication IP core of the FPGA. The RapidIO transaction operation consists of a request transaction and a response transaction, wherein a data packet is used as a basic transmission carrier between a switch and a terminal, and the switch and the terminal are interconnected through a switching structure (an internal software functional module for transaction request and transaction response generated in the data transmission process between the switch and a module (cascade device). The RapidIO packet encapsulates a bit field and Control symbol information that ensure reliable transfer of the transaction to the target endpoint, and the transaction information, and the switch fabric acknowledges receipt or transmission of the packet by the Control symbol.
Control symbol is a message unit used by the serial link port to manage various functions of serial link operation including link maintenance, packet definition, packet acknowledgement, error reporting, and error recovery. Control symbols in SRIO include long and short formats, with the difference that the rate of the serial link is lower than 5.5Gbps using a short format, higher than 5.5Gbps using a long format, which also provides some additional functionality to enhance the error detection capability of burst errors, and some other extended functionality. The method uses a Control symbol short format to realize the transmission of the synchronous Control instruction. All short format Control symbols are 24 bits long, the format is shown in fig. 6.
Short Control symbol carries a total of two functions, one of which is determined by the stype field and the other by the stype field. Wherein the parameter0 field and parameter1 field are used by the function represented by the stype field, and the cmd field is used by the function represented by the stype field. The function represented by stype field mainly includes state information during port transfer Control symbol, while the function represented by stype1 field mainly includes a delimiter for transferring RapidIO packets and requests for some receiving ports. Any Control symbol that does not contain a packet delimiter may be embedded in the packet, but it is noted that the manner and degree of embedding the Control symbol in the link affects the performance of the link and the system.
In the method, the issuing of the synchronous Control instruction adopts the Control symbol of a multicast event, and the event is different from other Control symbol events in that the information carried by the event is irrelevant to the Control symbol of the link transmission. The multicast event Control symbol allows the transmission of user defined events to be broadcast to the entire system. Its format is shown in fig. 7.
The PCS layer is responsible for channel segmentation (Striping), generating the idle sequence and converting the characters into corresponding 8B/10B encoded K and D codes.
The PMA layer is responsible for the engagement with the electrical layer and also for ensuring correct alignment of the different channels with each other.
The electrical layer represents the different devices, receivers and electrical connections therebetween.
Example 3:
1. the method for synchronizing the high-speed serial bus data is characterized in that based on a rapidIO high-speed communication protocol bus platform, a synchronous Control instruction is realized through a Control symbol instruction of a serial protocol layer in a rapidIO port structure.
2. The RapidIO protocol according to claim 1 is implemented by an FPGA chip with a high-speed communication interface, and the high-speed serial communication bus platform is built by calling the SRIO IP core of the FPGA.
3. The data synchronization according to claim 1, wherein it is ensured that a plurality of terminals in a plurality of modules in the system process the data at the same time or execute a control algorithm, and a corresponding control policy can be made or state information of the system can be reported in real time.
4. The Control symbol instruction of claim 1, wherein the serial protocol layer in the RapidIO port structure is a status flag indicating the status of the data packet and the link, which is lower than the logical transmission layer of the user interface, so that the data packet has higher priority in link transmission than the data, and the function is used to carry the synchronization signal to realize real-time transmission of the synchronization Control instruction, so that the real-time performance and reliability of the synchronization signal can be ensured.
The method for synchronizing a plurality of modules according to claim 3, wherein the plurality of modules adopt a cascade mode, the received synchronization control instruction is inconsistent in time, the internal of each module is required to be subjected to hierarchical delay, the synchronization of the system is realized by controlling the synchronization delay of each module through parameter control, and the synchronization error is adjustable and controllable.
6. The synchronization Control command according to claim 4, wherein the synchronization signal is carried by a Control symbol command, and the synchronization Control command can be sent at an idle time of a channel, or can be inserted into data when the channel is sending the data, and the data being sent is interrupted, and the synchronization Control command is sent first, and the data at the time of interruption before the synchronization Control command is sent is continued after the synchronization Control command is sent is completed.
7. The method according to claim 5, wherein the synchronization Control command is a multicast event of Control symbol, wherein the multicast event allows broadcasting user-defined event transmissions to the whole system, and the switch transmits the synchronization Control command to a plurality of terminals through a multicast function, thereby realizing synchronization of all terminals or devices in the system.
8. The switch of claim 6, wherein the switch is configured to implement broadcasting of the synchronization control instruction by implementing an internal multicast module set up by the FPGA, and further to implement data interaction between terminals or devices connected to the switch, and to insert the multicast synchronization control instruction into a data frame during data transmission.
Example 4:
based on the same conception, the invention provides a system for synchronizing high-speed serial bus data, which is introduced by combining a system structure diagram of FIG. 5 and comprises an FPGA, a switch and a plurality of cascade devices;
the FPGA is used for building a rapidIO high-speed communication protocol bus;
The switch is used for transmitting the data packet of the rapidIO high-speed communication protocol bus and the synchronous control instruction to a plurality of cascade devices through the switch;
the cascade devices are used for executing the synchronous control instruction to realize clock synchronization.
Preferably, the plurality of cascading devices comprise a multicast module and an internal synchronization module;
The multicast module is used for sending the synchronous control instruction to the subordinate equipment after receiving the synchronous control instruction by each level of equipment;
and the internal synchronization module is used for synchronizing clocks in the cascade equipment.
Preferably, the internal synchronization module comprises a hierarchical delay sub-module and a delay time sub-module;
the grading delay sub-module is used for grading and delaying to multicast to all terminals in the equipment after each grade of equipment receives the synchronous control instruction according to the specific number of the equipment so as to ensure the internal data synchronization of each equipment of the whole system;
the delay time submodule is used for taking the transmission time of the synchronous control instruction and the internal processing time of the switch as the delay time of each stage.
Preferably, the switch comprises a priority module;
the priority module is used for transmitting the data packet of the rapidIO high-speed communication protocol bus and the synchronous control instruction to a plurality of cascading devices through the switch according to the priority sequence;
the priority is sequentially from high to low, and the priority is data sent at the idle time of the data packet channel of the rapidIO high-speed communication protocol bus or data which is inserted into the channel and is being sent;
the data packet of the rapidIO high-speed communication protocol bus;
Non-timing data not controlled by the synchronization control instruction.
Preferably, the cascade devices further comprise a master module and a plurality of multi-stage slave modules;
the master module and the plurality of slave modules comprise synchronous expansion interfaces;
the master module is connected with a next-stage multi-stage slave module of the master module through a synchronous expansion interface of the master module;
Each multi-stage slave module is connected with a next-stage multi-stage slave module of the slave module through a synchronous expansion interface of the multi-stage slave module.
Preferably, the rapidIO high-speed communication protocol bus comprises a logic transmission layer, a serial protocol layer, a PCS layer, a PMA layer and an electric layer which are connected in sequence;
the logic transmission layer is used for transmitting character streams in the data packets to the serial protocol layer among the rapidIO high-speed communication protocol bus, the switch and the cascade equipment;
The serial protocol layer is used for realizing the real-time transmission of the synchronous control instruction based on the character stream in the data packet transmitted by the logic transmission layer;
The PCS layer is used for segmenting the data packet channel of the rapidIO high-speed communication protocol bus, generating idle time and executing character flow in the data packet;
The PMA layer is connected with the electrical layer and is used for correctly aligning each channel;
the electric layer is used for establishing electric connection with the plurality of cascade devices.
Preferably, the synchronous control instruction comprises a long format synchronous control instruction and a short format synchronous control instruction;
the long format synchronous control instruction is used for providing an expansion function and enhancing the error detection capability of burst errors;
The short format synchronous control instruction is used for transmitting a synchronous control instruction comprising state information in the process of transmitting the synchronous control instruction, a delimiter of a transmission data packet and a receiving port request of the multistage equipment;
Using the long format synchronization control instruction when the serial link transmitting data is higher than 5.5Gbps, and using the short format synchronization control instruction when the serial link transmitting data is lower than 5.5 Gbps;
wherein a synchronization control instruction without the delimiter is allowed to be embedded in a data packet of the RapidIO high-speed communication protocol bus.
Preferably, when the serial link is the RapidIO high-speed communication protocol bus, the speed of data transmitted by the RapidIO high-speed communication protocol bus is lower than 5.5Gbps, and the short-format synchronous control command is used.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is illustrative of the present invention and is not to be construed as limiting thereof, but rather as providing for the use of additional embodiments and advantages of all such modifications, equivalents, improvements and similar to the present invention are intended to be included within the scope of the present invention as defined by the appended claims.