小型无人机多路无线充电发射系统Multi-channel wireless charging and transmitting system for small UAV技术领域technical field
本发明属于电子设备的技术领域，尤其涉及一种小型无人机多路无线充电发射系统。The invention belongs to the technical field of electronic equipment, and in particular relates to a multi-channel wireless charging and transmitting system for small unmanned aerial vehicles.
背景技术Background technique
“无人机”即“无人驾驶飞机”，广义上为不需要驾驶员登机驾驶的各式遥控飞行器。无人机因其飞行速度快、打击目标准等良好性能，最早被应用于军事。二十世纪九十年代后，随着微机电系统(MEMS)技术的迅速发展及单片机性能的不断提升，搭载了小型惯性导航系统的多旋翼无人机问世。由此掀开了无人机小型化、民用化的革命浪潮。近年来，无人机逐渐被应用于航拍摄影，快递物流，环境监控，设备巡检等方面。目前我国国内小型无人机的市场发展迅速，小型无人机的应用场景也在不断拓宽。然而，目前市面上的无人机大多采用人工有线充电的方式，当无人机在户外进行作业时充电极为不便，这在一定程度上限制了无人机的大规模使用。同时，近年来无线充电技术不断成熟，并在汽车、手机及小型家电设备上得到了一定范围内的成功应用。相比于有线能量传输方式，无线充电不受空间限制，且无接插环节、无裸漏导体，更加适合为小型无人机供能。"UAV" means "unmanned aircraft", in a broad sense, it refers to all kinds of remote-controlled aerial vehicles that do not require a driver to board the plane. UAVs were first used in the military due to their good performances such as fast flight speed and target strike standards. After the 1990s, with the rapid development of micro-electromechanical systems (MEMS) technology and the continuous improvement of the performance of single-chip microcomputers, multi-rotor UAVs equipped with small inertial navigation systems came out. As a result, a revolutionary wave of UAV miniaturization and civilianization has been launched. In recent years, drones have gradually been used in aerial photography, express logistics, environmental monitoring, equipment inspection, etc. At present, the market of small UAVs in my country is developing rapidly, and the application scenarios of small UAVs are also expanding. However, most of the drones on the market currently use manual wired charging, which is extremely inconvenient to charge when the drone is operating outdoors, which limits the large-scale use of drones to a certain extent. At the same time, wireless charging technology has been maturing in recent years, and has been successfully applied to a certain range in automobiles, mobile phones and small home appliances. Compared with the wired energy transmission method, wireless charging is not limited by space, and has no plug-in links and no bare leakage conductors, which is more suitable for powering small drones.
与本申请最接近的现有技术有：公开号为CN110789369的中国专利“一种基于无线充电的无人机充电平台及充电方法”在线圈电磁优化等方面做出了创新；申请号为2018108887219的中国专利“一种电抗自适应无线能量发射系统”对无线充电发射系统在阻抗匹配等方面做出了一些的改进。但上述专利也存在一定的缺点：1.所采用的高频逆变电路为固定电压进行供电，而接收端反射到发射系统的等效阻抗则是千变万化的，当反射阻抗变小时，会导致逆变电流增大，从而对系统构成威胁甚至造成损坏，反之当反射阻抗变大时，则会导致逆变电流减小，造成充电功率过小，减慢充电速度。另一方面，当负载完全消失(如充满或将充电的设备移开)时系统不会自动停止发射能量，根据互感耦合理论，发射系统反而会最大功率发射能量，造成能量的损失和系统的损坏。2.上述无线充电器结构扩展性较差，一个充电器只能为单个待充电的无人机设备进行充能，不适用于小型无人机等需大规模充电的使用场景。The prior art closest to this application is: Chinese patent with publication number CN110789369 "A wireless charging-based unmanned aerial vehicle charging platform and charging method" has made innovations in coil electromagnetic optimization; application number 2018108887219 The Chinese patent "A Reactance Adaptive Wireless Energy Transmitting System" has made some improvements in impedance matching and other aspects of the wireless charging transmitting system. However, the above-mentioned patents also have certain shortcomings: 1. The high-frequency inverter circuit used is used to supply power with a fixed voltage, and the equivalent impedance reflected from the receiving end to the transmitting system is ever-changing. When the reflected impedance becomes smaller, it will lead to reverse The inverter current increases, thus posing a threat to the system or even causing damage. On the contrary, when the reflected impedance increases, the inverter current will decrease, causing the charging power to be too small and slowing down the charging speed. On the other hand, when the load completely disappears (for example, when the load is fully charged or the charged device is removed), the system will not automatically stop transmitting energy. According to the theory of mutual inductance coupling, the transmitting system will transmit energy at maximum power, resulting in energy loss and system damage. . 2. The above-mentioned wireless chargers have poor scalability. One charger can only charge a single UAV device to be charged, and is not suitable for use scenarios such as small UAVs that require large-scale charging.
综上，现有的无人机充电发射系统仍有进一步的改进空间。To sum up, the existing UAV charging and launching system still has room for further improvement.
发明内容SUMMARY OF THE INVENTION
本发明的主要目的在于提供一种适用于小型无人机的多路无线充电发射系统，针对现有技术进行改进，进一步提高效率、扩展接收系统的最大容量。The main purpose of the present invention is to provide a multi-channel wireless charging and transmitting system suitable for small unmanned aerial vehicles, improve the existing technology, further improve the efficiency, and expand the maximum capacity of the receiving system.
本发明的具体的技术方案如下：The concrete technical scheme of the present invention is as follows:
一种小型无人机多路无线充电发射系统，其结构有电源管理电路1、控制时序发生电路8、基准电压电路9、输出矩阵10；所述的电源管理电路1的输出端给所有模块提供直流电源，其输入端与市电相连；基准电压电路9为输出矩阵10中各输出通道电路提供基准电压，控制时序发生电路8为输出矩阵10中各输出通道电路提供PWM信号；其特征在于，所述的输出矩阵10中包含n个输出通道，n为2～8的整数，n个输出通道具有相同的电路结构，每个输出通道包括电压调节电路2、能量发射电路3、电流检测放大电路4、信号整形电路5、输出自动控制电路6、电压检测电路7，其中，电压调节电路2的输出端与能量发射电路3的输入端以及输出自动控制电路6的输入端相连，能量发射电路3的输出端与电流检测放大电路4的输入端相连，电流检测放大电路4的输出端与信号整形电路5的输入端相连，电压调节电路2的输入端分别与信号整形电路5的输出端以及基准电压电路9的输出端相连，基准电压电路9的输出端还与输出自动控制电路6的输入端相连，输出自动控制电路6的输出端与电桥驱动电路7相连，电桥驱动电路7的输出端与能量发射电路3的输入端相连，电桥驱动电路7受控制时序发生电路8的输出端控制；A multi-channel wireless charging and transmitting system for small unmanned aerial vehicles, its structure includes apower management circuit 1, a controlsequence generation circuit 8, areference voltage circuit 9, and anoutput matrix 10; the output end of thepower management circuit 1 is provided for all modules. The DC power supply, its input end is connected with the commercial power; thereference voltage circuit 9 provides the reference voltage for each output channel circuit in theoutput matrix 10, and the controlsequence generation circuit 8 provides the PWM signal for each output channel circuit in theoutput matrix 10; it is characterized in that, Theoutput matrix 10 includes n output channels, n is an integer from 2 to 8, the n output channels have the same circuit structure, and each output channel includes avoltage adjustment circuit 2, anenergy emission circuit 3, and a current detection amplifier circuit. 4. Thesignal shaping circuit 5, the outputautomatic control circuit 6, and thevoltage detection circuit 7, wherein the output end of thevoltage regulation circuit 2 is connected with the input end of theenergy emission circuit 3 and the input end of the outputautomatic control circuit 6, and theenergy emission circuit 3 The output terminal of thevoltage regulator circuit 2 is connected to the input terminal of the currentdetection amplifier circuit 4, the output terminal of the currentdetection amplifier circuit 4 is connected to the input terminal of thesignal shaping circuit 5, and the input terminal of thevoltage adjustment circuit 2 is respectively connected to the output terminal of thesignal shaping circuit 5 and the reference terminal. The output end of thevoltage circuit 9 is connected, the output end of thereference voltage circuit 9 is also connected with the input end of the outputautomatic control circuit 6, the output end of the outputautomatic control circuit 6 is connected with thebridge drive circuit 7, and the output end of thebridge drive circuit 7 is connected. The terminal is connected with the input terminal of theenergy emission circuit 3, and thebridge drive circuit 7 is controlled by the output terminal of the controlsequence generation circuit 8;
所述电源管理电路1的结构为，变压器T1的输入端与市电相连，三个输出端分别与整流桥D101、整流桥D102的输入端相连；整流桥D101的输出端负极接电解电容C101的负极并接地，整流桥D101的输出端正极接电解电容C101的正极并作为所述的电源管理电路1的第一输出端，记为端口HV_out，为电压调节电路2供电；整流桥D102的输出端负极接电解电容C102的负极并接地，整流桥D102的输出端正极接电解电容C102的正极并与芯片LM7812的1端口相连，还与电容C103的一端相连，电容C103的另一端与芯片LM7812的2端口相连并接地，电容C14的一端接地，另一端与芯片LM7812的3端口相连，并与电阻R2的一端相连，作为所述的电源管理电路1的第二输出端，记为端口P_out1，为系统中各模块提供电源VDD，电阻R2的另一端与电阻R1的一端及运放U1A的同相输入端相连，电阻R1的另一端接地，运放U1A的反相输入端与输出端相连，作为所述的电源管理电路1的第三输出端，记为端口P_out2，为系统提供电源VDD/2；The structure of thepower management circuit 1 is that the input end of the transformer T1 is connected to the mains, the three output ends are respectively connected to the input ends of the rectifier bridge D101 and the rectifier bridge D102; the negative electrode of the output end of the rectifier bridge D101 is connected to the electrolytic capacitor C101. The negative pole is connected to the ground, the positive pole of the output terminal of the rectifier bridge D101 is connected to the positive pole of the electrolytic capacitor C101 and is used as the first output terminal of thepower management circuit 1, denoted as port HV_out, which supplies power to thevoltage regulation circuit 2; the output terminal of the rectifier bridge D102 The negative pole is connected to the negative pole of the electrolytic capacitor C102 and grounded. The positive pole of the output terminal of the rectifier bridge D102 is connected to the positive pole of the electrolytic capacitor C102 and is connected to the 1 port of the chip LM7812, and is also connected to one end of the capacitor C103. The other end of the capacitor C103 is connected to the 2 port of the chip LM7812. The port is connected and grounded, one end of the capacitor C14 is grounded, the other end is connected to the 3 port of the chip LM7812, and is connected to one end of the resistor R2, as the second output of thepower management circuit 1, denoted as port P_out1, for the system Each module provides power supply VDD, the other end of the resistor R2 is connected to one end of the resistor R1 and the non-inverting input end of the op amp U1A, the other end of the resistor R1 is grounded, and the inverting input end of the op amp U1A is connected to the output end, as the described The third output terminal of thepower management circuit 1 of , denoted as port P_out2, provides power VDD/2 for the system;
所述电压调节电路2的结构为，运算放大器U3.1的同相输入端与电阻R8一端以及R9一端相连，运算放大器U3.1的反相输入端与电容C3一端、电阻R7一端以及运算放大器U4.2的反相输入端相连，电阻R7的另一端与运算放大器U3.1的输出端以及电阻R9的另一端相连，电容C3的另一端与电阻R8的另一端相连并接电源VDD/2；运算放大器U4.2的输出端与场效应管Q2的栅极相连，运算放大器U4.2的正电源端接电源VDD，运算放大器U4.2的负电源端接地，场效应管Q2的源极与二极管D2的阴极以及电感L2一端相连，场效应管Q2的漏极作为电压调节电路2的电压输入端，记为端口HV_in，与电源管理电路1的端口HV_out相连；电感L2的另一端与电解电容C4的正极相连，并作为电压调节电路2的补偿输出端，记为端口ADV_out，分别与能量发射电路3的端口ADV_in1以及输出自动控制电路6的端口ADV_in2相连；电解电容C4的负极与二极管D2的阳极相连并接地；运算放大器U5.1的同相输入端与电阻R12一端以及R13一端相连，运算放大器U5.1的反相输入端与电阻R10一端、电阻R11一端相连，电阻R10的另一端与运算放大器U5.1的输出端以及运算放大器U4.2的同相输入端相连，电阻R11的另一端作为电压调节电路的参考输入端，记为端口Vref_in1，与基准电压电路9的端口Vref_out1相连；电阻R12的另一端作为电压调节电路的取样输入端，记为端口ReshapeV_in，与信号整形电路5的端口ReshapeV_out相连；电阻R13的另一端接电源VDD/2；The structure of thevoltage regulation circuit 2 is that the non-inverting input end of the operational amplifier U3.1 is connected to one end of the resistor R8 and one end of the R9, and the inverting input end of the operational amplifier U3.1 is connected to one end of the capacitor C3, one end of the resistor R7 and one end of the operational amplifier U4. The inverting input of .2 is connected, the other end of the resistor R7 is connected to the output end of the operational amplifier U3.1 and the other end of the resistor R9, the other end of the capacitor C3 is connected to the other end of the resistor R8 and the power supply VDD/2; The output terminal of the operational amplifier U4.2 is connected to the gate of the FET Q2, the positive power supply terminal of the operational amplifier U4.2 is connected to the power supply VDD, the negative power supply terminal of the operational amplifier U4.2 is grounded, and the source of the FET Q2 is connected to the power supply VDD. The cathode of the diode D2 and one end of the inductor L2 are connected, and the drain of the FET Q2 is used as the voltage input end of thevoltage regulation circuit 2, denoted as port HV_in, which is connected to the port HV_out of thepower management circuit 1; the other end of the inductor L2 is connected to the electrolytic capacitor The positive pole of C4 is connected and used as the compensation output terminal of thevoltage regulation circuit 2, which is denoted as port ADV_out, which is respectively connected with the port ADV_in1 of theenergy transmitting circuit 3 and the port ADV_in2 of the outputautomatic control circuit 6; the negative pole of the electrolytic capacitor C4 is connected with the terminal of the diode D2 The anode is connected and grounded; the non-inverting input end of the operational amplifier U5.1 is connected to one end of the resistor R12 and one end of R13, the inverting input end of the operational amplifier U5.1 is connected to one end of the resistor R10 and one end of the resistor R11, and the other end of the resistor R10 is connected to the operation The output end of the amplifier U5.1 is connected to the non-inverting input end of the operational amplifier U4.2, and the other end of the resistor R11 is used as the reference input end of the voltage regulation circuit, denoted as port Vref_in1, which is connected to the port Vref_out1 of thereference voltage circuit 9; the resistor R12 The other end of the R13 is used as the sampling input end of the voltage adjustment circuit, which is marked as port ReshapeV_in, and is connected to the port ReshapeV_out of thesignal shaping circuit 5; the other end of the resistor R13 is connected to the power supply VDD/2;
所述能量发射电路3的结构为，场效应管Q3的栅极作为能量发射电路3的第一个驱动端，记为端口Drv_in1，与电桥驱动电路7的端口Drv_out1相连；场效应管Q3的源极分别与场效应管Q4的漏极以及电容C5一端相连，并作为能量发射电路3的第二个驱动端，记为端口Drv_in2，与电桥驱动电路7的端口Drv_out2相连；场效应管Q4的栅极与R14一端相连，并作为能量发射电路3的第三个驱动端，记为端口Drv_in3，与电桥驱动电路7的端口Drv_out3相连；场效应管Q5的栅极作为能量发射电路3的第四个驱动端，记为端口Drv_in4，与电桥驱动电路7的端口Drv_out4相连；场效应管Q5的源极分别与场效应管Q6的漏极以及电感L3一端相连，并作为能量发射电路3的第五个驱动端，记为端口Drv_in5，与电桥驱动电路7的端口Drv_out5相连，电感L3的另一端与电容C5的另一端相连；场效应管Q6的栅极与电阻R15一端相连，并作为能量发射电路3的第六个驱动端，记为端口Drv_in6，与电桥驱动电路7的端口Drv_out6相连；电阻R15的另一端分别与电阻R14的另一端、场效应管Q4的源极以及场效应管Q6的源极相连，并作为能量发射电路3的取样输出端，记为端口SampV_out，与电流检测放大电路4的端口SampV_in相连；场效应管Q3的漏极与场效应管Q5的漏极相连，并作为能量发射电路3的补偿输入端，记为端口ADV_in1，与电压调节电路2的端口ADV_out相连；The structure of theenergy emission circuit 3 is that the gate of the field effect transistor Q3 is used as the first drive end of theenergy emission circuit 3, which is denoted as port Drv_in1, and is connected to the port Drv_out1 of thebridge drive circuit 7; The source is connected to the drain of the field effect transistor Q4 and one end of the capacitor C5 respectively, and is used as the second drive end of theenergy emission circuit 3, denoted as port Drv_in2, and connected to the port Drv_out2 of thebridge drive circuit 7; Field effect transistor Q4 The gate is connected to one end of R14 and is used as the third drive terminal of theenergy emission circuit 3, which is denoted as port Drv_in3 and connected to the port Drv_out3 of thebridge drive circuit 7; the gate of the field effect transistor Q5 is used as theenergy emission circuit 3 The fourth drive terminal, denoted as port Drv_in4, is connected to the port Drv_out4 of thebridge drive circuit 7; the source of the field effect transistor Q5 is connected to the drain of the field effect transistor Q6 and one end of the inductor L3 respectively, and is used as theenergy emission circuit 3 The fifth drive end of the MOSFET, denoted as port Drv_in5, is connected to the port Drv_out5 of thebridge drive circuit 7, the other end of the inductor L3 is connected to the other end of the capacitor C5; the gate of the FET Q6 is connected to one end of the resistor R15, and As the sixth drive end of theenergy emission circuit 3, it is denoted as port Drv_in6, which is connected to the port Drv_out6 of thebridge drive circuit 7; the other end of the resistor R15 is respectively connected with the other end of the resistor R14, the source of the field effect transistor Q4 and the field The source of the effect transistor Q6 is connected, and is used as the sampling output end of theenergy emission circuit 3, denoted as port SampV_out, and connected to the port SampV_in of the currentdetection amplifier circuit 4; the drain of the field effect transistor Q3 is connected with the drain of the field effect transistor Q5. connected, and used as the compensation input end of the energy transmittingcircuit 3, denoted as port ADV_in1, and connected with the port ADV_out of the voltage regulatingcircuit 2;
所述电流检测放大电路4的结构为，运算放大器U7.2的同相输入端与电阻RS1一端相连，并作为电流检测放大电路4的取样输入端，记为端口SampV_in,与能量发射电路3的端口SampV_out相连，运算放大器U7.2的反相输入端分别与电阻R16一端、电阻R17一端、可变电阻W2一端以及可变电阻W2活动触点相连，运算放大器U7.2的输出端与电阻R16的另一端相连，并作为电流检测放大电路4的放大输出端，记为端口AmpV_out，与信号整形电路5的端口AmpV_in相连；可变电阻W2的另一端分别与电阻R18一端、电阻R19一端以及运算放大器U6.1的反相输入端相连，R17的另一端分别与R18的另一端以及运算放大器U6.1的输出端相连，R19的另一端接电源VDD/2，运算放大器U6.1的同相输入端分别与运算放大器U6.1的负电源端以及电阻RS1的另一端相连并接地，运算放大器U6.1的正电源端接电源VDD；The structure of the currentdetection amplifying circuit 4 is that the non-inverting input end of the operational amplifier U7.2 is connected to one end of the resistor RS1, and is used as the sampling input end of the current detecting amplifyingcircuit 4, denoted as port SampV_in, and the port of theenergy emission circuit 3. SampV_out is connected, the inverting input terminal of the operational amplifier U7.2 is respectively connected to one end of the resistor R16, one end of the resistor R17, one end of the variable resistor W2 and the movable contact of the variable resistor W2, the output terminal of the operational amplifier U7.2 is connected to the one end of the resistor R16 The other end is connected and used as the amplifying output end of the currentdetection amplifier circuit 4, denoted as port AmpV_out, and connected to the port AmpV_in of thesignal shaping circuit 5; the other end of the variable resistor W2 is respectively connected with one end of the resistor R18, one end of the resistor R19 and the operational amplifier The inverting input terminal of U6.1 is connected, the other terminal of R17 is connected to the other terminal of R18 and the output terminal of the operational amplifier U6.1 respectively, the other terminal of R19 is connected to the power supply VDD/2, and the non-inverting input terminal of the operational amplifier U6.1 They are respectively connected to the negative power supply terminal of the operational amplifier U6.1 and the other end of the resistor RS1 and grounded, and the positive power supply terminal of the operational amplifier U6.1 is connected to the power supply VDD;
所述信号整形电路5的结构为，运算放大器U8.2的正电源端接电源VDD，运算放大器U8.2的负电源端接地，运算放大器U8.2的反相输入端分别与电阻R21一端以及电容C7一端相连，运算放大器U8.2的同相输入端与电容C6一端相连并接地，电容C6的另一端分别与电阻R20一端、电阻R21的另一端以及电阻R22一端相连，电阻R20的另一端作为信号整形电路5的电压输入端，记为端口AmpV_in，与电流检测放大电路4的端口AmpV_out相连；电阻R22的另一端分别与电容C7的另一端、电阻R23一端以及运算放大器U8.2的输出端相连；运算放大器U9.1的反相输入端分别与电阻R24一端以及电容C9一端相连，运算放大器U9.1的同相输入端与电容C8一端相连并接地，电容C8的另一端分别与电阻R25一端、电阻R24的另一端以及电阻R23另一端相连；电阻R25的另一端分别与电容C9的另一端以及运算放大器U9.1的输出端相连，并作为信号整形电路5的整形输出端，记为端口ReshapeV_out，与电压调节电路2的端口ReshapeV_in相连；The structure of thesignal shaping circuit 5 is that the positive power supply terminal of the operational amplifier U8.2 is connected to the power supply VDD, the negative power supply terminal of the operational amplifier U8.2 is grounded, and the inverting input terminal of the operational amplifier U8.2 is connected to one end of the resistor R21 and one end respectively. One end of capacitor C7 is connected, the non-inverting input end of operational amplifier U8.2 is connected to one end of capacitor C6 and grounded, the other end of capacitor C6 is connected to one end of resistor R20, the other end of resistor R21 and one end of resistor R22 respectively, and the other end of resistor R20 is used as The voltage input end of thesignal shaping circuit 5, denoted as port AmpV_in, is connected to the port AmpV_out of the currentdetection amplifier circuit 4; the other end of the resistor R22 is respectively connected with the other end of the capacitor C7, one end of the resistor R23 and the output end of the operational amplifier U8.2 Connected; the inverting input end of the operational amplifier U9.1 is connected to one end of the resistor R24 and one end of the capacitor C9 respectively, the non-inverting input end of the operational amplifier U9.1 is connected to one end of the capacitor C8 and grounded, and the other end of the capacitor C8 is respectively connected to one end of the resistor R25 , the other end of the resistor R24 and the other end of the resistor R23 are connected; the other end of the resistor R25 is connected to the other end of the capacitor C9 and the output end of the operational amplifier U9. ReshapeV_out, connected to the port ReshapeV_in of thevoltage regulation circuit 2;
所述输出自动控制电路6的结构为，运算放大器U10.2的正电源端接电源VDD，运算放大器U10.2的负电源端接地，运算放大器U10.2的反相输入端作为输出自动控制电路6的参考输入端，记为端口Vref_in2，与基准电压电路9的端口Vref_out2相连，运算放大器U10.2的同相输入端与稳压二极管D3的阴极以及电阻R26一端相连，稳压二极管D5的阳极接地，电阻R26的另一端作为输出自动控制电路6的补偿输入端，记为端口ADV_in2，与电压调节电路2的端口ADV_out相连；运算放大器U10.2的输出端与三极管Q7的基极相连，三极管Q7的集电极接电源VDD，发射极分别与电阻R27一端、电阻R28一端以及三极管Q8的发射极相连，电阻R27的另一端与电容C10一端以及反相器U13.4的输入端相连，电阻R28的另一端以及电容C10的另一端接地，反相器U13.4的输出端与D触发器U11.1的时钟信号端Cp相连，D触发器U11.1的触发信号端D分别与清零端Cd以及电容C11一端相连并接地，电容C11的另一端分别与二极管D4的阳极、电阻R29一端以及D触发器U11.1的预置端Sd相连，二极管D4的阴极与电阻R29的另一端以及D触发器U11.1的反相位输出端Q非相连，D触发器U11.1的同相位输出端Q分别与D触发器U12.2的时钟信号端Cp以及反相器U15.2的输入端相连，反相器U15.2的输出端作为输出自动控制电路6的控制输出端，记为端口CtrlV_out，与电桥驱动电路7的端口CtrlV_in相连；D触发器U12.2的触发信号端D分别与D触发器U12.2的清零端Cd及电容C12一端相连，电容C12的另一端与二极管D5的阳极、电阻R30一端以及D触发器U12.2的预置端Sd相连，二极管D5的阴极分别与电阻R30的另一端、D触发器U12.2的反相位输出端Q非相连，D触发器U12.2的同相位输出端Q与反相器U14.1的输入端相连，反相器U14.1的输出端与三极管Q8的基极相连，三极管Q8的集电极接电源VDD；The structure of the outputautomatic control circuit 6 is that the positive power supply terminal of the operational amplifier U10.2 is connected to the power supply VDD, the negative power supply terminal of the operational amplifier U10.2 is grounded, and the inverting input terminal of the operational amplifier U10.2 is used as the output automatic control circuit. The reference input terminal of 6, marked as port Vref_in2, is connected to the port Vref_out2 of thereference voltage circuit 9, the non-inverting input terminal of the operational amplifier U10.2 is connected to the cathode of the Zener diode D3 and one end of the resistor R26, and the anode of the Zener diode D5 is grounded , the other end of the resistor R26 is used as the compensation input end of the outputautomatic control circuit 6, which is denoted as port ADV_in2, which is connected to the port ADV_out of thevoltage regulation circuit 2; the output end of the operational amplifier U10.2 is connected to the base of the transistor Q7, and the transistor Q7 The collector is connected to the power supply VDD, the emitter is connected to one end of the resistor R27, one end of the resistor R28 and the emitter of the transistor Q8, the other end of the resistor R27 is connected to one end of the capacitor C10 and the input of the inverter U13. The other end and the other end of the capacitor C10 are grounded, the output end of the inverter U13.4 is connected to the clock signal end Cp of the D flip-flop U11.1, and the trigger signal end D of the D flip-flop U11.1 is respectively connected to the clearing end Cd And one end of the capacitor C11 is connected and grounded, the other end of the capacitor C11 is respectively connected to the anode of the diode D4, one end of the resistor R29 and the preset end Sd of the D flip-flop U11.1, the cathode of the diode D4 is connected to the other end of the resistor R29 and the D trigger The anti-phase output terminal Q of the inverter U11.1 is not connected, and the in-phase output terminal Q of the D flip-flop U11.1 is connected to the clock signal terminal Cp of the D flip-flop U12.2 and the input terminal of the inverter U15.2 respectively. , the output end of the inverter U15.2 is used as the control output end of the outputautomatic control circuit 6, denoted as the port CtrlV_out, which is connected with the port CtrlV_in of thebridge drive circuit 7; the trigger signal end D of the D flip-flop U12.2 is respectively connected to the The clearing terminal Cd of the D flip-flop U12.2 is connected to one end of the capacitor C12, the other end of the capacitor C12 is connected to the anode of the diode D5, one end of the resistor R30 and the preset terminal Sd of the D flip-flop U12.2, and the cathode of the diode D5 is respectively It is not connected to the other end of the resistor R30 and the inverting output terminal Q of the D flip-flop U12.2. The in-phase output terminal Q of the D flip-flop U12.2 is connected to the input terminal of the inverter U14.1. The output terminal of U14.1 is connected to the base of the transistor Q8, and the collector of the transistor Q8 is connected to the power supply VDD;
所述电桥驱动电路7的结构为，电桥驱动器U16的电压输入端VCC以及电容C13一端接电源VDD，电容C13的另一端以及电桥驱动器U16的COM端接地，电桥驱动器U16的高电平输入端HIN分别与场效应管Q9的漏极以及电桥驱动器U17的低电平输入端LIN相连，并作为电桥驱动电路7的第一个控制输入端，记为端口TsV_in1,与控制时序发生电路8的端口TsV_out1相连，电桥驱动器U16的VB端分别与二极管D6的阴极以及电容C15一端相连，电桥驱动器U16的VS端分别与电容C15的另一端以及电阻R33一端相连，并作为电桥驱动电路7的第二个输出端，记为端口Drv_out2，与能量发射电路3的端口Drv_in2相连，电桥驱动器U16的高电平输出端HO与电阻R32一端相连，电阻R32的另一端与电阻R33的另一端相连，并作为电桥驱动电路7的第一个输出端，记为端口Drv_out1，与能量发射电路3的端口Drv_in1相连，二极管D6的阳极与电阻R31一端相连，电阻R31的另一端接电源VDD，电桥驱动器U16的低电平输出端LO与电阻R34一端相连，电阻R34的另一端作为电桥驱动电路7的第三个输出端，记为端口Drv_out3，与能量发射电路3的端口Drv_in3相连；电桥驱动器U17的电压输入端VCC以及电容C14一端接电源VDD，电容C14的另一端以及电桥驱动器U17的COM端接地，电桥驱动器U17的高电平输入端HIN分别与场效应管Q10的漏极以及电桥驱动器U16的低电平输入端LIN相连，并作为电桥驱动电路7的第二个控制输入端，记为端口TsV_in2,与控制时序发生电路8的端口TsV_out2相连，电桥驱动器U17的VB端分别与二极管D7的阴极以及电容C16一端相连，电桥驱动器U17的VS端分别与电容C16的另一端以及电阻R36一端相连，并作为电桥驱动电路7的第五个输出端，记为端口Drv_out5，与能量发射电路3的端口Drv_in5相连，电桥驱动器U17的高电平输出端HO与电阻R37一端相连，电阻R37的另一端与电阻R36的另一端相连，并作为电桥驱动电路7的第四个输出端，记为端口Drv_out4，与能量发射电路3的端口Drv_in4相连，二极管D7的阳极与电阻R38一端相连，电阻R38的另一端接电源VDD，电桥驱动器U17的低电平输出端LO与电阻R35一端相连，电阻R35的另一端作为电桥驱动电路7的第六个输出端，记为端口Drv_out6，与能量发射电路3的端口Drv_in6相连；场效应管Q9的源极以及场效应管Q10的源极接地，场效应管Q9的栅极与场效应管Q10的栅极相连并作为电桥驱动电路7的第三个控制输入端，记为端口CtrlV_in，与输出自动控制电路6的端口CtrlV-out相连；The structure of thebridge driver circuit 7 is that the voltage input terminal VCC of the bridge driver U16 and one end of the capacitor C13 are connected to the power supply VDD, the other end of the capacitor C13 and the COM terminal of the bridge driver U16 are grounded, and the high voltage of the bridge driver U16 is connected to the ground. The flat input terminal HIN is respectively connected with the drain of the field effect transistor Q9 and the low-level input terminal LIN of the bridge driver U17, and is used as the first control input terminal of thebridge driver circuit 7, which is denoted as port TsV_in1, and the control sequence The port TsV_out1 of thegenerating circuit 8 is connected, the VB terminal of the bridge driver U16 is respectively connected to the cathode of the diode D6 and one end of the capacitor C15, the VS terminal of the bridge driver U16 is respectively connected to the other end of the capacitor C15 and one end of the resistor R33, and is used as a power supply. The second output terminal of thebridge driver circuit 7, denoted as port Drv_out2, is connected to the port Drv_in2 of the energy transmittingcircuit 3, the high-level output terminal HO of the bridge driver U16 is connected to one end of the resistor R32, and the other end of the resistor R32 is connected to the resistor R32. The other end of R33 is connected and used as the first output end of thebridge drive circuit 7, denoted as port Drv_out1, which is connected to the port Drv_in1 of theenergy emission circuit 3, the anode of the diode D6 is connected to one end of the resistor R31, and the other end of the resistor R31 Connected to the power supply VDD, the low-level output end LO of the bridge driver U16 is connected to one end of the resistor R34, and the other end of the resistor R34 is used as the third output end of thebridge drive circuit 7, denoted as the port Drv_out3, which is connected with the energy transmittingcircuit 3. The port Drv_in3 is connected; the voltage input terminal VCC of the bridge driver U17 and one end of the capacitor C14 are connected to the power supply VDD, the other end of the capacitor C14 and the COM terminal of the bridge driver U17 are grounded, and the high-level input terminal HIN of the bridge driver U17 is respectively connected to the field The drain of the effect transistor Q10 is connected to the low-level input terminal LIN of the bridge driver U16, and is used as the second control input terminal of thebridge driver circuit 7, denoted as port TsV_in2, and connected to the port TsV_out2 of the controlsequence generation circuit 8 , the VB terminal of the bridge driver U17 is respectively connected with the cathode of the diode D7 and one end of the capacitor C16, the VS terminal of the bridge driver U17 is respectively connected with the other end of the capacitor C16 and one end of the resistor R36, and is used as the fifth terminal of thebridge driver circuit 7. One output terminal, denoted as port Drv_out5, is connected to the port Drv_in5 of the energy transmittingcircuit 3, the high-level output terminal HO of the bridge driver U17 is connected to one end of the resistor R37, the other end of the resistor R37 is connected to the other end of the resistor R36, and As the fourth output terminal of thebridge drive circuit 7, it is denoted as port Drv_out4, which is connected to the port Drv_in4 of theenergy emission circuit 3. The anode of the diode D7 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the power supply VDD. The bridge driver The low-level output terminal LO of U17 is connected to one end of the resistor R35, and the other end of the resistor R35 is used as The sixth output terminal of thebridge drive circuit 7, denoted as port Drv_out6, is connected to the port Drv_in6 of theenergy emission circuit 3; the source of the FET Q9 and the source of the FET Q10 are grounded, and the gate of the FET Q9 The pole is connected to the gate of the field effect transistor Q10 and is used as the third control input end of thebridge drive circuit 7, denoted as port CtrlV_in, and connected to the port CtrlV-out of the outputautomatic control circuit 6;
所述控制时序发生电路8的结构为，555定时器U27的接地端GND接地并分别与电容C17一端、电容C18一端以及电容C19一端相连，电容C18的另一端与555定时器U27的控制端CVOLT相连，555定时器U27的触发输入端TRIG分别与555定时器U27的阈值端THR、R40一端以及C17的另一端相连，R40的另一端分别与R39一端以及555定时器U27的放电端DIS相连，R39的另一端分别与555定时器U27的复位端RST以及电压输入端+VCC相连并接电源VDD；555定时器U27的输出端OUT分别与反相器25.6的输入端以及反相器26.5的输入端相连，反相器26.5的输出端作为控制时序发生电路8的第一个控制输出端，记为端口TsV_out1，与电桥驱动电路7相连；反相器25.6的输出端与电阻R41一端相连，电阻R41的另一端分别与电容C19的另一端以及反相器U20.6的输入端相连，反相器U20.6的输出端与D触发器U18.1的时钟信号端Cp相连，D触发器U18.1的预置端Sd分别与电容C20一端、电阻R42一端以及二极管D8的阳极相连，电容C20的另一端分别与D触发器U18.1的触发信号端D以及D触发器U18.1的清零端Cd相连，电阻R42的另一端分别与二极管D8的阴极以及D触发器U18.1的反相位输出端Q非相连，D触发器U18.1的同相位输出端Q与反相器19.3的输入端相连，反相器U19.3的输出端作为控制时序发生电路8的第二个控制输出端，记为端口TsV_out2,与电桥驱动电路7相连；The structure of the controlsequence generation circuit 8 is that the ground terminal GND of the 555 timer U27 is grounded and connected to one end of the capacitor C17, one end of the capacitor C18 and one end of the capacitor C19, and the other end of the capacitor C18 is connected to the control terminal CVOLT of the 555 timer U27. Connected, the trigger input terminal TRIG of 555 timer U27 is respectively connected with the threshold terminal THR of 555 timer U27, one end of R40 and the other end of C17, the other end of R40 is respectively connected with one end of R39 and the discharge terminal DIS of 555 timer U27, The other end of R39 is respectively connected to the reset terminal RST of the 555 timer U27 and the voltage input terminal +VCC and is connected to the power supply VDD; the output terminal OUT of the 555 timer U27 is respectively connected to the input terminal of the inverter 25.6 and the input of the inverter 26.5 The output terminal of the inverter 26.5 is used as the first control output terminal of the controlsequence generation circuit 8, which is denoted as port TsV_out1, which is connected to thebridge drive circuit 7; the output terminal of the inverter 25.6 is connected to one end of the resistor R41, The other end of the resistor R41 is connected to the other end of the capacitor C19 and the input end of the inverter U20.6 respectively, the output end of the inverter U20.6 is connected to the clock signal end Cp of the D flip-flop U18.1, the D flip-flop The preset terminal Sd of U18.1 is respectively connected to one end of the capacitor C20, one end of the resistor R42 and the anode of the diode D8, and the other end of the capacitor C20 is respectively connected to the trigger signal terminal D of the D flip-flop U18.1 and the D flip-flop U18.1 The clearing terminal Cd is connected, and the other end of the resistor R42 is not connected to the cathode of the diode D8 and the inverting output terminal Q of the D flip-flop U18.1 respectively, and the in-phase output terminal Q of the D flip-flop U18.1 is connected to the inverter. The input end of 19.3 is connected, and the output end of the inverter U19.3 is used as the second control output end of the controlsequence generation circuit 8, which is denoted as port TsV_out2, and is connected with thebridge drive circuit 7;
所述基准电压电路9的结构为，基准电压源U24的输入端IN与电容C21一端相连并接电源VDD，基准电压源U24的NR端与电容C22一端相连，基准电压源U24的接地端GND分别与电容C21的另一端、电容C22的另一端、电容C23一端以及电阻R43一端相连并接地，电容C23的另一端分别与基准电压源U24的输出端OUT、基准电压源U24的TRIM端、基准电压源U24的I.C./3端以及运算放大器U21.1的同相输入端相连，运算放大器U21.1的反相输入端分别与电阻R43的另一端、电容C24一端以及电阻R44一端相连，电容C24的另一端分别与运算放大器U21.1的输出端、可变电阻W3一端、可变电阻W4一端以及电阻R44的另一端相连，可变电阻W3的活动触点与运算放大器U22.2的同相输入端相连，运算放大器U22.2的输出端反馈给反相输入端，并作为基准电压电路9的第一个参考输出端，记为端口Vref_out1,与电压调节电路2的端口Vref_in1相连；可变电阻W4的活动触点与运算放大器U23.1的同相输入端相连，运算放大器U23.1的输出端反馈给反相输入端，并作为基准电压电路9的第二个参考输出端，记为端口Vref_out2,与输出自动控制电路6的端口Vref_in2相连；可变电阻W3的另一端以及可变电阻W4的另一端接地。The structure of thereference voltage circuit 9 is that the input terminal IN of the reference voltage source U24 is connected to one end of the capacitor C21 and is connected to the power supply VDD, the NR end of the reference voltage source U24 is connected to one end of the capacitor C22, and the ground terminals GND of the reference voltage source U24 are respectively connected. It is connected to the other end of the capacitor C21, the other end of the capacitor C22, one end of the capacitor C23 and one end of the resistor R43 and is connected to the ground. The I.C./3 terminal of the source U24 is connected to the non-inverting input terminal of the operational amplifier U21.1, and the inverting input terminal of the operational amplifier U21.1 is respectively connected to the other terminal of the resistor R43, one terminal of the capacitor C24 and one terminal of the resistor R44, and the other terminal of the capacitor C24 is respectively connected. One end is respectively connected to the output end of the operational amplifier U21.1, one end of the variable resistor W3, one end of the variable resistor W4 and the other end of the resistor R44, and the movable contact of the variable resistor W3 is connected to the non-inverting input end of the operational amplifier U22.2 , the output terminal of the operational amplifier U22.2 is fed back to the inverting input terminal, and is used as the first reference output terminal of thereference voltage circuit 9, denoted as port Vref_out1, which is connected to the port Vref_in1 of thevoltage adjustment circuit 2; The movable contact is connected to the non-inverting input terminal of the operational amplifier U23.1, and the output terminal of the operational amplifier U23.1 is fed back to the inverting input terminal, and is used as the second reference output terminal of thereference voltage circuit 9, denoted as port Vref_out2, and The port Vref_in2 of the outputautomatic control circuit 6 is connected; the other end of the variable resistor W3 and the other end of the variable resistor W4 are grounded.
所述能量发射电路3中，电感L3优选为10mH；电容C5优选为100pF；电阻R14、R15优选为18kΩ。In theenergy emission circuit 3, the inductance L3 is preferably 10mH; the capacitor C5 is preferably 100pF; the resistors R14 and R15 are preferably 18kΩ.
所述电流检测放大电路4中，电阻优选值：电阻R16、R17、R18、R19为10kΩ，电阻RS1为0.1Ω，可变电阻W2为100kΩ。In the currentdetection amplifying circuit 4, the preferred resistance values are as follows: the resistances R16, R17, R18, and R19 are 10kΩ, the resistance RS1 is 0.1Ω, and the variable resistance W2 is 100kΩ.
所述输出自动控制电路6中，电容优选值：电容C10为200nF，电容C11为1μF，C12为100nF；电阻优选值：电阻R26为20kΩ，电阻R27为10kΩ，电阻R28为2kΩ，电阻R29为1MΩ，电阻R30为100kΩ。In the outputautomatic control circuit 6, the preferred value of the capacitor: the capacitor C10 is 200nF, the capacitor C11 is 1μF, and the capacitor C12 is 100nF; the preferred value of the resistance: the resistance R26 is 20kΩ, the resistance R27 is 10kΩ, the resistance R28 is 2kΩ, and the resistance R29 is 1MΩ , the resistance R30 is 100kΩ.
所述控制时序发生电路8中，电容优选值：电容C17为100μF，电容C18、C19、C20为4.3nF；电阻优选值：电阻R39为700Ω，电阻R40为3.1kΩ，电阻R41为250Ω，电阻R42为8.2kΩ。In the controlsequence generation circuit 8, the preferred value of the capacitor: the capacitor C17 is 100μF, the capacitors C18, C19, and C20 are 4.3nF; the preferred value of the resistance: the resistance R39 is 700Ω, the resistance R40 is 3.1kΩ, the resistance R41 is 250Ω, and the resistance R42 is 250Ω. is 8.2kΩ.
有益效果：Beneficial effects:
1、本发明可以同时为多个无人机进行无线充电，使用方便。1. The present invention can wirelessly charge multiple drones at the same time, which is convenient to use.
2、本发明通过电压调节电路，使输出通道中的能量发射模块始终工作在最佳的电压，提高了发射模块的效率。2. The present invention makes the energy transmitting module in the output channel always work at the best voltage through the voltage regulating circuit, thereby improving the efficiency of the transmitting module.
3、本发明通过输出自动控制电路，使能量发射模块在空载时自动断电，且在有负载时自动启动，提高了可靠性和便利性。3. In the present invention, by outputting an automatic control circuit, the energy emission module is automatically powered off when no-load, and automatically starts when there is a load, thereby improving reliability and convenience.
附图说明Description of drawings
图1是本发明的总体结构框图。FIG. 1 is a block diagram of the overall structure of the present invention.
图2是单个输出通道电路连接框图。Figure 2 is a block diagram of a single output channel circuit connection.
图3是电源管理电路的原理电路图。FIG. 3 is a schematic circuit diagram of a power management circuit.
图4是电压调节电路的原理电路图。Fig. 4 is the principle circuit diagram of the voltage regulation circuit.
图5是能量发射电路的原理电路图。Fig. 5 is the principle circuit diagram of the energy transmitting circuit.
图6是电流检测放大电路的原理电路图。FIG. 6 is a schematic circuit diagram of the current detection amplifier circuit.
图7是信号整形电路的原理电路图。FIG. 7 is a schematic circuit diagram of a signal shaping circuit.
图8是输出自动控制的原理电路图。Fig. 8 is the principle circuit diagram of output automatic control.
图9是电桥驱动电路的原理电路图。FIG. 9 is a schematic circuit diagram of a bridge drive circuit.
图10是控制时序发生电路的原理电路图。FIG. 10 is a schematic circuit diagram of the control sequence generation circuit.
图11是基准电压电路的原理电路图。FIG. 11 is a schematic circuit diagram of the reference voltage circuit.
具体实施方式Detailed ways
以下结合附图对本发明的具体实施方案作进一步说明。The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.
如图1所示，本发明的一种小型无人机多路无线充电发射系统，其结构有电源管理电路1、控制时序发生电路8、基准电压电路9、输出矩阵10。所述的输出矩阵10中包含若干个电路输出通道(根据实际需求可以取2～8个)。所述的电源管理电路1将市电的220V交流电转换成直流稳压电源，为其它各模块提供所需的电压；基准电压电路9为输出矩阵10中各输出通道电路提供基准电压，控制时序发生电路8为输出矩阵10中各输出通道电路提供PWM信号。As shown in FIG. 1 , a multi-channel wireless charging and transmitting system for a small unmanned aerial vehicle of the present invention has a structure of apower management circuit 1 , a controlsequence generation circuit 8 , areference voltage circuit 9 and anoutput matrix 10 . Theoutput matrix 10 includes several circuit output channels (2 to 8 can be selected according to actual needs). Thepower management circuit 1 converts the 220V alternating current of the mains into a DC regulated power supply to provide the required voltages for other modules; thereference voltage circuit 9 provides a reference voltage for each output channel circuit in theoutput matrix 10, and controls the sequence generation.Circuit 8 provides PWM signals for each output channel circuit inoutput matrix 10 .
实施例2各输出通道的构成Example 2 Configuration of each output channel
系统中的输出矩阵10中的各个输出通道具有相同的结构，每个输出通道可为一个无人机进行无线充电，图2所示为单个输出通道的结构框图，单个输出通道的结构包括电压调节电路2、能量发射电路3、电流检测放大电路4、信号整形电路5、输出自动控制电路6、电压检测电路7。电压调节电路2的输出端与能量发射电路3的输入端以及输出自动控制电路6的输入端相连，能量发射电路3的输出端与电流检测放大电路4的输入端相连，电流检测放大电路4的输出端与信号整形电路5的输入端相连，电压调节电路2的输入端分别与信号整形电路5的输出端以及基准电压电路9的输出端相连，基准电压电路9的输出端还与输出自动控制电路6的输入端相连，输出自动控制电路6的输出端与电桥驱动电路7相连，电桥驱动电路7的输出端与能量发射电路3的输入端相连，电桥驱动电路7受控制时序发生电路8的输出端控制。Each output channel in theoutput matrix 10 in the system has the same structure, and each output channel can wirelessly charge a drone. Figure 2 shows the structure diagram of a single output channel. The structure of a single output channel includes voltage regulation.Circuit 2 ,energy emission circuit 3 , current detection andamplification circuit 4 , signal shapingcircuit 5 , outputautomatic control circuit 6 , andvoltage detection circuit 7 . The output end of thevoltage regulation circuit 2 is connected with the input end of theenergy emission circuit 3 and the input end of the outputautomatic control circuit 6, the output end of theenergy emission circuit 3 is connected with the input end of the current detection andamplification circuit 4, and the current detection andamplification circuit 4 is connected with the input end. The output end is connected with the input end of thesignal shaping circuit 5, the input end of thevoltage regulating circuit 2 is respectively connected with the output end of thesignal shaping circuit 5 and the output end of thereference voltage circuit 9, and the output end of thereference voltage circuit 9 is also connected with the output automatic control The input end of thecircuit 6 is connected, the output end of the outputautomatic control circuit 6 is connected with thebridge drive circuit 7, the output end of thebridge drive circuit 7 is connected with the input end of theenergy emission circuit 3, and thebridge drive circuit 7 is controlled by the timing sequence. The output ofcircuit 8 controls.
实施例3电源管理电路Embodiment 3 Power Management Circuit
所述的电源管理电路1的结构如图3所示：变压器T1的输入端与市电相连，三个输出端分别与整流桥D101、整流桥D102的输入端相连；整流桥D101的输出端负极接电解电容C101的负极并接地，整流桥D101的输出端正极接电解电容C101的正极并作为所述的电源管理电路1的第一输出端，记为端口HV_out，为电压调节电路2供电；整流桥D102的输出端负极接电解电容C102的负极并接地，整流桥D102的输出端正极接电解电容C102的正极并与芯片LM7812的1端口相连，还与电容C103的一端相连，电容C103的另一端与芯片LM7812的2端口相连并接地，电容C14的一端接地，另一端与芯片LM7812的3端口相连，并与电阻R2的一端相连，作为所述的电源管理电路1的第二输出端，记为端口P_out1，为系统中各模块提供电源VDD，电阻R2的另一端与电阻R1的一端及运放U1A的同相输入端相连，电阻R1的另一端接地，运放U1A的反相输入端与输出端相连，作为所述的电源管理电路1的第三输出端，记为端口P_out2，为系统提供电源VDD/2。The structure of thepower management circuit 1 is shown in Figure 3: the input end of the transformer T1 is connected to the mains, the three output ends are respectively connected to the input ends of the rectifier bridge D101 and the rectifier bridge D102; the output end of the rectifier bridge D101 is negative The negative electrode of the electrolytic capacitor C101 is connected to the ground, and the positive electrode of the output end of the rectifier bridge D101 is connected to the positive electrode of the electrolytic capacitor C101 and used as the first output end of thepower management circuit 1, which is denoted as port HV_out, which supplies power to thevoltage regulation circuit 2; The negative pole of the output terminal of the bridge D102 is connected to the negative pole of the electrolytic capacitor C102 and grounded. The positive pole of the output terminal of the rectifier bridge D102 is connected to the positive pole of the electrolytic capacitor C102 and is connected to the 1 port of the chip LM7812. It is also connected to one end of the capacitor C103 and the other end of the capacitor C103. It is connected to the 2 port of the chip LM7812 and grounded, one end of the capacitor C14 is grounded, the other end is connected to the 3 port of the chip LM7812, and is connected to one end of the resistor R2, as the second output of thepower management circuit 1, marked as Port P_out1 provides power VDD for each module in the system. The other end of resistor R2 is connected to one end of resistor R1 and the non-inverting input end of op amp U1A, the other end of resistor R1 is grounded, and the inverting input end and output end of op amp U1A Connected to each other as the third output terminal of thepower management circuit 1, denoted as port P_out2, to provide power supply VDD/2 for the system.
电源管理电路1将220V市电转换成3种不同的直流电压提供给系统各模块：用于给电压调节电路提供大功率的48V电压，通过端口HV_out输出；用于给各模块中模拟电路提供+5V供电的VDD，通过端口P_out1输出；用于给各模块提供2.5V供电的VDD/2，通过端口P_out2输出。Thepower management circuit 1 converts the 220V mains into 3 different DC voltages and provides them to each module of the system: the 48V voltage used to provide high power to the voltage regulation circuit is output through the port HV_out; it is used to provide + The 5V power supply VDD is output through port P_out1; the VDD/2 used to provide 2.5V power supply to each module is output through port P_out2.
实施例4电压调节电路Embodiment 4 Voltage Regulation Circuit
所述的电压调节电路2的结构如图4所示：运算放大器U3.1的同相输入端与电阻R8一端以及R9一端相连，运算放大器U3.1的反相输入端与电容C3一端、电阻R7一端以及运算放大器U4.2的反相输入端相连，电阻R7的另一端与运算放大器U3.1的输出端以及电阻R9的另一端相连，电容C3的另一端与电阻R8的另一端相连并接电源VDD/2；运算放大器U4.2的输出端与场效应管Q2的栅极相连，运算放大器U4.2的正电源端接电源VDD，运算放大器U4.2的负电源端接地，场效应管Q2的源极与二极管D2的阴极以及电感L2一端相连，场效应管Q2的漏极作为电压调节电路2的电压输入端，记为端口HV_in，与电源管理电路1的端口HV_out相连；电感L2的另一端与电解电容C4的正极相连，并作为电压调节电路2的补偿输出端，记为端口ADV_out，分别与能量发射电路3的端口ADV_in1以及输出自动控制电路6的端口ADV_in2相连；电解电容C4的负极与二极管D2的阳极相连并接地；运算放大器U5.1的同相输入端与电阻R12一端以及R13一端相连，运算放大器U5.1的反相输入端与电阻R10一端、电阻R11一端相连，电阻R10的另一端与运算放大器U5.1的输出端以及运算放大器U4.2的同相输入端相连，电阻R11的另一端作为电压调节电路的参考输入端，记为端口Vref_in1，与基准电压电路9的端口Vref_out1相连；电阻R12的另一端作为电压调节电路的取样输入端，记为端口ReshapeV_in，与信号整形电路5的端口ReshapeV_out相连；电阻R13的另一端接电源VDD/2。The structure of thevoltage regulation circuit 2 is shown in Figure 4: the non-inverting input end of the operational amplifier U3.1 is connected to one end of the resistor R8 and one end of the resistor R9, the inverting input end of the operational amplifier U3.1 is connected to one end of the capacitor C3 and one end of the resistor R7 One end is connected to the inverting input end of the operational amplifier U4.2, the other end of the resistor R7 is connected to the output end of the operational amplifier U3.1 and the other end of the resistor R9, the other end of the capacitor C3 is connected to the other end of the resistor R8 in parallel Power supply VDD/2; the output terminal of the operational amplifier U4.2 is connected to the gate of the field effect transistor Q2, the positive power supply terminal of the operational amplifier U4.2 is connected to the power supply VDD, the negative power supply terminal of the operational amplifier U4.2 is grounded, and the field effect transistor is connected to the ground. The source of Q2 is connected to the cathode of the diode D2 and one end of the inductor L2, the drain of the FET Q2 is used as the voltage input terminal of the voltage regulation circuit 2, denoted as port HV_in, and is connected to the port HV_out of the power management circuit 1; The other end is connected to the positive pole of the electrolytic capacitor C4, and is used as the compensation output end of the voltage regulating circuit 2, denoted as port ADV_out, which is respectively connected to the port ADV_in1 of the energy transmitting circuit 3 and the port ADV_in2 of the output automatic control circuit 6; The negative electrode is connected to the anode of diode D2 and grounded; the non-inverting input terminal of operational amplifier U5.1 is connected to one end of resistor R12 and one end of R13; The other end of the resistor R11 is connected to the output end of the operational amplifier U5.1 and the non-inverting input end of the operational amplifier U4.2, and the other end of the resistor R11 is used as the reference input end of the voltage regulation circuit, denoted as port Vref_in1, and the port of the reference voltage circuit 9 Vref_out1 is connected; the other end of the resistor R12 is used as the sampling input end of the voltage adjustment circuit, denoted as port ReshapeV_in, which is connected to the port ReshapeV_out of the signal shaping circuit 5; the other end of the resistor R13 is connected to the power supply VDD/2.
电压调节电路2将电流检测放大电路6检测的电流值(反映了有效负载的大小，并通过信号整形电路5进行整形)与基准电压电路9设定的参考值进行比较求差，然后根据此差值将HV-in端口接收到的48V电压(由电源管理电路1提供)转换成与实际负载匹配的电压后通过端口ADV-out输出至能量发射电桥3，作为能量发射电桥3的工作电压，以使能量发射电桥3工作于稳定的电流状态。Thevoltage adjustment circuit 2 compares the current value detected by the current detection amplifying circuit 6 (reflecting the size of the effective load, and is shaped by the signal shaping circuit 5) and the reference value set by thereference voltage circuit 9 to obtain a difference, and then according to the difference The value converts the 48V voltage received by the HV-in port (provided by the power management circuit 1) into a voltage that matches the actual load and then outputs it to theenergy transmission bridge 3 through the port ADV-out as the working voltage of theenergy transmission bridge 3 , so that theenergy emission bridge 3 works in a stable current state.
实施例5能量发射电路Embodiment 5 Energy transmitting circuit
所述的能量发射电路3的结构如图5所示：场效应管Q3的栅极作为能量发射电路3的第一个驱动端，记为端口Drv_in1，与电桥驱动电路7的端口Drv_out1相连；场效应管Q3的源极分别与场效应管Q4的漏极以及电容C5一端相连，并作为能量发射电路3的第二个驱动端，记为端口Drv_in2，与电桥驱动电路7的端口Drv_out2相连；场效应管Q4的栅极与R14一端相连，并作为能量发射电路3的第三个驱动端，记为端口Drv_in3，与电桥驱动电路7的端口Drv_out3相连；场效应管Q5的栅极作为能量发射电路3的第四个驱动端，记为端口Drv_in4，与电桥驱动电路7的端口Drv_out4相连；场效应管Q5的源极分别与场效应管Q6的漏极以及电感L3一端相连，并作为能量发射电路3的第五个驱动端，记为端口Drv_in5，与电桥驱动电路7的端口Drv_out5相连，电感L3的另一端与电容C5的另一端相连；场效应管Q6的栅极与电阻R15一端相连，并作为能量发射电路3的第六个驱动端，记为端口Drv_in6，与电桥驱动电路7的端口Drv_out6相连；电阻R15的另一端分别与电阻R14的另一端、场效应管Q4的源极以及场效应管Q6的源极相连，并作为能量发射电路3的取样输出端，记为端口SampV_out，与电流检测放大电路4的端口SampV_in相连；场效应管Q3的漏极与场效应管Q5的漏极相连，并作为能量发射电路3的补偿输入端，记为端口ADV_in1，与电压调节电路2的端口ADV_out相连。The structure of the described energy emission circuit 3 is shown in Figure 5: the gate of the field effect transistor Q3 is used as the first drive end of the energy emission circuit 3, which is denoted as port Drv_in1, and is connected to the port Drv_out1 of the bridge drive circuit 7; The source of the field effect transistor Q3 is connected to the drain of the field effect transistor Q4 and one end of the capacitor C5 respectively, and is used as the second drive end of the energy emission circuit 3, denoted as port Drv_in2, and connected to the port Drv_out2 of the bridge drive circuit 7 ; The gate of field effect transistor Q4 is connected with one end of R14, and is used as the third drive terminal of energy emission circuit 3, denoted as port Drv_in3, and connected with port Drv_out3 of bridge drive circuit 7; The gate of field effect transistor Q5 is used as The fourth drive end of the energy emission circuit 3, denoted as port Drv_in4, is connected to the port Drv_out4 of the bridge drive circuit 7; As the fifth drive end of the energy emission circuit 3, it is denoted as port Drv_in5, which is connected to the port Drv_out5 of the bridge drive circuit 7, and the other end of the inductor L3 is connected to the other end of the capacitor C5; the gate of the field effect transistor Q6 is connected to the resistor One end of R15 is connected and used as the sixth drive end of the energy emission circuit 3, denoted as port Drv_in6, and connected to the port Drv_out6 of the bridge drive circuit 7; the other end of the resistor R15 is respectively connected with the other end of the resistor R14, the field effect transistor Q4 The source of the FET Q6 is connected to the source of the FET Q6, and is used as the sampling output end of the energy emission circuit 3, denoted as port SampV_out, and connected to the port SampV_in of the current detection amplifier circuit 4; the drain of the FET Q3 is connected to the FET The drain of the tube Q5 is connected, and is used as the compensation input terminal of the energy transmitting circuit 3, denoted as port ADV_in1, and is connected to the port ADV_out of the voltage regulating circuit 2.
能量发射电路3在控制时序发生电路8提供的PWM时序(50kHz)的控制下将电压调节电路2提供的电压转换成振荡的正弦波电流流过电感L3(即发射线圈)，发射线圈将电流转换成变化的磁场能量进行发射，由无人机接收端的接收线圈接收，实现对无人机的无线充电。Theenergy transmitting circuit 3 converts the voltage provided by thevoltage regulating circuit 2 into an oscillating sine wave current under the control of the PWM timing (50kHz) provided by the control timing generatingcircuit 8 and flows through the inductor L3 (ie the transmitting coil), and the transmitting coil converts the current into It is transmitted into the changing magnetic field energy and received by the receiving coil of the receiving end of the drone to realize wireless charging of the drone.
实施例6电流检测放大电路Embodiment 6 Current detection amplifier circuit
所述的电流检测放大电路4的结构如图6所示：运算放大器U7.2的同相输入端与电阻RS1一端相连，并作为电流检测放大电路4的取样输入端，记为端口SampV_in,与能量发射电路3的端口SampV_out相连，运算放大器U7.2的反相输入端分别与电阻R16一端、电阻R17一端、可变电阻W2一端以及可变电阻W2活动触点相连，运算放大器U7.2的输出端与电阻R16的另一端相连，并作为电流检测放大电路4的放大输出端，记为端口AmpV_out，与信号整形电路5的端口AmpV_in相连；可变电阻W2的另一端分别与电阻R18一端、电阻R19一端以及运算放大器U6.1的反相输入端相连，R17的另一端分别与R18的另一端以及运算放大器U6.1的输出端相连，R19的另一端接电源VDD/2，运算放大器U6.1的同相输入端分别与运算放大器U6.1的负电源端以及电阻RS1的另一端相连并接地，运算放大器U6.1的正电源端接电源VDD。The structure of the currentdetection amplifying circuit 4 is shown in Figure 6: the non-inverting input terminal of the operational amplifier U7.2 is connected to one end of the resistor RS1, and is used as the sampling input terminal of the currentdetection amplifying circuit 4, which is denoted as port SampV_in, and energy. The port SampV_out of the transmittingcircuit 3 is connected, and the inverting input end of the operational amplifier U7.2 is respectively connected to one end of the resistor R16, one end of the resistor R17, one end of the variable resistor W2 and the movable contact of the variable resistor W2, and the output of the operational amplifier U7.2 The terminal is connected to the other end of the resistor R16, and is used as the amplification output terminal of the currentdetection amplifier circuit 4, which is marked as the port AmpV_out, and is connected to the port AmpV_in of thesignal shaping circuit 5; the other end of the variable resistor W2 is respectively connected with one end of the resistor R18, the resistor One end of R19 is connected to the inverting input end of the operational amplifier U6.1, the other end of R17 is connected to the other end of R18 and the output end of the operational amplifier U6.1 respectively, the other end of R19 is connected to the power supply VDD/2, and the other end of the operational amplifier U6. The non-inverting input terminal of 1 is respectively connected to the negative power supply terminal of the operational amplifier U6.1 and the other end of the resistor RS1 and is grounded, and the positive power supply terminal of the operational amplifier U6.1 is connected to the power supply VDD.
电流检测放大电路4通过取样电阻Rs对能量发射电路的工作电流进行采样并放大后输入至信号整形电路5。The currentdetection amplifying circuit 4 samples the working current of the energy emission circuit through the sampling resistor Rs, amplifies it, and then inputs it to thesignal shaping circuit 5 .
实施例7信号整形电路Embodiment 7 Signal shaping circuit
所述的信号整形电路5的结构如图7所示：所述信号整形电路5的结构为，运算放大器U8.2的正电源端接电源VDD，运算放大器U8.2的负电源端接地，运算放大器U8.2的反相输入端分别与电阻R21一端以及电容C7一端相连，运算放大器U8.2的同相输入端与电容C6一端相连并接地，电容C6的另一端分别与电阻R20一端、电阻R21的另一端以及电阻R22一端相连，电阻R20的另一端作为信号整形电路5的电压输入端，记为端口AmpV_in，与电流检测放大电路4的端口AmpV_out相连；电阻R22的另一端分别与电容C7的另一端、电阻R23一端以及运算放大器U8.2的输出端相连；运算放大器U9.1的反相输入端分别与电阻R24一端以及电容C9一端相连，运算放大器U9.1的同相输入端与电容C8一端相连并接地，电容C8的另一端分别与电阻R25一端、电阻R24的另一端以及电阻R23另一端相连；电阻R25的另一端分别与电容C9的另一端以及运算放大器U9.1的输出端相连，并作为信号整形电路5的整形输出端，记为端口ReshapeV_out，与电压调节电路2的端口ReshapeV_in相连。The structure of thesignal shaping circuit 5 is shown in FIG. 7 : the structure of thesignal shaping circuit 5 is that the positive power supply terminal of the operational amplifier U8.2 is connected to the power supply VDD, the negative power supply terminal of the operational amplifier U8.2 is grounded, and the operational amplifier U8.2 is grounded. The inverting input terminal of amplifier U8.2 is connected to one end of resistor R21 and one end of capacitor C7 respectively. The non-inverting input terminal of operational amplifier U8.2 is connected to one end of capacitor C6 and grounded, and the other end of capacitor C6 is connected to one end of resistor R20 and one end of resistor R21 respectively. The other end of the resistor R22 is connected to one end of the resistor R22, and the other end of the resistor R20 is used as the voltage input end of thesignal shaping circuit 5, denoted as port AmpV_in, and connected to the port AmpV_out of the currentdetection amplifier circuit 4; the other end of the resistor R22 is respectively connected with the capacitor C7. The other end, one end of resistor R23 and the output end of operational amplifier U8.2 are connected; the inverting input end of operational amplifier U9.1 is connected to one end of resistor R24 and one end of capacitor C9 respectively, and the non-inverting input end of operational amplifier U9.1 is connected to capacitor C8 One end is connected to ground and the other end of capacitor C8 is connected to one end of resistor R25, the other end of resistor R24 and the other end of resistor R23 respectively; the other end of resistor R25 is connected to the other end of capacitor C9 and the output end of operational amplifier U9.1 respectively , and as the shaping output terminal of thesignal shaping circuit 5 , denoted as the port ReshapeV_out, and connected to the port ReshapeV_in of thevoltage adjusting circuit 2 .
信号整形电路5对电流检测放大电路4输出的信号进行整形输出至电压调节电路2与基准电压进行比较。Thesignal shaping circuit 5 shapes the signal output by the currentdetection amplifying circuit 4 and outputs it to thevoltage adjusting circuit 2 for comparison with the reference voltage.
实施例8输出自动控制电路Example 8 Output automatic control circuit
所述的输出自动控制电路6的结构如图8所示：运算放大器U10.2的正电源端接电源VDD，运算放大器U10.2的负电源端接地，运算放大器U10.2的反相输入端作为输出自动控制电路6的参考输入端，记为端口Vref_in2，与基准电压电路9的端口Vref_out2相连，运算放大器U10.2的同相输入端与稳压二极管D3的阴极以及电阻R26一端相连，稳压二极管D5的阳极接地，电阻R26的另一端作为输出自动控制电路6的补偿输入端，记为端口ADV_in2，与电压调节电路2的端口ADV_out相连；运算放大器U10.2的输出端与三极管Q7的基极相连，三极管Q7的集电极接电源VDD，发射极分别与电阻R27一端、电阻R28一端以及三极管Q8的发射极相连，电阻R27的另一端与电容C10一端以及反相器U13.4的输入端相连，电阻R28的另一端以及电容C10的另一端接地，反相器U13.4的输出端与D触发器U11.1的时钟信号端Cp相连，D触发器U11.1的触发信号端D分别与清零端Cd以及电容C11一端相连并接地，电容C11的另一端分别与二极管D4的阳极、电阻R29一端以及D触发器U11.1的预置端Sd相连，二极管D4的阴极与电阻R29的另一端以及D触发器U11.1的反相位输出端Q非相连，D触发器U11.1的同相位输出端Q分别与D触发器U12.2的时钟信号端Cp以及反相器U15.2的输入端相连，反相器U15.2的输出端作为输出自动控制电路6的控制输出端，记为端口CtrlV_out，与电桥驱动电路7的端口CtrlV_in相连；D触发器U12.2的触发信号端D分别与D触发器U12.2的清零端Cd及电容C12一端相连，电容C12的另一端与二极管D5的阳极、电阻R30一端以及D触发器U12.2的预置端Sd相连，二极管D5的阴极分别与电阻R30的另一端、D触发器U12.2的反相位输出端Q非相连，D触发器U12.2的同相位输出端Q与反相器U14.1的输入端相连，反相器U14.1的输出端与三极管Q8的基极相连，三极管Q8的集电极接电源VDD。The structure of the outputautomatic control circuit 6 is shown in Figure 8: the positive power supply terminal of the operational amplifier U10.2 is connected to the power supply VDD, the negative power supply terminal of the operational amplifier U10.2 is grounded, and the inverting input terminal of the operational amplifier U10.2 As the reference input terminal of the outputautomatic control circuit 6, it is denoted as port Vref_in2, which is connected to the port Vref_out2 of thereference voltage circuit 9. The non-inverting input terminal of the operational amplifier U10.2 is connected to the cathode of the Zener diode D3 and one end of the resistor R26. The anode of the diode D5 is grounded, and the other end of the resistor R26 is used as the compensation input end of the outputautomatic control circuit 6, denoted as port ADV_in2, which is connected to the port ADV_out of thevoltage adjustment circuit 2; the output end of the operational amplifier U10.2 is connected to the base of the transistor Q7. The collector of the transistor Q7 is connected to the power supply VDD, the emitter is connected to one end of the resistor R27, one end of the resistor R28 and the emitter of the transistor Q8, the other end of the resistor R27 is connected to one end of the capacitor C10 and the input end of the inverter U13.4 The other end of the resistor R28 and the other end of the capacitor C10 are grounded, the output end of the inverter U13.4 is connected to the clock signal end Cp of the D flip-flop U11.1, and the trigger signal end D of the D flip-flop U11.1 is respectively It is connected to the clearing terminal Cd and one end of the capacitor C11 and grounded, and the other end of the capacitor C11 is respectively connected to the anode of the diode D4, one end of the resistor R29 and the preset terminal Sd of the D flip-flop U11.1, and the cathode of the diode D4 is connected to the resistor R29. The other end and the inverted output terminal Q of the D flip-flop U11.1 are not connected, and the in-phase output terminal Q of the D flip-flop U11.1 is respectively connected with the clock signal terminal Cp of the D flip-flop U12.2 and the inverter U15. The input end of 2 is connected, and the output end of the inverter U15.2 is used as the control output end of the outputautomatic control circuit 6, denoted as the port CtrlV_out, and connected with the port CtrlV_in of thebridge drive circuit 7; the trigger of the D flip-flop U12.2 The signal terminal D is respectively connected to the clear terminal Cd of the D flip-flop U12.2 and one end of the capacitor C12, and the other end of the capacitor C12 is connected to the anode of the diode D5, one end of the resistor R30 and the preset terminal Sd of the D flip-flop U12.2, The cathode of the diode D5 is respectively non-connected to the other end of the resistor R30 and the inverting output terminal Q of the D flip-flop U12.2, the in-phase output terminal Q of the D flip-flop U12.2 and the input terminal of the inverter U14.1 The output terminal of the inverter U14.1 is connected to the base of the transistor Q8, and the collector of the transistor Q8 is connected to the power supply VDD.
由实施例4的说明可知，当负载逐渐减小时，电压调节电路2输出的电压会逐渐减小，因此当负载完全消失时(即没有无人机充电或电已充满)电压调节电路2则会输出一个非常小的电压，因此当电压检测电路检测的电压小于某一预设值(由基准电压电路9设置)后，则判定系统处于空载状态，由端口CtrlV-out输出高电平使得电桥驱动电路7中的场效应管Q9、Q10导通，以使端口TsV-in1、TsV-in2接收的PWM信号(由控制时序发生电路8提供)锁死到0，电桥驱动电路7停止工作，进而使能量发射电桥3停止发射能量，使系统进入待机状态，有效减小了能量损耗。输出自动控制电路6还具备自动启动功能，由D触发器U11.1、反相器U12.2等构成的延时反相结构会在系统待机时每间隔一定时间产生一个触发信号，使系统尝试上电检测，如果检测到有负载存在，则维持电路正常的发射状态，如果上电尝试后发现系统依然是空载的，则再次控制系统进入断电状态，此过程在待机过程中持续重复。尝试上电检测的持续时间由电阻R30和电容C12决定，而两次尝试所间隔的休眠时间由电阻R29和电容C11，由于R29远大于R30，C11远大于C12，因此在待机过程中系统消耗的功耗大大降低。It can be seen from the description ofEmbodiment 4 that when the load gradually decreases, the output voltage of thevoltage regulation circuit 2 will gradually decrease, so when the load disappears completely (that is, no drone is charged or the battery is fully charged), thevoltage regulation circuit 2 will A very small voltage is output, so when the voltage detected by the voltage detection circuit is less than a certain preset value (set by the reference voltage circuit 9), it is determined that the system is in a no-load state, and the port CtrlV-out outputs a high level to make the power The field effect transistors Q9 and Q10 in thebridge drive circuit 7 are turned on, so that the PWM signals (provided by the control sequence generation circuit 8) received by the ports TsV-in1 and TsV-in2 are locked to 0, and thebridge drive circuit 7 stops working , and then make theenergy transmitting bridge 3 stop transmitting energy, so that the system enters a standby state, which effectively reduces the energy loss. The outputautomatic control circuit 6 also has an automatic start function. The delay inversion structure composed of D flip-flop U11.1, inverter U12.2, etc. will generate a trigger signal at certain intervals when the system is in standby, so that the system will try Power-on detection, if it is detected that there is a load, the normal transmission state of the circuit is maintained. If it is found that the system is still no-load after the power-on attempt, the system is controlled to enter the power-off state again, and this process continues to repeat during the standby process. The duration of the power-on detection is determined by the resistor R30 and the capacitor C12, and the sleep time between the two attempts is determined by the resistor R29 and the capacitor C11. Since R29 is much larger than R30 and C11 is much larger than C12, the system consumes a lot of power during the standby process. Power consumption is greatly reduced.
实施例9电桥驱动电路Embodiment 9 Bridge drive circuit
所述的电桥驱动电路7的结构如图9所示：电桥驱动器U16的电压输入端VCC以及电容C13一端接电源VDD，电容C13的另一端以及电桥驱动器U16的COM端接地，电桥驱动器U16的高电平输入端HIN分别与场效应管Q9的漏极以及电桥驱动器U17的低电平输入端LIN相连，并作为电桥驱动电路7的第一个控制输入端，记为端口TsV_in1,与控制时序发生电路8的端口TsV_out1相连，电桥驱动器U16的VB端分别与二极管D6的阴极以及电容C15一端相连，电桥驱动器U16的VS端分别与电容C15的另一端以及电阻R33一端相连，并作为电桥驱动电路7的第二个输出端，记为端口Drv_out2，与能量发射电路3的端口Drv_in2相连，电桥驱动器U16的高电平输出端HO与电阻R32一端相连，电阻R32的另一端与电阻R33的另一端相连，并作为电桥驱动电路7的第一个输出端，记为端口Drv_out1，与能量发射电路3的端口Drv_in1相连，二极管D6的阳极与电阻R31一端相连，电阻R31的另一端接电源VDD，电桥驱动器U16的低电平输出端LO与电阻R34一端相连，电阻R34的另一端作为电桥驱动电路7的第三个输出端，记为端口Drv_out3，与能量发射电路3的端口Drv_in3相连；电桥驱动器U17的电压输入端VCC以及电容C14一端接电源VDD，电容C14的另一端以及电桥驱动器U17的COM端接地，电桥驱动器U17的高电平输入端HIN分别与场效应管Q10的漏极以及电桥驱动器U16的低电平输入端LIN相连，并作为电桥驱动电路7的第二个控制输入端，记为端口TsV_in2,与控制时序发生电路8的端口TsV_out2相连，电桥驱动器U17的VB端分别与二极管D7的阴极以及电容C16一端相连，电桥驱动器U17的VS端分别与电容C16的另一端以及电阻R36一端相连，并作为电桥驱动电路7的第五个输出端，记为端口Drv_out5，与能量发射电路3的端口Drv_in5相连，电桥驱动器U17的高电平输出端HO与电阻R37一端相连，电阻R37的另一端与电阻R36的另一端相连，并作为电桥驱动电路7的第四个输出端，记为端口Drv_out4，与能量发射电路3的端口Drv_in4相连，二极管D7的阳极与电阻R38一端相连，电阻R38的另一端接电源VDD，电桥驱动器U17的低电平输出端LO与电阻R35一端相连，电阻R35的另一端作为电桥驱动电路7的第六个输出端，记为端口Drv_out6，与能量发射电路3的端口Drv_in6相连；场效应管Q9的源极以及场效应管Q10的源极接地，场效应管Q9的栅极与场效应管Q10的栅极相连并作为电桥驱动电路7的第三个控制输入端，记为端口CtrlV_in，与输出自动控制电路6的端口CtrlV-out相连。The structure of thebridge driver circuit 7 is shown in FIG. 9 : the voltage input terminal VCC of the bridge driver U16 and one end of the capacitor C13 are connected to the power supply VDD, the other end of the capacitor C13 and the COM terminal of the bridge driver U16 are grounded, and the bridge The high-level input terminal HIN of the driver U16 is respectively connected with the drain of the FET Q9 and the low-level input terminal LIN of the bridge driver U17, and is used as the first control input terminal of thebridge driving circuit 7, which is denoted as a port. TsV_in1 is connected to the port TsV_out1 of the control sequence generation circuit 8, the VB terminal of the bridge driver U16 is respectively connected to the cathode of the diode D6 and one end of the capacitor C15, the VS terminal of the bridge driver U16 is respectively connected to the other end of the capacitor C15 and one end of the resistor R33 connected to the bridge driver circuit 7 and used as the second output terminal of the bridge driver circuit 7, denoted as port Drv_out2, connected to the port Drv_in2 of the energy emission circuit 3, the high-level output terminal HO of the bridge driver U16 is connected to one end of the resistor R32, the resistor R32 The other end is connected to the other end of the resistor R33 and used as the first output end of the bridge drive circuit 7, denoted as port Drv_out1, connected to the port Drv_in1 of the energy emission circuit 3, the anode of the diode D6 is connected to one end of the resistor R31, The other end of the resistor R31 is connected to the power supply VDD, the low-level output end LO of the bridge driver U16 is connected to one end of the resistor R34, and the other end of the resistor R34 is used as the third output end of the bridge drive circuit 7, denoted as port Drv_out3, and The port Drv_in3 of the energy transmitting circuit 3 is connected; the voltage input terminal VCC of the bridge driver U17 and one end of the capacitor C14 are connected to the power supply VDD, the other end of the capacitor C14 and the COM terminal of the bridge driver U17 are grounded, and the high level input of the bridge driver U17 The terminal HIN is respectively connected with the drain of the field effect transistor Q10 and the low-level input terminal LIN of the bridge driver U16, and is used as the second control input terminal of the bridge driver circuit 7, which is denoted as port TsV_in2, and is connected with the control sequence generation circuit. 8 is connected to the port TsV_out2, the VB terminal of the bridge driver U17 is connected to the cathode of the diode D7 and one end of the capacitor C16 respectively, the VS terminal of the bridge driver U17 is connected to the other end of the capacitor C16 and one end of the resistor R36 respectively, and is used as a bridge driver The fifth output terminal ofcircuit 7, denoted as port Drv_out5, is connected to port Drv_in5 ofenergy emission circuit 3, the high-level output terminal HO of bridge driver U17 is connected to one end of resistor R37, and the other end of resistor R37 is connected to resistor R36. The other end is connected and used as the fourth output end of thebridge drive circuit 7, denoted as port Drv_out4, connected to the port Drv_in4 of theenergy emission circuit 3, the anode of the diode D7 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the power supply VDD, the low-level output terminal LO of the bridge driver U17 is connected to one end of the resistor R35, and the The other end is used as the sixth output end of thebridge drive circuit 7, which is denoted as port Drv_out6, which is connected to the port Drv_in6 of theenergy emission circuit 3; the source of the FET Q9 and the source of the FET Q10 are grounded, and the FET The gate of Q9 is connected to the gate of the field effect transistor Q10 and serves as the third control input terminal of thebridge driving circuit 7 , denoted as port CtrlV_in, and connected to the port CtrlV-out of the outputautomatic control circuit 6 .
电桥驱动电路7利用MOS管驱动芯片U16、U17将控制时序发生电路8输出的PWM信号提升至可驱动MOS管的级别，用于驱动能量发射电路3中Q3、Q4、Q5、Q6构成的MOS管电桥。Thebridge drive circuit 7 uses the MOS transistor drive chips U16 and U17 to increase the PWM signal output by the controlsequence generation circuit 8 to the level that can drive the MOS transistor, which is used to drive the MOS composed of Q3, Q4, Q5, and Q6 in theenergy emission circuit 3. Tube bridge.
实施例10控制时序发生电路Embodiment 10 Control sequence generating circuit
所述的控制时序发生电路8的结构如图10所示：555定时器U27的接地端GND接地并分别与电容C17一端、电容C18一端以及电容C19一端相连，电容C18的另一端与555定时器U27的控制端CVOLT相连，555定时器U27的触发输入端TRIG分别与555定时器U27的阈值端THR、R40一端以及C17的另一端相连，R40的另一端分别与R39一端以及555定时器U27的放电端DIS相连，R39的另一端分别与555定时器U27的复位端RST以及电压输入端+VCC相连并接电源VDD；555定时器U27的输出端OUT分别与反相器25.6的输入端以及反相器26.5的输入端相连，反相器26.5的输出端作为控制时序发生电路8的第一个控制输出端，记为端口TsV_out1，与电桥驱动电路7相连；反相器25.6的输出端与电阻R41一端相连，电阻R41的另一端分别与电容C19的另一端以及反相器U20.6的输入端相连，反相器U20.6的输出端与D触发器U18.1的时钟信号端Cp相连，D触发器U18.1的预置端Sd分别与电容C20一端、电阻R42一端以及二极管D8的阳极相连，电容C20的另一端分别与D触发器U18.1的触发信号端D以及D触发器U18.1的清零端Cd相连，电阻R42的另一端分别与二极管D8的阴极以及D触发器U18.1的反相位输出端Q非相连，D触发器U18.1的同相位输出端Q与反相器19.3的输入端相连，反相器U19.3的输出端作为控制时序发生电路8的第二个控制输出端，记为端口TsV_out2,与电桥驱动电路7相连。The structure of the controlsequence generation circuit 8 is shown in Figure 10: the ground terminal GND of the 555 timer U27 is grounded and connected to one end of the capacitor C17, one end of the capacitor C18 and one end of the capacitor C19, and the other end of the capacitor C18 is connected to the 555 timer. The control terminal CVOLT of U27 is connected to the control terminal CVOLT, the trigger input terminal TRIG of the 555 timer U27 is respectively connected to the threshold terminal THR of the 555 timer U27, one terminal of R40 and the other terminal of C17, and the other terminal of R40 is respectively connected to one terminal of R39 and the other terminal of the 555 timer U27. The discharge terminal DIS is connected, and the other end of R39 is connected to the reset terminal RST of the 555 timer U27 and the voltage input terminal +VCC and is connected to the power supply VDD; the output terminal OUT of the 555 timer U27 is respectively connected to the input terminal of the inverter 25.6 and the inverter. The input end of the inverter 26.5 is connected, and the output end of the inverter 26.5 is used as the first control output end of the controlsequence generation circuit 8, which is denoted as port TsV_out1, and is connected to thebridge drive circuit 7; the output end of the inverter 25.6 is connected to the One end of the resistor R41 is connected, and the other end of the resistor R41 is connected to the other end of the capacitor C19 and the input end of the inverter U20.6 respectively. The output end of the inverter U20.6 is connected to the clock signal end Cp of the D flip-flop U18.1 connected, the preset terminal Sd of D flip-flop U18.1 is respectively connected with one end of capacitor C20, one end of resistor R42 and the anode of diode D8, and the other end of capacitor C20 is respectively connected with the trigger signal terminals D and D trigger of D flip-flop U18.1 The zero-clearing terminal Cd of the device U18.1 is connected, the other end of the resistor R42 is not connected to the cathode of the diode D8 and the inverse output terminal Q of the D flip-flop U18.1 respectively, and the in-phase output terminal of the D flip-flop U18.1 is not connected. Q is connected to the input end of the inverter 19.3, and the output end of the inverter U19.3 is used as the second control output end of the controlsequence generation circuit 8, denoted as port TsV_out2, and is connected to thebridge drive circuit 7.
控制时序发生电路8利用555定时器和D触发器产生两组相反且带“死区”(用于保护后面所驱动的场效应管)的PWM信号，通过电桥驱动电路7提升功率后用于控制每个输出通道中的能量发射电桥3以产生高频振荡信号。The controlsequence generation circuit 8 uses the 555 timer and the D flip-flop to generate two sets of opposite PWM signals with "dead zone" (used to protect the field effect transistors driven later), which are used to increase the power through thebridge drive circuit 7. The energy-transmittingbridge 3 in each output channel is controlled to generate a high-frequency oscillating signal.
实施例11基准电压电路Embodiment 11 Reference Voltage Circuit
所述的基准电压电路9的结构如图11所示：基准电压源U24的输入端IN与电容C21一端相连并接电源VDD，基准电压源U24的NR端与电容C22一端相连，基准电压源U24的接地端GND分别与电容C21的另一端、电容C22的另一端、电容C23一端以及电阻R43一端相连并接地，电容C23的另一端分别与基准电压源U24的输出端OUT、基准电压源U24的TRIM端、基准电压源U24的I.C./3端以及运算放大器U21.1的同相输入端相连，运算放大器U21.1的反相输入端分别与电阻R43的另一端、电容C24一端以及电阻R44一端相连，电容C24的另一端分别与运算放大器U21.1的输出端、可变电阻W3一端、可变电阻W4一端以及电阻R44的另一端相连，可变电阻W3的活动触点与运算放大器U22.2的同相输入端相连，运算放大器U22.2的输出端反馈给反相输入端，并作为基准电压电路9的第一个参考输出端，记为端口Vref_out1,与电压调节电路2的端口Vref_in1相连；可变电阻W4的活动触点与运算放大器U23.1的同相输入端相连，运算放大器U23.1的输出端反馈给反相输入端，并作为基准电压电路9的第二个参考输出端，记为端口Vref_out2,与输出自动控制电路6的端口Vref_in2相连；可变电阻W3的另一端以及可变电阻W4的另一端接地。The structure of thereference voltage circuit 9 is shown in Figure 11: the input terminal IN of the reference voltage source U24 is connected to one end of the capacitor C21 and is connected to the power supply VDD, the NR end of the reference voltage source U24 is connected to one end of the capacitor C22, and the reference voltage source U24 The ground terminal GND is respectively connected to the other end of the capacitor C21, the other end of the capacitor C22, one end of the capacitor C23 and one end of the resistor R43 and is connected to the ground, and the other end of the capacitor C23 is respectively connected with the output terminal OUT of the reference voltage source U24, the output terminal of the reference voltage source U24 The TRIM terminal, the I.C./3 terminal of the reference voltage source U24 and the non-inverting input terminal of the operational amplifier U21.1 are connected, and the inverting input terminal of the operational amplifier U21.1 is respectively connected to the other terminal of the resistor R43, one terminal of the capacitor C24 and one terminal of the resistor R44. , the other end of the capacitor C24 is respectively connected with the output end of the operational amplifier U21.1, one end of the variable resistor W3, one end of the variable resistor W4 and the other end of the resistor R44, and the movable contact of the variable resistor W3 is connected with the operational amplifier U22.2 The non-inverting input terminal of 2 is connected, and the output terminal of the operational amplifier U22.2 is fed back to the inverting input terminal, and is used as the first reference output terminal of thereference voltage circuit 9, denoted as port Vref_out1, and connected with the port Vref_in1 of thevoltage regulating circuit 2; The movable contact of the variable resistor W4 is connected to the non-inverting input terminal of the operational amplifier U23.1, and the output terminal of the operational amplifier U23.1 is fed back to the inverting input terminal, and is used as the second reference output terminal of thereference voltage circuit 9. It is the port Vref_out2, which is connected to the port Vref_in2 of the outputautomatic control circuit 6; the other end of the variable resistor W3 and the other end of the variable resistor W4 are grounded.
基准电压电路9产生两组可调节大小的基准电压Vref-out1、Vref-out2用于为每个输出通道中的输出自动控制电路6和电压调节电路2提供参考电压。Thereference voltage circuit 9 generates two sets of adjustable reference voltages Vref-out1 and Vref-out2 for providing reference voltages for the outputautomatic control circuit 6 and thevoltage adjustment circuit 2 in each output channel.
