CN111324063A - Acquisition processing device for chip DTU and execution method thereof - Google Patents
Acquisition processing device for chip DTU and execution method thereofDownload PDFInfo
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及电力设备技术领域，尤其涉及一种用于芯片化DTU的采集处理装置及其执行方法。The present invention relates to the technical field of electric power equipment, and in particular, to a collection and processing device for chip-based DTU and an execution method thereof.
背景技术Background technique
目前，配电自动化系统中主要有FTU(馈线自动化终端)，TTU(配变终端)，DTU(站所终端)等配网终端。DTU作为配电自动化系统中非常重要的一个终端设备，对电网运行的状态监测，故障定位，故障隔离，故障恢复等起到非常重要的作用。传统DTU通常具备线路电压、电流监测，开关信号采集与控制，过电压、过电流等就地保护功能，但对电压、电流信号采集的频率、精度要求以及数据处理能力要求不高。At present, the distribution automation system mainly includes FTU (feeder automation terminal), TTU (distribution transformer terminal), DTU (station terminal) and other distribution network terminals. As a very important terminal equipment in the distribution automation system, DTU plays a very important role in state monitoring, fault location, fault isolation, and fault recovery of power grid operation. Traditional DTUs usually have on-site protection functions such as line voltage and current monitoring, switching signal acquisition and control, and overvoltage and overcurrent, but they do not require high frequency, accuracy, and data processing capabilities for voltage and current signal acquisition.
随着社会经济发展，用户对供电可靠性要求越来越高，配电网自动化运维能力要求相应提高，对多通道电压、电流数据采样的速度、精度要求越来越高，传统DTU的功能、性能均难以满足电力业务的发展，整体能力瓶颈已经出现，需要采用新技术解决数据采样的问题。With the development of society and economy, users have higher and higher requirements for power supply reliability, the requirements for automatic operation and maintenance capabilities of distribution networks are correspondingly improved, and the speed and accuracy of multi-channel voltage and current data sampling are getting higher and higher. , performance are difficult to meet the development of power business, the overall capacity bottleneck has emerged, need to adopt new technology to solve the problem of data sampling.
发明内容SUMMARY OF THE INVENTION
本发明实施例的目的是提供一种用于芯片化DTU的采集处理装置及其执行方法，能提高数据采样速率以及数据处理能力，满足数据采样的高频率和高精度的需求。The purpose of the embodiments of the present invention is to provide a collection and processing device for a chip DTU and an execution method thereof, which can improve the data sampling rate and data processing capability, and meet the requirements of high frequency and high precision of data sampling.
为实现上述目的，本发明一实施例提供了一种用于芯片化DTU的采集处理装置，所述装置包括至少一个AD芯片、FPGA单元、第一ARM处理器和第二ARM处理器；其中，To achieve the above object, an embodiment of the present invention provides a collection and processing device for a DTU in chips, the device includes at least one AD chip, an FPGA unit, a first ARM processor and a second ARM processor; wherein,
所述AD芯片，用于与所述FPGA单元的第一输入/输出端连接，以进行数据采集并发送给所述FPGA单元；The AD chip is used to connect with the first input/output end of the FPGA unit to collect data and send it to the FPGA unit;
所述FPGA单元，内设控制模块和存储模块，用于通过所述控制模块控制所述AD芯片进行数据采集和通过所述存储模块将接收到的数据进行存储；The FPGA unit has a built-in control module and a storage module, and is used for controlling the AD chip to perform data collection through the control module and storing the received data through the storage module;
所述第一ARM处理器，用于与所述FPGA单元的第二输入/输出端连接，以从所述FPGA单元中读取数据并进行处理；the first ARM processor, for connecting with the second input/output end of the FPGA unit, to read data from the FPGA unit and process it;
所述第二ARM处理器，用于与所述第一ARM处理器连接，以与所述第一ARM处理器进行数据交互和对数据进行处理。The second ARM processor is configured to be connected to the first ARM processor to perform data interaction and data processing with the first ARM processor.
本发明另一实施例提供了一种用于芯片化DTU的采集处理装置的执行方法，所述方法包括以下步骤：Another embodiment of the present invention provides a method for executing a device for collecting and processing a DTU in a chip, and the method includes the following steps:
AD芯片进行数据采集并发送给FPGA单元；The AD chip collects data and sends it to the FPGA unit;
所述FPGA单元将接收到的数据进行存储，以供第一ARM处理器读取；The FPGA unit stores the received data for the first ARM processor to read;
第一ARM处理器与所述FPGA单元中进行数据交互并对数据进行处理；The first ARM processor performs data interaction with the FPGA unit and processes the data;
第二ARM处理器与所述第一ARM处理器进行数据交互并对数据进行处理。The second ARM processor interacts with the first ARM processor and processes the data.
优选地，所述AD芯片进行数据采集并发送给FPGA单元，具体包括；Preferably, the AD chip collects data and sends it to the FPGA unit, specifically including;
所述AD芯片对输入的数据进行采集；The AD chip collects the input data;
所述FPGA单元通过内设的控制模块对所述AD芯片采集的数据进行预处理；The FPGA unit preprocesses the data collected by the AD chip through a built-in control module;
所述FPGA单元控制所述AD芯片将预处理后的数据发送给所述FPGA单元。The FPGA unit controls the AD chip to send the preprocessed data to the FPGA unit.
优选地，所述FPGA单元将接收到的数据进行存储，以供第一ARM处理器读取，具体包括：Preferably, the FPGA unit stores the received data for the first ARM processor to read, specifically including:
当所述FPGA单元接收到所述AD芯片发送过来的数据时，所述FPGA单元能通过内设的存储模块将接收到的数据存储在一个块随机存储器中，第一ARM处理器能从所述块随机存储器读取到相关的数据。When the FPGA unit receives the data sent from the AD chip, the FPGA unit can store the received data in a block random access memory through a built-in storage module, and the first ARM processor can The relevant data is read from the block random access memory.
优选地，所述FPGA单元在将接收到的数据存储在一个块随机存储器中之前，还包括：Preferably, before storing the received data in a block random access memory, the FPGA unit further comprises:
所述FPGA单元判断所述AD芯片的数据采集是否完成；The FPGA unit judges whether the data acquisition of the AD chip is completed;
若完成，则执行存储步骤；若未完成，则控制所述AD芯片继续进行数据采集。If completed, the storage step is performed; if not, the AD chip is controlled to continue data collection.
优选地，所述第一ARM处理器与所述FPGA单元中进行数据交互并对数据进行处理，具体包括：Preferably, the first ARM processor interacts with and processes data in the FPGA unit, specifically including:
所述第一ARM处理器通过采样数据处理程序获取所述FPGA单元中存储的采样数据；The first ARM processor obtains the sampled data stored in the FPGA unit through a sampled data processing program;
所述FPGA单元通过中断触发向所述第一ARM处理器发送输入开关量；The FPGA unit sends an input switch quantity to the first ARM processor through interrupt triggering;
所述第一ARM处理器根据所述第二ARM处理器发送的信号类型，向所述FPGA单元设置AD频率以及对所述AD芯片进行初始化配置。The first ARM processor sets the AD frequency to the FPGA unit and performs initial configuration on the AD chip according to the signal type sent by the second ARM processor.
优选地，所述第二ARM处理器与所述第一ARM处理器进行数据交互并对数据进行处理，具体包括：Preferably, the second ARM processor interacts and processes data with the first ARM processor, specifically including:
所述第二ARM处理器通过中断触发向所述第一ARM处理器发送PL中断的中断处理程序，以使所述第一ARM处理器设置所述AD频率以及对所述AD芯片进行初始化配置；The second ARM processor triggers an interrupt handler that sends a PL interrupt to the first ARM processor, so that the first ARM processor sets the AD frequency and initializes the AD chip;
所述第一ARM处理器将接收到的所述输入开关量通过中断触发所述第二ARM处理器来处理；The first ARM processor triggers the second ARM processor to process the received input switch quantity through an interrupt;
所述第一ARM处理器将获取到的所述采样数据通过中断触发所述第二ARM处理器来处理。The first ARM processor triggers the second ARM processor to process the acquired sample data through an interrupt.
与现有技术相比，本发明实施例所提供的一种用于芯片化DTU的采集处理装置及其执行方法，利用AD芯片、FPGA单元和两个ARM处理器替代传统的DTU，通过芯片直接控制AD采样以及对AD数据处理，以解决传统DTU无法实现高速、高精度数据同步采集的问题，能有效提高数据的采集速率和处理能力，满足数据采样的高频率和高精度的需求。Compared with the prior art, a collection and processing device for chip-based DTU and an execution method thereof provided by the embodiment of the present invention use an AD chip, an FPGA unit and two ARM processors to replace the traditional DTU, and directly through the chip Control AD sampling and AD data processing to solve the problem that traditional DTU cannot achieve high-speed and high-precision data synchronous acquisition, can effectively improve the data acquisition rate and processing capacity, and meet the high frequency and high precision requirements of data sampling.
附图说明Description of drawings
图1是本发明一实施例提供的一种用于芯片化DTU的采集处理装置的示意图；FIG. 1 is a schematic diagram of a collection and processing device for a chip-based DTU provided by an embodiment of the present invention;
图2是本发明一实施例提供的一种用于芯片化DTU的采集处理装置的执行方法的流程示意图；FIG. 2 is a schematic flowchart of an execution method of a collection and processing device for a chip-based DTU provided by an embodiment of the present invention;
图3是本发明一实施例提供的一种控制模块的状态流程示意图；3 is a schematic state flow diagram of a control module provided by an embodiment of the present invention;
图4是本发明一实施例提供的一种存储模块的状态流程示意图；FIG. 4 is a schematic state flow diagram of a storage module according to an embodiment of the present invention;
图5是本发明一实施例提供的FPGA单元、第一ARM处理器和第二ARM处理器三者之间的数据交互的示意图。FIG. 5 is a schematic diagram of data interaction among an FPGA unit, a first ARM processor, and a second ARM processor according to an embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
参见图1，是本发明实施例1提供的一种用于芯片化DTU的采集处理装置的示意图，所述装置包括至少一个AD芯片、FPGA单元、第一ARM处理器和第二ARM处理器；其中，Referring to FIG. 1, it is a schematic diagram of a collection and processing device for a DTU in a chip provided by Embodiment 1 of the present invention, and the device includes at least one AD chip, an FPGA unit, a first ARM processor and a second ARM processor; in,
所述AD芯片，用于与所述FPGA单元的第一输入/输出端连接，以进行数据采集并发送给所述FPGA单元；The AD chip is used to connect with the first input/output end of the FPGA unit to collect data and send it to the FPGA unit;
所述FPGA单元，内设控制模块和存储模块，用于通过所述控制模块控制所述AD芯片进行数据采集和通过所述存储模块将接收到的数据进行存储；The FPGA unit has a built-in control module and a storage module, and is used for controlling the AD chip to perform data collection through the control module and storing the received data through the storage module;
所述第一ARM处理器，用于与所述FPGA单元的第二输入/输出端连接，以从所述FPGA单元中读取数据并进行处理；the first ARM processor, for connecting with the second input/output end of the FPGA unit, to read data from the FPGA unit and process it;
所述第二ARM处理器，用于与所述第一ARM处理器连接，以与所述第一ARM处理器进行数据交互和对数据进行处理。The second ARM processor is configured to be connected to the first ARM processor to perform data interaction and data processing with the first ARM processor.
具体地，用于芯片化DTU的采集处理装置包括至少一个AD芯片、FPGA单元、第一ARM处理器和第二ARM处理器，该装置整体基于Xilinx的Zynq平台进行设计。其中，Specifically, the acquisition and processing device for the chip-based DTU includes at least one AD chip, an FPGA unit, a first ARM processor and a second ARM processor, and the device is designed based on the Zynq platform of Xilinx as a whole. in,
AD芯片，用于与FPGA单元的第一输入/输出端连接，以进行数据采集并发送给FPGA单元。一般地，AD芯片为AD7606或者AD7616，AD芯片的数量为一个或两个。每一个AD芯片对应采集一种频率的数据，多个AD芯片还能实现采样数据分频采集，满足采样数据的高频率需求。The AD chip is used for connecting with the first input/output end of the FPGA unit to collect data and send it to the FPGA unit. Generally, the AD chip is AD7606 or AD7616, and the number of AD chips is one or two. Each AD chip collects data of one frequency correspondingly, and multiple AD chips can also realize frequency division collection of sampled data to meet the high-frequency requirements of sampled data.
FPGA单元(现场可编程逻辑门阵列)，内设控制模块和存储模块，用于通过控制模块控制AD芯片进行数据采集和通过存储模块将接收到的数据进行存储。因为高速高精度的AD芯片功能在FPGA当中还无法实现，所以需要外挂高性能的AD芯片，在FPGA单元内部设置一个控制模块以控制AD芯片进行数据采集，达到高速AD采样的目的。The FPGA unit (Field Programmable Logic Gate Array) has a built-in control module and a storage module, which are used to control the AD chip to perform data acquisition through the control module and store the received data through the storage module. Because the function of high-speed and high-precision AD chip cannot be realized in FPGA, it is necessary to plug in a high-performance AD chip, and set a control module inside the FPGA unit to control the AD chip for data acquisition, so as to achieve the purpose of high-speed AD sampling.
第一ARM处理器，用于与FPGA单元的第二输入/输出端连接，以从FPGA单元中读取数据并进行处理。其中，第一ARM处理器包括第一CPU(以下用“CPU1”简述)，能与FPGA单元进行数据交互，实现数据实时高速计算的目的。一般地，第一ARM处理器处理实时数据。The first ARM processor is used for connecting with the second input/output terminal of the FPGA unit to read and process data from the FPGA unit. The first ARM processor includes a first CPU (hereinafter referred to as "CPU1"), which can perform data interaction with the FPGA unit to realize the purpose of real-time high-speed data calculation. Typically, the first ARM processor handles real-time data.
第二ARM处理器，用于与第一ARM处理器连接，以与第一ARM处理器进行数据交互和对数据进行处理。一般地，第二ARM处理器处理非实时数据，如UART串行接口传输数据、业务协议传输数据、文件系统操作等等。其中，第二ARM处理器包括第二CPU(以下用“CPU2”简述)。FPGA单元与第一ARM处理器、第二ARM处理器的双核架构实现高速AD采样与实时计算的技术架构，FPGA与双核CPU的交互逻辑，实现资源高效利用。The second ARM processor is configured to be connected to the first ARM processor to perform data interaction and data processing with the first ARM processor. Generally, the second ARM processor processes non-real-time data, such as UART serial interface transmission data, service protocol transmission data, file system operations, and the like. Wherein, the second ARM processor includes a second CPU (hereinafter briefly described as "CPU2"). The dual-core architecture of the FPGA unit, the first ARM processor and the second ARM processor realizes the technical architecture of high-speed AD sampling and real-time computing, and the interaction logic between the FPGA and the dual-core CPU realizes the efficient use of resources.
本发明实施例1通过提供一种用于芯片化DTU的采集处理装置，通过用AD芯片、FPGA单元和两个ARM处理器替代传统的DTU，以解决传统DTU无法实现高速、高精度数据同步采集的问题，能有效提高数据的采集速率和处理能力，满足数据采样的高频率和高精度的需求。Embodiment 1 of the present invention solves the problem that traditional DTUs cannot achieve high-speed and high-precision data synchronous acquisition by providing a collection and processing device for chip-based DTUs and replacing traditional DTUs with AD chips, FPGA units and two ARM processors. It can effectively improve the data collection rate and processing capacity, and meet the high frequency and high precision requirements of data sampling.
参见图2，是本发明实施例2提供的一种用于芯片化DTU的采集处理装置的执行方法的流程示意图，所述方法包括步骤S1至步骤S4：Referring to FIG. 2 , it is a schematic flowchart of an execution method of a collection and processing device for a chip DTU provided by Embodiment 2 of the present invention, and the method includes steps S1 to S4:
S1、AD芯片进行数据采集并发送给FPGA单元；S1, AD chip collects data and sends it to the FPGA unit;
S2、所述FPGA单元将接收到的数据进行存储，以供第一ARM处理器读取；S2, the FPGA unit stores the received data for the first ARM processor to read;
S3、第一ARM处理器与所述FPGA单元中进行数据交互并对数据进行处理；S3, the first ARM processor performs data interaction with the FPGA unit and processes the data;
S4、第二ARM处理器与所述第一ARM处理器进行数据交互并对数据进行处理。S4. The second ARM processor interacts with the first ARM processor and processes the data.
具体地，当系统上电后，需要采集的信号从AD芯片的输入端输入，AD芯片进行数据采集并发送给FPGA单元。Specifically, when the system is powered on, the signal to be collected is input from the input end of the AD chip, and the AD chip collects data and sends it to the FPGA unit.
当AD芯片的数据采集完成后，FPGA单元就将接收到的数据进行存储，以供第一ARM处理器读取。After the data collection of the AD chip is completed, the FPGA unit stores the received data for the first ARM processor to read.
第一ARM处理器与FPGA单元中进行数据交互并对数据进行处理。当第一ARM处理器的第一输入/输出端与FPGA单元的第二输入/输出端连接后，第一ARM处理器与FPGA单元能进行数据交互，方便数据的处理和计算，提高数据处理速率。The first ARM processor exchanges data with the FPGA unit and processes the data. After the first input/output terminal of the first ARM processor is connected with the second input/output terminal of the FPGA unit, the first ARM processor and the FPGA unit can perform data interaction, which facilitates data processing and calculation and improves the data processing rate. .
第二ARM处理器与第一ARM处理器进行数据交互并对数据进行处理。同样地，当第二ARM处理器的输入/输出端与第一ARM处理器的第二输入/输出端连接后，第二ARM处理器就能与第一ARM处理器进行数据交互，并且通过第一ARM处理器与FPGA单元建立通讯，实现数据交互，达到资源高效利用。The second ARM processor interacts with the first ARM processor and processes the data. Similarly, after the input/output terminal of the second ARM processor is connected with the second input/output terminal of the first ARM processor, the second ARM processor can perform data interaction with the first ARM processor, and An ARM processor establishes communication with the FPGA unit, realizes data interaction, and achieves efficient utilization of resources.
作为上述方案的改进，所述AD芯片进行数据采集并发送给FPGA单元，具体包括；As an improvement of the above scheme, the AD chip collects data and sends it to the FPGA unit, specifically including;
所述AD芯片对输入的数据进行采集；The AD chip collects the input data;
所述FPGA单元通过内设的控制模块对所述AD芯片采集的数据进行预处理；The FPGA unit preprocesses the data collected by the AD chip through a built-in control module;
所述FPGA单元控制所述AD芯片将预处理后的数据发送给所述FPGA单元。The FPGA unit controls the AD chip to send the preprocessed data to the FPGA unit.
具体地，AD芯片对输入的数据进行采集，输入的数据即为需要采集的信号。优选地，AD芯片为AD7606。Specifically, the AD chip collects the input data, and the input data is the signal to be collected. Preferably, the AD chip is AD7606.
FPGA单元通过内设的控制模块对AD芯片采集的数据进行预处理。也就是说，根据AD7606的操作时序要求，在FPGA中设计一个对串行模式下AD7606控制的控制模块，通过FPGA先对AD7606的数据进行预处理。其中，将AD7606替换成AD7616，处理过程也是类似的。AD7606为单芯片8个通道，AD7616为单芯片16通道，可以根据需要将AD芯片替换成多个AD7606和多个AD7616扩展的方式，以适应更复杂的数据处理。The FPGA unit preprocesses the data collected by the AD chip through the built-in control module. That is to say, according to the operation sequence requirement of AD7606, a control module is designed in FPGA to control AD7606 in serial mode, and the data of AD7606 is preprocessed through FPGA. Among them, replace AD7606 with AD7616, the processing process is also similar. AD7606 is a single chip with 8 channels, AD7616 is a single chip with 16 channels, AD chips can be replaced with multiple AD7606s and multiple AD7616 expansions as needed to adapt to more complex data processing.
FPGA单元控制AD芯片将预处理后的数据发送给FPGA单元。The FPGA unit controls the AD chip to send the preprocessed data to the FPGA unit.
为了进一步说明FPGA单元通过控制模块对AD芯片的控制流程，该实施例还提供一种控制模块的状态流程示意图，具体参见图3。由图3可知，控制模块的状态流程为：运行IDLE，获取AD芯片开始采样的使能信号，若使能信号为低电平，则无效，继续回到IDLE；若使能信号为高电平，则有效，获取对AD芯片的转换控制信号，当对AD芯片的转换控制信号为低电平时，判断AD芯片的忙信号，当AD芯片的忙信号为高电平时，继续判断AD芯片的忙信号；当AD芯片的忙信号为低电平时，判断当AD芯片的转换完成后，其第一个数据准备好的标识的状态，若状态为低电平，则继续判断第一个数据准备好的标识的状态；若状态为高电平，则读取AD芯片的采样数据；发送已完成一次AD的采样操作的标识的状态；判断其他模块从该模块读取数据完成通过的数据标识的状态，当状态为低电平，则继续判断该数据标识的状态；当状态为高电平，则回到IDLE。为了更好地理解图3的流程，可参见表1中关于控制模块的信号列表。In order to further illustrate the control flow of the AD chip by the FPGA unit through the control module, this embodiment also provides a state flow diagram of the control module, as shown in FIG. 3 for details. As can be seen from Figure 3, the state process of the control module is: run IDLE, and obtain the enable signal that the AD chip starts sampling. If the enable signal is low, it is invalid and continues to return to IDLE; if the enable signal is high , it is valid, obtain the conversion control signal to the AD chip, when the conversion control signal to the AD chip is low, judge the busy signal of the AD chip, when the busy signal of the AD chip is high, continue to judge the busy signal of the AD chip Signal; when the busy signal of the AD chip is low level, it is judged that after the conversion of the AD chip is completed, the state of its first data ready flag, if the state is low level, continue to judge that the first data is ready. If the status is high, read the sampling data of the AD chip; send the status of the mark that has completed an AD sampling operation; judge the status of the data mark that other modules read data from this module and complete the pass , when the state is low, continue to judge the state of the data identification; when the state is high, return to IDLE. For a better understanding of the flow of FIG. 3 , please refer to Table 1 for a list of signals for the control module.
表1控制模块的信号列表Table 1 Signal list of control module
作为上述方案的改进，所述FPGA单元将接收到的数据进行存储，以供第一ARM处理器读取，具体包括：As an improvement of the above solution, the FPGA unit stores the received data for the first ARM processor to read, specifically including:
当所述FPGA单元接收到所述AD芯片发送过来的数据时，所述FPGA单元能通过内设的存储模块将接收到的数据存储在一个块随机存储器中，第一ARM处理器能从所述块随机存储器读取到相关的数据。When the FPGA unit receives the data sent from the AD chip, the FPGA unit can store the received data in a block random access memory through a built-in storage module, and the first ARM processor can The relevant data is read from the block random access memory.
具体地，当FPGA单元接收到AD芯片发送过来的数据时，FPGA单元能通过内设的存储模块将接收到的数据存储在一个块随机存储器BlockRam中，第一ARM处理器能从块随机存储器BlockRam读取到相关的数据。存储模块又称ad_control_top模块，此模块的作用是把两个AD7606控制器读到的AD采样数据存入一个例化的BlockRam中，上位机可以从BlockRam中读取相关的数据。BlockRam的例化都是以块为单位，所以此功能占用了很少的存储器资源。BlockRam的寄存器分配如表2所示。Specifically, when the FPGA unit receives the data sent by the AD chip, the FPGA unit can store the received data in a block random access memory BlockRam through the built-in storage module, and the first ARM processor can store the received data from the block random access memory BlockRam. Read the relevant data. The storage module is also called the ad_control_top module. The function of this module is to store the AD sampling data read by the two AD7606 controllers into an instantiated BlockRam, and the host computer can read the relevant data from the BlockRam. BlockRam is instantiated in blocks, so this function takes up very little memory resources. The register allocation of BlockRam is shown in Table 2.
表2BlockRam的寄存器分配表Table 2 BlockRam's register allocation table
作为上述方案的改进，所述FPGA单元在将接收到的数据存储在一个块随机存储器中之前，还包括：As an improvement of the above solution, before the FPGA unit stores the received data in a block random access memory, it further includes:
所述FPGA单元判断所述AD芯片的数据采集是否完成；The FPGA unit judges whether the data acquisition of the AD chip is completed;
若完成，则执行存储步骤；若未完成，则控制所述AD芯片继续进行数据采集。If completed, the storage step is performed; if not, the AD chip is controlled to continue data collection.
具体地，FPGA单元判断AD芯片的数据采集是否完成；Specifically, the FPGA unit judges whether the data acquisition of the AD chip is completed;
若完成，则执行存储步骤；若未完成，则控制AD芯片继续进行数据采集。当系统上电后，存储模块即ad_control_top模块就会启动控制模块控制AD芯片进行数据采样，当存储模块识别到AD芯片采样完成后就会对BlockRam中的寄存器进行更新操作。If completed, the storage step is performed; if not, the AD chip is controlled to continue data acquisition. When the system is powered on, the storage module, namely the ad_control_top module, will start the control module to control the AD chip to sample data. When the storage module recognizes that the sampling of the AD chip is completed, it will update the registers in the BlockRam.
为了更了解存储模块的工作流程，本实施例提供一种存储模块的状态流程示意图，具体参见图4。由图4可知，存储模块的状态流程为：运行IDLE，读取频率基数，发送AD采样信号，当采样信号为高电平时，判断AD采样是否完成，若未完成，则继续等待判断AD采样是否完成；若已完成，则依次读取每一个通道的采样数据并存储到BlockRam中；当全部存储完毕后，发送数据读取完成标识，此时数据读取完成标识的状态为高电平，并往地址为0X8的BlockRam中写入读取数据完成标识字符0X5E。In order to better understand the work flow of the storage module, this embodiment provides a schematic diagram of the state flow of the storage module, as shown in FIG. 4 for details. As can be seen from Figure 4, the state process of the storage module is: run IDLE, read the frequency base, send AD sampling signal, when the sampling signal is high, judge whether AD sampling is completed, if not, continue to wait to judge whether AD sampling is complete. Completed; if completed, read the sampling data of each channel in turn and store them in BlockRam; when all the storage is completed, send the data read completion flag, the status of the data read completion flag is high at this time, and Write the read data completion identification character 0X5E to the BlockRam with the address 0X8.
作为上述方案的改进，所述第一ARM处理器与所述FPGA单元中进行数据交互并对数据进行处理，具体包括：As an improvement of the above solution, the first ARM processor and the FPGA unit perform data interaction and data processing, specifically including:
所述第一ARM处理器通过采样数据处理程序获取所述FPGA单元中存储的采样数据；The first ARM processor obtains the sampled data stored in the FPGA unit through a sampled data processing program;
所述FPGA单元通过中断触发向所述第一ARM处理器发送输入开关量；The FPGA unit sends an input switch quantity to the first ARM processor through interrupt triggering;
所述第一ARM处理器根据所述第二ARM处理器发送的信号类型，向所述FPGA单元设置AD频率以及对所述AD芯片进行初始化配置。The first ARM processor sets the AD frequency to the FPGA unit and performs initial configuration on the AD chip according to the signal type sent by the second ARM processor.
具体地，参见图5，是本发明该实施例提供的FPGA单元、第一ARM处理器和第二ARM处理器三者之间的数据交互的示意图。由图5可知，第一ARM处理器通过采样数据处理程序获取FPGA单元中存储的采样数据，即FPGA单元能将AD采样数据发送给第一ARM处理器，实质是发送给第一ARM处理器中的CPU1。Specifically, referring to FIG. 5 , it is a schematic diagram of data interaction among the FPGA unit, the first ARM processor, and the second ARM processor provided by this embodiment of the present invention. It can be seen from FIG. 5 that the first ARM processor obtains the sampling data stored in the FPGA unit through the sampling data processing program, that is, the FPGA unit can send the AD sampling data to the first ARM processor, which is essentially sent to the first ARM processor. CPU1.
FPGA单元通过中断触发向第一ARM处理器发送输入开关量，此时第一ARM处理器的CPU1执行开关量输入的硬件中断的中断处理程序。The FPGA unit sends the input switch quantity to the first ARM processor through the interrupt trigger, and at this time, the CPU1 of the first ARM processor executes the interrupt processing program of the hardware interrupt of the switch quantity input.
第一ARM处理器根据第二ARM处理器发送的信号类型，向FPGA单元设置AD频率以及对AD芯片进行初始化配置，此时第二ARM处理器的CPU2会向第一ARM处理器的CPU1发送PL中断的中断处理程序。The first ARM processor sets the AD frequency to the FPGA unit and initializes the AD chip according to the signal type sent by the second ARM processor. At this time, the CPU2 of the second ARM processor will send PL to the CPU1 of the first ARM processor. The interrupt handler for the interrupt.
作为上述方案的改进，所述第二ARM处理器与所述第一ARM处理器进行数据交互并对数据进行处理，具体包括：As an improvement of the above solution, the second ARM processor interacts with the first ARM processor and processes the data, specifically including:
所述第二ARM处理器通过中断触发向所述第一ARM处理器发送PL中断的中断处理程序，以使所述第一ARM处理器设置所述AD频率以及对所述AD芯片进行初始化配置；The second ARM processor triggers an interrupt handler that sends a PL interrupt to the first ARM processor, so that the first ARM processor sets the AD frequency and initializes the AD chip;
所述第一ARM处理器将接收到的所述输入开关量通过中断触发所述第二ARM处理器来处理；The first ARM processor triggers the second ARM processor to process the received input switch quantity through an interrupt;
所述第一ARM处理器将获取到的所述采样数据通过中断触发所述第二ARM处理器来处理。The first ARM processor triggers the second ARM processor to process the acquired sample data through an interrupt.
具体地，同样地参见图5，由图5可知，第二ARM处理器通过中断触发向第一ARM处理器发送PL中断的中断处理程序，以使第一ARM处理器设置AD频率以及对AD芯片进行初始化配置。Specifically, referring to FIG. 5 as well, it can be seen from FIG. 5 that the second ARM processor triggers an interrupt handler that sends a PL interrupt to the first ARM processor through an interrupt, so that the first ARM processor can set the AD frequency and the AD chip Perform initial configuration.
第一ARM处理器将接收到的输入开关量通过中断触发第二ARM处理器来处理；第一ARM处理器将获取到的采样数据通过中断触发第二ARM处理器来处理。在这两个处理过程中，实质是CPU1和CPU2在起作用，它们的通讯方式可以这样表达：The first ARM processor triggers the second ARM processor to process the received input switch quantity through an interrupt; the first ARM processor triggers the second ARM processor to process the acquired sample data through an interrupt. In these two processing processes, the essence is that CPU1 and CPU2 are at work, and their communication methods can be expressed as follows:
(1)CPU2通过中断触发CPU1裸机程序处理输出开关量或者设置AD频率；(1) CPU2 triggers CPU1 bare metal program to process output switch quantity or set AD frequency through interrupt;
(2)CPU1接收到的输入开关量通过中断触发CPU2来处理；(2) The input switch quantity received by CPU1 is processed by interrupt triggering CPU2;
(3)CPU1采集到的AD采样数据通过中断触发CPU2来处理。(3) The AD sampling data collected by CPU1 is processed by interrupt triggering CPU2.
其中，CPU1的程序主要功能如下：Among them, the main functions of the program of CPU1 are as follows:
(1)处理CPU2发过来的PL中断的中断处理程序：程序处理的是根据CPU2发过来的类型，输出开关量到硬件或者设置AD频率。(1) Interrupt processing program for processing the PL interrupt sent by CPU2: The program handles outputting the switch value to the hardware or setting the AD frequency according to the type sent by the CPU2.
(2)AD采样数据处理程序：程序处理的是采样AD数据，然后将数据类型设置为3或者4，通过触发PL中断的方式发给CPU2的linux应用程序处理AD采样数据。使用的是双buffer的形式，buffer1存满发给CPU1处理，接着存数据到buffer2。(2) AD sampling data processing program: The program processes the sampling AD data, and then sets the data type to 3 or 4, and sends it to the linux application of CPU2 to process the AD sampling data by triggering the PL interrupt. It uses the form of double buffer, buffer1 is full and sent to CPU1 for processing, and then saves the data to buffer2.
CPU2的程序主要功能如下：1)AD采样的Linux驱动程序；2)AD数据应用层处理算法；3)AD数据读取控制。The main functions of the program of CPU2 are as follows: 1) Linux driver for AD sampling; 2) AD data application layer processing algorithm; 3) AD data read control.
在ARM侧，双核CPU中，CPU2运行Linux操作系统，进行非实时数据处理，CPU1与FPGA紧密结合，完成实时数据处理。为了提高处理效率，CPU2与CPU1之间通过共享内存进行数据交互。CPU1和CPU2共享内存定义如下：On the ARM side, in the dual-core CPU, CPU2 runs the Linux operating system for non-real-time data processing, and CPU1 is closely integrated with FPGA to complete real-time data processing. In order to improve processing efficiency, data interaction is performed between CPU2 and CPU1 through shared memory. CPU1 and CPU2 shared memory is defined as follows:
CPU1和CPU2内存共享的地址范围：0xffff0000～0xffffffff，具体如表3所示。The memory sharing address range of CPU1 and CPU2: 0xffff0000～0xffffffff, as shown in Table 3.
表3CPU1和CPU2共享内存的数据定义Table 3 Data definition of shared memory of CPU1 and CPU2
综上，本发明实施例所提供的一种用于芯片化DTU的采集处理装置及其执行方法，通过用AD芯片、FPGA单元和两个ARM处理器替代传统的DTU，搭建了FPGA+ARM双核架构实现高速AD采样与实时计算的技术架构，还可以控制AD芯片分频采集，灵活配置多种采样频率，满足不同电力系统需求；通过FPGA与双核CPU的交互逻辑，实现资源高效利用。本发明的主要优势有：(1)数据采样频率能够根据业务需要灵活调整，最高可达到16.7Mbps以上的采样能力，同时可以根据CPU的处理能力灵活调整数据采样频率，提高CPU的整体运行效率，降低综合成本；(2)对于高频率、高精度采样数据，采用多级数据预处理方法，实现高实时算法处理计算，提高电力业务运行的效率，降低配电终端的整体成本；(3)终端内的各种算法处理逻辑可实现在线编程，可随时调整数据处理算法，大大提高系统灵活性。To sum up, a collection and processing device for chip-based DTU and an execution method thereof provided by the embodiments of the present invention construct an FPGA+ARM dual-core by replacing the traditional DTU with an AD chip, an FPGA unit and two ARM processors. The architecture realizes the technical architecture of high-speed AD sampling and real-time computing, and can also control the AD chip frequency division acquisition, flexibly configure multiple sampling frequencies to meet the needs of different power systems; through the interaction logic of FPGA and dual-core CPU, efficient use of resources is achieved. The main advantages of the present invention are as follows: (1) the data sampling frequency can be flexibly adjusted according to business needs, and the maximum sampling capacity can reach more than 16.7 Mbps, and at the same time, the data sampling frequency can be flexibly adjusted according to the processing capacity of the CPU, so as to improve the overall operating efficiency of the CPU, Reduce overall cost; (2) For high-frequency, high-precision sampling data, multi-level data preprocessing method is adopted to realize high real-time algorithm processing and calculation, improve the efficiency of power business operation, and reduce the overall cost of power distribution terminals; (3) Terminals All kinds of algorithm processing logic in the system can realize online programming, and the data processing algorithm can be adjusted at any time, which greatly improves the flexibility of the system.
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。The above are the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made, and these improvements and modifications may also be regarded as It is the protection scope of the present invention.
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