CN111293200A - LED high-voltage chip, preparation method thereof and manufacturing method of isolation groove - Google Patents

Abstract

Translated fromChinese

本发明涉及一种LED高压芯片及其制备方法、隔离槽的制作方法。所述隔离槽的制作方法包括：提供包括衬底以及设置于衬底上的发光半导体层的LED芯片主体；在发光半导体层上形成设有贯穿的第一开口的第一阻挡层和设有贯穿的第二开口的第二阻挡层，第一开口的侧边与衬底之间的倾斜角小于第二开口的侧边与衬底之间的倾斜角，且第一开口和第二开口并列设置；刻蚀发光半导体层，形成隔离槽，隔离槽包括第一槽体和第二槽体，第一槽体的侧壁与衬底之间的倾斜角小于第二槽体的侧壁与衬底之间的倾斜角。本发明通过一次刻蚀工艺即可在隔离槽的不同位置实现不同的角度需求，可以节约30％左右的成本。同时，可使LED高压芯片的发光面积增大10％～30％，亮度提升5％左右。

The invention relates to an LED high-voltage chip, a preparation method thereof, and a preparation method of an isolation groove. The manufacturing method of the isolation trench includes: providing an LED chip body including a substrate and a light-emitting semiconductor layer disposed on the substrate; forming a first barrier layer provided with a through first opening on the light-emitting semiconductor layer and providing a through-hole first barrier layer on the light-emitting semiconductor layer. The second barrier layer of the second opening, the inclination angle between the side of the first opening and the substrate is smaller than the inclination angle between the side of the second opening and the substrate, and the first opening and the second opening are arranged side by side ; Etch the light-emitting semiconductor layer to form an isolation groove, the isolation groove includes a first groove body and a second groove body, and the inclination angle between the sidewall of the first groove body and the substrate is smaller than the sidewall of the second groove body and the substrate inclination angle between. The present invention can realize different angle requirements at different positions of the isolation groove through one etching process, and can save about 30% of the cost. At the same time, the light-emitting area of the LED high-voltage chip can be increased by 10% to 30%, and the brightness can be increased by about 5%.

Description

Translated fromChinese

LED高压芯片及其制备方法、隔离槽的制作方法LED high voltage chip and preparation method thereof, and preparation method of isolation groove

技术领域technical field

本发明涉及LED芯片技术领域，特别是涉及LED高压芯片及其制备方法、隔离槽的制作方法。The invention relates to the technical field of LED chips, in particular to an LED high-voltage chip, a preparation method thereof, and a preparation method of an isolation groove.

背景技术Background technique

LED传统芯片的工作电压在3V左右，为了接入220V电压的国家电网，需要增加降压器件，但会产生10％左右的功耗并且增加成本。为了能够直接接入220V电压，传统做法为将几十个LED传统芯片进行串联，但会增加成本。所以，LED高压芯片的设计可以极大的减少成本。The operating voltage of the traditional LED chip is about 3V. In order to connect to the national grid with a voltage of 220V, a step-down device needs to be added, but it will generate about 10% of the power consumption and increase the cost. In order to be able to directly access the 220V voltage, the traditional method is to connect dozens of traditional LED chips in series, but it will increase the cost. Therefore, the design of the LED high-voltage chip can greatly reduce the cost.

在LED高压芯片的制备中，最重要的步骤是将芯片的发光半导体层分割成独立发光半导体单元的方法。而传统方法都是通过刻蚀发光半导体层的GaN层，形成彼此间隔离而共用衬底的独立发光半导体单元，然后在独立发光半导体单元之间通过蒸镀/溅射的方法制备出导电连接层，从而将独立发光半导体单元进行串联。目前，传统的高压芯片为保证串联时的导电连接层不发生断裂，刻蚀角度都会控制在50°以下，但刻蚀角度越小越占用发光面积，所以这道制程平均损失20％左右的发光面积。为减少这种损失，有报道进行了两次刻蚀形成两种刻蚀角度，但刻蚀制程成本高，又重新增加了成本。In the preparation of LED high-voltage chips, the most important step is the method of dividing the light-emitting semiconductor layer of the chip into individual light-emitting semiconductor units. The traditional method is to etch the GaN layer of the light-emitting semiconductor layer to form independent light-emitting semiconductor units that are isolated from each other and share a substrate, and then prepare a conductive connection layer between the independent light-emitting semiconductor units by evaporation/sputtering. , so that the independent light-emitting semiconductor units are connected in series. At present, in order to ensure that the conductive connection layer of traditional high-voltage chips does not break when connected in series, the etching angle is controlled below 50°, but the smaller the etching angle, the more light-emitting area is occupied, so this process loses about 20% of the light on average. area. In order to reduce this loss, it is reported that two etchings are performed to form two etching angles, but the cost of the etching process is high, and the cost is increased again.

发明内容SUMMARY OF THE INVENTION

基于此，有必要针对高压芯片的发光面积与成本问题，提供一种LED高压芯片及其制备方法、隔离槽的制作方法。Based on this, it is necessary to provide an LED high-voltage chip, a method for manufacturing the same, and a method for manufacturing an isolation groove in view of the light-emitting area and cost of the high-voltage chip.

一种LED高压芯片隔离槽的制作方法，包括以下步骤：A manufacturing method of an LED high-voltage chip isolation groove, comprising the following steps:

提供LED芯片主体，所述LED芯片主体包括衬底以及设置于所述衬底上的发光半导体层；An LED chip body is provided, the LED chip body includes a substrate and a light-emitting semiconductor layer disposed on the substrate;

在所述发光半导体层上形成第一阻挡层和第二阻挡层，所述第一阻挡层设有贯穿的第一开口，所述第二阻挡层设有贯穿的第二开口，所述第一开口的侧边与所述衬底之间的倾斜角小于所述第二开口的侧边与所述衬底之间的倾斜角，且所述第一开口和所述第二开口并列设置；A first barrier layer and a second barrier layer are formed on the light emitting semiconductor layer, the first barrier layer is provided with a first opening passing through, the second blocking layer is provided with a second opening passing through, and the first barrier layer The inclination angle between the side edge of the opening and the substrate is smaller than the inclination angle between the side edge of the second opening and the substrate, and the first opening and the second opening are arranged side by side;

刻蚀所述发光半导体层，形成隔离槽，所述隔离槽包括第一槽体和第二槽体，所述第一槽体的侧壁与所述衬底之间的倾斜角小于所述第二槽体的侧壁与所述衬底之间的倾斜角。The light-emitting semiconductor layer is etched to form an isolation trench, the isolation trench includes a first trench body and a second trench body, and the inclination angle between the sidewall of the first trench body and the substrate is smaller than that of the first trench body. The inclination angle between the sidewalls of the two groove bodies and the substrate.

在其中一个实施例中，所述第一开口的侧边包括相对设置的第一侧边a和第二侧边b，所述第一侧边a与所述衬底之间的倾斜角设为α₁′，所述第二侧边b与所述衬底之间的倾斜角设为α₂′，α₁′和α₂′均为20°～50°；及/或In one embodiment, the side of the first opening includes a first side a and a second side b that are oppositely arranged, and the inclination angle between the first side a and the substrate is set to α₁ ′, the inclination angle between the second side b and the substrate is set to α₂ ′, and both α₁ ′ and α₂ ′ are 20°˜50°; and/or

所述第二开口的侧边包括相对设置的第二侧边a和第二侧边b，所述第二侧边a与所述衬底之间的倾斜角设为β₁′，所述第二侧边b与所述衬底之间的倾斜角设为β₂′，β₁′和β₂′均为60°～90°。The side of the second opening includes a second side a and a second side b that are arranged opposite to each other, the inclination angle between the second side a and the substrate is set to β₁ ′, the first The inclination angle between the two sides b and the substrate is set as β₂ ′, and both β₁ ′ and β₂ ′ are 60°˜90°.

在其中一个实施例中，所述第一阻挡层采用第一光刻胶经曝光、显影及烘烤后形成。In one embodiment, the first barrier layer is formed by exposing, developing and baking a first photoresist.

在其中一个实施例中，所述第二阻挡层的材料包括金属、金属氧化物、硅化合物、第二光刻胶中的至少一种。In one embodiment, the material of the second barrier layer includes at least one of metal, metal oxide, silicon compound, and second photoresist.

在其中一个实施例中，所述第二阻挡层的材料包括金属、金属氧化物、硅化合物中的至少一种时，在所述发光半导体层上首先制作形成所述第二阻挡层，再制作形成所述第一阻挡层；In one embodiment, when the material of the second barrier layer includes at least one of metal, metal oxide, and silicon compound, the second barrier layer is first formed on the light-emitting semiconductor layer, and then the second barrier layer is formed. forming the first barrier layer;

所述第二阻挡层的材料为第二光刻胶时，在所述发光半导体层上首先制作形成所述第一阻挡层，再制作形成所述第二阻挡层。When the material of the second barrier layer is a second photoresist, the first barrier layer is first fabricated and formed on the light-emitting semiconductor layer, and then the second barrier layer is fabricated.

在其中一个实施例中，所述第二阻挡层的材料为第二光刻胶时，形成所述第二阻挡层的烘烤温度小于等于形成所述第一阻挡层的烘烤温度。In one embodiment, when the material of the second barrier layer is a second photoresist, the baking temperature for forming the second barrier layer is less than or equal to the baking temperature for forming the first barrier layer.

在其中一个实施例中，所述第一阻挡层和所述第二阻挡层的厚度均为1μm～12μm。In one embodiment, the thicknesses of the first barrier layer and the second barrier layer are both 1 μm˜12 μm.

在其中一个实施例中，所述发光半导体层包括依次设置于所述衬底上的N型半导体层、发光层和P型半导体层，在所述发光半导体层上形成所述第一阻挡层和所述第二阻挡层之前，先刻蚀所述发光半导体层以暴露出部分N型半导体层。In one embodiment, the light-emitting semiconductor layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially disposed on the substrate, and the first barrier layer and the first barrier layer are formed on the light-emitting semiconductor layer. Before the second barrier layer, the light emitting semiconductor layer is etched to expose part of the N-type semiconductor layer.

一种LED高压芯片制备方法，包括以下步骤：A method for preparing an LED high-voltage chip, comprising the following steps:

采用上述任一项所述LED高压芯片隔离槽的制作方法在LED芯片主体上刻蚀出隔离槽，所述隔离槽将发光半导体层隔离成多个发光半导体单元；Using the manufacturing method of the LED high-voltage chip isolation groove described in any one of the above, an isolation groove is etched on the LED chip main body, and the isolation groove isolates the light-emitting semiconductor layer into a plurality of light-emitting semiconductor units;

刻蚀所述第一槽体的任一侧壁，形成自P型半导体层延伸至N型半导体层的缺口；Etching any sidewall of the first groove body to form a gap extending from the P-type semiconductor layer to the N-type semiconductor layer;

在所述第一槽体上形成绝缘层，并暴露出自P型半导体层延伸至N型半导体层的缺口部分；forming an insulating layer on the first groove body, and exposing a gap portion extending from the P-type semiconductor layer to the N-type semiconductor layer;

在所述发光半导体单元的P型半导体层表面形成透明电极；forming a transparent electrode on the surface of the P-type semiconductor layer of the light-emitting semiconductor unit;

在所述绝缘层上形成导电连接层，以使所述透明电极与相邻发光半导体单元的所述缺口处暴露的N型半导体层连接，串联相邻的发光半导体单元。A conductive connection layer is formed on the insulating layer, so that the transparent electrode is connected to the N-type semiconductor layer exposed at the notch of the adjacent light-emitting semiconductor units, and the adjacent light-emitting semiconductor units are connected in series.

一种LED高压芯片，包括衬底、多个设置于所述衬底上的发光半导体单元、以及导电连接层，多个所述发光半导体单元通过隔离槽隔离，所述隔离槽包括第一槽体和第二槽体，其中，An LED high-voltage chip includes a substrate, a plurality of light-emitting semiconductor units disposed on the substrate, and a conductive connection layer, wherein the plurality of light-emitting semiconductor units are isolated by an isolation groove, and the isolation groove includes a first groove body and the second tank body, where,

所述第一槽体包括相对设置的第一侧壁a和第一侧壁b，所述第一侧壁a与所述衬底之间的倾斜角设为α₁，所述第一侧壁b与所述衬底之间的倾斜角设为α₂，α₁和α₂均为20°～50°；所述第二槽体包括相对设置的第二侧壁a和第二侧壁b，所述第二侧壁a与所述衬底之间的倾斜角设为β₁，所述第二侧壁b与所述衬底之间的倾斜角设为β₂，β₁和β₂均为60°～90°，所述导电连接层沿所述第一槽体的侧壁延伸并串联相邻的所述发光半导体单元。The first groove body includes a first side wall a and a first side wall b arranged oppositely, the inclination angle between the first side wall a and the substrate is set to α₁ , and the first side wall is set as α 1 . The inclination angle between b and the substrate is set as α₂ , and α₁ and α₂ are both 20° to 50°; the second groove body includes a second side wall a and a second side wall b arranged oppositely , the inclination angle between the second side wall a and the substrate is set as β₁ , the inclination angle between the second side wall b and the substrate is set as β₂ , β₁ and β₂ Both are 60°˜90°, and the conductive connection layer extends along the sidewall of the first groove body and connects the adjacent light-emitting semiconductor units in series.

本发明在发光半导体层上同时形成第一阻挡层和第二阻挡层，使得进行一次刻蚀工艺即可制作出隔离槽，可以节约30％左右的成本。同时，使制作出的隔离槽的第一槽体和第二槽体的侧壁与衬底实现不同角度的倾斜，在倾斜角度较小的第一槽体上沉积导电连接层实现发光半导体单元的串联，不仅可使LED高压芯片的发光面积增大10％～30％，亮度提升5％左右，而且保证了导电连接层批覆性能，提高可靠性。In the present invention, the first barrier layer and the second barrier layer are simultaneously formed on the light-emitting semiconductor layer, so that the isolation groove can be fabricated by one etching process, and the cost can be saved by about 30%. At the same time, the sidewalls of the first groove body and the second groove body of the produced isolation groove and the substrate are inclined at different angles, and a conductive connection layer is deposited on the first groove body with a smaller inclination angle to realize the light-emitting semiconductor unit. The series connection can not only increase the light-emitting area of the LED high-voltage chip by 10% to 30%, and increase the brightness by about 5%, but also ensure the coating performance of the conductive connection layer and improve the reliability.

附图说明Description of drawings

图1为LED芯片主体的结构示意图；FIG. 1 is a schematic structural diagram of an LED chip main body;

图2为图1的LED芯片主体上形成第一阻挡层和第二阻挡层的结构示意图；FIG. 2 is a schematic structural diagram of forming a first barrier layer and a second barrier layer on the LED chip body of FIG. 1;

图3为LED芯片主体刻蚀出隔离槽的结构示意图；FIG. 3 is a schematic structural diagram of an isolation groove etched from the main body of the LED chip;

图4为图3的俯视图；Fig. 4 is the top view of Fig. 3;

图5为刻蚀LED芯片主体暴露出部分N型半导体层的结构示意图；FIG. 5 is a schematic structural diagram of exposing part of the N-type semiconductor layer by etching the main body of the LED chip;

图6为图5的LED芯片主体上形成第一阻挡层和第二阻挡层的结构示意图；6 is a schematic structural diagram of forming a first barrier layer and a second barrier layer on the LED chip body of FIG. 5;

图7为LED高压芯片的第一槽体的侧壁刻蚀形成缺口后的结构示意图；7 is a schematic structural diagram of the sidewall of the first groove body of the LED high-voltage chip after etching to form a gap;

图8为LED高压芯片沿第一槽体处的剖面图。FIG. 8 is a cross-sectional view of the LED high-voltage chip along the first groove body.

图中：10、衬底；20、发光半导体层；30、第一阻挡层；40、第二阻挡层；50、发光半导体单元；60、第一槽体；70、第二槽体；100、绝缘层；101、导电连接层；102、透明电极；103、绝缘保护层；201、N型半导体层；202、发光层；203、P型半导体层；204、缺口；300、第一开口；301、第一侧边a；302、第一侧边b；400、第二开口；401、第二侧边a；402、第二侧边b；601、第一侧壁a；602、第一侧壁b；701、第二侧壁a；702、第二侧壁b。In the figure: 10, substrate; 20, light emitting semiconductor layer; 30, first barrier layer; 40, second barrier layer; 50, light emitting semiconductor unit; 60, first groove body; 70, second groove body; 100, Insulating layer; 101, conductive connection layer; 102, transparent electrode; 103, insulating protective layer; 201, N-type semiconductor layer; 202, light-emitting layer; 203, P-type semiconductor layer; 204, notch; 300, first opening; 301 , first side a; 302, first side b; 400, second opening; 401, second side a; 402, second side b; 601, first side wall a; 602, first side Wall b; 701, second side wall a; 702, second side wall b.

具体实施方式Detailed ways

以下将对本发明提供的LED高压芯片及其制备方法、隔离槽的制作方法作进一步说明。The following will further describe the LED high-voltage chip provided by the present invention, the preparation method thereof, and the preparation method of the isolation groove.

参见图1～图4，本发明提供的LED高压芯片的制备方法包括以下步骤：Referring to FIG. 1 to FIG. 4 , the preparation method of the LED high-voltage chip provided by the present invention includes the following steps:

S1，提供LED芯片主体，所述LED芯片主体包括衬底10以及设置于所述衬底上的发光半导体层20；S1, providing an LED chip body, the LED chip body comprising asubstrate 10 and a light-emittingsemiconductor layer 20 disposed on the substrate;

S2，在所述发光半导体层20上形成第一阻挡层30和第二阻挡层40，所述第一阻挡层30设有贯穿的第一开口300，所述第二阻挡层40设有贯穿的第二开口400，所述第一开口300的侧边与所述衬底10之间的倾斜角小于所述第二开口400的侧边与所述衬底10之间的倾斜角，且所述第一开口300和所述第二开口400并列设置；S2, forming afirst barrier layer 30 and asecond barrier layer 40 on the lightemitting semiconductor layer 20, thefirst barrier layer 30 is provided with a first opening 300 passing through, and thesecond barrier layer 40 is provided with a penetratingfirst opening 300 For the second opening 400, the inclination angle between the side of the first opening 300 and thesubstrate 10 is smaller than the inclination angle between the side of the second opening 400 and thesubstrate 10, and the The first opening 300 and thesecond opening 400 are arranged side by side;

S3，刻蚀所述发光半导体层20，形成隔离槽，所述隔离槽包括第一槽体60和第二槽体70，所述第一槽体60的侧壁与所述衬底10之间的倾斜角小于所述第二槽体70的侧壁与所述衬底10之间的倾斜角。S3 , etching the light-emittingsemiconductor layer 20 to form an isolation trench, the isolation trench includes afirst trench body 60 and asecond trench body 70 , and between the sidewall of thefirst trench body 60 and thesubstrate 10 The inclination angle is smaller than the inclination angle between the side wall of thesecond groove body 70 and thesubstrate 10 .

具体参见图1，步骤S1中所述发光半导体层20包括依次设置于所述衬底10上的N型半导体层201、发光层202和P型半导体层203。Referring specifically to FIG. 1 , in step S1 , the light-emittingsemiconductor layer 20 includes an N-type semiconductor layer 201 , a light-emitting layer 202 and a P-type semiconductor layer 203 sequentially disposed on thesubstrate 10 .

具体参见图2和图3，步骤S2中所述第一开口300的侧边包括相对设置的第一侧边a301和第一侧边b 302，所述第一侧边a 301与所述衬底10之间的倾斜角设为α₁′，所述第一侧边b 302与所述衬底10之间的倾斜角设为α₂′，α₁′和α₂′均为20°～50°。Referring specifically to FIG. 2 and FIG. 3 , in step S2, the sides of thefirst opening 300 include a first side a301 and afirst side b 302 that are oppositely disposed, and the first side a 301 is connected to the substrate. The inclination angle between 10 is set as α₁ ′, the inclination angle between thefirst side b 302 and thesubstrate 10 is set as α₂ ′, and α₁ ′ and α₂ ′ are both 20°˜50° °.

在刻蚀过程中，所述第一阻挡层30用于保护发光半导体层20，使刻蚀出所述第一槽体60。考虑到刻蚀过程的均匀性和稳定性，刻蚀后，第一槽体60的侧壁与所述衬底10之间的倾斜角与第一阻挡层30的侧边与所述衬底10之间的倾斜角大致相等。而第一槽体60主要用于沉积导电连接层，因此，为保证导电连接层的批覆效果和可靠性，优选的，α₁′和α₂′均为30°～40°。During the etching process, thefirst barrier layer 30 is used to protect the lightemitting semiconductor layer 20 so that thefirst groove body 60 is etched out. Considering the uniformity and stability of the etching process, after etching, the inclination angle between the sidewall of thefirst groove body 60 and thesubstrate 10 and the sidewall of thefirst barrier layer 30 and thesubstrate 10 The inclination angles between are approximately equal. Thefirst groove body 60 is mainly used for depositing the conductive connection layer. Therefore, in order to ensure the coating effect and reliability of the conductive connection layer, preferably, α₁ ′ and α₂ ′ are both 30°˜40°.

进一步的，α₁′＝α₂′，使所述第一侧边a 301和所述第一侧边b 302沿第一开口300的中轴线呈轴对称结构。Further, α₁ ′=α₂ ′, so that the first side a 301 and thefirst side b 302 have an axisymmetric structure along the central axis of thefirst opening 300 .

另外，所述第一侧边a 301和所述第一侧边b 302的最短距离为d₁′，d₁′＞0。In addition, the shortest distance between the first side a 301 and thefirst side b 302 is d₁ ′, and d₁ ′>0.

所述第二开口400的侧边包括相对设置的第二侧边a401和第二侧边b 402，所述第二侧边a 401与所述衬底10之间的倾斜角设为β₁′，所述第二侧边b 402与所述衬底10之间的倾斜角设为β₂′，β₁′和β₂′均为60°～90°。The sides of thesecond opening 400 include a second side a401 and asecond side b 402 that are oppositely arranged, and the inclination angle between the second side a 401 and thesubstrate 10 is set to be β₁ ′ , the inclination angle between thesecond side b 402 and thesubstrate 10 is set as β₂ ′, and both β₁ ′ and β₂ ′ are 60°˜90°.

在刻蚀过程中，所述第二阻挡层40用于保护发光半导体层20，使刻蚀出所述第二槽体70。因刻蚀过程的均匀性和稳定性，刻蚀后，第二槽体70的侧壁与所述衬底10之间的倾斜角与第二阻挡层40的侧边与所述衬底10之间的倾斜角大致相等。而第二槽体70主要用于隔离发光半导体单元50，因此，考虑到发光面积，优选的，β₁′和β₂′均为70°～80°。During the etching process, thesecond barrier layer 40 is used to protect the light emittingsemiconductor layer 20 so that thesecond groove body 70 is etched out. Due to the uniformity and stability of the etching process, after etching, the inclination angle between the sidewall of thesecond groove body 70 and thesubstrate 10 is the same as the distance between the sidewall of thesecond barrier layer 40 and thesubstrate 10 . The inclination angles between them are approximately equal. Thesecond groove body 70 is mainly used to isolate the light-emittingsemiconductor unit 50. Therefore, considering the light-emitting area, preferably, both β₁ ′ and β₂ ′ are 70°˜80°.

进一步的，β₁′＝β₂′，使所述第二侧边a 401和所述第二侧边b 402沿第二开口400的中轴线呈轴对称结构。Further, β₁ ′=β₂ ′, so that the second side a 401 and thesecond side b 402 have an axisymmetric structure along the central axis of thesecond opening 400 .

优选的，所述第一开口300的中轴线与所述第二开口400的中轴线共线。Preferably, the central axis of thefirst opening 300 is collinear with the central axis of thesecond opening 400 .

另外，所述第二侧边a 401和所述第二侧边b 402的最短距离为d₂′，d₂′＞0。In addition, the shortest distance between the second side a 401 and thesecond side b 402 is d₂ ′, and d₂ ′>0.

在刻蚀过程中，发光半导体层20沿垂直衬底10的方向逐渐被刻蚀，且沿平行衬底10的水平方向朝两侧开始刻蚀，以刻蚀出第一槽体60和第二槽体70。随着刻蚀进程，所述第一阻挡层30和所述第二阻挡层40逐渐呈悬空状态。为保证所述第一阻挡层30和所述第二阻挡层40在刻蚀过程中不出现坍塌的现象，优选的，所述第一阻挡层30和所述第二阻挡层40的厚度均为1μm～12μm。During the etching process, the light emittingsemiconductor layer 20 is gradually etched along the direction vertical to thesubstrate 10, and starts to etch toward both sides along the horizontal direction parallel to thesubstrate 10, so as to etch thefirst groove body 60 and thesecond groove body 60.Tank body 70. With the etching process, thefirst barrier layer 30 and thesecond barrier layer 40 are gradually in a suspended state. In order to ensure that thefirst barrier layer 30 and thesecond barrier layer 40 do not collapse during the etching process, preferably, the thicknesses of thefirst barrier layer 30 and thesecond barrier layer 40 are both 1μm～12μm.

具体的，所述第一阻挡层30采用第一光刻胶经曝光、显影及烘烤后形成。所述第一光刻胶要求可以形成上述厚度的胶层且在不同的温度下角度可调。包括Futurrex(美国)的PR1-4000A、Micro Resist(德国)的ma-P 1200、苏州研材微纳科技的SPR220等。Specifically, thefirst barrier layer 30 is formed by exposing, developing and baking a first photoresist. The first photoresist requires that an adhesive layer of the above-mentioned thickness can be formed and the angle can be adjusted at different temperatures. Including PR1-4000A of Futurrex (USA), ma-P 1200 of Micro Resist (Germany), SPR220 of Suzhou Yanmai Micro-nano Technology, etc.

所述第二阻挡层40的材料包括金属、金属氧化物、硅化合物、第二光刻胶中的至少一种。The material of thesecond barrier layer 40 includes at least one of metal, metal oxide, silicon compound, and second photoresist.

其中，所述金属包括Cr、Au、Ti、Pt等，所述金属氧化物包括Al₂O₃、TiO₂、Ti₃O₅等，所述硅化合物包括SiO₂、SiN等，所述第二光刻胶包括PR1-4000A、ma-P 1200、SPR220等。Wherein, the metal includes Cr, Au, Ti, Pt, etc., the metal oxide includes Al₂ O₃ , TiO₂ , Ti₃ O₅ , etc., the silicon compound includes SiO₂ , SiN, etc., the second Photoresists include PR1-4000A, ma-P 1200, SPR220, etc.

当第二阻挡层40的材料为第二光刻胶时，优选第二光刻胶与第一光刻胶为不同种类的光刻胶。从而在制备第二阻挡层40和第一阻挡层30时不会相互影响。When the material of thesecond barrier layer 40 is a second photoresist, preferably, the second photoresist and the first photoresist are different types of photoresists. Therefore, thesecond barrier layer 40 and thefirst barrier layer 30 will not influence each other when preparing thesecond barrier layer 40 .

具体的，第一光刻胶和第二光刻胶的烘烤温度越高，形成的角度越小。因此，当所述第二阻挡层40的材料为第二光刻胶时，在所述发光半导体层20上首先制作形成所述第一阻挡层30，再制作形成所述第二阻挡层40。此时，形成所述第二阻挡层40的烘烤温度小于等于形成所述第一阻挡层30的烘烤温度，使形成第二阻挡层40时既不会损伤第一阻挡层30，使第一阻挡层30的角度不会变小，也可以保证第二阻挡层40的角度。Specifically, the higher the baking temperature of the first photoresist and the second photoresist, the smaller the angle formed. Therefore, when the material of thesecond barrier layer 40 is a second photoresist, thefirst barrier layer 30 is first formed on the light emittingsemiconductor layer 20 , and then thesecond barrier layer 40 is formed. At this time, the baking temperature for forming thesecond barrier layer 40 is less than or equal to the baking temperature for forming thefirst barrier layer 30 , so that thefirst barrier layer 30 is not damaged when thesecond barrier layer 40 is formed, and thefirst barrier layer 30 is formed. The angle of thefirst barrier layer 30 will not become smaller, and the angle of thesecond barrier layer 40 can also be guaranteed.

优选的，形成第一阻挡层30的烘烤温度为80℃～150℃，烘烤时间≥120s。形成第二阻挡层40的烘烤温度为0℃～150℃，且小于形成第一阻挡层30的烘烤温度。Preferably, the baking temperature for forming thefirst barrier layer 30 is 80° C.˜150° C., and the baking time is ≥120 s. The baking temperature for forming thesecond barrier layer 40 is 0° C.˜150° C., which is lower than the baking temperature for forming thefirst barrier layer 30 .

考虑到金属层、金属氧化物层以及硅化合物层的制备过程时间较长(通常>1小时)，温度较高(通常>200℃)，所以，当所述第二阻挡层40的材料为金属、金属氧化物或硅化合物时，为了避免第一阻挡层30长时间在高温的环境下而导致恶化失效，在所述发光半导体层20上首先制作形成所述第二阻挡层40，再制作形成所述第一阻挡层30。Considering that the preparation process of the metal layer, metal oxide layer and silicon compound layer takes a long time (usually >1 hour) and the temperature is higher (usually >200° C.), when the material of thesecond barrier layer 40 is a metal , metal oxide or silicon compound, in order to avoid the deterioration and failure of thefirst barrier layer 30 caused by prolonged exposure to a high temperature environment, thesecond barrier layer 40 is first formed on the light-emittingsemiconductor layer 20, and then thesecond barrier layer 40 is formed. thefirst barrier layer 30 .

进一步的，第一阻挡层30的厚度为4μm～12μm。第二阻挡层40的材料为第二光刻胶时，第二阻挡层40的厚度为4μm～12μm，第二阻挡层40的材料为金属或氧化物时，第二阻挡层40的厚度为1μm～10μm。Further, the thickness of thefirst barrier layer 30 is 4 μm˜12 μm. When the material of thesecond barrier layer 40 is the second photoresist, the thickness of thesecond barrier layer 40 is 4 μm˜12 μm, and when the material of thesecond barrier layer 40 is metal or oxide, the thickness of thesecond barrier layer 40 is 1 μm ~10 μm.

步骤S3中，使用干法刻蚀等常规的刻蚀方法对发光半导体层20进行刻蚀，刻蚀完成后，去除第一阻挡层30和第二阻挡层40，形成隔离槽。In step S3, the light emittingsemiconductor layer 20 is etched by a conventional etching method such as dry etching. After the etching is completed, thefirst barrier layer 30 and thesecond barrier layer 40 are removed to form isolation trenches.

参见图3和图4，所述隔离槽将发光半导体层20隔离成多个相互间隔的发光半导体单元50。Referring to FIGS. 3 and 4 , the isolation trench isolates the light emittingsemiconductor layer 20 into a plurality of light emittingsemiconductor units 50 spaced apart from each other.

具体的，所述隔离槽包括第一槽体60和第二槽体70，所述第一槽体60的侧壁与所述衬底10之间的倾斜角小于所述第二槽体70的侧壁与所述衬底10之间的倾斜角。Specifically, the isolation trench includes afirst trench body 60 and asecond trench body 70 , and the inclination angle between the sidewall of thefirst trench body 60 and thesubstrate 10 is smaller than that of thesecond trench body 70 . The angle of inclination between the sidewall and thesubstrate 10 .

其中，所述第一槽体60包括相对设置的第一侧壁a 601和第一侧壁b 602，所述第一侧壁a 601与所述衬底10之间的倾斜角设为α₁，所述第一侧壁b 602与所述衬底10之间的倾斜角设为α₂，α₁和α₂均为20°～50°。Wherein, thefirst groove body 60 includes a first side wall a 601 and a firstside wall b 602 arranged oppositely, and the inclination angle between the first side wall a 601 and thesubstrate 10 is set to α₁ , the inclination angle between thefirst sidewall b 602 and thesubstrate 10 is set to α₂ , and both α₁ and α₂ are 20°˜50°.

而且，第一槽体60的第一侧壁a 601的结构与第一阻挡层30的第一侧边a301的结构大致相同，第一侧壁b 602的结构与第一侧边b 302的结构大致相同。因此，α₁和α₂也均优选为30°～40°。Moreover, the structure of the first sidewall a 601 of thefirst groove body 60 is substantially the same as the structure of the first side a301 of thefirst barrier layer 30 , and the structure of thefirst sidewall b 602 is the same as the structure of thefirst side b 302 roughly the same. Therefore, both α₁ and α₂ are also preferably 30° to 40°.

进一步的，α₁＝α₂，使所述第一侧壁a 601和所述第一侧壁b 602沿第一槽体60的沿所述隔离槽的延伸方向的中轴线呈轴对称结构。Further, α₁ =α₂ , so that the first side wall a 601 and the firstside wall b 602 have an axisymmetric structure along the central axis of thefirst groove body 60 along the extending direction of the isolation groove.

另外，第一侧壁a 601和所述第一侧壁b 602的最短距离为d₁，d₁＞0且d₁≥d₁′。In addition, the shortest distance between the first side wall a 601 and the firstside wall b 602 is d₁ , d₁ >0 and d₁ ≥ d₁ ′.

所述第二槽体70包括相对设置的第二侧壁a 701和第二侧壁b 702，所述第二侧壁a 701与所述衬底10之间的倾斜角设为β₁，所述第二侧壁b 702与所述衬底10之间的倾斜角设为β₂，β₁和β₂均为60°～90°。Thesecond groove body 70 includes a second side wall a 701 and a secondside wall b 702 arranged oppositely, and the inclination angle between the second side wall a 701 and thesubstrate 10 is set to β₁ , so The inclination angle between the secondside wall b 702 and thesubstrate 10 is set to β₂ , and both β₁ and β₂ are 60°˜90°.

而且，第二槽体70的第二侧壁a 701的结构与第二阻挡层40的第二侧边a 401的结构大致相同，第二侧壁b 702的结构与第二侧边b 402的结构大致相同。因此，β₁和β₂也均优选为70°～80°。Moreover, the structure of the second side wall a 701 of thesecond groove body 70 is substantially the same as the structure of the second side edge a 401 of thesecond barrier layer 40 , and the structure of the secondside wall b 702 is the same as that of the secondside wall b 402 The structure is roughly the same. Therefore, both β₁ and β₂ are also preferably 70° to 80°.

进一步的，β₁＝β₂，使所述第二侧壁a 701和所述第二侧壁b 702沿第二槽体70的沿所述隔离槽的延伸方向的中轴线呈轴对称结构。Further, β₁ =β₂ , so that the second side wall a 701 and the secondside wall b 702 have an axisymmetric structure along the central axis of thesecond groove body 70 along the extending direction of the isolation groove.

优选的，所述第一槽体60沿所述隔离槽的延伸方向的中轴线和所述第二槽体70沿所述隔离槽的延伸方向的中轴线共线，以使隔离槽所占面积较小。Preferably, the central axis of thefirst groove body 60 along the extension direction of the isolation groove and the central axis of thesecond groove body 70 along the extension direction of the isolation groove are collinear, so that the area occupied by the isolation groove is smaller.

另外，所述第二侧壁a 701和所述第二侧壁b 702的最短距离为d₂，d₂＞0，且d₂≥d₂′。In addition, the shortest distance between the second side wall a 701 and the secondside wall b 702 is d₂ , d₂ >0, and d₂ ≥ d₂ ′.

参见图5，在所述发光半导体层20上形成所述第一阻挡层30和所述第二阻挡层40之前，可先刻蚀所述发光半导体层20以暴露出部分N型半导体层201，然后在发光半导体层20上形成第一阻挡层30和第二阻挡层40。Referring to FIG. 5 , before forming thefirst barrier layer 30 and thesecond barrier layer 40 on the light-emittingsemiconductor layer 20 , the light-emittingsemiconductor layer 20 may be etched to expose part of the N-type semiconductor layer 201 , and then Thefirst barrier layer 30 and thesecond barrier layer 40 are formed on the light emittingsemiconductor layer 20 .

参见图6，所述第一阻挡层30中相对设置的第一侧边a 301和第一侧边b 302均延伸至暴露出部分N型半导体层201上，所述第二阻挡层40中相对设置的第二侧边a 401和第二侧边b 402也均延伸至暴露出部分N型半导体层201上。但是，所述第一侧边a 301和所述第一侧边b 302的距离d₁′仍大于0，所述第二侧边a401和所述第二侧边b 402的距离d₂′也仍大于0，从而，仍能够暴露部分N型半导体层201。进而，可以加快步骤S3中的刻蚀速度。Referring to FIG. 6 , the first side a 301 and thefirst side b 302 of thefirst barrier layer 30 that are arranged opposite to each other extend to the exposed part of the N-type semiconductor layer 201 , and the opposite side of thesecond barrier layer 40 The provided second side a 401 and thesecond side b 402 also extend to the exposed part of the N-type semiconductor layer 201 . However, the distance d₁ ′ between the first side a 301 and thefirst side b 302 is still greater than 0, and the distance d₂ ′ between the second side a 401 and thesecond side b 402 is also is still greater than 0, and thus, part of the N-type semiconductor layer 201 can still be exposed. Furthermore, the etching speed in step S3 can be accelerated.

参见图7和图8，本发明还提供一种LED高压芯片的制备方法，包括以下步骤：Referring to FIG. 7 and FIG. 8 , the present invention also provides a method for preparing an LED high-voltage chip, comprising the following steps:

(1)采用上述LED高压芯片隔离槽的制作方法在LED芯片主体上刻蚀出隔离槽，所述隔离槽将发光半导体层隔离成多个发光半导体单元50；(1) using the above-mentioned manufacturing method of the LED high-voltage chip isolation groove to etch an isolation groove on the LED chip body, and the isolation groove isolates the light-emitting semiconductor layer into a plurality of light-emittingsemiconductor units 50;

(2)刻蚀所述第一槽体60的任一侧壁，形成自P型半导体层203延伸至N型半导体层201的缺口204；(2) Etching any sidewall of thefirst groove body 60 to form agap 204 extending from the P-type semiconductor layer 203 to the N-type semiconductor layer 201;

(3)在所述第一槽体60上形成绝缘层100，并暴露出自P型半导体层203延伸至N型半导体层201的缺口204部分；(3) forming the insulatinglayer 100 on thefirst groove body 60, and exposing the part of thegap 204 extending from the P-type semiconductor layer 203 to the N-type semiconductor layer 201;

(4)在所述发光半导体单元50的P型半导体层203表面形成透明电极102；(4) forming atransparent electrode 102 on the surface of the P-type semiconductor layer 203 of the light-emittingsemiconductor unit 50;

(5)在所述绝缘层100上形成导电连接层101，以使所述透明电极102与相邻发光半导体单元50的所述缺口204处暴露的N型半导体层201连接，串联相邻的发光半导体单元50。(5) Aconductive connection layer 101 is formed on the insulatinglayer 100, so that thetransparent electrode 102 is connected to the N-type semiconductor layer 201 exposed at thenotch 204 of the adjacent light-emittingsemiconductor unit 50, and the adjacent light-emittingsemiconductor units 50 are connected inseries Semiconductor unit 50 .

在步骤(5)后，还包括形成绝缘保护层103，得到LED高压芯片；其中，所述绝缘保护层103覆盖所述发光半导体单元50和所述隔离槽表面，将发光半导体单元50、绝缘层100、导电连接层101以及透明电极102均覆盖。After step (5), it also includes forming an insulatingprotective layer 103 to obtain an LED high-voltage chip; wherein, the insulatingprotective layer 103 covers the surface of the light-emittingsemiconductor unit 50 and the isolation groove, and separates the light-emittingsemiconductor unit 50, the insulatinglayer 100 , theconductive connection layer 101 and thetransparent electrode 102 are all covered.

具体的，所述绝缘层的材料包括SiO₂、Si₃N₄、TiO₂、Ti₃O₅等中的至少一种。Specifically, the material of the insulating layer includes at least one of SiO₂ , Si₃ N₄ , TiO₂ , Ti₃ O₅ and the like.

所述透明电极102的材料包括氧化铟锡等。The material of thetransparent electrode 102 includes indium tin oxide and the like.

所述绝缘保护层的材料包括Al₂O₃、SiO₂等中的至少一种。The material of the insulating protection layer includes at least one of Al₂ O₃ , SiO₂ and the like.

参见图7和图8，为本发明提供的一种LED高压芯片，所述LED高压芯片包括衬底10、多个设置于所述衬底10上的发光半导体单元50、以及导电连接层101，多个所述发光半导体单元50通过隔离槽隔离，所述隔离槽包括第一槽体60和第二槽体70。7 and 8, it is an LED high-voltage chip provided by the present invention, the LED high-voltage chip includes asubstrate 10, a plurality of light-emittingsemiconductor units 50 disposed on thesubstrate 10, and aconductive connection layer 101, A plurality of the light emittingsemiconductor units 50 are isolated by isolation trenches, and the isolation trench includes afirst trench body 60 and asecond trench body 70 .

其中，所述第一槽体60包括相对设置的第一侧壁a 601和第一侧壁b 602，所述第一侧壁a 601与所述衬底10之间的倾斜角设为α₁，所述第一侧壁b 602与所述衬底10之间的倾斜角设为α₂，α₁和α₂均为20°～50°；所述第二槽体70包括相对设置的第二侧壁a 701和第二侧壁b 702，所述第二侧壁a 701与所述衬底10之间的倾斜角设为β₁，所述第二侧壁b 702与所述衬底10之间的倾斜角设为β₂，β₁和β₂均为60°～90°，所述导电连接层101沿所述第一槽体60的侧壁延伸并串联相邻的所述发光半导体单元50。Wherein, thefirst groove body 60 includes a first side wall a 601 and a firstside wall b 602 arranged oppositely, and the inclination angle between the first side wall a 601 and thesubstrate 10 is set to α₁ , the inclination angle between the firstside wall b 602 and thesubstrate 10 is set to α₂ , and α₁ and α₂ are both 20° to 50°; Two sidewalls a 701 and asecond sidewall b 702 , the inclination angle between the second sidewall a 701 and thesubstrate 10 is set to β₁ , thesecond sidewall b 702 and the substrate The inclination angle between 10 and 10 is set as β₂ , and β₁ and β₂ are both 60° to 90°. Theconductive connection layer 101 extends along the sidewall of thefirst groove body 60 and connects the adjacent light emitting diodes in series.Semiconductor unit 50 .

具体的，所述发光半导体单元50包括依次层叠设置于所述衬底10的N型半导体层201、发光层202和P型半导体层203，所述第一槽体60的任一侧壁设有自所述P型半导体层203延伸至所述N型半导体层201的缺口204，以暴露部分N型半导体层201，所述P型半导体层203表面设置有透明电极102，所述缺口204处暴露部分的N型半导体层201与相邻所述发光半导体单元50上的透明电极102通过所述导电连接层101连接，以使电流经所述透明电极102流至相邻发光半导体单元50的N型半导体层201。从而，使多个半导体单元50实现串联，形成LED高压芯片。Specifically, the light-emittingsemiconductor unit 50 includes an N-type semiconductor layer 201 , a light-emittinglayer 202 and a P-type semiconductor layer 203 stacked on thesubstrate 10 in sequence, and any sidewall of thefirst groove body 60 is provided with The P-type semiconductor layer 203 extends from the P-type semiconductor layer 203 to thenotch 204 of the N-type semiconductor layer 201 to expose part of the N-type semiconductor layer 201 , the P-type semiconductor layer 203 is provided with atransparent electrode 102 on the surface, and thenotch 204 is exposed Part of the N-type semiconductor layer 201 is connected to thetransparent electrode 102 on the adjacent light-emittingsemiconductor unit 50 through theconductive connection layer 101, so that current flows through thetransparent electrode 102 to the N-type of the adjacent light-emittingsemiconductor unit 50Semiconductor layer 201 . Thus, a plurality ofsemiconductor units 50 are connected in series to form an LED high-voltage chip.

具体的，所述导电连接层101与所述第一槽体60之间设置有绝缘层100，用于隔绝所述导电连接层101与所述第一槽体60接触。从而防止导电连接层101将同一发光半导体单元50的N型半导体层与P型半导体层导通，发生漏电。Specifically, an insulatinglayer 100 is disposed between theconductive connection layer 101 and thefirst groove body 60 to isolate theconductive connection layer 101 from contacting thefirst groove body 60 . Therefore, theconductive connection layer 101 can prevent the N-type semiconductor layer and the P-type semiconductor layer of the same light-emittingsemiconductor unit 50 from being electrically connected, and electric leakage is prevented.

具体的，所述LED高压芯片还包括绝缘保护层103，所述绝缘保护层103覆盖于所述发光半导体单元50和所述隔离槽表面，用于隔绝所述LED高压芯片与空气的接触。Specifically, the LED high-voltage chip further includes an insulatingprotective layer 103, and the insulatingprotective layer 103 covers the surface of the light-emittingsemiconductor unit 50 and the isolation groove for isolating the LED high-voltage chip from contacting the air.

可以理解，所述绝缘保护层103覆盖于所述发光半导体单元50和所述隔离槽表面时，将绝缘层100、导电连接层101以及透明电极102均覆盖。It can be understood that when the insulatingprotection layer 103 covers the surface of the light emittingsemiconductor unit 50 and the isolation trench, the insulatinglayer 100 , theconductive connection layer 101 and thetransparent electrode 102 are all covered.

因此，本发明在发光半导体层上同时形成第一阻挡层和第二阻挡层，使得进行一次刻蚀工艺即可制作出隔离槽，可以节约30％左右的成本。Therefore, in the present invention, the first barrier layer and the second barrier layer are simultaneously formed on the light-emitting semiconductor layer, so that the isolation trench can be fabricated by one etching process, and the cost can be saved by about 30%.

同时，本发明制作出的隔离槽的第一槽体的侧壁、第二槽体的侧壁与衬底实现不同角度的倾斜，在倾斜角度较小的第一槽体上沉积导电连接层实现发光半导体单元的串联，不仅可使LED高压芯片的发光面积增大10％～30％，亮度提升5％左右，而且保证了导电连接层批覆性能，提高可靠性。At the same time, the sidewalls of the first tank body and the sidewalls of the second tank body and the substrate of the isolation trench produced by the present invention are inclined at different angles, and a conductive connection layer is deposited on the first tank body with a smaller inclination angle. The series connection of light-emitting semiconductor units can not only increase the light-emitting area of the LED high-voltage chip by 10% to 30%, and increase the brightness by about 5%, but also ensure the coating performance of the conductive connection layer and improve reliability.

以下，将通过以下具体实施例对所述LED高压芯片及其制备方法、隔离槽的制作方法做进一步的说明。Hereinafter, the LED high-voltage chip, the manufacturing method thereof, and the manufacturing method of the isolation groove will be further described by the following specific embodiments.

实施例1：Example 1:

提供LED芯片主体，包括衬底以及依次设置于衬底上的N型半导体层、发光层和P型半导体层构成的发光半导体层。An LED chip body is provided, which includes a substrate and a light-emitting semiconductor layer consisting of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially arranged on the substrate.

在需要刻蚀出第一槽体的区域，以ma-P 1200为第一光刻胶进行涂胶，胶厚为12μm，进行对版、曝光及显影，然后对第一光刻胶进行在140℃温度下烘烤10分钟，固化得到第一阻挡层。该第一阻挡层设有贯穿的第一开口，第一开口包括沿其中轴线对称的第一侧边a和第一侧边b，第一侧边a和第一侧边b的距离d₁′为3μm，第一侧边a以及第一侧边b与衬底之间的倾斜角α₁′和α₂′均为20°。In the area where the first groove body needs to be etched, use ma-P 1200 as the first photoresist to apply glue, the glue thickness is 12μm, carry out plate registration, exposure and development, and then the first photoresist is processed at 140 Bake for 10 minutes at a temperature of °C, and cure to obtain a first barrier layer. The first barrier layer is provided with a first opening passing through, the first opening includes a first side a and a first side b symmetrical along its axis, and the distance d₁ ′ between the first side a and the first side b is 3 μm, and the inclination angles α₁ ′ and α₂ ′ between the first side a and the first side b and the substrate are both 20°.

在剩余需要刻蚀出第二槽体的区域，以PR1-4000为第二光刻胶进行涂胶，胶厚为10μm，进行对版、曝光及显影，然后对第二光刻胶进行在110℃温度下烘烤10分钟，固化得到第二阻挡层。该第二阻挡层设有贯穿的第二开口，第二开口包括沿其中轴线对称的第二侧边a和第二侧边b，第二侧边a和第二侧边b的距离d₂′为3μm，第二侧边a以及第二侧边b与衬底之间的倾斜角β₁′和β₂′均为60°。其中，第一开口的中轴线和第二开口的中轴线共线。In the remaining area where the second groove body needs to be etched, use PR1-4000 as the second photoresist to apply glue, the glue thickness is 10μm, carry out plate registration, exposure and development, and then carry out the second photoresist at 110 Bake for 10 minutes at a temperature of °C, and cure to obtain a second barrier layer. The second barrier layer is provided with a second opening passing through, the second opening includes a second side a and a second side b symmetrical along the central axis, and the distance d₂ ′ between the second side a and the second side b is 3 μm, and the inclination angles β₁ ′ and β₂ ′ between the second side a and the second side b and the substrate are both 60°. Wherein, the central axis of the first opening and the central axis of the second opening are collinear.

采用干法刻蚀的方法刻蚀发光半导体层，形成包括第一槽体和第二槽体的隔离槽，刻蚀完成后去除第一阻挡层和第二阻挡层。The light-emitting semiconductor layer is etched by dry etching to form an isolation groove including a first groove body and a second groove body, and the first barrier layer and the second barrier layer are removed after the etching is completed.

然后刻蚀第一槽体的第一侧壁a，形成自P型半导体层延伸至N型半导体层的缺口，再依次沉积SiO₂绝缘层，氧化铟锡透明电极，在绝缘层上沉积串联发光半导体单元的导电连接层，以及沉积Al₂O₃绝缘保护层后，得到LED高压芯片。Then the first sidewall a of the first groove body is etched to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer, and then a_SiO2 insulating layer, an indium tin oxide transparent electrode are deposited in sequence, and a tandem light-emitting layer is deposited on the insulating layer. After the conductive connection layer of the semiconductor unit and the Al₂ O₃ insulating protective layer are deposited, the LED high voltage chip is obtained.

该LED高压芯片包括衬底、多个设置于衬底上的发光半导体单元、以及导电连接层，多个发光半导体单元通过隔离槽隔离，隔离槽包括第一槽体和第二槽体。其中，第一槽体包括沿其中轴线轴对称的第一侧壁a和第一侧壁b，第一侧壁a和第一侧壁b的最短距离d₁为3μm，第一侧壁a以及第一侧壁b与衬底之间的倾斜角α₁和α₂均为20°。The LED high-voltage chip includes a substrate, a plurality of light-emitting semiconductor units arranged on the substrate, and a conductive connection layer. The plurality of light-emitting semiconductor units are isolated by an isolation groove, and the isolation groove includes a first groove body and a second groove body. Wherein, the first groove body includes a first side wall a and a first side wall b that are axially symmetric along its axis, the shortest distance d₁ between the first side wall a and the first side wall b is 3 μm, the first side wall a and The inclination angles α₁ and α₂ between the first sidewall b and the substrate are both 20°.

第二槽体包括沿其中轴线对称的第二侧壁a和第二侧壁b，第二侧壁a和第二侧壁b的最短距离d₂为3μm，第二侧壁a以及第二侧壁b与衬底之间的倾斜角β₁和β₂均为60°。其中，第一槽体的中轴线与第二槽体的中轴线共线。The second groove body includes a second side wall a and a second side wall b symmetrical along the center axis, the shortest distance d₂ between the second side wall a and the second side wall b is 3 μm, the second side wall a and the second side wall The inclination angles β₁ and β₂ between the wall b and the substrate are both 60°. Wherein, the central axis of the first groove body is collinear with the central axis of the second groove body.

实施例2：Example 2:

提供LED芯片主体，包括衬底以及依次设置于衬底上的N型半导体层、发光层和P型半导体层构成的发光半导体层。An LED chip body is provided, which includes a substrate and a light-emitting semiconductor layer consisting of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially arranged on the substrate.

采用常规MESA(平台)刻蚀发光半导体层以暴露出部分N型半导体层。The light emitting semiconductor layer is etched using a conventional MESA (platform) to expose part of the N-type semiconductor layer.

在需要刻蚀出第一槽体的区域，以ma-P1200为第一光刻胶进行涂胶，胶厚为10μm，进行对版、曝光及显影，然后对第一光刻胶进行在130℃温度下烘烤10分钟，固化得到第一阻挡层。该第一阻挡层设有贯穿的第一开口，第一开口包括沿其中轴线对称的第一侧边a和第一侧边b，第一侧边a和第一侧边b的距离d₁′为3μm，第一侧边a以及第一侧边b与衬底之间的倾斜角α₁′和α₂′均为30°。In the area where the first groove body needs to be etched, use ma-P1200 as the first photoresist to apply glue, the glue thickness is 10 μm, carry out plate registration, exposure and development, and then carry out the first photoresist at 130 ℃. Bake at the temperature for 10 minutes, and cure to obtain the first barrier layer. The first barrier layer is provided with a first opening passing through, the first opening includes a first side a and a first side b symmetrical along its axis, and the distance d₁ ′ between the first side a and the first side b is 3 μm, and the inclination angles α₁ ′ and α₂ ′ between the first side a and the first side b and the substrate are both 30°.

在剩余需要刻蚀出第二槽体的区域，以PR1-4000A为第二光刻胶进行涂胶，胶厚为8μm，进行对版、曝光及显影，然后对第二光刻胶进行在80℃温度下烘烤分钟，固化得到第二阻挡层。该第二阻挡层设有贯穿的第二开口，第二开口包括沿其中轴线对称的第二侧边a和第二侧边b，第二侧边a和第二侧边b的距离d₂′为3μm，第二侧边a以及第二侧边b与衬底之间的倾斜角β₁′和β₂′均为70°。其中，第一开口的中轴线和第二开口的中轴线共线。In the remaining area where the second groove body needs to be etched, use PR1-4000A as the second photoresist to apply glue, the glue thickness is 8 μm, carry out plate registration, exposure and development, and then carry out the second photoresist at 80 Bake at a temperature of ℃ for one minute, and cure to obtain a second barrier layer. The second barrier layer is provided with a second opening passing through, the second opening includes a second side a and a second side b symmetrical along the central axis, and the distance d₂ ′ between the second side a and the second side b is 3 μm, and the inclination angles β₁ ′ and β₂ ′ between the second side a and the second side b and the substrate are both 70°. Wherein, the central axis of the first opening and the central axis of the second opening are collinear.

采用干法刻蚀的方法刻蚀发光半导体层，形成包括第一槽体和第二槽体的隔离槽，刻蚀完成后去除第一阻挡层和第二阻挡层。The light-emitting semiconductor layer is etched by dry etching to form an isolation groove including a first groove body and a second groove body, and the first barrier layer and the second barrier layer are removed after the etching is completed.

然后刻蚀第一槽体的第一侧壁a，形成自P型半导体层延伸至N型半导体层的缺口，再依次沉积Si₃N₄绝缘层，氧化铟锡透明电极，在绝缘层上沉积串联发光半导体单元的导电连接层，以及沉积SiO₂绝缘保护层后，得到LED高压芯片。Then the first sidewall a of the first groove body is etched to form a gap extending from the P-type semiconductor layer to the N-type semiconductor layer, and then a Si₃ N₄ insulating layer and an indium tin oxide transparent electrode are sequentially deposited on the insulating layer. After connecting the conductive connection layers of the light-emitting semiconductor units in series, and depositing the SiO₂ insulating protective layer, the LED high-voltage chip is obtained.

该LED高压芯片包括衬底、多个设置于衬底上的发光半导体单元、以及导电连接层，多个发光半导体单元通过隔离槽隔离，隔离槽包括第一槽体和第二槽体。其中，第一槽体包括沿其中轴线轴对称的第一侧壁a和第一侧壁b，第一侧壁a和第一侧壁b的最短距离d₁为3μm，第一侧壁a以及第一侧壁b与衬底之间的倾斜角α₁和α₂均为30°。The LED high-voltage chip includes a substrate, a plurality of light-emitting semiconductor units arranged on the substrate, and a conductive connection layer. The plurality of light-emitting semiconductor units are isolated by an isolation groove, and the isolation groove includes a first groove body and a second groove body. Wherein, the first groove body includes a first side wall a and a first side wall b that are axially symmetric along its axis, the shortest distance d₁ between the first side wall a and the first side wall b is 3 μm, the first side wall a and The inclination angles α₁ and α₂ between the first sidewall b and the substrate are both 30°.

第二槽体包括沿其中轴线对称的第二侧壁a和第二侧壁b，第二侧壁a和第二侧壁b的最短距离d₂为3μm，第二侧壁a以及第二侧壁b与衬底之间的倾斜角β₁和β₂均为70°。其中，第一槽体的中轴线与第二槽体的中轴线共线。The second groove body includes a second side wall a and a second side wall b symmetrical along the center axis, the shortest distance d₂ between the second side wall a and the second side wall b is 3 μm, the second side wall a and the second side wall The inclination angles β₁ and β₂ between the wall b and the substrate are both 70°. Wherein, the central axis of the first groove body is collinear with the central axis of the second groove body.

实施例3：Example 3:

提供LED芯片主体，包括衬底以及依次设置于衬底上的N型半导体层、发光层和P型半导体层构成的发光半导体层。An LED chip body is provided, which includes a substrate and a light-emitting semiconductor layer consisting of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially arranged on the substrate.

采用常规MESA(平台)刻蚀发光半导体层以暴露出部分N型半导体层。The light emitting semiconductor layer is etched using a conventional MESA (platform) to expose part of the N-type semiconductor layer.

在需要刻蚀出第二槽体的区域，沉积金属Ti作为第二阻挡层，厚度为4μm。该第二阻挡层设有贯穿的第二开口，第二开口包括相对设置的第二侧边a和第二侧边b，第二侧边a和第二侧边b的距离d₂′为3μm，第二侧边a与衬底之间的倾斜角β₁′为90°，第二侧边b与衬底之间的倾斜角β₂′为90°。In the area where the second groove body needs to be etched, metal Ti is deposited as the second barrier layer with a thickness of 4 μm. The second barrier layer is provided with a second opening passing through, the second opening includes a second side a and a second side b arranged oppositely, and the distance d₂ ′ between the second side a and the second side b is 3 μm , the inclination angle β₁ ′ between the second side a and the substrate is 90°, and the inclination angle β₂ ′ between the second side b and the substrate is 90°.

在需要刻蚀出第一槽体的区域，以ma-P 1200为第一光刻胶进行涂胶，胶厚为8μm，进行对版、曝光及显影，然后对第一光刻胶进行在110℃温度下烘烤20分钟，固化得到第一阻挡层。该第一阻挡层设有贯穿的第一开口，第一开口包括相对设置的第一侧边a和第一侧边b，第一侧边a和第一侧边b的距离d₁′为4μm，第一侧边a与衬底之间的倾斜角α₁′为40°，第一侧边b与衬底之间的倾斜角α₂′为40°。In the area where the first groove body needs to be etched, use ma-P 1200 as the first photoresist to apply glue, the glue thickness is 8 μm, carry out plate registration, exposure and development, and then carry out the first photoresist at 110 Bake at a temperature of ℃ for 20 minutes, and solidify to obtain a first barrier layer. The first barrier layer is provided with a first opening through it, the first opening includes a first side a and a first side b arranged oppositely, and the distance d₁ ′ between the first side a and the first side b is 4 μm , the inclination angle α₁ ' between the first side a and the substrate is 40°, and the inclination angle α₂ ' between the first side b and the substrate is 40°.

采用干法刻蚀的方法刻蚀发光半导体层，形成包括第一槽体和第二槽体的隔离槽，刻蚀完成后去除第一阻挡层和第二阻挡层。The light-emitting semiconductor layer is etched by dry etching to form an isolation groove including a first groove body and a second groove body, and the first barrier layer and the second barrier layer are removed after the etching is completed.

然后刻蚀第一槽体的第一侧壁a，形成自P型半导体层延伸至N型半导体层的缺口，再依次沉积SiO₂绝缘层，氧化铟锡透明电极，在绝缘层上沉积串联发光半导体单元的导电连接层，以及沉积SiO₂绝缘保护层后，得到LED高压芯片。Then the first sidewall a of the first groove body is etched to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer, and then a_SiO2 insulating layer, an indium tin oxide transparent electrode are deposited in sequence, and a tandem light-emitting layer is deposited on the insulating layer. After the conductive connection layer of the semiconductor unit and the SiO₂ insulating protective layer are deposited, the LED high voltage chip is obtained.

该LED高压芯片包括衬底、多个设置于衬底上的发光半导体单元、以及导电连接层，多个发光半导体单元通过隔离槽隔离，隔离槽包括第一槽体和第二槽体。其中，第一槽体包括相对设置的第一侧壁a和第一侧壁b，第一侧壁a和第一侧壁b的最短距离d₁为3μm，第一侧壁a与衬底之间的倾斜角α₁为40°，第一侧壁b与衬底之间的倾斜角α₂为40°。The LED high-voltage chip includes a substrate, a plurality of light-emitting semiconductor units arranged on the substrate, and a conductive connection layer. The plurality of light-emitting semiconductor units are isolated by an isolation groove, and the isolation groove includes a first groove body and a second groove body. Wherein, the first groove body includes a first side wall a and a first side wall b arranged opposite to each other, the shortest distance d₁ between the first side wall a and the first side wall b is 3 μm, and the distance between the first side wall a and the substrate is 3 μm. The inclination angle α₁ between them is 40°, and the inclination angle α₂ between the first sidewall b and the substrate is 40°.

第二槽体包括相对设置的第二侧壁a和第二侧壁b，第二侧壁a和第二侧壁b的最短距离d₂为3μm，第二侧壁a与衬底之间的倾斜角β₁为90°，第二侧壁b与衬底之间的倾斜角β₂为90°。The second groove body includes a second side wall a and a second side wall b arranged opposite to each other, the shortest distance d₂ between the second side wall a and the second side wall b is 3 μm, and the distance between the second side wall a and the substrate is 3 μm. The inclination angle β₁ is 90°, and the inclination angle β₂ between the second sidewall b and the substrate is 90°.

实施例4：Example 4:

提供LED芯片主体，包括衬底以及依次设置于衬底上的N型半导体层、发光层和P型半导体层构成的发光半导体层。An LED chip body is provided, which includes a substrate and a light-emitting semiconductor layer consisting of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially arranged on the substrate.

采用常规MESA(平台)刻蚀发光半导体层以暴露出部分N型半导体层。The light emitting semiconductor layer is etched using a conventional MESA (platform) to expose part of the N-type semiconductor layer.

在需要刻蚀出第二槽体的区域，沉积SiO₂作为第二阻挡层，厚度为4μm。该第二阻挡层设有贯穿的第二开口，第二开口包括相对设置的第二侧边a和第二侧边b，第二侧边a和第二侧边b的距离d₂′为3μm，第二侧边a与衬底之间的倾斜角β₁′为80°，第二侧边b与衬底之间的倾斜角β₂′为80°。In the area where the second groove body needs to be etched, SiO₂ is deposited as a second barrier layer with a thickness of 4 μm. The second barrier layer is provided with a second opening passing through, the second opening includes a second side a and a second side b arranged oppositely, and the distance d₂ ′ between the second side a and the second side b is 3 μm , the inclination angle β₁ ' between the second side a and the substrate is 80°, and the inclination angle β₂ ' between the second side b and the substrate is 80°.

在需要刻蚀出第一槽体的区域，以ma-P 1200为第一光刻胶进行涂胶，胶厚为6μm，进行对版、曝光及显影，然后对第一光刻胶进行在80℃温度下烘烤10分钟，固化得到第一阻挡层。该第一阻挡层设有贯穿的第一开口，第一开口包括相对设置的第一侧边a和第一侧边b，第一侧边a和第一侧边b的距离d₁′为3μm，第一侧边a与衬底之间的倾斜角α₁′为50°，第一侧边b与衬底之间的倾斜角α₂′为50°。In the area where the first groove body needs to be etched, use ma-P 1200 as the first photoresist to apply glue, the glue thickness is 6 μm, carry out plate registration, exposure and development, and then carry out the first photoresist at 80 Bake for 10 minutes at a temperature of °C, and cure to obtain a first barrier layer. The first barrier layer is provided with a through first opening, the first opening includes a first side a and a first side b that are oppositely arranged, and the distance d₁ ′ between the first side a and the first side b is 3 μm , the inclination angle α₁ ' between the first side a and the substrate is 50°, and the inclination angle α₂ ' between the first side b and the substrate is 50°.

采用干法刻蚀的方法刻蚀发光半导体层，形成包括第一槽体和第二槽体的隔离槽，刻蚀完成后去除第一阻挡层和第二阻挡层。The light-emitting semiconductor layer is etched by dry etching to form an isolation groove including a first groove body and a second groove body, and the first barrier layer and the second barrier layer are removed after the etching is completed.

然后刻蚀第一槽体的第一侧壁a，形成自P型半导体层延伸至N型半导体层的缺口，再依次沉积Si₃N₄绝缘层，氧化铟锡透明电极，在绝缘层上沉积串联发光半导体单元的导电连接层，以及沉积SiO₂绝缘保护层后，得到LED高压芯片。Then the first sidewall a of the first groove body is etched to form a gap extending from the P-type semiconductor layer to the N-type semiconductor layer, and then a Si₃ N₄ insulating layer and an indium tin oxide transparent electrode are sequentially deposited on the insulating layer. After connecting the conductive connection layers of the light-emitting semiconductor units in series, and depositing the SiO₂ insulating protective layer, the LED high-voltage chip is obtained.

该LED高压芯片包括衬底、多个设置于衬底上的发光半导体单元、以及导电连接层，多个发光半导体单元通过隔离槽隔离，隔离槽包括第一槽体和第二槽体。其中，第一槽体包括相对设置的第一侧壁a和第一侧壁b，第一侧壁a和第一侧壁b的最短距离d₁为3μm，第一侧壁a与衬底之间的倾斜角α₁为50°，第一侧壁b与衬底之间的倾斜角α₂为50°。The LED high-voltage chip includes a substrate, a plurality of light-emitting semiconductor units arranged on the substrate, and a conductive connection layer. The plurality of light-emitting semiconductor units are isolated by an isolation groove, and the isolation groove includes a first groove body and a second groove body. Wherein, the first groove body includes a first side wall a and a first side wall b arranged opposite to each other, the shortest distance d₁ between the first side wall a and the first side wall b is 3 μm, and the distance between the first side wall a and the substrate is 3 μm. The inclination angle α₁ between them is 50°, and the inclination angle α₂ between the first sidewall b and the substrate is 50°.

第二槽体包括相对设置的第二侧壁a和第二侧壁b，第二侧壁a和第二侧壁b的最短距离d₂为3μm，第二侧壁a与衬底之间的倾斜角β₁为80°，第二侧壁b与衬底之间的倾斜角β₂为80°。The second groove body includes a second side wall a and a second side wall b arranged opposite to each other, the shortest distance d₂ between the second side wall a and the second side wall b is 3 μm, and the distance between the second side wall a and the substrate is 3 μm. The inclination angle β₁ is 80°, and the inclination angle β₂ between the second sidewall b and the substrate is 80°.

实施例5：Example 5:

提供LED芯片主体，包括衬底以及依次设置于衬底上的N型半导体层、发光层和P型半导体层构成的发光半导体层。An LED chip body is provided, which includes a substrate and a light-emitting semiconductor layer consisting of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially arranged on the substrate.

采用常规MESA(平台)刻蚀发光半导体层以暴露出部分N型半导体层。The light emitting semiconductor layer is etched using a conventional MESA (platform) to expose part of the N-type semiconductor layer.

在需要刻蚀出第二槽体的区域，沉积Al₂O₃作为第二阻挡层，厚度为1μm。该第二阻挡层设有贯穿的第二开口，第二开口包括相对设置的第二侧边a和第二侧边b，第二侧边a和第二侧边b的距离d₂′为3μm，第二侧边a与衬底之间的倾斜角β₁′为90°，第二侧边b与衬底之间的倾斜角β₂′为90°。In the region where the second groove body needs to be etched, Al₂ O₃ is deposited as a second barrier layer with a thickness of 1 μm. The second barrier layer is provided with a second opening passing through, the second opening includes a second side a and a second side b arranged oppositely, and the distance d₂ ′ between the second side a and the second side b is 3 μm , the inclination angle β₁ ′ between the second side a and the substrate is 90°, and the inclination angle β₂ ′ between the second side b and the substrate is 90°.

在需要刻蚀出第一槽体的区域，以ma-P 1200为第一光刻胶进行涂胶，胶厚为8μm，进行对版、曝光及显影，然后对第一光刻胶进行在110℃温度下烘烤20分钟，固化得到第一阻挡层。该第一阻挡层设有贯穿的第一开口，第一开口包括相对设置的第一侧边a和第一侧边b，第一侧边a和第一侧边b的距离d₁′为4μm，第一侧边a与衬底之间的倾斜角α₁′为40°，第一侧边b与衬底之间的倾斜角α₂′为38°。In the area where the first groove body needs to be etched, use ma-P 1200 as the first photoresist to apply glue, the glue thickness is 8 μm, carry out plate registration, exposure and development, and then carry out the first photoresist at 110 Bake at a temperature of ℃ for 20 minutes, and solidify to obtain a first barrier layer. The first barrier layer is provided with a first opening through it, the first opening includes a first side a and a first side b arranged oppositely, and the distance d₁ ′ between the first side a and the first side b is 4 μm , the inclination angle α₁ ' between the first side a and the substrate is 40°, and the inclination angle α₂ ' between the first side b and the substrate is 38°.

采用干法刻蚀的方法刻蚀发光半导体层，形成包括第一槽体和第二槽体的隔离槽，刻蚀完成后去除第一阻挡层和第二阻挡层。The light-emitting semiconductor layer is etched by dry etching to form an isolation groove including a first groove body and a second groove body, and the first barrier layer and the second barrier layer are removed after the etching is completed.

然后刻蚀第一槽体的第一侧壁a，形成自P型半导体层延伸至N型半导体层的缺口，再依次沉积SiO₂绝缘层，氧化铟锡透明电极，在绝缘层上沉积串联发光半导体单元的导电连接层，以及沉积SiO₂绝缘保护层后，得到LED高压芯片。Then the first sidewall a of the first groove body is etched to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer, and then a_SiO2 insulating layer, an indium tin oxide transparent electrode are deposited in sequence, and a tandem light-emitting layer is deposited on the insulating layer. After the conductive connection layer of the semiconductor unit and the SiO₂ insulating protective layer are deposited, the LED high voltage chip is obtained.

该LED高压芯片包括衬底、多个设置于衬底上的发光半导体单元、以及导电连接层，多个发光半导体单元通过隔离槽隔离，隔离槽包括第一槽体和第二槽体。其中，第一槽体包括相对设置的第一侧壁a和第一侧壁b，第一侧壁a和第一侧壁b的最短距离d₁为3μm，第一侧壁a与衬底之间的倾斜角α₁为40°，第一侧壁b与衬底之间的倾斜角α₂为38°。The LED high-voltage chip includes a substrate, a plurality of light-emitting semiconductor units arranged on the substrate, and a conductive connection layer. The plurality of light-emitting semiconductor units are isolated by an isolation groove, and the isolation groove includes a first groove body and a second groove body. Wherein, the first groove body includes a first side wall a and a first side wall b arranged opposite to each other, the shortest distance d₁ between the first side wall a and the first side wall b is 3 μm, and the distance between the first side wall a and the substrate is 3 μm. The inclination angle α₁ between them is 40°, and the inclination angle α₂ between the first sidewall b and the substrate is 38°.

第二槽体包括相对设置的第二侧壁a和第二侧壁b，第二侧壁a和第二侧壁b的最短距离d₂为3μm，第二侧壁a与衬底之间的倾斜角β₁为90°，第二侧壁b与衬底之间的倾斜角β₂为90°。The second groove body includes a second side wall a and a second side wall b arranged opposite to each other, the shortest distance d₂ between the second side wall a and the second side wall b is 3 μm, and the distance between the second side wall a and the substrate is 3 μm. The inclination angle β₁ is 90°, and the inclination angle β₂ between the second sidewall b and the substrate is 90°.

以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only represent several embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims (10)

1. A manufacturing method of an LED high-voltage chip isolation groove is characterized by comprising the following steps:

providing an LED chip main body, wherein the LED chip main body comprises a substrate and a light-emitting semiconductor layer arranged on the substrate;

forming a first barrier layer and a second barrier layer on the light-emitting semiconductor layer, wherein the first barrier layer is provided with a first penetrating opening, the second barrier layer is provided with a second penetrating opening, an inclination angle between the side edge of the first opening and the substrate is smaller than an inclination angle between the side edge of the second opening and the substrate, and the first opening and the second opening are arranged in parallel;

and etching the light-emitting semiconductor layer to form an isolation groove, wherein the isolation groove comprises a first groove body and a second groove body, and the inclination angle between the side wall of the first groove body and the substrate is smaller than the inclination angle between the side wall of the second groove body and the substrate.

2. The method for manufacturing the LED high-voltage chip isolation groove according to claim 1, wherein the side of the first opening comprises a first side a and a second side b which are oppositely arranged, and the inclination angle between the first side a and the substrate is set to α₁' the inclination angle between the second side edge b and the substrate is set to α₂′，α₁' and α₂' are all 20 to 50 degrees; and/or

The side of the second opening comprises a second side a and a second side b which are oppositely arranged, and the inclination angle between the second side a and the substrate is set to β₁' the inclination angle between the second side edge b and the substrate is set to β₂′，β₁' and β₂' are all 60-90 degrees.

3. The method for manufacturing the LED high-voltage chip isolation groove according to claim 2, wherein the first blocking layer is formed by exposing, developing and baking a first photoresist.

4. The method of claim 3, wherein the material of the second barrier layer comprises at least one of a metal, a metal oxide, a silicon compound, and a second photoresist.

5. The method for manufacturing the LED high-voltage chip isolation groove according to claim 4, wherein when the material of the second barrier layer comprises at least one of metal, metal oxide and silicon compound, the second barrier layer is firstly manufactured and formed on the light-emitting semiconductor layer, and then the first barrier layer is manufactured and formed;

when the material of the second barrier layer is the second photoresist, the first barrier layer is firstly manufactured and formed on the light-emitting semiconductor layer, and then the second barrier layer is manufactured and formed.

6. The method of claim 5, wherein when the second barrier layer is made of a second photoresist, the baking temperature for forming the second barrier layer is less than or equal to the baking temperature for forming the first barrier layer.

7. The method for manufacturing the LED high-voltage chip isolation groove according to claim 1, wherein the thickness of the first barrier layer and the thickness of the second barrier layer are both 1-12 μm.

8. The manufacturing method of the LED high-voltage chip isolation groove as claimed in claims 1 to 7, wherein the light emitting semiconductor layer comprises an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate, and the light emitting semiconductor layer is etched to expose a part of the N-type semiconductor layer before the first barrier layer and the second barrier layer are formed on the light emitting semiconductor layer.

9. The preparation method of the LED high-voltage chip is characterized by comprising the following steps:

etching an isolation groove on an LED chip main body by adopting the manufacturing method of the LED high-voltage chip isolation groove of any one of claims 1 to 9, wherein the isolation groove isolates a light-emitting semiconductor layer into a plurality of light-emitting semiconductor units;

etching any side wall of the first groove body to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer;

forming an insulating layer on the first groove body, and exposing a gap part extending from the P-type semiconductor layer to the N-type semiconductor layer;

forming a transparent electrode on the surface of the P-type semiconductor layer of the light-emitting semiconductor unit;

and forming a conductive connecting layer on the insulating layer so that the transparent electrode is connected with the N-type semiconductor layer exposed at the gap of the adjacent light-emitting semiconductor unit to connect the adjacent light-emitting semiconductor units in series.

10. An LED high-voltage chip is characterized by comprising a substrate, a plurality of luminous semiconductor units arranged on the substrate and a conductive connecting layer, wherein the luminous semiconductor units are isolated by an isolation groove, the isolation groove comprises a first groove body and a second groove body, wherein,

the first groove body comprises a first side wall a and a first side wall b which are oppositely arranged, and the inclination angle between the first side wall a and the substrate is set to α₁The inclination angle between the first sidewall b and the substrate is set to α₂，α₁And α₂The angle of inclination between the second side wall a and the substrate is β₁The inclination angle between the second sidewall b and the substrate is set to β₂，β₁And β₂The conductive connecting layer extends along the side wall of the first groove body and is connected with the adjacent light-emitting semiconductor units in series.

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