CN111293099A - Semiconductor circuit structure and manufacturing method thereof - Google Patents
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及一种线路结构，尤其涉及一种半导体线路结构及其制作方法。The present invention relates to a circuit structure, in particular to a semiconductor circuit structure and a manufacturing method thereof.
背景技术Background technique
在常见的半导体线路封装制程中，半导体芯片可采用打线接合或覆晶接合等方式电性连接于线路基板，以覆晶接合的电性连接方式为例，其需先在半导体芯片上制作形成凸块，接着，半导体芯片以凸块接合于线路基板的接垫上；此外，为提高芯片线路的布线设计上的弹性，在半导体制程中，亦可在芯片上形成重布线路(RDL)，将芯片原有的接垫通过重布线的方式移到其它适合接合的区域。In a common semiconductor circuit packaging process, the semiconductor chip can be electrically connected to the circuit substrate by wire bonding or flip chip bonding. Taking the electrical connection method of flip chip bonding as an example, it needs to be fabricated on the semiconductor chip first. Then, the semiconductor chip is bonded to the pads of the circuit substrate with bumps; in addition, in order to improve the flexibility of the wiring design of the chip circuit, in the semiconductor process, a redistributed line (RDL) can also be formed on the chip. The original pads of the chip are moved to other areas suitable for bonding by rerouting.
以在半导体芯片上制作形成凸块的步骤为例，其需先在半导体芯片形成图案化光致抗蚀剂层，以局部暴露出凸块下金属层(under bump metallurgy,UBM)，接着，采用电镀的方式形成凸块于凸块下金属层。之后，移除图案化光致抗蚀剂层，并依据线路设计将未与凸块相叠合的凸块下金属层的至少部分蚀刻去除。在蚀刻去除部分凸块下金属层的步骤中，若产生过度蚀刻的情形，则会衍生出底切(undercut)问题，甚至蚀刻到凸块侧壁，从而导致凸块与凸块下金属层接触不良，进而造成半导体元件的可靠度下降。由于制作重布线路(RDL)的方式与制作凸块方式雷同，因此，相同的问题也会出现在制作重布线路(RDL)上。Taking the step of forming bumps on a semiconductor chip as an example, it is necessary to form a patterned photoresist layer on the semiconductor chip to partially expose the under bump metallurgy (UBM), and then, using The bumps are formed on the metal layer under the bumps by electroplating. After that, the patterned photoresist layer is removed, and at least part of the under-bump metal layer that is not overlapped with the bump is etched and removed according to the circuit design. In the step of removing part of the under-bump metal layer by etching, if over-etching occurs, an undercut problem will arise, and even the sidewall of the bump will be etched, so that the bump will be in contact with the under-bump metal layer. Defects, resulting in a decrease in the reliability of the semiconductor element. Since the way of making a redistributed line (RDL) is the same as that of making a bump, the same problem also occurs in making a redistributed line (RDL).
发明内容SUMMARY OF THE INVENTION
本发明提供一种半导体线路结构的制作方法，其能避免产生底切问题。The present invention provides a method for fabricating a semiconductor circuit structure, which can avoid the problem of undercutting.
本发明提供一种半导体线路结构，其具有良好的可靠度。The present invention provides a semiconductor circuit structure with good reliability.
本发明的半导体线路结构的制作方法包括以下步骤。首先，提供半导体基板，其中半导体基板设有凸块下金属层。接着，形成图案化光致抗蚀剂层于凸块下金属层上，其中图案化光致抗蚀剂层形成有开孔，以局部暴露出凸块下金属层。开孔划分为第一孔部与第二孔部，其中第一孔部位于第二孔部与凸块下金属层之间，且第一孔部的孔径大于第二孔部的孔径。接着，形成导电层于第一孔部内，且导电层连接凸块下金属层。接着，形成第一金属层于第二孔部内，且第一金属层连接导电层。接着，形成第二金属层于第二孔部内，且第二金属层连接第一金属层。接着，移除图案化光致抗蚀剂层。接着，局部移除导电层，以形成导电部。之后，局部移除凸块下金属层，以形成与导电部相连接的凸块下金属垫。The fabrication method of the semiconductor circuit structure of the present invention includes the following steps. First, a semiconductor substrate is provided, wherein the semiconductor substrate is provided with an under-bump metal layer. Next, a patterned photoresist layer is formed on the under-bump metal layer, wherein the patterned photoresist layer is formed with openings to partially expose the under-bump metal layer. The opening is divided into a first hole portion and a second hole portion, wherein the first hole portion is located between the second hole portion and the under-bump metal layer, and the diameter of the first hole portion is larger than that of the second hole portion. Next, a conductive layer is formed in the first hole portion, and the conductive layer is connected to the metal layer under the bump. Next, a first metal layer is formed in the second hole portion, and the first metal layer is connected to the conductive layer. Next, a second metal layer is formed in the second hole portion, and the second metal layer is connected to the first metal layer. Next, the patterned photoresist layer is removed. Next, the conductive layer is partially removed to form a conductive portion. Afterwards, the under-bump metal layer is partially removed to form an under-bump metal pad connected to the conductive portion.
在本发明的一实施例中，上述的形成图案化光致抗蚀剂层于凸块下金属层上的步骤包括以下步骤。首先，形成第一光致抗蚀剂层于凸块下金属层上。接着，形成第二光致抗蚀剂层于第一光致抗蚀剂层上。之后，对第一光致抗蚀剂层与第二光致抗蚀剂层进行曝光显影，以在第一光致抗蚀剂层形成第一孔部，并在第二光致抗蚀剂层形成第二孔部。In an embodiment of the present invention, the above-mentioned step of forming the patterned photoresist layer on the under-bump metal layer includes the following steps. First, a first photoresist layer is formed on the under bump metal layer. Next, a second photoresist layer is formed on the first photoresist layer. After that, the first photoresist layer and the second photoresist layer are exposed and developed to form a first hole in the first photoresist layer, and a first hole is formed in the second photoresist layer. A second hole portion is formed.
在本发明的一实施例中，上述的形成所述图案化光致抗蚀剂层于凸块下金属层上的步骤包括以下步骤。首先，形成光致抗蚀剂层于凸块下金属层上。接着，对光致抗蚀剂层进行曝光显影。之后，以在光致抗蚀剂层上形成预留孔，对位于预留孔内的光致抗蚀剂层进行干蚀刻，以局部移除位于预留孔内的光致抗蚀剂层进而形成第一孔部与第二孔部。In an embodiment of the present invention, the above-mentioned step of forming the patterned photoresist layer on the under-bump metal layer includes the following steps. First, a photoresist layer is formed on the under bump metal layer. Next, the photoresist layer is exposed and developed. After that, a reserved hole is formed on the photoresist layer, and the photoresist layer in the reserved hole is dry-etched to partially remove the photoresist layer in the reserved hole and then A first hole portion and a second hole portion are formed.
在本发明的一实施例中，上述的导电层的外径大于第一金属层的外径，通过移除导电层未与第一金属层相重叠的部分，以使制作所得的导电部的外径等于第一金属层的外径。In an embodiment of the present invention, the outer diameter of the conductive layer is larger than the outer diameter of the first metal layer. The diameter is equal to the outer diameter of the first metal layer.
在本发明的一实施例中，上述的第一孔部的孔径自第二孔部朝向半导体基板渐增。In an embodiment of the present invention, the diameter of the first hole portion increases gradually from the second hole portion toward the semiconductor substrate.
在本发明的一实施例中，上述的导电层的外径大于第一金属层的外径，且导电层的外径自第一金属层朝向半导体基板渐增。通过沿着导电层的外轮廓局部移除导电层，以使制作所得的导电部的外径自第一金属层朝向半导体基板渐增，其中导电部具有连接第一金属层的端部，且端部的外径等于第一金属层的外径。In an embodiment of the present invention, the outer diameter of the conductive layer is larger than the outer diameter of the first metal layer, and the outer diameter of the conductive layer gradually increases from the first metal layer toward the semiconductor substrate. By partially removing the conductive layer along the outer contour of the conductive layer, the outer diameter of the fabricated conductive portion gradually increases from the first metal layer toward the semiconductor substrate, wherein the conductive portion has an end portion connected to the first metal layer, and the end portion The outer diameter is equal to the outer diameter of the first metal layer.
在本发明的一实施例中，上述的导电部具有连接凸块下金属层的端部。通过移除凸块下金属层未与端部相重叠的部分以及凸块下金属层邻近端部的外壁面的另一部分，以使制作所得的凸块下金属垫的外径小于端部的外径。In an embodiment of the present invention, the above-mentioned conductive portion has an end portion connected to the under-bump metal layer. By removing the part of the under-bump metal layer that does not overlap with the end and another part of the outer wall surface of the under-bump metal layer adjacent to the end, the outer diameter of the obtained under-bump metal pad is smaller than the outer diameter of the end. path.
在本发明的一实施例中，上述的凸块下金属垫位于导电部在半导体基板上的正投影范围内。In an embodiment of the present invention, the above-mentioned under-bump metal pad is located within the orthographic projection range of the conductive portion on the semiconductor substrate.
本发明的半导体线路结构包括半导体基板、凸块下金属垫、导电部、第一金属层以及第二金属层。凸块下金属垫设置于半导体基板上。导电部设置于凸块下金属垫上，且凸块下金属垫位于导电部与半导体基板之间。第一金属层设置于导电部上，且导电部位于第一金属层与凸块下金属垫之间。第二金属层设置于第一金属层上，且第一金属层位于第二金属层与导电部之间。导电部具有连接第一金属层的第一端部，且第一端部的外径等于第一金属层的外径。The semiconductor circuit structure of the present invention includes a semiconductor substrate, an under-bump metal pad, a conductive portion, a first metal layer and a second metal layer. The under-bump metal pad is disposed on the semiconductor substrate. The conductive portion is disposed on the under-bump metal pad, and the under-bump metal pad is located between the conductive portion and the semiconductor substrate. The first metal layer is disposed on the conductive portion, and the conductive portion is located between the first metal layer and the under-bump metal pad. The second metal layer is disposed on the first metal layer, and the first metal layer is located between the second metal layer and the conductive portion. The conductive part has a first end connected to the first metal layer, and the outer diameter of the first end is equal to the outer diameter of the first metal layer.
在本发明的一实施例中，上述的导电部的外径为等径。In an embodiment of the present invention, the outer diameters of the above-mentioned conductive portions are equal diameters.
在本发明的一实施例中，上述的导电部的外径自第一金属层朝向半导体基板渐增。In an embodiment of the present invention, the outer diameter of the conductive portion is gradually increased from the first metal layer toward the semiconductor substrate.
在本发明的一实施例中，上述的导电部具有连接凸块下金属垫的第二端部，且第二端部的外径大于凸块下金属垫的外径。In an embodiment of the present invention, the conductive portion has a second end portion connected to the under-bump metal pad, and the outer diameter of the second end portion is larger than the outer diameter of the under-bump metal pad.
基于上述，本发明的半导体线路结构的制作方法通过图案化光致抗蚀剂层的开孔设计，能够防止制作导电部(例如导电柱或重布线路)时所可能产生的底切问题，以增加导电部与第一金属层接触面积及导电部与凸块下金属层的接触面积。藉此，制作所得的半导体线路结构得具有良好的可靠度。Based on the above, the fabrication method of the semiconductor circuit structure of the present invention can prevent the undercut problem that may occur during the fabrication of conductive parts (such as conductive pillars or redistribution lines) by designing the openings in the patterned photoresist layer, so as to avoid the problem of undercutting. The contact area between the conductive part and the first metal layer and the contact area between the conductive part and the metal layer under the bump are increased. Thereby, the fabricated semiconductor circuit structure must have good reliability.
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.
附图说明Description of drawings
图1A至图1F是本发明一实施例的半导体线路结构的制作过程的剖面示意图；1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor circuit structure according to an embodiment of the present invention;
图2A至图2G是本发明另一实施例的半导体线路结构的制作过程的剖面示意图；2A to 2G are schematic cross-sectional views of a manufacturing process of a semiconductor circuit structure according to another embodiment of the present invention;
图3是本发明再一实施例的半导体线路结构的剖面示意图。3 is a schematic cross-sectional view of a semiconductor circuit structure according to still another embodiment of the present invention.
附图标记说明Description of reference numerals
10、10a、20：半导体线路结构10, 10a, 20: Semiconductor circuit structure
100、200：半导体基板100, 200: Semiconductor substrate
101、201：接垫101, 201: Pad
102、202：介电层102, 202: Dielectric layer
103、203：表面103, 203: Surface
110、210：凸块下金属层110, 210: Metal layer under bump
112、112a、212：凸块下金属垫112, 112a, 212: under-bump metal pads
120、220：光致抗蚀剂层120, 220: photoresist layer
121：第一光致抗蚀剂层121: First Photoresist Layer
122：第二光致抗蚀剂层122: Second Photoresist Layer
123、223：开孔123, 223: Opening
124、224：第一孔部124, 224: The first hole
125、225：第二孔部125, 225: Second hole
130、230：图案化光致抗蚀剂层130, 230: Patterned photoresist layer
140、240：导电层140, 240: Conductive layer
142、242：导电柱142, 242: Conductive column
142a：重布线路142a: Rerouting
143、243：第一端部143, 243: first end
144、244：第二端部144, 244: second end
150、150a、250：第一金属层150, 150a, 250: the first metal layer
160、160a、260：第二金属层160, 160a, 260: the second metal layer
231：预留孔231: reserved hole
D1、D2、D3、D4：孔径D1, D2, D3, D4: Aperture
d1、d2、d3、d4、d5、d6、d7：外径d1, d2, d3, d4, d5, d6, d7: outer diameter
具体实施方式Detailed ways
图1A至图1F是本发明一实施例的半导体线路结构的制作过程的剖面示意图。请参考图1A，首先，提供半导体基板100，其可为晶圆或芯片，选用上视晶圆级尺寸封装、晶圆级芯片尺寸封装或芯片级尺寸封装而定。在本实施例中，半导体基板100的表面103设有接垫101、介电层102以及凸块下金属层110，接垫101设置于表面103上，而介电层102覆盖表面103但暴露出接垫101的至少部分。凸块下金属层110覆盖介电层102，并与暴露于介电层102外的接垫101相接触。举例来说，凸块下金属层110可为钛/铜叠层，且钛层位于铜层与介电层102之间。特别说明的是，凸块下金属层110的叠层组合不限于上述，在其他实施例中，凸块下金属层可为钛-钨/铬-铜/铜叠层、铬/铬-铜/铜叠层、钛-钨/铜叠层、钛/铜/镍叠层、钛-钨/镍-钒/铜叠层或其他适用者。1A to 1F are schematic cross-sectional views of a fabrication process of a semiconductor circuit structure according to an embodiment of the present invention. Referring to FIG. 1A , first, a
请参考图1B，接着，通过贴合、印刷或涂布等方式形成光致抗蚀剂层120于凸块下金属层110上，且全面覆盖凸块下金属层110。在本实施例中，光致抗蚀剂层120包括第一光致抗蚀剂层121与第二光致抗蚀剂层122，就其制作顺序而论，首先，形成第一光致抗蚀剂层121于凸块下金属层110上，之后，形成第二光致抗蚀剂层122于第一光致抗蚀剂层121上。第一光致抗蚀剂层121位于第二光致抗蚀剂层122与凸块下金属层110之间，其中第一光致抗蚀剂层121与第二光致抗蚀剂层122可同为正光致抗蚀剂，且第一光致抗蚀剂层121的感光剂含量高于第二光致抗蚀剂层122的感光剂含量。举例来说，第一光致抗蚀剂层121的感光剂含量与第二光致抗蚀剂层122的感光剂含量的比率介于1.5到2倍之间。Referring to FIG. 1B , then, a
请参考图1C，接着，对第一光致抗蚀剂层121与第二光致抗蚀剂层122进行曝光显影，本实施例采用同一道光罩(图未示)对第一光致抗蚀剂层121与第二光致抗蚀剂层122进行曝光，因第一光致抗蚀剂层121的感光剂含量高于第二光致抗蚀剂层122的感光剂含量，第一光致抗蚀剂层121受光照处对显影剂的溶解度高于第二光致抗蚀剂层122受光照处对显影剂的溶解度。也就是说，在对曝光后的第一光致抗蚀剂层121与第二光致抗蚀剂层122进行显影时，第一光致抗蚀剂层121受光照处的显影速率较于第一光致抗蚀剂层121受光照处的显影速度为快，使得在第一光致抗蚀剂层121所形成的第一孔部124的孔径D1大于在第二光致抗蚀剂层122所形成的第二孔部125的孔径D2。至此，图案化光致抗蚀剂层130大致完成，且相互连通的第一孔部124与第二孔部125构成开孔123，以局部暴露出凸块下金属层110。Referring to FIG. 1C , then, the
请参考图1D，接着，通过电镀、无电镀、化学气相沉积、物理气相沉积或其他适用的制程形成导电层140于第一孔部124内，其中导电层140连接凸块下金属层110，且填满第一孔部124。接着，通过电镀、无电镀、化学气相沉积、物理气相沉积或其他适用的制程形成第一金属层150于第二孔部125内，其中第一金属层150连接导电层140，且未将第二孔部125填满。接着，通过电镀、无电镀、化学气相沉积、物理气相沉积或其他适用的制程形成第二金属层160于第二孔部125内，并形成于第一金属层150上，以将第二孔部125未被第一金属层150填满的其他区域填满。也就是说，第二孔部125被相连接的第一金属层150与第二金属层160填满，其中第一金属层150位于导电层140与第二金属层160之间，且导电层140、第一金属层150以及第二金属层160可分别为铜层、镍层与金层，但不限于此。Referring to FIG. 1D , then, a
请参考图1E，接着，移除图案化光致抗蚀剂层130，以使导电层140、第一金属层150、第二金属层160以及凸块下金属层110外露。基于开孔123的设计，导电层140的外径d1大于第一金属层150的外径d2，且导电层140具有未与第一金属层150重叠的部分。特别说明的是，导电层140未与第一金属层150相重叠的部分泛指导电层140在平行于表面103的方向上超出于第一金属层150的外壁面的部分。Referring to FIG. 1E , then, the patterned
请同时参考图1E及图1F，接着，蚀刻移除导电层140未与第一金属层150相重叠的部分，以制作得到导电部，在本实施例中，导电部可为导电柱142，且导电柱142的外径d3等于第一金属层150的外径d2。另一方面，导电柱142具有连接第一金属层150的第一端部143，其中导电柱142的外径d3为等径设计，且第一端部143的外径(即外径d3)等于第一金属层150的外径d2。基于将导电柱142的母材(即导电层140)的外径设定为大于第一金属层150的外径，在对母材(即导电层140)进行蚀刻时，仅有母材(即导电层140)未与第一金属层150相重叠的部分会被蚀刻移除，以确保制作所得的导电柱142的外径等于第一金属层150的外径，并使第一端部143完全接触第一金属层150，从而提高导电柱142与第一金属层150的接触面积，避免因底切问题影响到导电柱142与第一金属层150的接合强度。Referring to FIG. 1E and FIG. 1F at the same time, then, the portion of the
之后，局部移除凸块下金属层110，以形成与导电柱142相连接的凸块下金属垫112。进一步来说，导电柱142具有连接凸块下金属层110的第二端部144，其中凸块下金属层110可概分为未与第二端部144相重叠的第一部分以及第二端部144相重叠的第二部分，凸块下金属层110的第一部分泛指凸块下金属层110在平行于表面103的方向上超出于第二端部144的外壁面的区块，且凸块下金属层110的第二部分泛指凸块下金属层110位于第二端部144在半导体基板100上的正投影范围内的另一区块。After that, the under-
在局部移除凸块下金属层110的过程中，凸块下金属层110的第一部分被蚀刻移除，而凸块下金属层110的第二部分邻近第二端部144的外壁面的局部被蚀刻移除，以使制作所得的凸块下金属垫112位于导电柱142在半导体基板100上的正投影范围内，且凸块下金属垫112的外径d4小于第二端部144的外径(即外径d3)。也就是说，在垂直于表面103的方向上，凸块下金属垫112在半导体基板100上的正投影与导电柱142在半导体基板100上的正投影相重叠，且凸块下金属垫112在半导体基板100上的正投影落在导电柱142在半导体基板100上的正投影内。In the process of partially removing the under-
至此，半导体线路结构10的制作已大致完成，除导电柱142与第一金属层150的接触面积与接合强度大幅提高外，导电柱142与凸块下金属垫112的接触面积与接合强度也大幅提高，故半导体线路结构10可具有良好的可靠度。So far, the fabrication of the
请继续参考图1F，半导体线路结构10包括半导体基板100、凸块下金属垫112、导电柱142、第一金属层150以及第二金属层160。凸块下金属垫112设置于半导体基板100上。导电柱142设置于凸块下金属垫112上，且凸块下金属垫112位于导电柱142与半导体基板100之间。第一金属层150设置于导电柱142上，且导电柱142位于第一金属层150与凸块下金属垫112之间。第二金属层160设置于第一金属层150上，且第一金属层150位于第二金属层160与导电柱142之间，其中导电柱142具有连接第一金属层150的第一端部143，且第一端部143的外径(即外径d3)等于第一金属层150的外径d2。Please continue to refer to FIG. 1F , the
特别说明的是，本实施例的半导体线路结构10包括两组凸块下金属垫112、导电柱142、第一金属层150以及第二金属层160的组合，其中一组凸块下金属垫112、导电柱142、第一金属层150以及第二金属层160可为功能凸块，用以传输信号、传输电力或接地，而另一组凸块下金属垫112、导电柱142、第一金属层150以及第二金属层160可为虚拟凸块，用以在后续封装程序中起支撑的效用，但本发明不以此为限。在其他实施例中，凸块下金属垫、导电柱、第一金属层以及第二金属层的组合的组数可视实际需求而增减。Specifically, the
图2A至图2G是本发明另一实施例的半导体线路结构的制作过程的剖面示意图。需说明的是，本实施例的半导体线路结构20及其制程与上一实施例半导体线路结构10及其制程相近，故相同或相似元件使用相同或相似标号，且相同或相似的技术内容可参照上一实施例，下文不重复赘述。2A to 2G are schematic cross-sectional views of a fabrication process of a semiconductor circuit structure according to another embodiment of the present invention. It should be noted that the
请参考图2A，首先，提供半导体基板200。在本实施例中，半导体基板200的表面203设有接垫201、介电层202以及凸块下金属层210，接垫201设置于表面203上，而介电层202覆盖表面203但暴露出接垫201的至少部分。凸块下金属层210覆盖介电层202，并与暴露于介电层202外的接垫201相接触。Referring to FIG. 2A , first, a
请参考图2B，接着，通过贴合、印刷或涂布等方式形成光致抗蚀剂层220于凸块下金属层210上，且全面覆盖凸块下金属层210，其中光致抗蚀剂层220可为正光致抗蚀剂。接着，对光致抗蚀剂层220进行曝光显影，以在光致抗蚀剂层220上形成预留孔231，如图2C所示。接着，对预留孔231内的光致抗蚀剂层220进行干蚀刻制程，例如非等向性蚀刻制程，以局部移除位于预留孔231内的光致抗蚀剂层220，进而形成第一孔部224与第二孔部225，其中第一孔部224位于第二金属层260与凸块下金属层210之间，且第一孔部224的孔径D3大于第二孔部225的孔径D4。Referring to FIG. 2B , then, a
至此，图案化光致抗蚀剂层230大致完成，且相互连通的第一孔部224与第二孔部225构成开孔223，以局部暴露出凸块下金属层210，而第一孔部224的孔径D3自第二孔部225朝向半导体基板200渐增。也就是说，第一孔部224在平行于表面203的方向上具有多个截面，且第一孔部224中越远离第二孔部225的截面的尺寸越大。So far, the patterned
请参照图2E，接着，形成导电层240于第一孔部224内，其中导电层240连接凸块下金属层210，且填满第一孔部224。接着，形成第一金属层250于第二孔部225内，其中第一金属层250连接导电层240，且未将第二孔部225填满。随后，形成第二金属层260于第二孔部225内，并形成于第一金属层250上，以将第二孔部225未被第一金属层250填满的其他区域填满。也就是说，第二孔部225被相连接的第一金属层250与第二金属层260填满，其中第一金属层250位于导电层240与第二金属层260之间。Referring to FIG. 2E , then, a
请参照图2F，接着，移除图案化光致抗蚀剂层230，以使导电层240、第一金属层250、第二金属层260以及凸块下金属层210外露。基于开孔223的设计，导电层240的外径自第一金属层250朝向半导体基板200渐增，且导电层240的外径大于第一金属层250的外径d5。也就是说，导电层240在平行于表面203的方向上具有多个截面，且导电层240中越远离第一金属层250的截面的尺寸越大。另一方面，导电层240具有未与第一金属层250重叠的部分，特别说明的是，导电层240未与第一金属层250相重叠的部分泛指导电层240在平行于表面203的方向上超出于第一金属层250的外壁面的部分。Referring to FIG. 2F , then, the patterned
请同时参照图2F及图2G，接着，沿着导电层240的外轮廓局部蚀刻移除导电层240未与第一金属层250相重叠的部分，以制作得到导电部，在本实施例中，导电部可为导电柱242，且导电柱242的外径自第一金属250层朝向半导体基板200渐增。进一步来说，导电柱242在垂直于表面203的方向上的截面轮廓与导电层240在垂直于表面203的方向上的截面轮廓仍相似，但导电柱242在垂直于表面203的方向上的截面轮廓的尺寸略微缩减。另一方面，导电柱242具有连接第一金属层250的第一端部243，其中第一端部243完全接触第一金属层250，且第一端部243的外径等于第一金属层250的外径d5。如此为之，有助于提高导电柱242与第一金属层250的接触面积，避免因底切问题影响到导电柱242与第一金属层250的接合强度。2F and FIG. 2G at the same time, then, along the outer contour of the
由于导电柱242在垂直于表面203的方向上的截面轮廓与导电层240在垂直于表面203的方向上的截面轮廓仍相似，且导电柱242的最小外径落在第一端部243，因此导电柱242的外径自第一端部243朝向半导体基板200渐增。也就是说，导电柱242在平行于表面203的方向上具有多个截面，且导电柱242中越远离第一金属层250的截面的尺寸越大。Since the cross-sectional profile of the
之后，局部移除凸块下金属层210，以形成与导电柱242相连接的凸块下金属垫212。进一步来说，导电柱242具有连接凸块下金属层210的第二端部244，其中凸块下金属层210可概分为未与第二端部244相重叠的第一部分以及第二端部244相重叠的第二部分，凸块下金属层210的第一部分泛指凸块下金属层210在平行于表面203的方向上超出于第二端部244的外壁面的区块，且凸块下金属层210的第二部分泛指凸块下金属层210位于第二端部244在半导体基板200上的正投影范围内的另一区块。After that, the under-
在局部移除凸块下金属层210的过程中，凸块下金属层210的第一部分被蚀刻移除，而凸块下金属层110的第二部分邻近第二端部244的外壁面的局部被蚀刻移除，以使制作所得的凸块下金属垫212位于导电柱242在半导体基板200上的正投影范围内，且凸块下金属垫212的外径d6小于第二端部244的外径d7。也就是说，在垂直于表面203的方向上，凸块下金属垫212在半导体基板200上的正投影与导电柱242在半导体基板200上的正投影相重叠，且凸块下金属垫212在半导体基板200上的正投影落在导电柱242在半导体基板200上的正投影内。In the process of partially removing the under-
至此，本实施例的半导体线路结构20的制作大致完成，除导电柱242与第一金属层250的接触面积与接合强度大幅提高外，导电柱242与凸块下金属垫212的接触面积与接合强度也大幅提高，故半导体线路结构20可具有良好的可靠度。So far, the fabrication of the
请继续参考图2G，半导体线路结构20包括半导体基板200、凸块下金属垫212、导电柱242、第一金属层250以及第二金属层260。凸块下金属垫212设置于半导体基板200上。导电柱242设置于凸块下金属垫212上，且凸块下金属垫212位于导电柱242与半导体基板200之间。第一金属层250设置于导电柱242上，且导电柱242位于第一金属层250与凸块下金属垫212之间。第二金属层260设置于第一金属层250上，且第一金属层250位于第二金属层260与导电柱242之间，其中导电柱242具有连接第一金属层250的第一端部243，且第一端部243的外径等于第一金属层250的外径d5。Please continue to refer to FIG. 2G , the
特别说明的是，本实施例的半导体线路结构20包括两组凸块下金属垫212、导电柱242、第一金属层250以及第二金属层260的组合，其中一组凸块下金属垫212、导电柱242、第一金属层250以及第二金属层260可为功能凸块，用以传输信号、传输电力或接地，而另一组凸块下金属垫212、导电柱242、第一金属层250以及第二金属层260可为虚拟凸块，用以在后续封装程序中起支撑的效用，但本发明不以此为限。在其他实施例中，凸块下金属垫、导电柱、第一金属层以及第二金属层的组合的组数可视实际需求而增减。Specifically, the
图3是本发明再一实施的半导体线路结构的剖面示意图。需说明的是，本实施例的半导体线路结构10a的结构及其制作方法与上述实施例的半导体线路结构10的结构及其制作方法相近，以下仅就两者的差异作说明。3 is a schematic cross-sectional view of a semiconductor circuit structure according to still another embodiment of the present invention. It should be noted that the structure and fabrication method of the
请参考图3，在本实施例中，导电部可为重布线路142a，其中重布线路142a的相对两端面分别连接凸块下金属垫112a与第一金属层150a，第二金属层160a连接第一金属层150a，且第一金属层150a位于重布线路142a与第二金属层160a之间。进一步来说，参酌半导体线路结构10的制作方法，通过将光致抗蚀剂层的厚度减薄，便能制作得到相应的重布线路142a、第一金属层150a以及第二金属层160a。另一方面，因重布线路142a与第一金属层150a的接触面积与接合强度大幅提高，且重布线路142a与凸块下金属垫112a的接触面积与接合强度也大幅提高，故半导体线路结构10a可具有良好的可靠度。Referring to FIG. 3 , in this embodiment, the conductive portion may be a
综上所述，本发明的半导体线路结构的制作方法通过图案化光致抗蚀剂层的开孔设计，能够防止制作导电部(例如导电柱或重布线路)时所可能产生的底切问题，以增加导电部与第一金属层接触面积及导电部与凸块下金属层的接触面积，并提升导电部与第一金属层的接合强度及导电部与凸块下金属层的接合强度。藉此，制作所得的半导体线路结构得具有良好的可靠度。To sum up, the fabrication method of the semiconductor circuit structure of the present invention can prevent the undercut problem that may occur when fabricating conductive parts (such as conductive pillars or redistribution lines) through the design of the openings in the patterned photoresist layer. to increase the contact area between the conductive part and the first metal layer and the contact area between the conductive part and the under-bump metal layer, and improve the bonding strength between the conductive part and the first metal layer and the bonding strength between the conductive part and the under-bump metal layer. Thereby, the fabricated semiconductor circuit structure must have good reliability.
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the claims.
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