CN111162120A

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Info

Publication number: CN111162120A
Application number: CN201911382949.1A
Authority: CN
Inventors: 殷华湘; 张青竹; 张兆浩
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-05-15
Also published as: WO2021128447A1

Abstract

Translated fromChinese

本发明公开一种存储器件、存储器及其制作方法、电子设备和芯片，涉及存储器技术领域，以延长存储器件数据保存时长，从而提高存储器件的存储能力。所述存储器件包括衬底以及形成在衬底上的负电容晶体管以及与负电容晶体管电连接的电容。所述存储器包括上述技术方案所提的存储器件。本发明提供的存储器件用于电子设备中。

The invention discloses a storage device, a storage device and a manufacturing method thereof, an electronic device and a chip, and relates to the technical field of storage devices, so as to prolong the data storage time of the storage device and improve the storage capacity of the storage device. The memory device includes a substrate and a negative capacitance transistor formed on the substrate and a capacitor electrically connected to the negative capacitance transistor. The memory includes the storage device mentioned in the above technical solution. The memory device provided by the present invention is used in electronic equipment.

Description

Memory device, memory and manufacturing method thereof, electronic equipment and chip

Technical Field

The invention relates to the technical field of memories, in particular to a memory device, a memory, a manufacturing method of the memory device, electronic equipment and a chip.

Background

Dynamic Random Access Memory (DRAM) is one of the most common types of system Memory. The DRAM mainly comprises a memory device and a peripheral circuit, wherein the memory device is a core of the DRAM and is used for storing data.

For a DRAM, the memory device includes a transistor and a capacitor. The transistor is used for controlling data reading and programming of the storage device, and the capacitor is used for storing data. At the same time, the DRAM also periodically refreshes the memory devices to improve the storage capacity of the memory devices. However, periodically refreshing the memory devices does not fundamentally improve the storage capability of the DRAM.

Disclosure of Invention

The invention aims to provide a storage device, a manufacturing method of the storage device, electronic equipment and a chip, so that the data storage time of the storage device is prolonged, and the storage capacity of the storage device is improved.

In order to achieve the above object, the present invention provides a memory device. The memory device includes:

a substrate;

a negative capacitance transistor formed on the substrate and a capacitance electrically connected to the negative capacitance transistor, the negative capacitance transistor for controlling a degree of leakage of the memory device.

Optionally, the negative capacitor transistor includes a gate structure that is a ferroelectric gate stack structure.

Optionally, the negative capacitor transistor includes a gate structure including a gate conductive layer and at least one dielectric layer stacked together, where the at least one dielectric layer is located between the substrate and the gate conductive layer, and at least one of the at least one dielectric layer is a ferroelectric dielectric layer.

Optionally, the negative capacitor transistor is a fin transistor or a buried channel transistor.

Compared with the prior art, the storage device provided by the invention has the advantages that the negative capacitance transistor and the capacitor electrically connected with the negative capacitance transistor are formed on the substrate. The negative capacitance transistor has an ultra-steep sub-threshold swing, a smaller threshold voltage, a faster switching speed and a smaller leakage current, so that the negative capacitance transistor has extremely high grid control capability. Therefore, when the storage device provided by the invention contains the negative capacitance transistor, the storage device has smaller leakage current. When the memory device has smaller leakage current, the data storage duration of the memory device is inversely proportional to the leakage current of the memory device, so that when the negative capacitance transistor is in an off state, the memory device has longer data storage duration, the memory performance of the memory device is improved, the refresh frequency of the memory device can be reduced to a certain extent, and the purpose of reducing power consumption is achieved.

The invention also provides a memory. The memory comprises at least one memory device and peripheral circuits according to the above technical scheme; the peripheral circuit is electrically connected to a negative capacitance transistor included in at least one of the memory devices.

Optionally, the number of the memory devices is multiple, and negative capacitance transistors and capacitances included in the multiple memory devices are formed on the same substrate; the memory further comprises an isolation structure, a passivation layer and a pressure point structure electrically connected with the peripheral circuit, wherein the isolation structure and the peripheral circuit are formed on the substrate; a plurality of the memory devices include negative capacitance transistors electrically isolated from each other by the isolation structure; the passivation layer covers the surface of the isolation structure, the negative capacitor transistors, the capacitors and the peripheral circuit, which faces away from the substrate; the pressure point structure is formed on the surface of the passivation layer, which faces away from the substrate.

Compared with the prior art, the beneficial effects of the memory provided by the invention are the same as those of the memory device in the technical scheme, and are not described herein again.

The invention also provides a manufacturing method of the memory, which is characterized by comprising the following steps:

providing a substrate;

forming at least one negative capacitance transistor on a surface of the substrate; forming peripheral circuitry over the substrate; electrically connecting the at least one negative capacitance transistor with the peripheral circuit;

forming at least one capacitor on the surface of the substrate; the at least one capacitor is electrically connected to the at least one negative capacitor transistor as at least one memory device;

electrically connecting the at least one capacitor with the peripheral circuit.

Optionally, the negative capacitor transistor includes a gate structure including a gate conductive layer and at least one dielectric layer stacked together, the at least one dielectric layer is located between the substrate and the gate conductive layer, and at least one of the at least one dielectric layer is a ferroelectric dielectric layer.

Optionally, the at least one capacitor and the at least one negative capacitor transistor are plural; after the at least one negative capacitor transistor is formed on the surface of the substrate and before the peripheral circuit is formed on the surface of the substrate, the manufacturing method of the memory further comprises the following steps:

forming an isolation structure on a surface of the substrate such that a plurality of the negative-capacitance transistors are electrically isolated from each other by the isolation structure;

after the at least one capacitor and the peripheral circuit are electrically connected together, the manufacturing method of the memory further comprises the following steps:

forming a passivation layer on the surface of the isolation structure, the negative capacitor transistors, the capacitors and the peripheral circuit, which faces away from the substrate;

and forming a pressure point structure electrically connected with the peripheral circuit on the surface of the passivation layer, which is far away from the substrate.

Compared with the prior art, the beneficial effects of the manufacturing method of the memory provided by the embodiment of the invention are the same as the beneficial effects of the memory device in the technical scheme, and are not repeated herein.

The invention also provides electronic equipment. The electronic equipment comprises the memory according to the technical scheme.

Optionally, the electronic device further comprises a processor; the processor is electrically connected with the memory.

Compared with the prior art, the electronic device provided by the invention has the same beneficial effects as the memory in the technical scheme, and the detailed description is omitted.

The invention also provides a chip. The chip comprises the memory of the technical scheme.

Optionally, the chip further includes a processor electrically connected to the memory.

Compared with the prior art, the beneficial effects of the chip provided by the invention are the same as those of the memory device in the technical scheme, and are not repeated herein.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of an electronic device according to the prior art;

FIG. 2 is a block diagram of an electronic device according to the prior art;

FIG. 3 is a schematic diagram of a prior art memory array;

FIG. 4 is a schematic circuit diagram of a prior art memory device;

FIG. 5 is a schematic circuit diagram of a memory device according to an embodiment of the present invention;

FIG. 6 is a schematic perspective view of a memory device according to an embodiment of the present invention;

figure 7 is a first cross-sectional view of a memory device along a direction of fin structure extension according to an embodiment of the present invention;

fig. 8 is a first cross-sectional view of a memory device along an extension direction of a gate structure according to an embodiment of the present invention;

figure 9 is a second cross-sectional view of a memory device along the direction of fin structure extension according to an embodiment of the present invention;

fig. 10 is a second cross-sectional view of a memory device along an extending direction of a gate structure according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating a memory structure according to an embodiment of the present invention;

FIG. 12 is a flowchart illustrating a method for fabricating a memory according to an embodiment of the present invention;

FIG. 13 is a flowchart illustrating a method for fabricating a memory according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

fig. 15 is a schematic diagram of a chip structure according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of the various regions, layers and the relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations from actual practice due to manufacturing tolerances or technical limitations are possible, and those skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as may be desired in practice.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In addition, in the present invention, directional terms such as "upper" and "lower" are defined with respect to a schematically placed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may be changed accordingly according to the change of the orientation in which the components are placed in the drawings.

In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.

Fig. 1 shows a schematic structural diagram of an electronic device in the prior art. The electronic device may be a computer, a mobile phone, a base station, a server, etc., but is not limited thereto. The electronic device includes aprocessor 110 and a Dynamic Random Access Memory (DRAM) 120. Theprocessor 110 is electrically connected to the DRAM. Theprocessor 110 may store data into the DRAM or read data stored by the DRAM.

As shown in fig. 1, theprocessor 110 may be a single processor or may be a general term for multiple processing elements. For example, theprocessor 110 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement embodiments of the present invention, such as: one or more microprocessors (DSP for short), or one or more Field programmable gate arrays (FPGA for short).

Fig. 2 shows a block diagram of an electronic device in the prior art. As shown in fig. 2, the dynamicrandom access memory 120 includes amemory array 121,peripheral circuits 122, and interconnection lines (not shown in fig. 2). Thememory array 121 includesmemory devices 1210 arranged in an array. Theperipheral circuit 122 includes a logic circuit 1221, an input-output circuit 1222, an address decoder 1223, a power supply circuit (not shown in fig. 2), and the like.

Fig. 2 is merely an example showing some circuits included in the peripheral circuit and the main connection relationship between the respective circuits, and does not illustrate the connection relationship between the logic circuit 1221 and the respective circuits. It should be understood that the logic circuit 1221 and the address decoder 1223, the logic circuit 1221 and the power supply circuit, the logic circuit 1221 and the input/output circuit 1222, thememory array 121 and the address decoder 1223, thememory array 121 and the power supply circuit, thememory array 121 and the input/output circuit 1222, and the address decoder 1223 and the input/output circuit 1222 are interconnected by interconnection lines.

As shown in fig. 2, the input/output circuit 1222 includes sense amplifiers, data registers, address registers, and the like. To support processor access to data stored by the DRAM, the electronic device further includes a system bus IOB0, and an address bus IOB1, a data bus IOB2, and a read/write control bus IOB3, each coupled tosystem bus IOB 0. Theprocessor 110 and the address register are electrically connected via an address bus IOB1, theprocessor 110 and the input/output circuit 1222 are electrically connected via a data bus IOB2, and theprocessor 110 and the logic circuit 1221 are electrically connected via a read/write control bus IOB 3.

As shown in FIG. 2, theprocessor 110 sends a data address and an access command to thememory array 121, and an address register in the I/O circuit 1222 can search for a target address according to the data address and send the target address to the address decoder 1223. The address decoder 1223 resolves the desired target address from the target address, and the address decoder 1223 selects thememory device 1210 from thememory array 121 that matches the target address based on the desired target address under the control of the logic circuit 1221. When the access command is a read command, thememory device 1210 outputs data through a data register included in the input/output circuit 1222. The output data is transmitted to the processor through the data bus. When the access command is a write command, theprocessor 110 sends data to the data register included in the input/output circuit 1222 through the data bus, and the data register included in the input/output circuit 1222 sends data to the selectedmemory device 1210 under the control of the logic circuit 1221 to store the data using thememory device 1210.

Illustratively, fig. 3 illustrates a schematic diagram of a memory array in the prior art. As shown in fig. 3, thememory array 121 includes a matrix ofmemory devices 1210. Thematrixed memory devices 1210 include 5 rows ofmemory devices 1210 and 6 columns ofmemory devices 1210. Accordingly, the interconnection line includes 5 word lines WL and 6 bit lines BL. The address decoder 12231223 includes arow decoder 1223R and a column decoder 1223C. Therow decoder 1223R is connected to the 5row memory devices 1210 through 5 word lines WL in a one-to-one correspondence to control thememory devices 1210 of the corresponding column to be turned on by providing a row strobe signal to thecorresponding memory devices 1210, and the column decoder 1223C is connected to the 6column memory devices 1210 through 6 bit lines BL in a one-to-one correspondence to control thecorresponding memory devices 1210 to provide a row strobe signal to control thememory devices 1210 of the corresponding column to output or store data.

Fig. 4 shows a schematic diagram of a memory device in the prior art. As shown in fig. 4, for a DRAM, eachmemory device 1210 includes a substrate (not shown in fig. 4) and a transistor M1 and a capacitor C1 formed on the substrate. The gate of the transistor M1 is connected to the word line WL, the first electrode of the transistor M1 is electrically connected to the bit line BL, and the second electrode of the transistor M1 is electrically connected to the capacitor C1. The type of the transistor can be selected according to actual needs, such as common NMOS or PMOS. As for whether the first electrode and the second electrode of the transistor M1 are sources or drains, it can be determined according to the conventional art. The transistor M1 is used to control the data reading and programming of thememory device 1210, and the capacitor C1 is used to store data. Since the capacitor C1 is prone to leak current, which results in loss of the data signal stored in the capacitor C1, in thememory array 121 shown in fig. 3, the power circuit (not shown in fig. 3) is also electrically connected to the capacitor C1 through 6 power lines (not shown in fig. 3), so that under the control of the logic circuit 1221, the power circuit periodically charges the memory cells contained in the 6-column memory device 1210 through the 6 power lines in a one-to-one correspondence manner, thereby ensuring that the data signal stored in the capacitor C1 is not lost, and improving the storage performance of thememory device 1210. However, thememory device 1210 still has leakage, so that periodically refreshing thememory device 1210 cannot fundamentally improve the storage capability of the DRAM.

In view of the above problems, the inventors have analyzed thememory device 1210 shown in fig. 4 to find that: due to an increase in the data retention period of thememory device 1210 and the leakage current of thememory device 1210. And the leakage current of thememory device 1210 comes not only from the capacitor C1 but also from the transistor M1 and the like. Based on this, fig. 5 shows a schematic structural diagram of a memory device provided by an embodiment of the present invention. As shown in fig. 5, thememory device 200 is applied to a DRAM. Also, when thememory device 200 is applied to a DRAM, reference may be made to the foregoing for the manner in which thememory device 200 is interconnected with peripheral circuits of the DRAM, which will not be described in detail below.

As shown in fig. 5 to 10, thememory device 200 includes asubstrate 210, and a negative capacitance transistor M2 formed on thesubstrate 210 and a capacitor C2 electrically connected to the negative capacitance transistor M2. It should be understood that thesubstrate 210 may be a semiconductor substrate, and the material thereof may be a semiconductor material such as silicon, germanium, etc.

As shown in fig. 5, the negative capacitor transistor M2 has an ultra-steep sub-threshold swing, a smaller threshold voltage, a faster switching rate, and a smaller leakage current, so that the negative capacitor transistor M2 has an extremely high gate control capability, and therefore, when the negative capacitor transistor M2 is in an off state, the leakage current of the negative capacitor transistor M2 is relatively small, so that the leakage current of thememory device 200 is relatively reduced, and when thememory device 200 has a smaller leakage current, since the data retention time of thememory device 200 is inversely proportional to the leakage current of thememory device 200, when the negative capacitor transistor M2 is in an off state, thememory device 200 has a relatively long data retention time, which not only improves the storage performance of thememory device 200, but also reduces the refresh frequency of thememory device 200 to a certain extent, thereby achieving the purpose of reducing power consumption.

As one possible implementation, as shown in fig. 6, the negative-capacitance transistor M2 described above includes a gate structure G and two electrode structures that a conventional transistor has. As shown in fig. 7 and 9, one of the two electrode structures is a source structure S, and the other electrode structure is a drain structure D, and the like. As for the type of the negative capacitor transistor M2, it may be a PMOS negative capacitor transistor or an MMOS negative capacitor transistor, and is not limited herein.

For example, as shown in fig. 7 and 9, when the negative capacitor transistor M2 is a PMOS negative capacitor transistor, the gate structure G and the source structure S are both electrically connected to the input/output circuit, and the drain structure D is electrically connected to the capacitor C2. When the negative capacitor transistor M2 is an NMOS negative capacitor transistor, the gate structure G and the drain structure D are both electrically connected to the input/output circuit, and the source structure S is electrically connected to the capacitor C2.

In an alternative, as shown in fig. 5 and 6, the gate structure G is a ferroelectric gate stack structure. This ferroelectric gate stack structure can improve the gating capability of the negative capacitor transistor M2 and reduce the power consumption of the negative capacitor transistor M2.

In an alternative, as shown in fig. 7 to 10, the gate structure G or the ferroelectric gate stack structure includes a gate conductive layer GE and at least one dielectric layer GI stacked together. The at least one dielectric layer GI is located between the gate conductive layer GE and thesubstrate 210. At least one of the at least one dielectric layer GI is a ferroelectric dielectric layer. At this time, such a gate structure G can improve the gate controllability of the negative capacitance transistor M2 and reduce the power consumption of the negative capacitance transistor M2.

In a first example, as shown in fig. 7 and 8, when at least one dielectric layer GI includes: a first dielectric layer GI1 and a second dielectric layer GI2 laminated together. The second dielectric layer GI2 is a ferroelectric dielectric layer. The second dielectric layer GI2 is located between the gate conductive layer GE and the first dielectric layer GI 1. The first dielectric layer GI1, the second dielectric layer GI2, and the gate conductive layer GE are sequentially stacked in a direction away from thesubstrate 210.

In a second example, as shown in fig. 9 and 10, when at least one dielectric layer GI includes: a first dielectric layer GI1, a second dielectric layer GI2, and a third dielectric layer GI3 adjacent to the gate conductive layer GE, which are sequentially stacked together. The third dielectric layer GI3 is a ferroelectric dielectric layer. The second dielectric layer GI2 is located between the first dielectric layer GI1 and the third dielectric layer GI 3. Further, the first dielectric layer GI1, the second dielectric layer GI2, the third dielectric layer GI3, and the gate conductive layer GE are sequentially stacked in a direction away from thesubstrate 210.

As shown in fig. 6 to 8, the gate conductive layer GE may be a metal gate or a polysilicon gate, or may be a gate made of a conductive material such as indium tin oxide.

The ferroelectric dielectric layer may be a dielectric layer prepared from an oxide of one or both of a semiconductor and a rare earth, and the material contained in the ferroelectric dielectric layer may be generally represented by ferroelectric HMOx. M may be a semiconductor or a rare earth. It should be understood that the semiconductor here may be one or both of silicon and zirconium, but is not limited thereto. The rare earth can be one or two of lanthanum and yttrium, but is not limited to the lanthanum and the yttrium. For example, the ferroelectric dielectric layer is an oxide containing zirconium. Such an oxide may contain not only zirconium but also other semiconductors, rare earths, and the like.

As shown in fig. 7 and 8, the first dielectric layer GI1 may be a common insulatinglayer 220, which may be a dielectric layer formed by using an organic insulating material or an inorganic oxide. For example: the first dielectric layer GI1 may be a dielectric layer made of photoresist or the like. Another example is: the first dielectric layer GI1 may be a dielectric layer made of silicon oxide, aluminum oxide, or the like.

As shown in fig. 7 and 8, the second dielectric layer GI2 may be made of a high-k dielectric material to further increase the dielectric capability of the dielectric layer, thereby enhancing the gate control capability of the transistor. The dielectric constant of the high-k material can be determined according to the actual application environment, and will not be described herein. For example: the high-k material may be a high-k material such as hafnium oxide, aluminum oxide, zirconium oxide, etc., but is not limited thereto.

As a possible implementation manner, as shown in fig. 5, the negative capacitor transistor M2 is a fin transistor. For example: the Fin Transistor is a Fin Field-Effect Transistor (abbreviated as FinFET). It is a new CMOS transistor. The FinFET may improve circuit control and reduce leakage current, shortening the gate length of the transistor, thereby further improving the memory performance of thememory device 200.

As a possible implementation, as shown in fig. 5, the negative capacitor transistor M2 is a buried channel transistor. At this time, the negative capacitor transistor M2 can also reduce the thickness of thememory device 200 while ensuring a higher gate control capability, so that the memory is developed to be thinner and smaller. For example: when the negative capacitor transistor M2 is a fin transistor, the fin transistor may be a buried channel transistor.

For the fin transistor, as shown in fig. 6 to 10, the fin transistor may be a silicon-on-insulator (SOI) fin transistor, or a bulk silicon fin transistor. As for the kind of the Capacitor, a Stacked Capacitor (abbreviated as SC) or a trench Capacitor (abbreviated as TC) may be selected.

A memory device provided by an embodiment of the present invention is described below with reference to fig. 7 to 10. It is to be understood that the following description is intended to be illustrative, and not restrictive.

The storage device provided by the embodiment of the invention is composed of a bulk silicon fin transistor and a stacked capacitor. Specifically, the bulk silicon FIN transistor mainly includes a substrate 210 (e.g., a silicon substrate) having a FIN structure FIN, an insulatinglayer 220, a gate structure G, a source structure S, a drain structure D, and the like. The stacked capacitor includes an upper electrode PC, a lower electrode SN, and a capacitance dielectric layer CI disposed between the upper electrode PC and the lower electrode SN.

In practical structure, the FIN structure FIN and thesubstrate 210 are a single structure. Insulatinglayer 220 is formed onsubstrate 210 in areas not covered by FIN structure FIN. Also, the insulatinglayer 220 may be formed on thesubstrate 210 in a region not covered by the FIN structure FIN using a shallow trench isolation technique. The cross-sectional shape of the FIN structure FIN may be rectangular, trapezoidal, or anisotropic, and is not limited herein.

Structurally, the FIN structure FIN passes through the gate structure G. In terms of process, various process methods may be used to form the gate structure G in the region where the FIN structure FIN is used to form the conductive channel. The process for fabricating the gate structure is diversified. For example: atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation and reflow processes, and the like.

The source structure S and the drain structure D are formed on the FIN structure FIN. For example: ion implantation may be performed to form a source structure S and a drain structure D on the surface of the FIN structure FIN facing away from thesubstrate 210. Also, the gate structure G is located between the source structure S and the drain structure D. In addition, in order to ensure that the gate structure G is electrically isolated from the source structure S, the drain structure D and the FIN structure FIN, two inner side walls SW may be disposed in the gap, so that the gate structure G is electrically isolated from the drain structure D and the FIN structure FIN by one of the inner side walls SW and is electrically isolated from the source structure S and the FIN structure FIN by the other inner side wall SW. It should be understood that the bottom of the two inner side walls SW should be in contact with the substrate 210 (i.e., the bottom of the two inner side walls should be flush with the root of the FIN structure FIN) to ensure the effectiveness of electrical isolation.

To reduce unnecessary electrical losses, the bulk silicon fin transistor further includes a conductive contact layer formed on the surface of the source structure S facing away from thesubstrate 210 and the surface of the drain structure D facing away from thesubstrate 210. The conductive contact layer contains a material having high conductivity and relatively low resistance. The conductive contact layer has high conductivity, so that the loss of electric signals can be reduced, and the accuracy of data stored in or taken out from the capacitor can be ensured to be high when the data is accessed.

For example, a combination of a physical sputtering process and an annealing process may be used to form a conductive contact layer on the surface of the source structure S facing away from thesubstrate 210 and the surface of the drain structure D facing away from thesubstrate 210. For example: when thesubstrate 210 is a silicon substrate, a physical sputtering process is adopted to sputter titanium metal on the surface of the source electrode structure S deviating from thesubstrate 210 and the surface of the drain electrode structure D deviating from thesubstrate 210, and then an annealing process is adopted to anneal the titanium metal, so that the titanium metal film is silicided to form TiSi₂. At this time, the surface of the source structure S facing away from thesubstrate 210 and the surface of the drain structure D facing away from thesubstrate 210 are both made of TiSi₂The conductive contact layer of (1).

When the bulk silicon fin transistor is an N-type silicon fin transistor, the source structure S is away from the surface of thesubstrate 210 to form a capacitor conductive contact layer SNY, and the drain structure D is away from the surface of thesubstrate 210 to form a bit line conductive contact layer BLY.

In practical application, after the bulk silicon fin transistor is manufactured, an interlayer dielectric layer ILC needs to be deposited on the surface of the bulk silicon fin transistor to serve as a planarization layer, and a bit line contact hole BLC and a capacitor contact hole SNC are formed in the interlayer dielectric layer ILC, so that a bit line BL formed on the surface of the interlayer dielectric layer ILC away from thesubstrate 210 and a lower electrode PC of a stacked capacitor can be electrically connected with the bulk silicon fin transistor. As for the gate structure, a word line signal is transmitted through the word lines WL disposed at the same layer.

When the bulk silicon fin transistor is an NMOS bulk silicon fin transistor, the bitline BL may contact the bitline conductive contact layer BLY through the bitline contact hole BLC. At this time, the bit line contact hole BLC provides an electrical connection path for the bit line conductive contact layer BLY and the bit line BL. The lower electrode SN of the stack capacitor may be electrically connected to the capacitor conductive contact layer SNY through the capacitor contact hole SNC, and the upper electrode PC of the stack capacitor may be connected to the power line VDD. At this time, the capacitor contact hole SNC provides an electrical connection path for the capacitor conductive contact layer SNY and the capacitor contact hole SNC, and the power supply line VDD is formed on the surface of the upper electrode PC provided with the stacked capacitor to supply a power supply signal to the upper electrode PC.

Fig. 11 shows a schematic structural diagram of a memory according to an embodiment of the present invention. As shown in fig. 10, thememory 300 includes at least one memory device and peripheral circuits. The memory device may be thememory device 210 shown in fig. 5-10. The peripheral circuitry may beperipheral circuitry 122 shown in fig. 2. Specifically, theperipheral circuit 122 shown in fig. 2 is electrically connected to at least one of the negative capacitance transistor C2 and the capacitor C2 included in thememory device 210 shown in fig. 5.

Compared with the prior art, the beneficial effects of the memory provided by the embodiment of the invention are the same as those of the memory device described in the embodiment of the invention, and are not described herein again.

It should be understood that thememory device 300 shown in fig. 11 includes a plurality of thememory devices 200 shown in fig. 5. A plurality ofmemory devices 200 share the substrate 11 shown in fig. 11. The peripheral circuits, memory devices and capacitors may constitute theintermediate layer 320 shown in fig. 11.

As a possible implementation, when thememory 300 shown in fig. 11 includes a plurality of thememory devices 200 shown in fig. 5, as shown in fig. 11, thememory 300 includes an isolation structure (not shown in fig. 11), apassivation layer 330, and adot structure 340 in addition to thesubstrate 310 and theintermediate layer 320 shared by the plurality of memory devices. Theperipheral circuitry 122 and isolation structures shown in fig. 2 are formed on asubstrate 210. Apassivation layer 330 covers the surface of theintermediate layer 320 facing away from thesubstrate 310. Thepressure point structure 340 is formed on the surface of thepassivation layer 330 facing away from thesubstrate 210. At this time, the pressure point structure is electrically connected with the peripheral circuit. Also, the plurality of negative capacitance transistors M2 included in thememory device 200 shown in fig. 5 are electrically isolated from each other by an isolation structure. Thepressure point structure 340 may receive a signal input from an external device through a pin or output data output from a memory through a pin.

As shown in fig. 5, an embodiment of the invention further provides a method for manufacturing a memory. The manufacturing method of the memory comprises the following steps:

step S101: a substrate is provided. The substrate is typically a semiconductor substrate of silicon, germanium, or the like.

Step S102: at least one negative capacitance transistor is formed on a surface of the substrate. The negative capacitor transistor is the negative capacitor transistor M2 shown in fig. 5. As for the type of the negative capacitance transistor, it may be a PMOS negative capacitance transistor or an MMOS negative capacitance transistor, and is not limited herein. It should be understood that whether the substrate is a P-type substrate or an N-type substrate should be determined according to the type of the negative capacitor transistor. When the negative capacitance transistor is a PMOS negative capacitance transistor, the substrate is an N-type substrate. When the negative capacitance transistor is an NMOS negative capacitance transistor, the substrate is a P-type substrate.

Step S103: peripheral circuitry is formed over the substrate. The specific circuit configuration of the peripheral circuit can be described with reference to fig. 2, and is not described in detail here. The peripheral circuit includes a plurality of logic transistors in terms of the types of devices included in the respective circuits included in the peripheral circuit. In this case, the forming of the peripheral circuit on the surface of the substrate includes:

forming a gate structure of a plurality of logic transistors above a substrate; source and drain structures of a plurality of logic transistors are formed over a substrate. It should be understood that the formation of the peripheral circuits over the substrate is described here only briefly, and each logic transistor also includes other film layers such as an insulating layer.

Step S104: at least one negative capacitance transistor is electrically connected with the peripheral circuit. The electrical connections here may be interconnected by interconnecting lines. This step is also called middle lane interconnect. It should be understood that the interconnection of the negative capacitor transistor and the peripheral circuit is referred to above and will not be described in detail.

Step S105: at least one capacitor is formed over the substrate, and at least one negative capacitor transistor is electrically connected to the at least one capacitor as at least one memory device. The capacitance may be the capacitance C2 shown in fig. 5. The electrical connections here may be interconnected by interconnecting lines. The interconnection mode is one-to-one corresponding interconnection, namely, one capacitor is interconnected with one negative capacitor transistor. It should be understood that the specific formation position of the capacitor should be determined according to the type of the capacitor. For example: when the capacitor is a stacked capacitor, the capacitor should be located above the negative capacitor transistor.

Step S106: at least one capacitor is electrically connected with the peripheral circuit. The electrical connections may be interconnected by interconnection lines, and of course, other ways of interconnection may be selected, and are not limited in detail.

Compared with the prior art, the manufacturing method of the memory provided by the embodiment of the invention has the same beneficial effects as the memory device provided by the embodiment, and the details are not repeated here.

It should be noted that, in order to ensure the above memory chip, after step S107, the manufacturing method of the above memory further includes an assembling process and a packaging process, which may refer to the prior art specifically, and is not limited herein.

As one possible implementation, the negative capacitance transistor includes a gate structure, a source structure, a drain structure, and the like of a conventional transistor.

For example, as shown in fig. 5 to 10, the negative capacitor transistor may include a gate structure as described above with reference to the gate structure of the negative capacitor transistor M2. However, the gate structure of the negative capacitor transistor M2 is a ferroelectric gate stack structure.

Furthermore, the gate structure or the ferroelectric gate stack structure should include a gate conductive layer and at least one dielectric layer stacked together. The at least one dielectric layer is located between the substrate and the gate conductive layer. At least one of the at least one dielectric layer is a ferroelectric dielectric layer.

As a possible implementation, the negative capacitor transistor may be a fin transistor or a buried channel transistor.

As a possible implementation, the at least one capacitor and the at least one negative capacitor transistor are plural. At this time, forming at least one negative capacitance transistor on a surface of a substrate includes: a plurality of negative capacitance transistors are formed on a surface of a substrate.

For example, after forming at least one negative capacitor transistor on the surface of the substrate and before forming the peripheral circuit above the substrate, the method for manufacturing the memory further includes:

an isolation structure is formed on a surface of the substrate such that the plurality of negative-capacitance transistors are electrically isolated from each other by the isolation structure. The isolation structure may be a junction isolation structure, a dielectric isolation structure, a local oxidation isolation structure, a trench isolation structure, etc., but is not limited to the list, and is not listed here.

After at least one capacitor is electrically connected with the peripheral circuit, the manufacturing method of the memory further comprises the following steps:

forming apassivation layer 330 on a surface of the isolation structure, the plurality of negative capacitor transistors, the plurality of electrical and peripheral circuits facing away from the substrate; apressure point structure 340 electrically connected with peripheral circuits is formed on the surface of thepassivation layer 330 facing away from thesubstrate 310, and the specific structure is shown in fig. 11.

For clarity of description of the method for manufacturing the memory provided by the embodiment of the invention, the following description is made in detail with reference to fig. 12. It should be understood that the following is only a brief introduction of the main steps of the method for manufacturing the memory according to the embodiment of the present invention, and the detailed steps are not described.

The following describes a method for manufacturing a memory according to an embodiment of the present invention with reference to fig. 13. It is to be understood that the memory shown in fig. 13 includes a memory device exemplified by the memory devices shown in fig. 6 to 11.

Step S201: asubstrate 210 is provided.

Step S202: FIN structures FIN are formed on the surface of thesubstrate 210. The number of FIN structures FIN is not limited herein and may be determined according to the actual process.

Step S203: the insulatinglayer 220 is formed in a region of thesubstrate 210 where the FIN structure FIN is not formed using a shallow trench channel isolation method.

Step S204: and forming a plurality of gate structures G of the bulk silicon FIN transistors on the FIN structures FIN.

Step S205: and forming a source electrode structure S and a drain electrode structure D of a plurality of bulk silicon FIN transistors on the FIN structure FIN to obtain a plurality of bulk silicon FIN transistors. It should be understood that the structure of each bulk silicon fin transistor can be referred to above, and is not described herein.

Step S206: an isolation structure is formed on the surface of thesubstrate 210 such that the plurality of bulk silicon fin transistors are electrically isolated from each other by the isolation structure.

Step S207: gate structures, source structures and drain structures of peripheral circuits are formed on the surface of the insulatinglayer 220 facing away from thesubstrate 210. At this time, the transistors included in the peripheral circuit and the bulk silicon fin transistors already fabricated share the insulatinglayer 220, which can effectively simplify the memory fabrication process.

Step S208: and interconnecting a plurality of bulk silicon fin transistors with peripheral circuits.

Step S209: and forming an interlayer dielectric layer ILD on the surfaces of the bulk silicon fin transistors and the peripheral circuit.

Step S210: a plurality of stacked capacitors and bit lines BL are formed on the surface of the ILD facing away from thesubstrate 210, and the stacked capacitors are electrically connected to the bulk silicon fin transistors in a one-to-one correspondence. For example: when the bulk silicon fin type transistor is an N-type body silicon fin type transistor, each stacked capacitor is electrically connected with the source electrode structure S of the corresponding bulk silicon fin type transistor through a capacitor contact hole SNC formed in the interlayer dielectric layer ILC. The bit line BL is electrically connected to the drain structure D of the bulk silicon fin transistor through a bit line contact hole BLC formed in the interlayer dielectric layer ILC.

Step 211: a plurality of stacked capacitors are interconnected with peripheral circuitry. That is, in the case where the peripheral circuit includes a power supply circuit, the upper electrode PC included in each stacked capacitor is interconnected with the power supply circuit included in the peripheral circuit through the power supply line VDD. It should be appreciated that whenstep 210 is completed, the resulting structure is essentially theintermediate layer 320 of fig. 11 without thepassivation layer 330 and thebump structure 340.

Step S212: apassivation layer 330, shown in figure 11, is formed on the surfaces of the isolation structures, the plurality of bulk silicon fin transistors, the plurality of stacked capacitors, and the peripheral circuitry facing away from thesubstrate 210.

Step S213: apressure point structure 340 electrically connected with peripheral circuits, which is shown in fig. 11, is formed on the surface of the passivation layer facing away from thesubstrate 210.

When the memory is assembled and packaged, the memory is in the form of a chip. Based on this, the embodiment of the invention also provides a chip. The chip includes the memory described in the above embodiments. Compared with the prior art, the beneficial effects of the chip provided by the embodiment of the invention are the same as those of thememory device 200 shown in fig. 5 to 10, and are not described herein again.

Fig. 14 shows a schematic structural diagram of an electronic device according to an embodiment of the present invention. As shown in fig. 14, the electronic device 400 includes a memory 410. The memory 410 is thememory 300 shown in fig. 11.

Compared with the prior art, the electronic device provided by the embodiment of the invention has the same beneficial effects as the memory devices shown in fig. 5 to 10, and the details are not repeated herein.

As a possible implementation, as shown in fig. 14, the electronic device 400 further includes a processor 420 in communication with a memory 410.

In some cases, as shown in fig. 14, the electronic device 400 may include a memory 410 and a processor 420, which are integrated with a communication interface and the like, and packaged into a chip to form a chip applied to the electronic device.

Fig. 15 shows a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 15, the chip 500 may be a chip applied to the electronic device 400 shown in fig. 14. As shown in fig. 15, the chip 500 includes a processor 510, a memory 520, and a communication interface 530. Processor 510, communication interface 530, and memory 520 are coupled together by abus system 540. The memory 520 is thememory 300 described in fig. 11.

As shown in fig. 15, the memory 520 is used to store computer programs or instructions and data. The processor 510 may be a single-core processor or a dual-core processor, and is configured to execute a computer program or instructions to perform the method or steps represented by the computer program or instructions.

As shown in fig. 15, the communication interface 530 may use any transceiver or the like for communicating with other devices or communication networks.

As shown in FIG. 15, thebus system 540 has a path for transferring information between the components. Thebus system 540 may include a power bus, an address bus, a read/write control bus, a data bus, and the like, in addition to the data bus. But for clarity of illustration the various buses are labeled as a bus system in figure 15.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A memory device, comprising:

a substrate;

2. The memory device of claim 1 wherein said negative capacitor transistor includes a gate structure that is a ferroelectric gate stack structure.

3. The memory device of claim 1, wherein the negative capacitor transistor includes a gate structure including a gate conductive layer and at least one dielectric layer stacked together between the substrate and the gate conductive layer, at least one of the at least one dielectric layer being a ferroelectric dielectric layer.

4. The memory device of any of claims 1 to 3, wherein the negative capacitor transistor is a fin transistor or a buried channel transistor.

5. A memory comprising peripheral circuitry and at least one memory device as claimed in any one of claims 1 to 4; the peripheral circuit is electrically connected to a negative capacitance transistor and a capacitor included in at least one of the memory devices.

6. The memory according to claim 5, wherein the memory device is plural, and a negative capacitance transistor and a capacitor included in the plural memory devices are formed on the same substrate; the memory further comprises an isolation structure, a passivation layer and a pressure point structure electrically connected with the peripheral circuit, wherein the isolation structure and the peripheral circuit are formed on the substrate; a plurality of the memory devices include negative capacitance transistors electrically isolated from each other by the isolation structure; the passivation layer covers the surface of the isolation structure, the negative capacitor transistors, the capacitors and the peripheral circuit, which faces away from the substrate; the pressure point structure is formed on the surface of the passivation layer, which faces away from the substrate.

7. A method for manufacturing a memory, comprising:

providing a substrate;

forming at least one capacitor over the substrate, the at least one capacitor electrically connected with the at least one negative capacitor transistor as at least one memory device;

electrically connecting the at least one capacitor with the peripheral circuit.

8. The method of claim 7, wherein the negative capacitor transistor comprises a gate structure that is a ferroelectric gate stack structure.

9. The method of claim 7, wherein the negative capacitor transistor comprises a gate structure including a gate conductive layer and at least one dielectric layer stacked together between the substrate and the gate conductive layer, at least one of the at least one dielectric layer being a ferroelectric dielectric layer.

10. The method of any of claims 7 to 9, wherein the negative capacitor transistor is a fin transistor or a buried channel transistor.

11. The method for manufacturing a memory according to any one of claims 7 to 9, wherein the at least one capacitor and the at least one negative capacitor transistor are plural; after the at least one negative capacitor transistor is formed on the surface of the substrate and before the peripheral circuit is formed above the substrate, the manufacturing method of the memory further comprises the following steps:

12. An electronic device comprising the memory of claim 5 or 6.

13. The electronic device of claim 12, further comprising a processor; the processor is electrically connected with the memory.

14. A chip comprising the memory of claim 5 or 6.

15. The chip of claim 14, wherein the chip further comprises a processor electrically connected to the memory.