CN111161788A - Aging testing device of memory - Google Patents

Abstract

The invention discloses a burn-in test device of a memory, which comprises a PCB circuit board; the PCB circuit board is provided with at least two test stations, each test station is provided with a test circuit and a connecting socket, and the memory to be tested is connected with the test circuit through the connecting socket; the test circuit comprises an input circuit and an output circuit, the input circuit is connected with the signal input end of the memory to be tested, and the input circuit is used for inputting a specific test signal to the memory to be tested; the output circuit is connected with the signal output end of the memory to be tested and used for reading the signal to be tested from the memory to be tested. The burn-in test device can burn-in test the memory to test the reliability of the memory.

Description

Aging testing device of memory

Technical Field

The invention relates to the technical field of device testing, in particular to a burn-in testing device of a memory.

Background

With the development of the manufacturing technology of the domestic components, the domestic components are increasingly applied to various system devices. In order to ensure the reliability of the components, the aging test of the components is an important link for screening the components, and the aging test can eliminate the early failure of the components caused by the process or manufacturing problems through the dual functions of electric stress and thermal stress. At present, no device capable of performing burn-in test on a mass storage device exists.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a burn-in test apparatus for a memory, which can perform a burn-in test on the memory to test the reliability of the memory.

Based on the above purpose, the invention provides a burn-in test device of a memory, which comprises a PCB circuit board;

the PCB circuit board is provided with at least two test stations, each test station is provided with a test circuit and a connecting socket, and the memory to be tested is connected with the test circuit through the connecting socket;

the test circuit comprises an input circuit and an output circuit, the input circuit is connected with the signal input end of the memory to be tested, and the input circuit is used for inputting a specific test signal to the memory to be tested; the output circuit is connected with the signal output end of the memory to be tested and used for reading the signal to be tested from the memory to be tested.

Optionally, the test circuit further includes a power circuit and a clock circuit, the power circuit is connected to the power end of the memory to be tested, and the clock circuit is connected to the clock signal end of the memory to be tested.

Optionally, the input circuit inputs the specific test signal to the memory to be tested once, and the output circuit reads the signal to be tested from the memory to be tested for multiple times in a circulating manner.

The aging test device of the memory, provided by the invention, comprises the PCB, wherein the PCB is provided with at least two test stations, each test station is provided with a test circuit and a connecting socket, and the memory to be tested is connected with the test circuit through the connecting socket; the test circuit comprises an input circuit and an output circuit, wherein the input circuit is used for inputting a specific test signal to the memory to be tested, and the output circuit is used for reading the signal to be tested from the memory to be tested. The burn-in test device can burn-in test the memory to test the reliability of the memory.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a device structure according to an embodiment of the present invention;

FIG. 2 is a block diagram of a test station according to an embodiment of the present invention;

FIG. 3 is a timing diagram of test signals input according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a signal under test according to an embodiment of the present invention;

FIGS. 5A-5D are schematic diagrams illustrating a portion of a circuit schematic of a test circuit according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

Fig. 1 is a schematic structural layout diagram of an apparatus according to an embodiment of the present invention, and fig. 2 is a structural block diagram of a test station according to an embodiment of the present invention. As shown in the figure, the aging test device for the memory provided by the embodiment of the invention is realized based on a PCB, the PCB is provided with at least two test stations, each test station is provided with a test circuit and a connection socket, and the memory to be tested is connected with the test circuit through the connection socket.

The test circuit includes a peripheral circuit and an input-output circuit. The peripheral circuit comprises a power supply circuit and a clock circuit, wherein the power supply circuit is connected with a power supply end of the memory to be tested and used for supplying power to the memory to be tested; the clock circuit is connected with a clock signal end of the memory to be tested and used for providing a clock signal for the memory to be tested.

The input and output circuit comprises an input circuit and an output circuit, the input circuit is connected with the signal input end of the memory to be tested, and the input circuit is used for inputting a specific test signal to the memory to be tested; the output circuit is connected with the signal output end of the memory to be tested and used for reading the signal to be tested from the memory to be tested.

The input circuit inputs a test signal of a specific period to the memory to be tested, the test signal of the specific period is stored in the memory to be tested, the output circuit reads the signal to be tested from the memory to be tested, and whether the storage function of the memory to be tested is normal or not is judged according to the read signal to be tested. As shown in fig. 3 and 4, in some embodiments, atest signal 1, atest signal 2, and a test signal 3 with a specific period are input into the to-be-tested memory through the input circuit, and the output circuit is used to read the to-be-testedsignal 1, the to-be-testedsignal 2, and the to-be-tested signal 3 from the to-be-tested memory, where if the to-be-testedsignal 1 is the same as thetest signal 1, the to-be-tested signal 2 is the same as thetest signal 2, and the to-be-tested signal 3 is the same as the test.

The test circuit also includes an address configuration circuit for configuring addresses of the memory.

In the aging test process, in order not to influence the service life of the memory to be tested, a test signal of a specific period is input to the memory to be tested through an input circuit, the signal to be tested is read from the memory to be tested for multiple times in a circulating mode through an output circuit, and whether the function of the memory to be tested is normal or not is judged through the read signal to be tested. For example, the input circuit inputs a test signal "1" with a specific period, the output circuit cyclically reads the signal to be tested, verifies whether the signal to be tested is "1", and if the signal to be tested is "1", the memory function of the memory to be tested is normal.

In an embodiment, the burn-in test apparatus of the present invention is used to perform a burn-in test on a Static Random-Access Memory (SRAM). The SRAM to be tested has two independent input/output ports, each providing 19-bit address bits and 36-bit data bits, both input/output ports allowing access to the same memory location. In synchronous read operation, the maximum single data rate for each input/output port is 125MHz 36.

As shown in fig. 5A, a power source end of the SRAM to be tested is connected to a 3.3V power source, a clock signal end of the SRAM is connected to a clock circuit, and the clock circuit provides the SRAM with a square wave clock signal having an amplitude of 3.3V, a frequency of 500KHz, and a duty ratio of 50% to drive a crystal oscillator inside the SRAM to work; fig. 5B is a circuit diagram of address configuration of the SRAM to be tested, and fig. 5C and 5D are circuit diagrams of data bit connection of the SRAM to be tested.

In some embodiments, the PCB circuit board is a three-layer board design. The top plate is designed with a power line, a ground line and an input line of each test station, the bottom plate is designed with a voltage sampling line of each test station and an output line of each test station, and the power line, the ground line, the input line, the output line and the voltage sampling line are electrically connected with corresponding pins of the memory to be tested through connecting sockets (such as golden fingers). Specifically, when the memory to be tested is connected to the test station through the connecting socket, the power circuit is connected with the power end of the memory to be tested through the power line, the input circuit is connected with the signal input end of the memory to be tested through the input line, the output circuit is connected with the signal output end of the memory to be tested through the output line, the grounding end of the memory to be tested is grounded through the ground line, and the voltage sampling end of the memory to be tested is connected with the monitoring equipment through the voltage sampling line and used for detecting the voltage state of the device in real time.

The apparatus of the foregoing embodiment is used to implement the corresponding method in the foregoing embodiment, and has the beneficial effects of the corresponding method embodiment, which are not described herein again.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures for simplicity of illustration and discussion, and so as not to obscure the invention. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present invention is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The embodiments of the invention are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (3)

1. The aging test device of the memorizer is characterized by comprising a PCB circuit board;

the PCB circuit board is provided with at least two test stations, each test station is provided with a test circuit and a connecting socket, and the memory to be tested is connected with the test circuit through the connecting socket;

the test circuit comprises an input circuit and an output circuit, the input circuit is connected with the signal input end of the memory to be tested, and the input circuit is used for inputting a specific test signal to the memory to be tested; the output circuit is connected with the signal output end of the memory to be tested and used for reading the signal to be tested from the memory to be tested.

2. The apparatus of claim 1, wherein the test circuit further comprises a power circuit connected to the power terminal of the memory under test and a clock circuit connected to the clock signal terminal of the memory under test.

3. The apparatus of claim 1, wherein the input circuit inputs the specific test signal to the memory under test once, and the output circuit reads the signal under test from the memory under test a plurality of times in a cycle.

Images