CN111128048B - Display panel and display device - Google Patents
Display panel and display deviceDownload PDFInfo
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- CN111128048B CN111128048BCN202010092488.0ACN202010092488ACN111128048BCN 111128048 BCN111128048 BCN 111128048BCN 202010092488 ACN202010092488 ACN 202010092488ACN 111128048 BCN111128048 BCN 111128048B
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- 239000011521glassSubstances0.000claimsabstractdescription44
- 239000000758substrateSubstances0.000claimsabstractdescription44
- 230000005611electricityEffects0.000claimsdescription5
- 230000000149penetrating effectEffects0.000abstract1
- 238000010586diagramMethods0.000description10
- 230000000694effectsEffects0.000description6
- 239000010409thin filmSubstances0.000description5
- 238000000034methodMethods0.000description3
- 230000009286beneficial effectEffects0.000description1
- 239000003990capacitorSubstances0.000description1
- 238000004020luminiscence typeMethods0.000description1
- 230000004048modificationEffects0.000description1
- 238000012986modificationMethods0.000description1
- 230000003287optical effectEffects0.000description1
- 230000002093peripheral effectEffects0.000description1
- 230000008569processEffects0.000description1
- 230000008707rearrangementEffects0.000description1
- 230000004044responseEffects0.000description1
- 238000006467substitution reactionMethods0.000description1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
- G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Translated fromChinese
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
At present, a large-size display panel is mostly spliced by a plurality of small-size splicing units.
In the prior art, the splicing unit comprises a glass substrate, a light-emitting circuit layer is arranged on the glass substrate, and due to the arrangement of a driving chip, a plurality of signal lines and signal routing lines, a large splicing gap exists in a large-size display panel spliced and finished by the splicing unit, so that the watching effect is influenced.
Therefore, there is a need for a seamlessly-tiled display panel and a display device to improve the viewing effect.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display panel and a display device, which solve the technical problem that the viewing effect is affected due to a large splicing gap of a large-sized display panel in the prior art.
In a first aspect, an embodiment of the present invention provides a display panel, including:
mounting a plate;
the splicing units are arranged on the mounting plate in an array mode and comprise glass substrates;
the light-emitting circuit layer is positioned on the front surface of the glass substrate and comprises a plurality of signal wires;
the circuit board is located the relative back that sets up in glass substrate and front includes the signal routing layer that the multilayer piles up in proper order, and is located adjacently insulating layer between the signal routing layer, the signal routing layer is through running through the insulating layer and glass substrate's first electrically conductive via hole with correspond the setting signal line electricity is connected, glass substrate is in orthographic projection on the mounting panel is located the circuit board is in the orthographic projection on the mounting panel.
Optionally, the display device further comprises a driving chip arranged on the front surface of the glass substrate and electrically connected with the circuit board through a flexible circuit.
Optionally, the driving chip includes a first sub-driving chip and a second sub-driving chip, where the first sub-driving chip is disposed on a first side of the display panel, and/or is disposed on a second side of the display panel, which is parallel to and opposite to the first side;
the second sub-driver chip is arranged on a third side edge of the display panel, which is perpendicular to the first side edge, and/or on a fourth side edge of the display panel, which is parallel to and opposite to the third side edge.
Optionally, the signal lines include a plurality of data signal lines, a plurality of gate signal lines, a plurality of first power supply signal lines, and a plurality of second power supply signal lines; and/or the presence of a gas in the gas,
the signal routing layer comprises a data signal routing layer which is electrically connected with the data signal line through a bonding pad which is arranged corresponding to the first conductive through hole; the grid signal wiring layer is electrically connected with the grid signal wire through a bonding pad which is arranged corresponding to the first conductive through hole; the first power supply signal routing layer is electrically connected with the first power supply signal line through a bonding pad which is arranged corresponding to the first conductive through hole; and a second power signal wiring layer electrically connected to the second power signal line through a pad disposed corresponding to the first conductive via.
Optionally, the same row of the gate signal routing layer of the splicing unit is electrically connected, the same row of the data signal routing layer of the splicing unit is electrically connected, and the same row of the first power signal routing layer of the splicing unit is electrically connected, and the same row of the second power signal routing layer of the splicing unit is electrically connected.
Optionally, the light-emitting circuit layer further includes a light-emitting unit defined by each data signal line and each gate signal line crossing each other, a first electrode of the light-emitting unit is electrically connected to the data signal line, and a second electrode of the light-emitting unit is electrically connected to the gate signal line.
Optionally, the light emitting circuit layer further includes a signal input circuit layer and a light emitting driving circuit layer, the signal input circuit layer is electrically connected to the data signal line and the gate signal line, the signal input circuit layer is configured to provide a driving power signal for the light emitting driving circuit layer, and the light emitting driving circuit layer is configured to drive the light emitting unit to emit light.
Optionally, the light emitting unit comprises a light emitting diode or an organic light emitting diode.
Optionally, the light emitting diode comprises a micro light emitting diode and/or a mini light emitting diode.
In a second aspect, an embodiment of the present invention provides a display device, including the display panel according to any one of the first aspect.
According to the technical scheme in the embodiment, the first conductive via hole leads the electric signals of the plurality of signal lines included by the light-emitting circuit layer to the back of the glass substrate, and the first conductive via hole penetrates through the insulating layer of the circuit board and the glass substrate, so that the plurality of signal lines can be electrically connected with the signal wiring layer included by the circuit board through the first conductive via hole. The glass substrate is in orthographic projection on the mounting panel is located the circuit board is in the orthographic projection on the mounting panel, realized promptly that signal line and signal walk the electric connection of line, do not occupy the area that display element is used for showing, a plurality of splice units that the array was arranged can realize seamless concatenation at the in-process of concatenation, have solved among the prior art that the jumbo size display panel that splice unit concatenation was accomplished has very big concatenation gap to the technical problem who watches the effect has been influenced.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a circuit board according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a circuit board according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a circuit board according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a circuit board according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a light-emitting circuit layer according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another light-emitting circuit layer according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
An embodiment of the present invention provides a schematic structural diagram of a display panel, and referring to fig. 1, thedisplay panel 10 includes: amounting plate 100; thesplicing units 200 arranged in an array are positioned on themounting plate 100, and eachsplicing unit 200 comprises aglass substrate 201; a lightemitting circuit layer 202 on thefront surface 2010 of theglass substrate 201, wherein the lightemitting circuit layer 202 comprises a plurality of signal lines; thecircuit board 203 is located therelative back 2011 that sets up ofglass substrate 201 and front, includes the signal routing layer that the multilayer stacked gradually to and be located the insulating layer between the adjacent signal routing layer, the signal routing layer is connected with the signal line that corresponds the setting through the first electrically conductive viahole 204 that runs through insulating layer andglass substrate 201,glass substrate 201 is in orthographic projection on themounting panel 100 is locatedcircuit board 203 is in the orthographic projection on themounting panel 100.
Fig. 1 exemplarily shows 4splicing units 200, and the number of the splicing units is not limited in the present embodiment.
In the present embodiment, the first conductive via 204 guides the electrical signals of the plurality of signal lines included in the light-emitting circuit layer 202 to theback 2011 of theglass substrate 201, and since the first conductive via 204 penetrates through the insulating layer of thecircuit board 203 and theglass substrate 201, the plurality of signal lines can be electrically connected through the first conductive via 204 and the signal routing layer included in thecircuit board 203. And the orthographic projection of theglass substrate 201 on themounting plate 100 is located in the orthographic projection of thecircuit board 203 on themounting plate 100, so that the electric connection of the signal line and the signal wiring is realized, the area of thesplicing units 200 for displaying is not occupied, and seamless splicing can be realized in the splicing process of thesplicing units 200 arranged in an array.
In the prior art, the light-emitting circuit layer 202 is located on thefront surface 2010 of theglass substrate 201, the light-emitting circuit layer 202 comprises a plurality of signal lines, the signal line layers are usually arranged on theglass substrate 201, and a large splicing gap exists in a large-size display panel which is spliced and finished by the splicing units, so that the technical problem of the viewing effect is influenced.
In the technical solution of this embodiment, the first conductive via 204 guides the electrical signals of the plurality of signal lines included in the lightemitting circuit layer 202 to theback 2011 of theglass substrate 201, and since the first conductive via 204 penetrates through the insulating layer of thecircuit board 203 and theglass substrate 201, the plurality of signal lines may be electrically connected through the first conductive via 204 and the signal routing layer included in thecircuit board 203.Glass substrate 201 is in orthographic projection on themounting panel 100 is locatedcircuit board 203 is in the orthographic projection on themounting panel 100, realized promptly that signal line and signal walk the electric connection of line, do not occupy the area that display element is used for showing, a plurality ofsplice unit 200 that the array was arranged can realize seamless concatenation at the in-process of concatenation, have solved among the prior art that the jumbo size display panel that the splice unit concatenation was accomplished has very big concatenation gap to the technical problem who watches the effect has been influenced.
Optionally, on the basis of the above technical solution, referring to fig. 1 and fig. 2, thedisplay panel 10 further includes adriving chip 300 disposed on thefront surface 2010 of theglass substrate 201 and electrically connected to thecircuit board 203 through aflexible circuit 400.
In this embodiment, thedriving chip 300 is disposed on thefront surface 2010 of theglass substrate 201, and is electrically connected to thecircuit board 203 through theflexible circuit 400, so that thedriving chip 300 is electrically connected to the signal routing layer included in thecircuit board 203. Note that a part of theflexible circuit 400 is located on thefront surface 2010 of theglass substrate 201, and a part of the flexible circuit is bent to theback surface 2011 of theglass substrate 201.
Alternatively, referring to fig. 2 and 3, theadjacent driving chips 300 are electrically connected to each other through the second conductive via 205 on theglass substrate 201, and a connection line connected to the second conductive via 205 is disposed on theback 2011 of theglass substrate 201. Fig. 2 and 3 show exemplary 9splicing units 200.
Optionally, on the basis of the above technical solution, referring to fig. 2 and fig. 3, thedriving chip 300 includes afirst sub-driving chip 301 and asecond sub-driving chip 302, where thefirst sub-driving chip 301 is disposed on thefirst side 11 of thedisplay panel 10, and/or is disposed on thesecond side 12 of the display panel parallel to and opposite to thefirst side 11; thesecond sub-driver chip 302 is disposed on athird side 13 of thedisplay panel 10 perpendicular to thefirst side 11, and/or on afourth side 14 of thedisplay panel 10 parallel to and opposite to thethird side 13.
Therefore, as can be seen from fig. 3, thesplicing units 200 are of 3 types, and the splicing unit located at 4 top corners of the display panel is referred to as a firsttype splicing unit 206, and includes aglass substrate 201 provided with two driving chips, namely afirst sub-driving chip 301 and asecond sub-driving chip 302; the non-vertexangle splicing unit 207 located at the side of thedisplay panel 10 is called a second type splicing unit, and includes aglass substrate 201 provided with a driving chip, which may be afirst sub-driving chip 301 or asecond sub-driving chip 302; the third type ofsplicing unit 208 is located in the middle of thedisplay panel 10, and includes aglass substrate 201 without a driving chip. The firsttype splicing unit 206, the secondtype splicing unit 207 and the thirdtype splicing unit 208 can realize display panels with any size.
Optionally, on the basis of the above technical solution, the signal lines include a plurality of data signal lines, a plurality of gate signal lines, a plurality of first power signal lines, and a plurality of second power signal lines; and/or, referring to fig. 4, the signal routing layer includes a datasignal routing layer 2031 electrically connected to the data signal line through apad 2035 disposed corresponding to the first conductive via 204; referring to fig. 5, the gatesignal wiring layer 2032 is electrically connected to the gate signal line through apad 2035 provided corresponding to the first conductive via 204; referring to fig. 6, the first powersignal wiring layer 2033 is electrically connected to the first power signal line through apad 2035 provided corresponding to the first conductive via 204; referring to fig. 7, and the second powersignal wiring layer 2034, are electrically connected to the second power signal line through apad 2035 provided corresponding to the first conductive via 204. Optionally, anexternal interface 2036 is further included for electrically connecting to peripheral circuits.
It should be noted that a straight line where the first conductive via 204 corresponding to thepad 2035 electrically connecting the data signal line and the datasignal routing layer 2031 in fig. 4 is located is perpendicular to a straight line where the first conductive via 204 corresponding to the gatesignal routing layer 2032 and the gate signal line electrically connectingpad 2035 in fig. 5 is located; in fig. 6, the first conductive via 204 of the first conductive via 204, which is correspondingly disposed between the first powersignal routing layer 2033 and the first power signal lineelectrical connection pad 2035, is located at a top corner of the splicing unit; the first conductive via 204 of the first conductive via 204, which is illustrated in fig. 7 and is disposed to correspond to the second power signalline routing layer 2034 and the second power signal lineelectrical connection pad 2035, is located at a top corner of the splice unit, and the first conductive via 204 of the first conductive via 204, which is illustrated in fig. 7 and is disposed to correspond to the second power signalline routing layer 2034 and the second power signal lineelectrical connection pad 2035, surrounds the first conductive via 204 of the first conductive via 204, which is disposed to correspond to the first power signalline routing layer 2033 and the first power signal lineelectrical connection pad 2035 in fig. 6.
Optionally, on the basis of the above technical solution, the gatesignal routing layers 2032 of the same row of thesplicing units 200 are electrically connected, the datasignal routing layers 2031 of the same column of thesplicing units 200 are electrically connected, the first powersignal routing layers 2033 of the same row of thesplicing units 200 are electrically connected, and the second powersignal routing layers 2034 of the same column of thesplicing units 200 are electrically connected. It can thus be achieved that the row oftile units 200 of the same row share one ormore driver chips 300, and thetile units 200 of the same column share one ormore driver chips 300.
Optionally, on the basis of the above technical solution, referring to fig. 8, the light-emitting circuit layer 202 further includes a light-emitting unit 2023 defined by eachdata signal line 2021 and eachgate signal line 2022 intersecting with each other, a first electrode of the light-emitting unit 2023 is electrically connected to thedata signal line 2021, and a second electrode of the light-emitting unit 2023 is electrically connected to thegate signal line 2022.
Optionally, on the basis of the above technical solution, referring to fig. 9, the lightemitting circuit layer 202 further includes a signal input circuit layer and a light emitting driving circuit layer, the signal input circuit layer is electrically connected to thedata signal line 2021 and thegate signal line 2022, the signal input circuit layer is configured to provide a driving power signal for the light emitting driving circuit layer, and the light emitting driving circuit layer is configured to drive thelight emitting unit 2023 to emit light. Illustratively, referring to fig. 9, the signal input wiring layer includes a first thin film transistor T1 and a capacitor C, and the light emission driving wiring layer includes a second thin film transistor T2. Wherein the first thin film transistor T1 and the second thin film transistor T2 are both P-type thin film transistors. Fig. 9 illustrates an exemplary circuit configuration of 2T1C, but the present embodiment is not limited thereto.
Referring to fig. 9, the first power signal line 2024(VSS) is electrically connected to the first powersignal wiring layer 2033, and the second power signal line 2025(VDD) is electrically connected to the first powersignal wiring layer 2034.
Optionally, on the basis of the above technical solution, thelight emitting unit 2023 includes a light emitting diode or an organic light emitting diode. The light emitting diode or the organic light emitting diode is a self-luminous light emitting unit, an optical system is simple, the size, the weight and the cost of the whole system can be reduced, and meanwhile, the characteristics of low power consumption, quick response and the like are considered.
Optionally, on the basis of the above technical solution, the light emitting diode includes a micro light emitting diode and/or a mini light emitting diode. The micro light-emitting diode and/or the mini light-emitting diode have small size, can reduce the pixel pitch from millimeter level to micron level, and has the advantages of self-luminescence, high brightness, low power consumption, high color gamut and the like, so that the display panel can display high-quality pictures and simultaneously reduce the production cost.
Based on the same inventive concept, the embodiment of the present invention further provides a display device, including thedisplay panel 10 according to any of the above technical solutions. The display device provided by the embodiment adopts the display panel, so that the display device has the same beneficial effects as the display panel.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising:
mounting a plate;
the splicing units are arranged on the mounting plate in an array mode and comprise glass substrates;
the light-emitting circuit layer is positioned on the front surface of the glass substrate and comprises a plurality of signal wires;
the circuit board is positioned on the back surface of the glass substrate opposite to the front surface, and comprises a plurality of signal wiring layers which are sequentially stacked and an insulating layer positioned between the adjacent signal wiring layers, the signal wiring layers are electrically connected with the signal wires which are correspondingly arranged through first conductive through holes which penetrate through the insulating layer and the glass substrate, and the orthographic projection of the glass substrate on the mounting plate is positioned in the orthographic projection of the circuit board on the mounting plate;
the splicing units also comprise a first type splicing unit, a second type splicing unit and a third type splicing unit;
the first type of splicing unit is positioned at the top corner position of the display panel and comprises a first sub-driving chip and a second sub-driving chip;
the second type of splicing unit is positioned at a non-vertex angle position of the side edge of the display panel and comprises the first sub-driving chip or the second sub-driving chip;
the third type of splicing unit is located in the middle of the display panel and is not provided with a driving chip.
2. The display panel according to claim 1,
the drive chip is arranged on the front surface of the glass substrate and is connected with the circuit board through a flexible circuit.
3. The display panel according to claim 2,
the driving chip comprises the first sub-driving chip and the second sub-driving chip, and the first sub-driving chip is arranged on a first side edge of the display panel and/or arranged on a second side edge of the display panel, which is parallel to and opposite to the first side edge;
the second sub-driver chip is arranged on a third side edge of the display panel, which is perpendicular to the first side edge, and/or on a fourth side edge of the display panel, which is parallel to and opposite to the third side edge.
4. The display panel according to claim 1,
the signal lines include a plurality of data signal lines, a plurality of gate signal lines, a plurality of first power signal lines, and a plurality of second power signal lines; and/or the presence of a gas in the gas,
the signal routing layer comprises a data signal routing layer which is electrically connected with the data signal line through a bonding pad which is arranged corresponding to the first conductive through hole; the grid signal wiring layer is electrically connected with the grid signal wire through a bonding pad which is arranged corresponding to the first conductive through hole; the first power supply signal routing layer is electrically connected with the first power supply signal line through a bonding pad which is arranged corresponding to the first conductive through hole; and a second power signal wiring layer electrically connected to the second power signal line through a pad disposed corresponding to the first conductive via.
5. The display panel according to claim 4,
the same row the grid signal routing layer electricity of concatenation unit is connected, same row the data signal routing layer electricity of concatenation unit is connected, same row the first power signal routing layer electricity of concatenation unit is connected, same row the second power signal routing layer electricity of concatenation unit is connected.
6. The display panel according to claim 4,
the light-emitting circuit layer further comprises light-emitting units, wherein each data signal line and each grid signal line are determined in a crossed mode, a first electrode of each light-emitting unit is electrically connected with the data signal line, and a second electrode of each light-emitting unit is electrically connected with the grid signal line.
7. The display panel according to claim 6,
the light-emitting circuit layer further comprises a signal input circuit layer and a light-emitting driving circuit layer, the signal input circuit layer is electrically connected with the data signal line and the grid signal line respectively, the signal input circuit layer is used for providing a driving power supply signal for the light-emitting driving circuit layer, and the light-emitting driving circuit layer is used for driving the light-emitting units to emit light.
8. The display panel according to claim 6,
the light emitting unit includes a light emitting diode or an organic light emitting diode.
9. The display panel according to claim 8,
the light emitting diode comprises a micro light emitting diode and/or a mini light emitting diode.
10. A display device comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010092488.0ACN111128048B (en) | 2020-02-14 | 2020-02-14 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010092488.0ACN111128048B (en) | 2020-02-14 | 2020-02-14 | Display panel and display device |
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| Publication Number | Publication Date |
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| CN111128048A CN111128048A (en) | 2020-05-08 |
| CN111128048Btrue CN111128048B (en) | 2022-03-08 |
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| CN202010092488.0AActiveCN111128048B (en) | 2020-02-14 | 2020-02-14 | Display panel and display device |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599306B (en)* | 2020-06-19 | 2021-06-22 | 熊周成 | LED display unit and LED display screen |
| US11495149B2 (en)* | 2020-08-24 | 2022-11-08 | PlayNitride Display Co., Ltd. | Display apparatus |
| CN112164326B (en)* | 2020-09-18 | 2021-07-13 | 熊周成 | Display circuit board, manufacturing method thereof and LED display screen |
| CN112562526A (en)* | 2020-12-11 | 2021-03-26 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| JP2022098886A (en)* | 2020-12-22 | 2022-07-04 | 日本放送協会 | Multi-display |
| CN112634774B (en)* | 2020-12-25 | 2023-03-24 | 深圳Tcl新技术有限公司 | Light source plate, display unit and display device |
| CN116072010A (en)* | 2021-11-02 | 2023-05-05 | 武汉华星光电半导体显示技术有限公司 | Splicing display panels and display devices |
| CN114695423B (en)* | 2022-03-23 | 2025-07-25 | 武汉华星光电半导体显示技术有限公司 | Spliced panel |
| CN114864624B (en)* | 2022-05-12 | 2023-08-08 | 滁州惠科光电科技有限公司 | Display panel and display |
| CN119255649B (en)* | 2024-02-29 | 2025-08-29 | 荣耀终端股份有限公司 | Display module, method for manufacturing display module, and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104460136A (en)* | 2014-12-30 | 2015-03-25 | 京东方科技集团股份有限公司 | Liquid crystal optical grating, manufacturing and drive methods thereof and spliced screen |
| CN104777681A (en)* | 2015-04-01 | 2015-07-15 | 上海中航光电子有限公司 | Array substrate and display panel |
| CN206773687U (en)* | 2017-04-28 | 2017-12-19 | 厦门天马微电子有限公司 | Touch-control display panel and touch control display apparatus |
| KR20190072197A (en)* | 2017-12-15 | 2019-06-25 | 엘지디스플레이 주식회사 | Tiling display device and apparatus for tiling thereof |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202178258U (en)* | 2011-06-30 | 2012-03-28 | 四川虹视显示技术有限公司 | OLED display, OLED display module group, and splicing structure of OLED display module group |
| CN102629059B (en)* | 2012-01-31 | 2015-05-27 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, liquid crystal panel and liquid crystal display |
| CN102751308B (en)* | 2012-07-02 | 2015-07-08 | 广东威创视讯科技股份有限公司 | Organic light emitting diode (OLED) display panel and OLED spliced display screen with same |
| WO2014043850A1 (en)* | 2012-09-18 | 2014-03-27 | 深圳市柔宇科技有限公司 | Large-size display screen and manufacturing method thereof |
| WO2014059601A1 (en)* | 2012-10-16 | 2014-04-24 | 深圳市柔宇科技有限公司 | Oled mosaic display screen and manufacturing method thereof |
| CN103077664B (en)* | 2013-01-15 | 2015-01-21 | 佛山鼎辉光电科技有限公司 | Flexible LED (Light Emitting Diode) display screen |
| CN203536440U (en)* | 2013-11-19 | 2014-04-09 | 四川虹视显示技术有限公司 | PMOLED tiled display screen |
| CN104614911A (en)* | 2015-03-03 | 2015-05-13 | 京东方科技集团股份有限公司 | Substrate as well as manufacturing method and display device thereof |
| US10211188B2 (en)* | 2016-12-01 | 2019-02-19 | Cheng Chang TransFlexDisplay Corp. | Method for making an LED module and module made thereof |
| EP3499052B1 (en)* | 2017-12-15 | 2021-11-17 | LG Display Co., Ltd. | Tiled display device and tiling apparatus therefor |
| CN109920804A (en)* | 2019-03-27 | 2019-06-21 | 京东方科技集团股份有限公司 | A display substrate and its preparation method and display device |
| CN110599946B (en)* | 2019-08-08 | 2021-11-16 | 长春希达电子技术有限公司 | High-density LED display box body based on TFT glass substrate and display screen |
- 2020
- 2020-02-14CNCN202010092488.0Apatent/CN111128048B/enactiveActive
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104460136A (en)* | 2014-12-30 | 2015-03-25 | 京东方科技集团股份有限公司 | Liquid crystal optical grating, manufacturing and drive methods thereof and spliced screen |
| CN104777681A (en)* | 2015-04-01 | 2015-07-15 | 上海中航光电子有限公司 | Array substrate and display panel |
| CN206773687U (en)* | 2017-04-28 | 2017-12-19 | 厦门天马微电子有限公司 | Touch-control display panel and touch control display apparatus |
| KR20190072197A (en)* | 2017-12-15 | 2019-06-25 | 엘지디스플레이 주식회사 | Tiling display device and apparatus for tiling thereof |
Non-Patent Citations (2)
| Title |
|---|
| "A high-throughput screen identifies small molecule";Jing Zhang;《Nucleic Acids Research》;20191230;第47卷(第07期);第3667–3679页* |
| "数字化投影系统边缘融合技术的应用与分析";郭斌;《数字技术与应用》;20171230(第04期);第242页* |
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