Disclosure of Invention
Since the starting power is directly related to the sensitivity of the (radio frequency) energy harvesting, the effective range of the radio frequency energy harvesting is affected. According to the background introduction above, current energy harvesting solutions with minimum starting power also require 3 μ W. In response to this problem, the present invention proposes a set of solutions with smaller starting power, namely a micro energy harvesting management system with low voltage start and voltage monitoring function, which reduces the energy harvesting starting power to 0.252 μ W.
According to one aspect of the present invention, a micro energy collection management system with low voltage start and voltage monitoring function for solving the technical problems comprises:
one end of the first energy storage device is grounded, the other end of the first energy storage device is connected with the output end of the RF-to-DC module, and the input end of the RF-to-DC module is connected with the radio frequency energy collecting antenna and used for converting the radio frequency energy into direct current for output;
a first voltage monitoring chip having an input port connected to the other end of the first energy storage device and an indication output port for indicating that the voltage input at the input port is greater than a voltage threshold V when the first voltage monitoring chip works normallyThresholdIf so, outputting a high level, otherwise, outputting a low level;
the S pole of the first N-type switching tube is grounded, and the G pole of the first N-type switching tube is connected with the indication output port;
one end of the first pull-up resistor is connected with the D pole of the first N-type switching tube, and the other end of the first pull-up resistor is connected with the other end of the first energy storage device;
the G pole of the first P-type switching tube is connected with the D pole of the first N-type switching tube, and the S pole of the first P-type switching tube is connected with the other end of the first energy storage device;
the S pole of the second N-type switching tube is connected with the other end of the first energy storage device;
one end of the input capacitor is grounded, and the other end of the input capacitor is connected with the D pole of the first P-type switching tube and the S pole of the second N-type switching tube respectively;
the two power input ends of the DC/DC conversion chip are connected with two ends of the input capacitor; minimum starting voltage V of DC/DC conversion chipIn_StartupIs less than or equal toStarting voltage V of first voltage monitoring chipThreshold;
One end of the second energy storage device is grounded, and the other end of the second energy storage device is connected with the output end of the DC/DC conversion chip;
the S pole of the second P-type MOS tube is connected with the other end of the second energy storage device, and the D pole of the second P-type MOS tube is used for connecting a power supply input terminal of a system load chip; the system load chip is provided with a high/low level output end;
the S pole of the third P-type MOS tube is connected with the other end of the second energy storage device, and the G pole of the third P-type MOS tube is connected with the D pole of the second P-type MOS tube;
the second voltage monitoring chip is provided with an input terminal and an indication output terminal, the input terminal of the second voltage monitoring chip is connected with the S pole of the third P-type MOS tube, when the indication output terminal is used for the normal work of the second voltage monitoring chip, when the voltage input by the input terminal is smaller than a voltage threshold value Vth, a low level is output, otherwise, a high level is output, the voltage of the high level is equal to the input voltage on the input terminal, and when the third P-type MOS tube is conducted, the high level is the voltage Vin of the second energy storage device;
one end of the second pull-up resistor is connected with the other end of the second energy storage device, and the other end of the second pull-up resistor is connected with the G pole of the second P-type MOS tube;
the D pole of the third N-type MOS tube is connected with the G pole of the second P-type MOS tube, and the S pole of the third N-type MOS tube is grounded;
the first voltage division current-limiting resistor is connected in series between the indication output terminal of the second voltage monitoring chip and the G pole of the third N-type MOS tube;
the second voltage-dividing current-limiting resistor is connected in series between the D pole of the second P-type MOS tube and the G pole of the third N-type MOS tube;
one end of the third pull-up resistor is connected with the D pole of the second P-type MOS tube, the other end of the third pull-up resistor is connected with the G pole of the second N-type switching tube, and the other end of the third pull-up resistor is used for being connected with the high/low level output end;
the first N-type switch tube is an NMOS and satisfies the following conditions: vDDL<VGS(th)<VThreshold,VGS(th)Is the threshold of the first N-type switch tubeVoltage, VDDLIs the minimum working voltage at which the first voltage monitoring chip can normally operate; or the first N-type switch tube is a PNP transistor and satisfies VDDL<Vbe<VThreshold,VbeIs static direct current voltage between the b pole and the e pole of the PNP transistor;
leakage current I of the first energy storage deviceLeakageQuiescent current I of first voltage monitoring chipMonitorSatisfies the following conditions: i isLeakage+IMonitor_≤360nA;VThreshold、VIn_StartupSatisfies the following conditions: vIn_Startup≤VThreshold≤0.7V。
According to another aspect of the present invention, the invention solves the technical problem by providing a micro energy collection management system with low voltage start and voltage monitoring function, comprising:
one end of the first energy storage device is grounded, the other end of the first energy storage device is connected with the output end of the RF-to-DC module, and the input end of the RF-to-DC module is connected with the radio frequency energy collecting antenna and used for converting the radio frequency energy into direct current for output;
a first voltage monitoring chip having an input port connected to the other end of the first energy storage device and an indication output port for indicating that the voltage input at the input port is greater than a voltage threshold V when the first voltage monitoring chip works normallyThresholdIf so, outputting a high level, otherwise, outputting a low level;
the S pole of the first N-type switching tube is grounded, and the G pole of the first N-type switching tube is connected with the indication output port;
one end of the first pull-up resistor is connected with the D pole of the first N-type switching tube, and the other end of the first pull-up resistor is connected with the other end of the first energy storage device;
the G pole of the first P-type switching tube is connected with the D pole of the first N-type switching tube, and the S pole of the first P-type switching tube is connected with the other end of the first energy storage device;
the S pole of the second N-type switching tube is connected with the other end of the first energy storage device;
one end of the input capacitor is grounded, and the other end of the input capacitor is connected with the D pole of the first P-type switching tube and the S pole of the second N-type switching tube respectively;
the two power input ends of the DC/DC conversion chip are connected with two ends of the input capacitor; minimum starting voltage V of DC/DC conversion chipIn_StartupLess than or equal to the starting voltage V of the first voltage monitoring chipThreshold;
One end of the second energy storage device is grounded, and the other end of the second energy storage device is connected with the output end of the DC/DC conversion chip;
the S pole of the second P-type MOS tube is connected with the other end of the second energy storage device, and the D pole of the second P-type MOS tube is used for connecting a power supply input terminal of a system load chip; the system load chip is provided with a high/low level output end;
the S pole of the third P-type MOS tube is connected with the other end of the second energy storage device, and the G pole of the third P-type MOS tube is connected with the D pole of the second P-type MOS tube;
the second voltage monitoring chip is provided with an input terminal and an indication output terminal, the input terminal of the second voltage monitoring chip is connected with the S pole of the third P-type MOS tube, when the indication output terminal is used for the normal work of the second voltage monitoring chip, when the voltage input by the input terminal is smaller than a voltage threshold value Vth, a low level is output, otherwise, a high level is output, the voltage of the high level is equal to the input voltage on the input terminal, and when the third P-type MOS tube is conducted, the high level is the voltage Vin of the second energy storage device;
one end of the second pull-up resistor is connected with the other end of the second energy storage device, and the other end of the second pull-up resistor is connected with the G pole of the second P-type MOS tube;
a G pole of the third N-type MOS tube is connected with the indication output terminal of the second voltage monitoring chip, a D pole of the third N-type MOS tube is connected with the G pole of the second P-type MOS tube, and an S pole of the third N-type MOS tube is grounded;
a G pole of the fourth N-type MOS tube is connected with a D pole of the second P-type MOS tube, the D pole is connected with the G pole of the second P-type MOS tube, and the S pole is grounded;
one end of the third pull-up resistor is connected with the D pole of the second P-type MOS tube, the other end of the third pull-up resistor is connected with the G pole of the second N-type switching tube, and the other end of the third pull-up resistor is used for being connected with the high/low level output end;
a first N-type switchThe tube is NMOS and satisfies: vDDL<VGS(th)<VThreshold,VGS(th)Is the threshold voltage, V, of the first N-type switch tubeDDLIs the minimum working voltage at which the first voltage monitoring chip can normally operate; or the first N-type switch tube is a PNP transistor and satisfies VDDL<Vbe<VThreshold,VbeIs static direct current voltage between the b pole and the e pole of the PNP transistor;
leakage current I of the first energy storage deviceLeakageQuiescent current I of first voltage monitoring chipMonitorSatisfies the following conditions: i isLeakage+IMonitor_≤360nA;VThreshold、VIn_StartupSatisfies the following conditions: vIn_Startup≤VThreshold≤0.7V。
Further, in the micro energy collection management system with low voltage start and voltage monitoring function of the invention, the first energy storage device is a tantalum capacitor, the first voltage monitoring chip is R3114Q071, and the DC/DC conversion chip is TPS 61098.
Further, in the micro energy collection management system with low voltage start and voltage monitoring function of the present invention, the system load chip is MSP430FR5969, and the second voltage monitoring chip is TPS3831, TPS3839, R3114 or R3116.
Further, in the micro energy collection management system with low voltage starting and voltage monitoring functions, the model of the first N-type switch tube is SSM3K56MFV, the model of the first P-type switch tube is 2SB815-7 transistor, and the model of the second N-type switch tube is SSM3K56 MFV.
Further, in the micro energy collection management system with low voltage starting and the voltage monitoring function, the first pull-up resistor is 1.3M omega, the third pull-up resistor is 1.3M omega, the input capacitor is 1 muF, and the first energy storage device is 0.1 muF.
Further, in the micro energy harvesting management system with low voltage start and voltage monitoring function of the present invention,
when the DC/DC conversion chip is started, the voltage on the first energy storage device begins to drop, the first P-type switch tube begins to be gradually disconnected due to the fact that VGS between the G pole and the S pole of the first P-type switch tube is reduced, and a feedback control loop formed by a third pull-up resistor and a second N-type switch tube maintains the conducting state of the first energy storage device and the DC/DC conversion chip after the DC/DC conversion chip is started; finally, the system load chip is started to run and controls the high/low level output port to output low level after a task is completed, so that the second N-type switching tube is switched from on to off, the DC/DC conversion chip is switched off, and a starting cycle is ended; the energy harvesting process continues with the next cycle being initiated when the voltage of the first energy storage device again reaches the voltage threshold of the first voltage monitoring chip.
Further, in the micro energy harvesting management system with low voltage start and voltage monitoring function of the present invention,
(1) the G pole initial state of the third P type MOS tube defaults to a low level, so that the voltage Vin on the second energy storage device meets the following conditions: when Vin is more than or equal to 0 and less than Vth _ pmos5, the third P-type MOS tube is disconnected, when Vth _ pmos5 is more than or equal to Vin and less than Vth, the third P-type MOS tube is connected to indicate that the output of the output terminal is low level, the third N-type MOS tube is disconnected at the moment, and the second P-type MOS tube is disconnected under the action of a second pull-up resistor, so that the input voltage of the power input terminal is 0V, and a system load chip is not powered and cannot be started; wherein Vth _ pmos5 represents the turn-on threshold voltage of the third P-type MOS transistor;
(2) when Vin is larger than or equal to Vth, the output of the indication output terminal is changed into high level, and the voltage of the G electrode of the third N-type MOS tube rises to the voltage
R3, R4 and
the magnitude of the first voltage-dividing current-limiting resistor, the magnitude of the second voltage-dividing current-limiting resistor, and the magnitude of the voltage output by the indicating output terminal are in this order, and R3 and R4 are set to satisfy: when the output of the indication output terminal becomes high level, R4 Vin/(R4+ R3) exceeds the minimum turn-on voltage of the third N-type MOS tube; at this time, the third N-type MOS tube is conducted, and then the second P-type MOS tubeThe system load chip is started, the voltage of the G pole of the third N-type MOS tube and the voltage of the G pole of the third P-type MOS tube rise to Vin, and the third P-type MOS tube is disconnected;
(3) the second voltage monitoring chip is powered down after the third P-type MOS tube is disconnected, the output of the indication output terminal goes low again, and the G voltage of the third N-type MOS tube is reduced to R3 Vin/(R4+ R3), and R3 and R4 are set to satisfy the following conditions: when the output of the indication output terminal changes to low level, R3 Vin/(R4+ R3) exceeds the minimum turn-on voltage of the third N-type MOS tube; at this time, the third N-type MOS transistor is still turned on, so that the start-up operation state of the system load chip can be maintained.
Further, in the micro energy collection management system with low voltage start and voltage monitoring function of the present invention, R4-R3-10M Ω.
Further, in the micro energy harvesting management system with low voltage start and voltage monitoring function of the present invention,
(1) the G pole initial state of the third P type MOS tube defaults to a low level, so that the voltage Vin on the second energy storage device meets the following conditions: when Vin is more than or equal to 0 and less than Vth _ pmos5, the third P-type MOS tube is disconnected, and when Vth _ pmos5 is more than or equal to Vin and less than Vth, the second P-type MOS tube is connected to indicate that the output of the output terminal is low level, the first N-type MOS tube is disconnected at the moment, and the second P-type MOS tube is disconnected under the action of a pull-up resistor, so that the input voltage of the power input terminal is 0V, and a system load chip is not powered and cannot be started; wherein Vth _ pmos5 represents the turn-on threshold voltage of the third P-type MOS transistor;
(2) when Vin is larger than or equal to Vth, the output of the indication output terminal is changed into high level, the third N-type MOS tube is conducted, and then the second P-type MOS tube is conducted, so that the input voltage of the power input terminal is Vin, on one hand, a system load chip is started, on the other hand, the voltage of the G pole of the third N-type MOS tube is increased to Vin, and the fourth N-type MOS tube is conducted; the voltage of the G pole of the third P-type MOS tube rises to Vin, and the third P-type MOS tube is disconnected;
(3) and after the third P-type MOS tube is disconnected, the second voltage monitoring chip is powered down, the output of the indication output terminal becomes low level, the third N-type MOS tube is disconnected, but the fourth N-type MOS tube is still connected, so that the starting operation state of the system load chip can be maintained.
The micro energy collection management system with low voltage starting and voltage monitoring functions, which is disclosed by the invention, has the following beneficial effects: the invention realizes a micro-energy collection and power management system which can be started at 0.7V and 360nA, reduces the energy collection starting power to 0.252 mu W, and can obviously improve the sensitivity of energy collection; the invention can be used for energy collection in the environments of weak illumination, low vibration intensity, small temperature difference and the like, and is particularly suitable for scenes based on radio frequency energy collection; through tests, the minimum radio frequency input power of-20.5 dBm @915MHz capable of running can be realized, and the spatial range of radio frequency energy collection can be effectively expanded; meanwhile, the normal electricity utilization of the system is ensured by adding a voltage monitoring function.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a first embodiment of a micro energy collection and management system with low voltage start and voltage monitoring function, the micro energy collection and management system capable of starting at 0.7V and 360nA of the present embodiment includes: the voltage monitoring circuit comprises a first energy storage device C1, a first voltage monitoring chip U1, a first N-type switching tube Q1, a first pull-up resistor R1, a first P-type switching tube Q2, a second N-type switching tube Q3, an input capacitor C2, a DC/DC conversion chip U2, a second energy storage device C3, a second P-type MOS tube Q4, a third P-type MOS tube Q5, a second voltage monitoring chip U3, a second pull-up resistor R2, a third N-type MOS tube Q6, a first voltage division current limiting resistor R3, a second voltage division current limiting resistor R4, a decoupling capacitor C4 and a third pull-up resistor R5.
The first energy storage device C1 has a lower end grounded and an upper end connected to the output end (right side) of the RF-to-DC module RFDC, wherein the input end (left side) of the RF-to-DC module RFDC is connected to the RF energy collecting antenna TX for converting the RF energy into DC power for output. The first energy storage device C1 may be a capacitor, a super capacitor, a battery, etc. having a charge storage function, and should have low leakage current and low self-discharge characteristics, the capacity of the first energy storage device C1 should be determined according to the power consumption of the system load chip U4 when the system load chip U4 is started and operated once, the invention takes 220 muf tantalum capacitor as an example, the leakage current ILeakageLess than 10 nA.
The first voltage monitor chip U1 has an input port VIN and an indication output port
The input port VIN is connected with the upper end of the first energy storage device C1 to indicate the output port
When the first voltage monitoring chip works normally, the voltage input at the input port VIN is greater than the voltage threshold V
ThresholdWhen the voltage is high, the high level is output, otherwise, the low level is output. The first voltage monitoring chip U1 generally comprises a reference voltage source, a resistor divider network, and a voltage comparator, and is capable of continuously monitoring the supply voltage VIN.
When VIN is more than 0V and less than V
DDLIn time of abnormal operation, the output port is indicated due to the sub-threshold characteristic of the MOSFET inside the first voltage monitor chip U1
While outputting a high level, indicating an output port
Output voltage of
Selecting a suitable Q1 to make its threshold V
GS(th)>V
DDLThen Q1 does not conduct and Q2 does not conduct and the first energy storage device C1 continues to accumulate energy. Wherein V
DDLIs the minimum operating voltage at which the first voltage monitor U1 can function properly.
When V is
DDL<VIN<V
ThresholdTime, indicate the output port
At low, Q1 and Q2 are still not conductive, as above.
When V is
ThresholdWhen VIN is less than or equal to the output port
Output high level
Selecting an appropriate Q1 to make it V
GS(th)<V
ThresholdThen Q1 turns on and Q2 also turns on and the buck/boost circuit (i.e., DC/DC converter chip) U2 starts to start.
The S pole of the first N-type switching tube Q1 is grounded, and the G pole is connected with the indication output port
One end of the first pull-up resistor R1 is connected to the D pole of the first N-type switch tube Q1, and the other end is connected to the upper end of the first energy storage device C1.
The G pole of the first P-type switch tube Q2 is connected with the D pole of the first N-type switch tube Q1, and the S pole is connected with the upper end of the first energy storage device C1.
The S pole of the second N-type switching tube Q3 is connected with the upper end of the first energy storage device C1.
The lower end of the input capacitor C3 is grounded, and the upper end is connected to the D pole of the first P-type switch Q2 and the S pole of the second N-type switch Q3, respectively.
The DC/DC conversion chip U2 has two power input terminals VIN and GND connected to two ends of the input capacitor C2. The DC/DC conversion chip U2 has a DC-to-DC conversion function, and can be a switch step-up/step-down or LDO circuit, and it should be noted that the minimum starting voltage of the DC/DC conversion chip U2VIn_StartupShould be less than or equal to the starting voltage V of the electric voltage monitoring chip U1ThresholdAnd has wider input voltage range and higher power conversion efficiency as much as possible. Taking the DC/DC conversion chip U2 as TPS61098 as an example, the minimum start voltage may be lower than 0.7V. In addition, the value of the input capacitor C2 is also critical, and too small a value will cause DC-DC instability, while too large a value will cause VStorage to drop too fast, so that Q2 is turned off early due to too small VGS. The present invention takes C2 ═ 1 μ F as an example.
The lower end of the second energy storage device C3 is grounded, and the upper end of the second energy storage device C3 is connected with the output end of the DC/DC conversion chip U2; the system load chip U4 has a high/low output I/O. In this manner, the system load chip U4 may be powered by two capacitors. The lower end of the second energy storage device C3 is grounded, and the upper end is used for connecting the DC/DC conversion chip U2 at the left end, so that the DC/DC conversion chip U2 charges the second energy storage device C3, and the voltage Vin across the second energy storage device C3 gradually increases until the maximum voltage value, that is, the voltage value output by the DC/DC conversion chip U2, is reached. The second energy storage device C3 includes a capacitor, a battery, and a super capacitor. In this embodiment, the second energy storage device C3 is greater than or equal to the first energy storage capacitor C1, and in another embodiment of the present invention, the second energy storage device C4 may be smaller than the first energy storage capacitor C1.
The S pole of the second P-type MOS transistor Q4 is connected with the other end of the second energy storage device C3, and the D pole is used for connecting a power supply input terminal VCC of a system load chip U4; the system load chip U4 has a high/low output I/O.
The S pole of the third P-type MOS transistor Q5 is connected with the other end of the second energy storage device C3, and the G pole is connected with the D pole of the second P-type MOS transistor Q4.
The second voltage monitoring chip U3 has an input terminal VIN and an indication output terminal
The input terminal VIN of the second voltage monitor chip U3 is connected to the S pole of the third P-type MOS transistor Q5, and the indication output terminal
ForWhen the second voltage monitoring chip U3 works normally, when the voltage input from the input terminal VIN is smaller than the voltage threshold Vth, a low level is output, otherwise, a high level is output, the voltage of the high level is equal to the input voltage at the input terminal, and when the third P-type MOS transistor Q5 is turned on, the high level is the voltage VIN of the second energy storage device C3. The second voltage monitor chip U3 may employ TPS3831, TPS3839, R3114, R3116.
One end of the second pull-up resistor R2 is connected to the other end of the second energy storage device C3, and the other end is connected to the G electrode of the second P-type MOS transistor Q4.
The D pole of the third N-type MOS transistor Q6 is connected with the G pole of the second P-type MOS transistor Q4, and the S pole is grounded.
The first voltage-dividing current-limiting resistor R3 is connected in series with the indication output terminal of the second voltage monitoring chip U3
And the G pole of the third N-type MOS transistor Q6.
The second voltage-dividing current-limiting resistor R4 is connected in series between the D pole of the second P-type MOS transistor Q4 and the G pole of the third N-type MOS transistor Q6.
One end of the third pull-up resistor R5 is connected to the D-pole of the second P-type MOS transistor Q4, the other end is connected to the G-pole of the second N-type switching transistor Q3, and the other end of the third pull-up resistor R5 is used for connecting the high/low level output terminal I/O. In this embodiment, the magnitude of the third pull-up resistor R6 is 1.3M Ω.
The lower end of the decoupling capacitor C4 is grounded, the upper end of the decoupling capacitor C4 is connected to the upper end of the third P-type MOS transistor Q4 and is used for being connected to the power input terminals VCC and GND of the system load chip U4, and the decoupling capacitor C4 is used for power supply decoupling of the system load chip U4, where in the present invention, the second decoupling capacitor C5 is 0.22 μ F as an example.
The first N-type switch Q1 is NMOS and satisfies: vDDL<VGS(th)<VThreshold,VGS(th)Is the threshold voltage, V, of the first N-type switch tube Q1DDLIs the minimum operating voltage at which the first voltage monitor chip U1 can function properly; or, the first N-type switch tube Q1 is a PNP transistor and satisfies VDDL<Vbe<VThreshold,VbeIs a PNP crystalStatic dc voltage between the b and e poles of the tube. In addition, the first voltage monitor chip U1 should have the lowest possible threshold voltage VThresholdAnd quiescent current IMonitorIn this embodiment, the first voltage monitoring chip U1 is R3114Q071, VThreshold=0.7V,IMonitorA typical value of (a) is 350 nA.
Leakage current I of first energy storage device C1LeakageQuiescent current I of the first voltage monitor chip U1MonitorSatisfies the following conditions: i isLeakage+IMonitor_≤360nA;VThreshold、VIn_StartupSatisfies the following conditions: vIn_Startup≤VThreshold≤0.7V。
In this embodiment, the system load chip U4 is MSP430FR5969, the P-type switch tube Q2 is a PMOS or NPN transistor, the second N-type switch tube Q3 is an NMOS, the first N-type switch tube Q1 is a SSM3K56MFV, the first P-type switch tube Q2 is a 2SB815-7 transistor, and the second N-type switch tube Q3 is a SSM3K56 MFV. The first pull-up resistor R1 is 1.3M omega, and the third pull-up resistor R2 is 1.3M omega.
When the DC/DC conversion chip is started, the voltage of the first energy storage device C1 will start to drop, the P-type switch Q2 will start to be gradually disconnected due to the reduction of VGS between the G pole and the S pole of the P-type switch Q2 (before disconnection, the power supply has a voltage monitoring function, and after disconnection, the power supply does not have), a feedback control loop composed of the third pull-up resistor R5 and the second N-type switch Q3 will maintain the conducting state of the first energy storage device C1 and the DC/DC conversion chip after the DC/DC conversion chip is started; finally, the system load chip U4 is started to operate and controls the high/low level output port I/O to output low level after completing one task, so that the second N-type switch tube Q3 is changed from on to off, and the DC/DC conversion chip U2 is turned off, and a starting cycle is ended; the energy harvesting process continues, starting the next cycle when the voltage of the first energy storage device C1 again reaches the voltage threshold of the first voltage monitor chip U1.
The working principle of the voltage monitoring part is as follows:
(1) the initial state of the G pole of the third P-type MOS transistor Q5 defaults to a low level, so the voltage Vin across the second energy storage device C3 satisfies: when Vin is more than or equal to 0 and less than Vth _ pmos5, the third P-type MOS tube Q5 is disconnected, when Vth _ pmos5 is more than or equal to Vin and less than Vth, the third P-type MOS tube Q5 is connected to indicate that the output of the output terminal is low level, at the moment, the third N-type MOS tube Q6 is disconnected, and the second P-type MOS tube Q4 is disconnected under the action of the second pull-up resistor R2, so that the input voltage of the power supply input terminal VCC is 0V, and the system load chip U4 is not powered and cannot be started; wherein Vth _ pmos5 represents the turn-on threshold voltage of the third P-type MOS transistor Q5.
(2) When Vin is greater than or equal to Vth, the output of the indication output terminal changes to high level, and the voltage of the G pole of the third N-type MOS transistor Q6 rises to the voltage
R3, R4 and
the first voltage-dividing current-limiting resistor R3, the second voltage-dividing current-limiting resistor R4 and the voltage output by the indicating output terminal are sequentially arranged, and R3 and R4 are set to satisfy: when the output of the indication output terminal becomes high level, R4 Vin/(R4+ R3) exceeds the minimum turn-on voltage of the third N-type MOS tube Q6; at this time, the third N-type MOS transistor Q6 is turned on, then the second P-type MOS transistor Q4 is turned on, the system load chip U4 is turned on, the voltages of the G-pole of the third N-type MOS transistor Q6 and the G-pole of the third P-type MOS transistor Q5 rise to Vin, and the third P-type MOS transistor Q5 is turned off.
(3) The second voltage monitoring chip U3 is powered down after the third P-type MOS transistor Q5 is turned off, the output of the indication output terminal goes low again, and then the G-voltage of the third N-type MOS transistor Q6 drops to R3 × Vin/(R4+ R3), and R3 and R4 are set to satisfy: when the output of the indication output terminal changes to low level, R3 Vin/(R4+ R3) exceeds the minimum turn-on voltage of the third N-type MOS tube Q6; at this time, the third N-type MOS transistor Q6 is still turned on, so that the startup operation state of the system load chip U4 can be maintained.
In the present embodiment, the current consumption (without calculating the system load chip and other system loads) after the voltage monitoring part (the circuit between Vin to C4) is started up is mainly: VCC/R2 and VCC/(R3+ R4). In this embodiment, the larger the resistances of the second pull-up resistor R2, the first voltage-dividing current-limiting resistor R3 and the second voltage-dividing current-limiting resistor R4 are, the smaller the power consumed by them is, so in this embodiment, the larger the values of the second pull-up resistor R2, the first voltage-dividing current-limiting resistor R3 and the second voltage-dividing current-limiting resistor R4 should be, and in this embodiment, the sizes of R2, R3 and R4 satisfy: r2 ═ R3 ═ R4 ═ 10M Ω.
The circuit characteristics of the voltage monitoring section of the present embodiment are: the power supply valve is positioned at a VCC power supply end, so that the integrity of a system ground plane is ensured; after system startup, using VCC and VCC

The voltage division of the resistor maintains the Q2 to be conducted, thereby leading the Q1 to be conducted, continuously supplying power to the system, and starting and maintaining do not need digital logic control in the system load; the voltage monitor integrated chip is adopted, so that the integration level is high, the circuit composition is simple, the cost is low, the part of operation power consumption is reduced to the lowest 150nA from uA level (the power consumption of the second voltage monitoring chip U3, namely I _ U3 when the voltage monitoring chip is not turned off), after the system is started, the power supply of the second voltage monitoring chip U3 is turned off through Q4, and the part of current consumption is reduced to VCC/R1+ VCC/(R2+ R3) after the system is started.
Referring to fig. 2, fig. 2 is a circuit schematic of a first embodiment of a micro energy harvesting management system with voltage monitoring capability that can be enabled at 0.7V,360 nA. The micro energy collection management system capable of starting at 0.7V and 360nA of the embodiment comprises: the voltage monitoring circuit comprises a first energy storage device C1, a first voltage monitoring chip U1, a first N-type switching tube Q1, a first pull-up resistor R1, a first P-type switching tube Q2, a second N-type switching tube Q3, an input capacitor C2, a DC/DC conversion chip U2, a second energy storage device C3, a second P-type MOS tube Q4, a third P-type MOS tube Q5, a second voltage monitoring chip U3, a second pull-up resistor R2, a third N-type MOS tube Q6, a fourth N-type MOS tube Q7, a decoupling capacitor C4 and a third pull-up resistor R3.
The first energy storage device C1 has a lower end grounded and an upper end connected to the output (right side) of the RF-to-DC module RFDC, wherein the input (left side) of the RF-to-DC module RFDC is connected to the RF energy collecting antenna TX for converting RF energy into RF energyAnd outputting the direct current. The first energy storage device C1 may be a capacitor, a super capacitor, a battery, etc. having a charge storage function, and should have low leakage current and low self-discharge characteristics, the capacity of the first energy storage device C1 should be determined according to the power consumption of the system load chip U4 when the system load chip U4 is started and operated once, the invention takes 220 muf tantalum capacitor as an example, the leakage current ILeakageLess than 10 nA.
The first voltage monitor chip U1 has an input port VIN and an indication output port
The input port VIN is connected with the upper end of the first energy storage device C1 to indicate the output port
When the first voltage monitoring chip works normally, the voltage input at the input port VIN is greater than the voltage threshold V
ThresholdWhen the voltage is high, the high level is output, otherwise, the low level is output. The first voltage monitoring chip U1 generally comprises a reference voltage source, a resistor divider network, and a voltage comparator, and is capable of continuously monitoring the supply voltage VIN.
When VIN is more than 0V and less than V
DDLIn time of abnormal operation, the output port is indicated due to the sub-threshold characteristic of the MOSFET inside the first voltage monitor chip U1
While outputting a high level, indicating an output port
Output voltage of
Selecting a suitable Q1 to make its threshold V
GS(th)>V
DDLThen Q1 does not conduct and Q2 does not conduct and the first energy storage device C1 continues to accumulate energy. Wherein V
DDLIs the minimum operating voltage at which the first voltage monitor U1 can function properly.
When V is
DDL<VIN<V
ThresholdTime, indicate the output port
At low, Q1 and Q2 are still not conductive, as above.
When V is
ThresholdWhen VIN is less than or equal to the output port
Output high level
Selecting an appropriate Q1 to make it V
GS(th)<V
ThresholdThen Q1 turns on and Q2 also turns on and the buck/boost circuit (i.e., DC/DC converter chip) U2 starts to start.
The S pole of the first N-type switching tube Q1 is grounded, and the G pole is connected with the indication output port
One end of the first pull-up resistor R1 is connected to the D pole of the first N-type switch tube Q1, and the other end is connected to the upper end of the first energy storage device C1.
The G pole of the first P-type switch tube Q2 is connected with the D pole of the first N-type switch tube Q1, and the S pole is connected with the upper end of the first energy storage device C1.
The S pole of the second N-type switching tube Q3 is connected with the upper end of the first energy storage device C1.
The lower end of the input capacitor C3 is grounded, and the upper end is connected to the D pole of the first P-type switch Q2 and the S pole of the second N-type switch Q3, respectively.
The DC/DC conversion chip U2 has two power input terminals VIN and GND connected to two ends of the input capacitor C2. The DC/DC conversion chip U2 has a DC-to-DC conversion function, and can be a switch buck/boost or LDO circuit, and it should be noted that the minimum starting voltage V of the DC/DC conversion chip U2In_StartupShould be less than or equal to the starting voltage V of the electric voltage monitoring chip U1ThresholdAnd has wider input voltage range and higher power conversion efficiency as much as possible. Taking the DC/DC conversion chip U2 as TPS61098 as an example, the minimum start voltage may be lower than 0.7V. In addition, input electricityThe value of C2 is also critical, and too small results in unstable DC-DC, and too large results in too fast VStorage reduction, so that Q2 is turned off early due to too small VGS. The present invention takes C2 ═ 1 μ F as an example.
The lower end of the second energy storage device C3 is grounded, and the upper end of the second energy storage device C3 is connected with the output end of the DC/DC conversion chip U2; the system load chip U4 has a high/low output I/O. In this manner, the system load chip U4 may be powered by two capacitors. The lower end of the second energy storage device C3 is grounded, and the upper end is used for connecting the DC/DC conversion chip U2 at the left end, so that the DC/DC conversion chip U2 charges the second energy storage device C3, and the voltage Vin across the second energy storage device C3 gradually increases until the maximum voltage value, that is, the voltage value output by the DC/DC conversion chip U2, is reached. The second energy storage device C3 includes a capacitor, a battery, and a super capacitor. In this embodiment, the second energy storage device C3 is greater than or equal to the first energy storage capacitor C1, and in another embodiment of the present invention, the second energy storage device C4 may be smaller than the first energy storage capacitor C1.
The S pole of the second P-type MOS transistor Q4 is connected with the other end of the second energy storage device C3, and the D pole is used for connecting a power supply input terminal VCC of a system load chip U4; the system load chip U4 has a high/low output I/O.
The S pole of the third P-type MOS transistor Q5 is connected with the other end of the second energy storage device C3, and the G pole is connected with the D pole of the second P-type MOS transistor Q4.
The second voltage monitoring chip U3 has an input terminal VIN and an indication output terminal
The input terminal VIN of the second voltage monitor chip U3 is connected to the S pole of the third P-type MOS transistor Q5, and the indication output terminal
When the second voltage monitoring chip U3 works normally, when the voltage input from the input terminal VIN is smaller than the voltage threshold Vth, a low level is output, otherwise, a high level is output, the high level voltage is equal to the input voltage at the input terminal, and when the third P-type MOS transistor Q5 is turned on, the high level is the second energy storageVoltage Vin of piece C3. The second voltage monitor chip U3 may employ TPS3831, TPS3839, R3114, R3116.
One end of the second pull-up resistor R2 is connected to the other end of the second energy storage device C3, and the other end is connected to the G electrode of the second P-type MOS transistor Q4.
The G pole of the third N-type MOS tube Q6 is connected with the indication output terminal of the second voltage monitoring chip U3, the D pole is connected with the G pole of the second P-type MOS tube Q4, and the S pole is grounded;
and a G pole of the fourth N-type MOS transistor Q7, a G pole of the fourth N-type MOS transistor Q7 is connected with a D pole of the second P-type MOS transistor Q4, the D pole is connected with a G pole of the second P-type MOS transistor Q4, and the S pole is grounded.
One end of the third pull-up resistor R3 is connected to the D-pole of the second P-type MOS transistor Q4, the other end is connected to the G-pole of the second N-type switching transistor Q3, and the other end of the third pull-up resistor R3 is used for connecting the high/low level output terminal I/O. In this embodiment, the magnitude of the third pull-up resistor R6 is 1.3M Ω.
The lower end of the decoupling capacitor C4 is grounded, the upper end of the decoupling capacitor C4 is connected to the upper end of the third P-type MOS transistor Q4 and is used for being connected to the power input terminals VCC and GND of the system load chip U4, and the decoupling capacitor C4 is used for power supply decoupling of the system load chip U4, where in the present invention, the second decoupling capacitor C5 is 0.22 μ F as an example.
The first N-type switch Q1 is NMOS and satisfies: vDDL<VGS(th)<VThreshold,VGS(th)Is the threshold voltage, V, of the first N-type switch tube Q1DDLIs the minimum operating voltage at which the first voltage monitor chip U1 can function properly; or, the first N-type switch tube Q1 is a PNP transistor and satisfies VDDL<Vbe<VThreshold,VbeIs static direct current voltage between the b pole and the e pole of the PNP transistor. In addition, the first voltage monitor chip U1 should have the lowest possible threshold voltage VThresholdAnd quiescent current IMonitorIn this embodiment, the first voltage monitoring chip U1 is R3114Q071, VThreshold=0.7V,IMonitorA typical value of (a) is 350 nA.
Leakage current I of first energy storage device C1LeakageQuiescent current I of the first voltage monitor chip U1MonitorSatisfies the following conditions: i isLeakage+IMonitor_≤360nA;VThreshold、VIn_StartupSatisfies the following conditions: vIn_Startup≤VThreshold≤0.7V。
In this embodiment, the system load chip U4 is MSP430FR5969, the P-type switch tube Q2 is a PMOS or NPN transistor, the second N-type switch tube Q3 is an NMOS, the first N-type switch tube Q1 is a SSM3K56MFV, the first P-type switch tube Q2 is a 2SB815-7 transistor, and the second N-type switch tube Q3 is a SSM3K56 MFV. The first pull-up resistor R1 is 1.3M omega, and the third pull-up resistor R2 is 1.3M omega.
When the DC/DC conversion chip is started, the voltage of the first energy storage device C1 will start to drop, the P-type switch Q2 will start to be gradually disconnected due to the reduction of VGS between the G pole and the S pole of the P-type switch Q2 (before disconnection, the power supply has a voltage monitoring function, and after disconnection, the power supply does not have), a feedback control loop composed of the third pull-up resistor R5 and the second N-type switch Q3 will maintain the conducting state of the first energy storage device C1 and the DC/DC conversion chip after the DC/DC conversion chip is started; finally, the system load chip U4 is started to operate and controls the high/low level output port I/O to output low level after completing one task, so that the second N-type switch tube Q3 is changed from on to off, and the DC/DC conversion chip U2 is turned off, and a starting cycle is ended; the energy harvesting process continues, starting the next cycle when the voltage of the first energy storage device C1 again reaches the voltage threshold of the first voltage monitor chip U1.
The operating principle of the voltage monitoring section (circuit between Vin to C4) is:
(1) the initial state of the G pole of the third P-type MOS transistor Q5 defaults to a low level, so the voltage Vin across the second energy storage device C3 satisfies: when Vin is more than or equal to 0 and less than Vth _ pmos5, the third P-type MOS tube Q5 is disconnected, and when Vth _ pmos5 is more than or equal to Vin and less than Vth, the second P-type MOS tube Q4 is connected to indicate that the output of the output terminal is at a low level, at the moment, the first N-type MOS tube is disconnected, and the second P-type MOS tube Q4 is disconnected under the action of a pull-up resistor, so that the input voltage of the power input terminal VCC is 0V, and the system load chip U4 is not powered and cannot be started; wherein Vth _ pmos5 represents the turn-on threshold voltage of the third P-type MOS transistor Q5.
(2) When Vin is greater than or equal to Vth, the indication output terminal
When the output of the third N-type MOS transistor Q6 becomes a high level, the third N-type MOS transistor Q6 is turned on, and then the second P-type MOS transistor Q4 is turned on, so that the input voltage of the power input terminal VCC is Vin, at this time, on one hand, the system load chip U4 is started, on the other hand, the voltage of the G-pole of the third N-type MOS transistor Q6 rises to Vin, and the fourth N-type MOS transistor Q7 is turned on; the voltage of the G electrode of the third P-type MOS transistor Q5 rises to Vin, and the third P-type MOS transistor Q5 is turned off.
(3) After the third P-type MOS transistor Q5 is turned off, the second voltage monitoring chip U3 is powered down, the output of the indication output terminal goes low again, the third N-type MOS transistor Q6 is turned off, but the fourth N-type MOS transistor Q7 is still turned on, so that the startup operation state of the system load chip U4 can be maintained.
In this embodiment, the current consumption (without calculating the system load chip and other system loads) after the voltage monitoring part is started is mainly: the second voltage monitors the current I _ U3 consumed by the chip U3 and VCC/R2. In this embodiment, the larger the second pull-up resistor R2 is, the smaller the consumed power is, so in this embodiment, the second pull-up resistor R2 should take a larger value, and in this embodiment, R2 takes a value of 10M Ω.
The circuit characteristics of the voltage monitoring section of the present embodiment are: the power supply valve is positioned at a VCC power supply end, so that the integrity of a system ground plane is ensured; after the system is started, Q7 is conducted by VCC, so that Q4 is maintained to be conducted, power is continuously supplied to the system, and digital logic control in system loads is not needed for starting and maintaining; the voltage monitor integrated chip is adopted, so that the integration level is high, the circuit composition is simple, the cost is low, the part of operation power consumption is reduced to the lowest 150nA from uA level (the power consumption of the second voltage monitoring chip U3, namely I _ U3 when the voltage monitoring chip is not turned off), after the system is started, the power supply of the second voltage monitoring chip U3 is turned off through Q5, and the part of current consumption is reduced to VCC/R2 after the system is started.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.