CN110993566A - A method for directional self-assembly and mask-controlled fabrication of semiconductor nanostructures - Google Patents

Abstract

The invention discloses a method for preparing a semiconductor nano structure by directional self-assembly and mask regulation, which comprises the steps of forming a double-layer hard mask layer, a photoetching stack layer and a buffer layer on a semiconductor substrate, spin-coating a Block Copolymer (BCP) layer on the buffer layer, and annealing to form a self-assembly template pattern; and then removing a certain block to form a photoetching pattern, transferring the pattern to the buffer layer, the photoetching stacking layer and the second hard mask layer in sequence, depositing a dielectric layer on the patterned second hard mask layer, then flattening, removing the second hard mask layer, and transferring the pattern to the first mask layer and the semiconductor substrate by taking the patterned dielectric layer as a mask. The invention can greatly overcome the problem of directional self-assembly caused by the thickness of the block copolymer and low etching selectivity among different block molecules in the existing pattern transfer process.

Description

Method for preparing semiconductor nano structure by directional self-assembly and mask regulation

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for preparing a semiconductor nano structure by directional self-assembly and mask regulation.

Background

Over fifty years, various technologies have been continuously developed to drive the semiconductor industry forward, and despite many challenges, moore's law has been maintained for the history of continuous innovation. As it becomes increasingly difficult to improve the performance of CMOS devices by continuous scaling, other methods for improving device performance, in addition to scaling, become critical.

Currently, the use of non-planar semiconductor devices, such as semiconductor fin field effect transistors (finfets), has pushed CMOS devices forward from the 22nm technology node. FinFET devices can achieve higher drive currents with smaller and smaller dimensions than conventional planar devices. In a FinFET device, a functional gate structure spans across a semiconductor fin. With the further development of the technology, in the coming years, the stacked wrap gate nanowire device may be widely used to replace the FinFET device at the 3nm or 2nm technology node. But the fabrication process is mostly compatible with FinFET devices, especially Fin formation processes.

Advanced technology nodes require high density of semiconductor fins and precise customization capabilities. The advent of new integrated circuits in each generation, through which lithography is one of the core fabrication technologies supporting the above-mentioned generations of integrated circuit devices, is always marked by the main technical hallmarks of achieving smaller feature sizes with lithography processes. However, optical lithography has inherent limitations for minimum size, which is determined by the wavelength of the light.

Directed self-assembly (DSA) is a novel patterning process that uses Block Copolymer (BCP) materials to form periodic structures, such as one-dimensional arrays of semiconductor line structures. The method has the advantages of low cost, high pattern resolution and the like, has unique advantages in the aspects of large-area regular pattern manufacturing and through hole manufacturing, and has attracted extensive attention in recent years. DSA techniques use a restrictive structural or chemical directing pattern to direct BCP to a predetermined location and anneal to form the desired morphology.

In more than ten years, the preparation of nano-structures and nano-devices by constructing self-assembly templates has become a current research hotspot. The key point is that the template is prepared by self-assembly of the block copolymer (template preparation), a photoetching pattern is further formed, and the photoetching pattern is transferred to the substrate by a dry etching technology (template transfer), so that the nano-structure array and the nano-device with controllable different sizes can be prepared. Different patterns, such as spherical, columnar, lamellar and the like, can be formed by changing the chain length, the composition, the annealing condition and the like of the block copolymer to perform oriented self-assembly in a film, a hole and a groove.

By a directed self-assembly process, high density (e.g., below 30nm pitch) line/space arrays can be achieved. However, the surface morphology of the block copolymer self-assembly is closely related to its thickness, so the thickness of the block copolymer material is typically below 50nm, and the higher the resolution, the lower the thickness; meanwhile, the etching selection among different block molecules is lower, and great challenges are provided for the control of key size, uniformity and accurate control of line roughness.

In particular, when one of the blocks is removed, because of the low etch selectivity between the blocks, the CD and thickness of the remaining blocks are difficult to control precisely, and there are problems that the CD becomes large and the thickness becomes small, which poses a serious challenge to the control of the etch process.

In view of the foregoing, there is a need for a method for more reliably and uniformly fabricating high density semiconductor nanostructures that overcomes the problem of control of the directed self-assembly process caused by the prior art pattern transfer process. The invention provides a novel self-assembly pattern transfer method, which is used for controlling CD better through fine regulation and control of a mask, so that the pattern can be transferred to a substrate structure with high fidelity. Arrays of Fins in FinFET devices and arrays of nanowires in gate-all Nanowire (GAA Nanowire) devices can then be fabricated in semiconductor substrates, or used to fabricate devices or structures for other applications such as gratings in optoelectronic devices, according to particular needs.

Disclosure of Invention

The invention provides a method for preparing a high-density semiconductor structure with high reliability, which can greatly overcome the problem of directional self-assembly caused by the thickness of a block copolymer and low etching selectivity among different block polymer molecules in the existing pattern transfer process. The method specifically comprises the following steps:

providing a semiconductor substrate, sequentially forming a first hard mask layer, a second hard mask layer and a photoetching stacking layer on the semiconductor substrate, and forming a plurality of guide structure patterns on the photoetching stacking layer;

depositing a Block Copolymer (BCP) layer between the guide structure patterns, annealing to form a directional self-assembly pattern consisting of a plurality of phase-separated polymer blocks, and filling the whole area between the guide structures with the phase-separated different polymer blocks and periodically repeating;

selectively removing the certain polymer block region, using the remaining polymer block region as an etching mask, sequentially transferring the etching mask pattern to the photoetching stack layer and the second hard mask layer, then removing the photoetching stack layer pattern, and retaining the second hard mask layer pattern;

depositing a dielectric layer on the second hard mask pattern, filling the pattern and covering the second hard mask pattern, then performing CMP planarization, stopping on the second hard mask, removing the second hard mask pattern to form a reversed dielectric pattern, etching the first hard mask layer by taking the dielectric layer of the pattern as a mask, and etching the semiconductor substrate by taking the double-layer mask to form the final semiconductor nano structure.

Preferably, wherein the guide structure pattern is formed of hardened photoresist or formed of a hard mask by photolithography and etching.

Preferably, the self-assembled pattern is formed of a diblock copolymer, a triblock copolymer, or other multiblock copolymer, wherein the widths of the polymer block regions formed may be the same or different.

Preferably, a buffer layer is arranged between the photoetching stacking layer and the Block Copolymer (BCP) layer, and the pattern forming the block copolymer layer is transferred to the buffer layer and then transferred to the photoetching stacking layer and the second hard mask layer.

Preferably, a neutral material layer is provided on the surface of the buffer layer, and the neutral material layer is in direct contact with or not in contact with the side wall of the guide structure pattern.

Preferably, a block copolymer may be directly deposited on the surface of the buffer layer without using a neutral material layer, wherein the material of the block copolymer layer is selected from Polystyrene-Polycarbonate (PS-b-PC).

Preferably, the buffer layer material is selected from polysilicon or amorphous silicon, and is obtained by etching with halogen-based, fluorine-based and fluorocarbon-based gases by using a certain copolymer block as a mask, wherein the etching gas is preferably Cl₂HBr or SF₆、CH₂F₂。

Preferably, the first polymer block or the second polymer block is selectively removed by an etching process using oxygen plasma, and the neutral material layer under the removed block layer is simultaneously selectively removed.

Preferably, the photolithography stack layer comprises an Optical Planarization (OPL) layer and an anti-reflective coating (ARC) layer or a stack of an Optical Planarization (OPL) layer and an insulating dielectric layer or a single insulating dielectric layer, wherein the Optical Planarization Layer (OPL) is preferably inorganic amorphous carbon or spin-on carbon or diamond-like carbon, the anti-reflective coating (ARC) layer is preferably a silicon-containing anti-reflective coating material, and the insulating dielectric layer is preferably silicon oxide, silicon nitride or silicon oxynitride. Preferably, the first hard mask layer or the second hard mask layer is a silicon-based dielectric material or a metal compound material, the materials of the two materials can be the same or different, the silicon-based dielectric material is selected from silicon oxide, silicon nitride, polysilicon and amorphous silicon, and the metal compound material is selected from aluminum oxide, titanium oxide and titanium nitride.

The invention solves the CD process control problem, reduces the serious dependence of the block mask on the thickness by adding the buffer layer between the BCP layer and the photoetching stack layer, and brings more space for the subsequent CD regulation and control. The size and the period of the original self-assembly template pattern are changed by regulating and controlling the size and the shape of the CD of the photoetching stack layer, and finally the size of the CD and the period of the Fin of the FinFET device can be regulated, so that more process tolerance is provided for the Fin forming technology.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing the method for fabricating semiconductor nanostructures according to the present invention by directed self-assembly and mask modulation with reference to the accompanying drawings, in which:

FIG. 1 is a self-assembling template pattern;

FIG. 2 selectively removes a certain block pattern;

FIG. 3 the lithographic pattern is transferred onto the buffer layer;

FIG. 4 etch the anti-reflective ARC layer;

FIG. 5 removes the residual buffer layer and the second block pattern layer;

FIG. 6 etch photo-lithographically planarize the OPL layer;

FIG. 7 transfers the pattern to the first hard mask layer;

FIG. 8 removes the remaining etched anti-reflective ARC layer and the lithographically planarized OPL layer;

FIG. 9 deposits dielectric material;

FIG. 10 CMP planarization;

FIG. 11 illustrates removing the first mask layer;

FIG. 12 etch the second hard mask layer;

FIG. 13 illustrates a semiconductor structure etched;

FIG. 14 removes the first and second hard mask layers;

Detailed Description

The following definitions and abbreviations are used for the interpretation of the claims and the specification. As used herein, the terms "comprising," "including," "containing," "having," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements, articles, or apparatus not expressly listed or inherent to such composition, mixture, process, method, or apparatus.

As used herein, the articles "a" and "an" preceding an element or component are intended to be non-limiting with respect to the number of instances (i.e., occurrences) of the element or component. Thus, "a" or "an" should be understood to include one or at least one, and the singular form of an element or component also includes the plural unless the number clearly is the singular. The present application will now be described in more detail by reference to the following discussion and the accompanying drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application. The present invention will be described in further detail with reference to the accompanying drawings and examples.

The invention provides a method for preparing a high-density semiconductor nano device structure with high reliability, which can greatly overcome the process control problem caused by the thickness of a block copolymer and the weaker etching selectivity among different block molecules in the existing self-assembly pattern transfer process.

Specifically, the method comprises the following steps:

fig. 1 illustrates a cross-sectional view of a semiconductor stack formed by a directed self-assembly (DSA) technique. First, asemiconductor substrate 1 is provided, and a firsthard mask layer 2, a second hard mask layer 2', a photolithography stack layer 3 and a buffer layer 4 are sequentially formed thereon. Wherein the buffer layer 4 is primarily to form a transition between the photolithographically stacked layer 3 and the block copolymer layer to facilitate patterning of the block copolymer, it should be noted that the buffer layer 4 is merely preferred and in another embodiment, the buffer layer 4 may not be employed and the block copolymer layer may be formed directly on the photolithographically stacked layer 3. In the following discussion of the embodiments, the buffer layer 4 is included, unless otherwise specifically mentioned, in order to fully illustrate the concept of the present invention.

Thesemiconductor substrate 1 may be composed of any semiconductor material including, but not limited to, Si, Ge, SiGe, SiC, SiGeC, carbon nanotubes, and III/V compound semiconductors such as InAs, GaN, GaAs, and InP. Multilayer materials composed of these semiconductor materials may also be used as the semiconductor substrate. Thesemiconductor substrate 1 may be composed of a single crystal semiconductor material, and single crystal silicon is selected as thesemiconductor substrate 1 in the present embodiment. In other embodiments, the semiconductor substrate may be a polycrystalline or amorphous semiconductor material. The method of the present application can then be used to obtain satisfactory semiconductor nanostructures, such as arrays of Fin in FinFET devices and arrays of Nanofire in Gate Nanowire (GAA) devices, in semiconductor substrates, as desired.

In another embodiment, thesemiconductor substrate 1 may comprise a semiconductor-on-insulator (SOI) substrate (not specifically shown). Although not specifically shown, those skilled in the art understand that the SOI substrate includes a support substrate, an insulator layer on the surface of the support substrate, and a semiconductor layer on the topmost of the upper surface of the insulator layer. The support substrate provides mechanical support for the insulator layer and the topmost semiconductor layer. In such an embodiment, a semiconductor structure such as a Fin array in a FinFET can then be fabricated into the topmost semiconductor layer of the SOI substrate using the method of the present invention. In this embodiment, the Fin array is formed on the topmost surface of the insulator layer.

The support substrate and the uppermost semiconductor layer of the SOI substrate may comprise the same or different semiconductor materials. In one embodiment, the support substrate and the topmost semiconductor layer are both comprised of silicon. In some embodiments, the support substrate is a non-semiconductor material, including, for example, a dielectric material and/or a conductive material.

In some embodiments, the topmost semiconductor layers of the support substrate and the SOI substrate may have the same or different crystal orientations. For example, the crystal orientation of the supporting substrate and/or the semiconductor layer may be 100, 110, or 111. Other crystallographic orientations than those specifically mentioned may also be used in the present invention. The substrate and/or the top semiconductor layer of the SOI substrate may be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. Typically, at least the topmost semiconductor layer is a single crystal semiconductor material. In some embodiments, the topmost semiconductor layer, which is located on top of the insulator layer, may be processed to include semiconductor regions having different crystal orientations.

The insulator layer of the SOI substrate may be a crystalline or amorphous oxide or nitride. In some embodiments, the insulator layer is an oxide, such as silicon dioxide. The insulator layer may be continuous or discontinuous. When discontinuous insulator regions are present, the insulator regions may exist as isolated islands surrounded by semiconductor material.

In one example, the thickness of the topmost semiconductor layer of the SOI substrate may be 5nm to 50 nm. In some embodiments, and when an ETSOI (ultra-thin semiconductor on insulator) substrate is used, the semiconductor layer of the topmost layer of the SOI has a thickness of less than 10 nm. If the thickness of the uppermost semiconductor layer is not within one of the above ranges, a thinning technique such as CMP planarization or etching may be used to reduce the thickness of the uppermost semiconductor layer to within the range. The insulator layer of the above-mentioned SOI substrate generally has a thickness of 10nm to 200nm, and more typically has a thickness of 100nm to 150 nm. The thickness of the support substrate of the SOI substrate is not relevant to the present invention.

The firsthard mask layer 2 and the second hard mask layer 2' comprise a conventional silicon-based dielectric material such as silicon oxide, silicon nitride, or a metal oxide such as HfO₂、ZrO₂、La₂O₃、Al₂O₃、TiO₂Etc., HfO is used in the present embodiment₂As a hard mask layer. In some embodiments, the first and second hard mask layers 2 and 2' may also be composed of nitrogen-doped silicon carbide, a nitrogen-doped hydrogenated silicon carbide layer, or carbon-doped silicon oxide. Nitrogen-doped silicon carbide is a compound of silicon, carbon and nitrogen, e.g. SiCN, nitrogen-doped hydrogenated silicon carbide is a compound of silicon, carbon, nitrogen and hydrogen, e.g. SiCNH, carbon-doped oxygenThe silicon oxide is a compound of silicon, carbon, and oxygen, and is represented by SiCO, for example.

The lithography stack layer 3 comprises a stack of an Optical Planarization (OPL) layer 3' and an anti-reflective coating (ARC) layer 3 ", or may be composed of an OPL layer and a silicon-based insulating dielectric layer, or a stack of single insulating dielectric layers, to enable high fidelity pattern transfer to the underlying hard mask layer, ensuring good topography control. The Optical Planarization (OPL) layer may be inorganic amorphous carbon, or may be an organic material such as spin-on carbon or diamond-like carbon, which provides a smooth and flat surface for the underlying structure. In one embodiment, the Optical Planarization (OPL) layer may be formed by spin coating, (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), evaporation, or chemical solution deposition. The thickness of the OPL is generally selected according to the particular etch dimensions, with the current trend being to use smaller and smaller thicknesses, e.g. 10nm to 100 nm. The silicon-based insulating dielectric layer may be silicon oxide, silicon nitride or silicon oxynitride, and may be formed by spin coating, (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), high density plasma chemical vapor deposition (HPCVD), chemical solution deposition, Atomic Layer Deposition (ALD), or the like.

The anti-reflective coating (ARC) comprises a silicon-containing anti-reflective coating material, in this embodiment a silicon anti-reflective coating (SiARC) is used, which minimizes light reflection during photolithography. The anti-reflective coating (ARC)4 "may be formed by spin coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), plasma enhanced ALD (peald), evaporation, or chemical solution deposition. The silicon antireflection layer can also be replaced by a silicon-based insulating dielectric layer such as silicon oxide, silicon nitride or silicon oxynitride.

A buffer layer 4 is deposited on the lithography stack layer 3, the buffer layer 4 may be amorphous silicon or polysilicon. Then, on the surface thereof, a pattern of confining or inducing guide structures may be formed according to a predetermined design using Graphoepitaxy (Graphoepitaxy directed self-assembly) or Chemoepitaxy (Chemoepitaxy) or other suitable methods. The guide structure pattern may have a surface topography, or be substantially free of a surface topography, may be formed from hardened photoresist or may employ lithographic and etching techniques to form the chemical guide pattern. The DSA technique for forming a block copolymer is not particularly limited in the present invention. By changing the chain length, composition, annealing condition and the like of the block copolymer, the block copolymer can be directionally self-assembled in a film, a hole or a groove, and different block copolymer layer patterns such as spheres, columns, layers and the like can be formed. The pattern of the block copolymer layer is not particularly limited in the present invention.

In one embodiment, before forming the self-assembled template pattern using the Block Copolymer (BCP), it is generally necessary to form a layer of neutral material (not shown) on the surface of the buffer layer 4, which may or may not directly contact the sidewalls of the guide pattern. The neutral material layer may be formed after the formation of the guide structure or before the formation of the guide structure, and the present invention is not particularly limited thereto. In some other embodiments, however, some BCP materials, such as Polystyrene-Polycarbonate (PS-b-PC), may form an oriented self-assembled pattern perpendicular to the bottom surface in the guide structure without using a neutral layer material, depending on the material and process characteristics of the particular block polymer.

The layer of neutral material is a polymer layer that can adhere to the underlying surface and acquire a certain surface energy, typically a random copolymer containing a polar polymer component and a non-polar polymer component, including materials that are chemically neutral to the different polymer blocks in the block copolymer material used for DSA, i.e., the neutral materials have substantially the same wetting affinity for the different polymer blocks in the block copolymer material, thus facilitating the formation of polymer blocks oriented perpendicular to the upper surface of the layer of neutral material. "random" refers to a polymeric material that lacks any defined repeating blocks. In one example, the neutral material may comprise a random copolymer of Polymethylmethacrylate (PMMA) as a component of the polar polymer and Polystyrene (PS) as a component of the non-polar polymer. By controlling the ratio of the non-polar polymer component (i.e., PS) to the polar polymer component (i.e., PMMA) during the synthesis phase, the desired surface properties can be achieved. In some embodiments, to anchor the random copolymer on the surface ofbuffer layer 5, one or several functional groups may be added to the ends of the polymer chains or in random positions of the polymer chains to react with the buffer layer and establish covalent bonds. The neutral material layer may be formed by spin coating, evaporation or chemical solution deposition, and may be 2nm to 20nm thick, or even smaller thicknesses may be used.

In one embodiment, the neutral material layer may be made of a polymer brush material having ends substituted with reactive functional groups capable of attaching to the surface of the buffer layer 4, which is a random copolymer having ends of a block copolymer material substituted with reactive functional groups. Exemplary polymeric brush materials for use in the present invention are random copolymers comprised of block copolymer materials having reactive groups such as hydroxyl, amino, halogen groups, and the like. These reactive groups can react with the hydroxylated groups present on the surface of the buffer layer. In one embodiment, when the block copolymer for DSA is a diblock copolymer of Polystyrene (PS) and Polymethylmethacrylate (PMMA), the neutral material layer may be PS-r-PMMA-OH consisting of styrene and random methyl acrylate having hydroxyl groups. The hydroxyl groups at the ends of the polymer chains will be covalently bonded to the hydroxyl groups on the surface ofbuffer layer 5 by a condensation reaction. Because there is only one reactive functional group per polymer chain, the reaction will be self-limiting, and only one monolayer of polymer brush material will be anchored on the surface ofbuffer layer 5, the unreacted polymer brush material remaining soluble in the solvent.

To form the layer of neutral material, a polymer brush material may be spin coated into the guide structure and onto the surface of the buffer layer 4. The polymer brush material is baked at a suitable temperature to activate the reaction between the polymer and the functional groups on the surface of buffer layer 4, and then excess polymer brush material not bound to the surface of buffer layer 4 is removed using a neutral solvent that does not significantly affect the neutral material layer. Of course, depending on the polymeric material used, the solvent used to remove excess polymeric brush material may vary, and suitable solvents include, but are not limited to, Propylene Glycol Monomethyl Ether Acetate (PGMEA), n-butyl acetate (nBA), toluene, and anisole.

To form the nanoscale periodic pattern, the block copolymer material is first dissolved in a suitable solvent to form a block copolymer solution, which is then applied over the layer of neutral material and between the guide patterns to provide a layer of block copolymer. The solvent system used to dissolve the block copolymer material and form the block copolymer solution may comprise any suitable solvent, including, but not limited to, toluene, Propylene Glycol Monomethyl Ether Acetate (PGMEA), Propylene Glycol Monomethyl Ether (PGME), and acetone. The block copolymer solution may be applied by any suitable technique, including but not limited to spin coating, spray coating, and dip coating.

The block copolymer layer includes a first polymer block and a second polymer block that are immiscible with each other. In some embodiments of the invention, the material providing the copolymer layer is self-planarizing. Microphase separation of the different polymer blocks comprised in the block copolymer layer can be achieved by annealing at a temperature to form an alternating periodic pattern with perpendicular orientation on the nanometer scale. By "nanoscale" is meant herein the level of feature sizes less than 50 nm. Exemplary block copolymers that can be used to form nanoscale periodic patterns include, but are not limited to, poly (styrene-b-methyl methacrylate) (PS-b-PMMA), poly (ethylene oxide-b-isoprene) (PEO-b-PI), poly (ethylene oxide-b-methyl methacrylate) (PEO-b-PMMA), poly (ethylene oxide-b-ethyl ethylene) (PEO-b-PEE), poly (styrene-b-vinyl pyridine) (PS-b-PVP), poly (styrene-b-butadiene) (PS-b-PBD), poly (styrene-b-ferrocenyldimethylsilane) (PS-b-PFS), poly (styrene-b-lactic acid) (PS-b-PLA), and poly (styrene-b-dimethylsiloxane) Alkane) (PS-b-PDMS). In one embodiment, PS-b-PMMA is preferably used.

In addition, the block copolymer may be formed of a diblock copolymer, and the block copolymer layer may be formed of a triblock copolymer or other multiblock copolymers according to another embodiment of the present invention, but the present invention is not limited thereto. The diblock copolymer PS-b-PMMA was used in this example to form a block copolymer layer. However, in other embodiments of the present invention, any suitable block copolymer may be used to form the block copolymer layer. In the present embodiment, the block copolymer layer includes afirst polymer block 5 composed of a first component PMMA and a second polymer block 6 composed of a second component PS. In one embodiment, the block copolymer layer may be annealed at elevated temperatures by solvent vapor annealing or by thermal annealing to form thefirst polymer block 5 and the second polymer block 6. The annealing may be performed at a temperature of about 150 ℃ to about 300 ℃ for a duration of 30 seconds to about 5 hours. In other embodiments of the present invention, other annealing conditions (i.e., temperature and time) may also be used to convert the copolymer layer into a self-assembled block copolymer structure. As shown in fig. 1, each first phase separatedpolymer block 5 and each second phase separated polymer block 6 of each self-assembled block copolymer structure repeat in a regular pattern. Thus, in accordance with the present invention, a certain phase separated polymer block within a self-assembled structure formed of a particular block copolymer can be used to define and fabricate nanowires in a semiconductor Fin or a gate Nanowire device (GAA Nanowire) in a FinFET device, while another phase separated polymer block can be used to define the spacing between each semiconductor Fin or Nanowire in the same self-assembled structure. The specific size is generally determined by the respective chemical nature of the polymer blocks. Each first phase separated polymer block has a first width L1 and each second phase separated polymer block has a second width L2. In some embodiments, the second width L2 is the same as the first width L1. In other embodiments, the second width L2 is different from the first width L1. This allows for the selection of an appropriate block copolymer in defining the final semiconductor nanostructure, depending on the design requirements of the device, so that more control over the results can be achieved. Each of the first and second widths is nano-scale and may be generally less than 50 nm.

As in FIG. 2, O may be used₂Ar or fluorocarbon-based gas, O₂The first phase separatedpolymer block 5 is selectively removed by plasma dry etching while the second phase separated polymer block 6 is used as an etching mask to form a directional self-assembled lithographic pattern. The first phase separated poly(s) may also be selectively removed using a wet development process (e.g., UV radiation followed by solvent washing)Polymer block 5, thereby forming a nano-scale lithographic pattern. In the process, the corresponding part of the neutral layer below the first phase-separatedpolymer block 5 is also removed. In other embodiments, other etching methods may be used to remove the first phase-separatedpolymer block 5, which is not specifically limited in the present invention. After selective removal of the first polymer blocks 5, the remaining second polymer blocks 6 define the structure of the semiconductor, while the distance between adjacent second polymer blocks defines the pitch of the semiconductor structure. In one embodiment, the first polymer block is PMMA, the second polymer block is PS, and the PMMA is selectively removed using the PS as a mask.

Subsequently, the resist pattern is transferred to the buffer layer 4, and the resist pattern can be obtained using halogen-based, fluorine-based, and fluorocarbon-based gases, preferably Cl₂HBr or SF₆、CH₂F₂As shown in fig. 3. The buffer layer may be etched using any suitable etching process, such as a dry etching process, e.g., plasma etching, reactive ion etching, pulsed plasma etching, etc. The present invention is not particularly limited in this regard. By adopting the polycrystalline silicon or amorphous silicon material, the excessive consumption of the block molecules caused by the etching of the conventional mask material can be reduced, so that the high dependence of the block copolymer on the etching technology is reduced, and the better fidelity and integrity can be realized in the pattern transfer process.

Subsequently, the pattern obtained above can be transferred into the photolithographic stack 3 by methods known in the art, as shown in fig. 4, and then the buffer layer 4 and the pattern and the remaining copolymer pattern thereon are removed, as shown in fig. 5. In the process, isotropic etching can be adopted to transversely shrink the obtained pattern to obtain a pattern with a smaller size, so that the transverse expansion of the CD caused by the etching morphology is avoided. In another embodiment, a fluorocarbon based gas such as CF may be used₄、CHF₃And O₂The hybrid plasma of (a) is used to micro-scale the antireflective coating (ARC). The etched anti-reflective layer is then transferred to an Optical Planarization (OPL) layer, in which process O may be used₂Ar or halogen-based gases such as Cl₂HBr or fluorocarbon based gases such as CF₄And O₂The hybrid plasma of (a) micro-shrinks the Optical Planarization (OPL) layer (not shown in the figure) resulting in an etched lithographic stack, as shown in fig. 6.

The pattern of the lithographic stack 3 is further transferred onto the second hard mask layer 2', depending on the material used for the second hard mask layer, as shown in fig. 7. All remaining portions of the stack including the Optical Planarization (OPL) layer 3' and the anti-reflective coating (ARC) layer 3 "are then removed, resulting in a second hard mask pattern with good etch profile and clean-out, as shown in fig. 8. This process may be performed by dry etching, wet etching, or any other suitable etching process. As an example, an oxygen plasma may be used to strip the entire patterned photoresist layer OPL while also completely removing the remaining material above.

A dielectric layer 7 is then deposited over the second hard mask layer 2 ' pattern, the dielectric layer 7 filling the pattern in the second hard mask layer 2 ' and covering the second hard mask layer 2 ' to a height, as shown in figure 9. In fig. 9, a simple demonstration is simply made in order to show the relief profile according to the actual deposition process. In one embodiment of the present invention, the dielectric layer material may be silicon nitride. After the deposition is completed, the dielectric layer is subjected to Chemical Mechanical Polishing (CMP) and stopped on the second hard mask layer 2 'with the second hard mask layer 2' as a stop layer, as shown in fig. 10. Then, the pattern of the second hard mask layer 2' is removed to form an inverted dielectric layer pattern, the firsthard mask layer 2 is etched by using the pattern of the dielectric layer 7 as a mask, and the inverted pattern is transferred onto the firsthard mask layer 2, as shown in fig. 11 to 12. The semiconductor substrate is then etched with a double mask of dielectric layer 7 and firsthard mask layer 2, and the double mask pattern is then removed to form a semiconductor structure having the desired pattern geometry and topography, as shown in fig. 13 and 14, respectively. The structure may be a Fin array in a FinFET device, a Nanowire array in a gate-all Nanowire (GAA Nanowire) device, or a dummy gate electrode array. In some embodiments, the etched semiconductor structure may also be a trench, a hole, a line, and other regular or irregular patterns or patterns. On the basis of the formed semiconductor structure, semiconductor structures such as a source-drain region, a grid electrode and the like can be formed according to the existing semiconductor manufacturing process, and finally a required semiconductor device is formed.

By means of the whole process, the buffer layer material is introduced, the problem of etching process caused by weak etching resistance of the segmented copolymer molecules is reduced, and the mask budget of subsequent etching is increased by adopting a multi-layer pattern transfer method, so that the size of a geometric pattern meeting the expectation can be obtained on the semiconductor substrate. The method is compatible with the state-of-the-art FinFET device fabrication process, and the disclosed method also provides more space for the CD and pitch control of the semiconductor structure, i.e., the final feature size can be further scaled down.

Although the invention has been described in detail hereinabove with respect to specific embodiments thereof, it will be apparent to those skilled in the art that modifications and improvements can be made thereto without departing from the scope of the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (10)

Translated fromChinese

1.一种定向自组装和掩膜调控制备半导体纳米结构的方法，其特征在于：1. a method for directional self-assembly and mask control to prepare semiconductor nanostructure, is characterized in that:提供一半导体衬底(1)，在其上依次形成第一硬掩膜层(2)和第二硬掩膜层(2’)、光刻堆叠层(3)，在所述光刻堆叠层(3)形成多个引导结构图案；A semiconductor substrate (1) is provided on which a first hard mask layer (2), a second hard mask layer (2'), and a photolithography stack layer (3) are formed in sequence, and the photolithography stack layer is (3) forming a plurality of guiding structure patterns;在所述引导结构图案之间沉积嵌段共聚物(BCP)层，经退火形成具有多个相分离的聚合物嵌段组成的定向自组装图形，由相分离的不同聚合物嵌段填充引导结构之间的整个区域并呈周期性重复；A block copolymer (BCP) layer is deposited between the guiding structure patterns, annealed to form a directed self-assembled pattern composed of a plurality of phase-separated polymer blocks, and the guiding structures are filled by the phase-separated different polymer blocks the entire area between and repeats periodically;选择性地去除所述某一聚合物嵌段区域，利用余下的聚合物嵌段区域作为刻蚀掩膜，在将所述刻蚀掩膜图形依次转移到所述光刻堆叠层(3)、所述第二硬掩膜层(2’)上，然后去除光刻堆叠层(3)图案，保留第二硬掩膜层(2’)图形；Selectively removing a certain polymer block region, using the remaining polymer block region as an etching mask, and transferring the etching mask pattern to the photolithography stack layer (3), On the second hard mask layer (2'), the pattern of the photolithography stack layer (3) is then removed, and the pattern of the second hard mask layer (2') is retained;在所述第二硬掩膜(2’)图形上沉积一层电介质层(7)，填充图案并覆盖第二硬掩膜(2’)图形，然后进行CMP平坦化，停止在所述第二硬掩膜(2’)上，去除所述第二硬掩膜(2’)图形形成反转的电介质图形，以图案的电介质层(7)为掩膜刻蚀所述第一硬掩膜层(2)，再以该双层掩模刻蚀半导体衬底(1)，形成最终的半导体纳米结构。A dielectric layer (7) is deposited on the second hard mask (2') pattern, filling the pattern and covering the second hard mask (2') pattern, followed by CMP planarization, stopping at the second hard mask (2') pattern On the hard mask (2'), the pattern of the second hard mask (2') is removed to form a reversed dielectric pattern, and the patterned dielectric layer (7) is used as a mask to etch the first hard mask layer (2), and then etching the semiconductor substrate (1) with the double-layer mask to form a final semiconductor nanostructure.2.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，其中所述引导结构图案由硬化的光刻胶形成或由硬掩膜经光刻和刻蚀形成。2 . The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1 , wherein the guiding structure pattern is formed by hardened photoresist or formed by photolithography and etching from a hard mask. 3 .3.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，所述自组装图形由二元嵌段共聚物形成、三元嵌段共聚物或其他多元嵌段共聚物形成，其中形成的聚合物嵌段区域宽度可以相同或不同。3. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein the self-assembly pattern is formed by a binary block copolymer, a ternary block copolymer or other multi-component block copolymers formed, wherein the polymer block domains formed may be of the same or different widths.4.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，在所述光刻堆叠层(3)和嵌段共聚物(BCP)层之间设置缓冲层(4)，将所述形成嵌段共聚物层图案转移到所述缓冲层(4)后再转移到所述光刻堆叠层(3)和所述第二硬掩膜层(2’)上。4. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein a buffer layer (4) is provided between the lithography stack layer (3) and the block copolymer (BCP) layer , transferring the forming block copolymer layer pattern to the buffer layer (4) and then transferring it to the lithography stack layer (3) and the second hard mask layer (2').5.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，在所述缓冲层(4)表面具有一中性材料层，所述中性材料层直接接触或不接触所述引导结构图案的侧壁。5. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein a neutral material layer is provided on the surface of the buffer layer (4), and the neutral material layer directly contacts or does not contact sidewalls of the guide structure pattern.6.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，在所述缓冲层(4)表面可以不采用中性材料层，而直接沉积嵌段共聚物，其中所述嵌段共聚物层材料选自聚苯乙烯-聚碳酸酯(Polystyrene-b-Polycarbonate，PS-b-PC)。6. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein a neutral material layer may not be used on the surface of the buffer layer (4), but a block copolymer is directly deposited, wherein the The block copolymer layer material is selected from polystyrene-polycarbonate (Polystyrene-b-Polycarbonate, PS-b-PC).7.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，所述缓冲层(4)材料选自多晶硅或非晶硅，以某一共聚物嵌段为掩膜采用卤基、氟基及碳氟基气体刻蚀得到，所述刻蚀气体优选为Cl₂、HBr或SF₆、CH₂F₂。7. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein the material of the buffer layer (4) is selected from polysilicon or amorphous silicon, and a certain copolymer block is used as a mask. Halogen-based, fluorine-based and fluorocarbon-based gases are obtained by etching, and the etching gas is preferably Cl₂ , HBr or SF₆ , CH₂ F₂ .8.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，采用氧等离子体的刻蚀工艺选择性去除所述第一聚合物嵌段(5)或第二聚合物嵌段(6)，所去除的嵌段层下方的中性材料层同时被选择性去除。8 . The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1 , wherein the first polymer block ( 5 ) or the second polymer is selectively removed by an etching process of oxygen plasma. 9 . Block (6), the neutral material layer below the removed block layer is simultaneously selectively removed.9.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，所述光刻堆叠层(3)包括光学平坦化(OPL)层(3”)和抗反射涂层(ARC)(3’)堆叠层或光学平坦化(OPL)层和绝缘介质层或单一绝缘介质层的堆叠层，其中所述光学平坦化层(OPL)优选为无机非晶碳或旋涂碳或类金刚石碳，所述抗反射涂层(ARC)优选为含硅的抗反射涂层材料，所述绝缘介质层优选为氧化硅、氮化硅或氮氧化硅。9. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein the lithography stack layer (3) comprises an optical planarization (OPL) layer (3") and an anti-reflection coating ( ARC) (3') stacked layer or optical planarization (OPL) layer and insulating dielectric layer or a stacked layer of a single insulating dielectric layer, wherein the optical planarization layer (OPL) is preferably inorganic amorphous carbon or spin-on carbon or Diamond-like carbon, the anti-reflection coating (ARC) is preferably a silicon-containing anti-reflection coating material, and the insulating medium layer is preferably silicon oxide, silicon nitride or silicon oxynitride.10.如权利要求1所述的定向自组装制备半导体纳米结构的方法，其特征在于，所述第一硬掩膜层(2)或第二硬掩膜层(2’)为硅基电介质材料或金属化合物材料，两者材料可以相同或不同，所述硅基电介质材料选自氧化硅、氮化硅、多晶硅、非晶硅，所述金属化合物材料选自氧化铝、氧化钛、氮化钛。10. The method for preparing semiconductor nanostructures by directional self-assembly according to claim 1, wherein the first hard mask layer (2) or the second hard mask layer (2') is a silicon-based dielectric material Or metal compound materials, the two materials can be the same or different, the silicon-based dielectric material is selected from silicon oxide, silicon nitride, polysilicon, amorphous silicon, the metal compound material is selected from aluminum oxide, titanium oxide, titanium nitride .

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