CN110850284A - Current protection tester - Google Patents
Current protection testerDownload PDFInfo
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- CN110850284A CN110850284ACN201911376426.6ACN201911376426ACN110850284ACN 110850284 ACN110850284 ACN 110850284ACN 201911376426 ACN201911376426 ACN 201911376426ACN 110850284 ACN110850284 ACN 110850284A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3277—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
- G01R31/3278—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches of relays, solenoids or reed switches
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Abstract
Description
Technical Field
The invention belongs to the technical field of testers, and particularly relates to a current protection tester.
Background
At present, the fixed value checking work of a current relay in a secondary circuit of a current transformer of a power system occupies a great proportion in the routine equipment regular checking or engineering construction work of relay protection of a current sampling circuit of a 66KV transformer substation or an intelligent transformer substation, and the quality of debugging is very important. Therefore, the design of the constant value checking device of the current relay with good working effect is particularly important for the current protection constant value debugging work.
Disclosure of Invention
Aiming at the problems, the invention provides the current protection tester with good working effect.
In order to achieve the purpose, the invention adopts the following technical scheme that the invention comprises a central processing unit, a current acquisition part, a triangular wave generating circuit, an SPWM modulator, a half-bridge driving circuit, a filter circuit, a current output port, a switching voltage stabilizing circuit, an analog-to-digital conversion part, a sine wave generator, a switching trigger circuit and a linear voltage stabilizing circuit, and is characterized in that a signal output port of the sine wave generator and a signal output port of the triangular wave generating circuit are connected with a signal input port of the SPWM modulator;
the output port of the half-bridge driving circuit is connected with the current output port of the switching voltage stabilizing circuit through the filter circuit;
the input port of the linear voltage stabilizing circuit is connected with the voltage output port of the switch voltage stabilizing circuit;
the output port of the switch trigger circuit is connected with the control port of the switch voltage stabilizing circuit;
the input port of the analog-to-digital conversion part is connected with the output port of the current acquisition part, and the output port of the analog-to-digital conversion part is connected with the signal input port of the central processing unit;
the control signal output port of the central processing unit is respectively connected with the control signal input port of the switch voltage stabilizing circuit, the control signal input port of the switch trigger circuit, the control signal input port of the sine wave generator and the control signal input port of the triangular wave generating circuit.
As a preferred scheme, the current collecting part of the invention comprises an AD8552 chip UA2 and an AD8551 chip U8, wherein apin 2 of UA2 is respectively connected with apin 1 of a J5 current collecting interface (current of a current output port is collected by a current transformer), one end of a resistor R16 and one end of a resistor R21, the other end of the resistor R16 is respectively connected with the other end of R21, apin 1 of UA2 and one end of a resistor R20, apin 3 of UA2 is respectively connected with apin 2 of J5, apin 5 of UA2, apin 1 of U8 and apin 4 of U8, apin 3 of U8 is respectively connected with one end of a resistor R26, one end of a resistor R28 and one end of a capacitor C40, the other end of R26 is connected with an end 3.3, and the other end of C40 and the other end of R58;
the 7 feet of UA2 are connected with the cathode of diode D10 and the anode of diode D11, the anode of D10 is connected with one end of resistor R24, one end of capacitor C34 and the VL-end, the other end of R24 is connected with the 6 feet of UA2, the other end of C34, one end of capacitor C30, one end of resistor R19 and the other end of R20, the other end of R19 is connected with the other end of C30, the cathode of D9 and one end of resistor R18, and the other end of R18 is connected with the VL + end.
As another preferred scheme, the input power supply of the switching voltage stabilizing circuit of the present invention employs a battery.
As another preferred scheme, the battery provided by the invention adopts a 12-volt lithium battery.
As another preferable scheme, the triangular wave generating circuit of the invention comprises an AD8551 chip U9, wherein 3 pins of U9 are respectively connected with one end of a resistor R35, one end of a resistor R36 and one end of a capacitor C49, the other end of R35 is connected with an AVCC5V end, and the other end of C49 is respectively connected with the other end of R36 and an AGND end;
the 4 feet of U9 are connected with one end of a resistor R38 and one end of a resistor R39 respectively, the other end of R38 is connected with one end of a resistor R37 and one end of a capacitor C52 respectively through a capacitor C50, the other end of C52 is grounded, the other end of R37 is connected with a 200K end, and the other end of R39 is connected with the 1 foot and the T _ W end of U9 respectively.
As another preferred scheme, the SPWM modulator of the present invention includes a LM393 chip UA1, apin 3 of UA1 is connected to an IN + terminal, apin 2 of UA1 is connected to a T _ W terminal, apin 4 of UA1 is connected to apin 8 of UA1 and one end of a resistor R5 through a capacitor C16, and the other end of R5 is connected to apin 1 of UA1 and a PWMOUT terminal.
As another preferred scheme, the half-bridge driving circuit of the invention comprises an EG3113 chip U3, whereinpins pin 1 of U3 is respectively connected to an anode of a diode D3, a PVCC terminal, apin 2 of a tube Q1 of IPP048N12N, apin 2 of a tube Q2 of PP048N12N, and one end of a resistor R8; apin 1 of the Q1 is respectively connected with apin 7 of the U3 and one end of a resistor R7 through a resistor R6, apin 8 of the U3 is respectively connected with a cathode of the D3 and one end of a capacitor C18, and the other end of the C18 is respectively connected with apin 6 of the U3, apin 3 of the Q1, apin 3 of the Q2 of the PP048N12N tube, apin 2 of the Q4 of the PP048N12N tube, apin 2 of the Q5 of the PP048N12N tube and one end of an inductor L1; the other end of R7 is connected withpin 1 of Q2;
the other end of the L1 is respectively connected with the SOUT end and the anode of a capacitor C3, the cathode of the C3 is connected with the 4 pin of an SFK-112DM relay LS1, the 1 pin of the LS1 is connected with the cathode of a diode D5, the anode of the D5 is respectively connected with the 2 pin of the LS1 and the 3 pin of a 2N7002/SOT tube Q3, and the 1 pin of the Q3 is connected with the HRSEN1 end.
As another preferred scheme, the filter circuit of the invention comprises common-mode inductors GL1, GL2 and GL3 (1 mH 30A), wherein apin 1 of GL1 is connected with apin 3 of LS1, and apin 2 of GL1 is connected with apin 2 of Q3;pins pins pins pins pins pins
As another preferred scheme, the switching regulator circuit of the present invention includes an AME5268 chip U10, an AME5268 chip U11, an INA194 chip U14, a common mode inductor GL4 (1mH 3A), and an AD8551 chip U16, where apin 7 of the U10 is connected to a PVCCEN (12V power on and off control) terminal, apin 2 of the U10 is connected to apin 4 and a VIN terminal of the GL4 through an L2, apin 3 of the GL4 is connected to apin 2 of the U11, and apin 7 of the U11 is connected to a SYSTEM _ EN terminal;
the VIN end is respectively connected with the source electrode of the Q7 of the AOD403 tube and the source electrode of the Q8 of the AOD403 tube, the grid electrode of Q7 and the grid electrode of Q8 are connected with the drain electrode of the Q10 of the 2N7002 chip, the grid electrode of Q10 is connected with the SYSTEM _ EN end, and the source electrode of Q10 is connected with the GND end;
the drain of Q7 and the drain of Q8 are connected withpin 3 of U14,pin 1 of U14 is connected withpin 3 of U16, andpin 1 of U16 is connected with I _ OVER (when the input current is too large, the half-bridge drive output is closed).
As another preferred scheme, the central processing unit adopts a stm32f103c8t6 chip U1, 20 pins of U1 are connected with the grid electrode of a 2N7002 tube Q6, and the drain electrode of Q6 is connected with an output relay;
the 43 pin of U1 is connected to the grid of Q9 of 2N7002 tube, the drain of Q9 is connected to connector J9, and the source of Q9 is grounded.
As another preferable scheme, the analog-to-digital conversion part of the invention adopts a CS1237 chip U4, wherein 3 and 4 pins of U4 are respectively connected with VL-end and VL + end, and 5 and 6 pins of U4 are respectively connected with CS1237CK end and CS1237D end.
IN another preferred scheme, the sine wave generator of the invention adopts a PT8211 chip U7,pins pin 8 of U7 is connected with an IN + terminal through a resistor R22.
Secondly, the switch trigger circuit comprises a CD4013B/SO chip U17, wherein apin 1 of U17 is connected with a SYSTEM _ EN end.
In addition, the linear voltage stabilizing circuit comprises an SGM2032-33 chip U12, an SGM2032-50 chip U13 and an SGM2032-33 chip U15, wherein apin 1 of the U12 is connected with a VCC5V end, apin 5 of the U12 is connected with a VCC3.3 end, apin 1 of the U13 is connected with a VCC5V end, and apin 5 of the U13 is connected with an AVCC5V end; the 1 pin of U15 is connected to VCC5V terminal, and the 5 pin of U15 is connected to AVCC3.3 terminal.
The invention has the beneficial effects.
The invention is convenient for the constant value check of the current relay in the secondary circuit of the current transformer of the power system through the mutual matching of all the parts.
Drawings
The invention is further described with reference to the following figures and detailed description. The scope of the invention is not limited to the following expressions.
FIG. 1 is a schematic diagram of an SPWM modulator, a triangular wave generating circuit and a sine wave generating circuit of the invention.
Fig. 2, 3 and 4 are schematic diagrams of a half-bridge driving circuit and a filter circuit of the invention.
Fig. 5 is a schematic circuit diagram of the analog-to-digital conversion part of the present invention.
Fig. 6 is a schematic diagram of a current collection portion of the present invention.
FIGS. 7, 8 and 9 are schematic diagrams of the CPU circuit of the present invention.
FIGS. 10 and 11 are schematic diagrams of a switching regulator circuit according to the present invention.
FIG. 12 is a schematic diagram of a linear voltage regulator circuit of the present invention.
Fig. 13 is a schematic diagram of the switch trigger circuit of the present invention.
Detailed Description
As shown in the figure, the invention comprises a central processing unit, a current acquisition part, a triangular wave generating circuit, an SPWM modulator, a half-bridge driving circuit, a filter circuit, a current output port, a switch voltage stabilizing circuit, an analog-to-digital conversion part, a sine wave generator, a switch trigger circuit and a linear voltage stabilizing circuit, and is characterized in that a control signal output port of the central processing unit is connected with a control signal input port of the switch voltage stabilizing circuit (an ON/OFF port is connected with a CD4013 through a field effect tube to control the closing of a switch power supply circuit), and a signal output port of the sine wave generator and a signal output port of the triangular wave generating circuit are connected with a signal;
the output port of the half-bridge driving circuit is connected with the current output port of the switching voltage stabilizing circuit through the filter circuit;
the input port of the linear voltage stabilizing circuit is connected with the voltage output port of the switch voltage stabilizing circuit;
the output port of the switch trigger circuit is connected with the control port of the switch voltage stabilizing circuit;
the input port of the analog-to-digital conversion part is connected with the output port of the current acquisition part, and the output port of the analog-to-digital conversion part is connected with the signal input port of the central processing unit;
the control signal output port of the central processing unit is respectively connected with the control signal input port of the switch voltage stabilizing circuit, the control signal input port of the switch trigger circuit, the control signal input port of the sine wave generator and the control signal input port of the triangular wave generating circuit.
A built-in 12 volt lithium battery can be used as a working power supply. The 12 volt dc voltage is converted to a 50HZ ac current. The battery is used as a working power supply, so that the device is small in size and convenient to carry.
A touch screen type liquid crystal panel can be arranged (a port j3 in the circuit diagram is communicated with a serial port configuration screen with a touch function).
The device shell can be made of aluminum plates, and the aluminum plates of the shell are provided with heat dissipation sheets.
The present invention may set the output to 20/30 amps.
The invention has small volume, can be placed in a backpack, and additionally, two test wires, a screwdriver, a micro multimeter and other simple tools are placed in the residual space of the backpack.
The invention generates a high-power sine wave current source through pulse modulation, the lithium battery generates voltage, the sine wave pulse modulation is generated through the SPWM modulator and then is sent to the half-bridge driving amplifier, a large-current (such as 60A) pulse signal is generated, the sine wave current is filtered and reduced by the filter circuit to be output, the alternating current acquisition part feeds the current value acquired in real time back to the processor, and the current value is converted into a corresponding voltage value to be output through PID operation, so that the dynamic voltage regulation is realized, and the output current is kept to be not changed along with the load. The switch voltage stabilizing circuit limits the output of the power supply to ensure the stable operation of the system, and the current can be set, displayed in real time, preset and programmed through the touch screen.
When the current output port is used, the current output port is connected with the control signal input port of the current relay to be tested, the current output port outputs a certain current value, and whether the current relay to be tested works under the control of the current value is detected to detect and verify the current relay to be tested.
The current acquisition part comprises an AD8552 chip UA2 and an AD8551 chip U8, wherein apin 2 of the UA2 is respectively connected with apin 1 of a current acquisition interface J5, one end of a resistor R16 and one end of a resistor R21, the other end of the resistor R16 is respectively connected with the other end of the R21, apin 1 of the UA2 and one end of a resistor R20, apin 3 of the UA2 is respectively connected with apin 2 of the J5, apin 5 of the UA2, apin 1 of the U8 and apin 4 of the U8, apin 3 of the U8 is respectively connected with one end of the resistor R26, one end of the resistor R28 and one end of the capacitor C40, the other end of the R26 is connected with an AVCC3.3 end, and;
the 7 feet of UA2 are connected with the cathode of diode D10 and the anode of diode D11, the anode of D10 is connected with one end of resistor R24, one end of capacitor C34 and the VL-end, the other end of R24 is connected with the 6 feet of UA2, the other end of C34, one end of capacitor C30, one end of resistor R19 and the other end of R20, the other end of R19 is connected with the other end of C30, the cathode of D9 and one end of resistor R18, and the other end of R18 is connected with the VL + end.
The triangular wave generating circuit comprises an AD8551 chip U9, wherein 3 pins of a U9 are respectively connected with one end of a resistor R35, one end of a resistor R36 and one end of a capacitor C49, the other end of R35 is connected with an AVCC5V end, and the other end of C49 is respectively connected with the other end of R36 and an AGND end;
the 4 feet of U9 are connected with one end of a resistor R38 and one end of a resistor R39 respectively, the other end of R38 is connected with one end of a resistor R37 and one end of a capacitor C52 respectively through a capacitor C50, the other end of C52 is grounded, the other end of R37 is connected with a 200K end, and the other end of R39 is connected with the 1 foot and the T _ W end of U9 respectively.
The square wave of the maximum 200k is converted into a triangular wave by R37, C52 and C50, and the signal is compressed to a proper voltage range interval by a U9 operational amplifier.
The current sampling is carried out to convert the 0-20A current signal into a 0-10 ma current signal through a current transformer.
The voltage is converted into an alternating current voltage signal through the operational amplifier UA2A, and the alternating current voltage signal is converted into a differential voltage effective value direct current voltage signal through UA2B and sent to the cpu adc acquisition circuit.
The SPWM modulator comprises an LM393 chip UA1, wherein apin 3 of UA1 is connected with an IN + end, apin 2 of UA1 is connected with a T _ W end, apin 4 of UA1 is respectively connected with apin 8 of UA1 and one end of a resistor R5 through a capacitor C16, and the other end of R5 is respectively connected with apin 1 of UA1 and a PWMOUT end.
IN + inputs a sine wave analog signal, and T _ W inputs a triangular wave signal.
PWMOUT outputs a sine wave modulated pulse signal.
The half-bridge driving circuit comprises an EG3113 chip U3, pins 2 and 3 of U3 are connected with a PWMOUT end, andpin 1 of U3 is respectively connected with an anode of a diode D3, a PVCC end, apin 2 of an IPP048N12N tube Q1, apin 2 of a PP048N12N tube Q2 and one end of a resistor R8; apin 1 of the Q1 is respectively connected with apin 7 of the U3 and one end of a resistor R7 through a resistor R6, apin 8 of the U3 is respectively connected with a cathode of the D3 and one end of a capacitor C18, and the other end of the C18 is respectively connected with apin 6 of the U3, apin 3 of the Q1, apin 3 of the Q2 of the PP048N12N tube, apin 2 of the Q4 of the PP048N12N tube, apin 2 of the Q5 of the PP048N12N tube and one end of an inductor L1; the other end of R7 is connected withpin 1 of Q2;
the other end of the L1 is respectively connected with the SOUT end and the anode of a capacitor C3, the cathode of the C3 is connected with the 4 pin of an SFK-112DM relay LS1, the 1 pin of the LS1 is connected with the cathode of a diode D5, the anode of the D5 is respectively connected with the 2 pin of the LS1 and the 3 pin of a 2N7002/SOT tube Q3, and the 1 pin of the Q3 is connected with the HRSEN1 end.
The input sine modulation pulse signal is amplified to the peak value 60A output by the half-bridge driving, and is restored to sine wave output through an L1 inductor and a C5 capacitor.
The filter circuit comprises GL1, GL2 and GL3, wherein apin 1 of the GL1 is connected with apin 3 of the LS1, and apin 2 of the GL1 is connected with apin 2 of the Q3;pins pins pins pins
The switching voltage stabilizing circuit comprises an AME5268 chip U10, an AME5268 chip U11, an INA194 chip U14, a GL4 and an AD8551 chip U16, wherein apin 7 of the U10 is connected with a PVCCEN end, apin 2 of the U10 is respectively connected with apin 4 and a pin VIN end of the GL4 through L2, apin 3 of the GL4 is connected with apin 2 of the U11, and apin 7 of the U11 is connected with a SYSTEM _ EN end;
the VIN end is respectively connected with the source electrode of the Q7 of the AOD403 tube and the source electrode of the Q8 of the AOD403 tube, the grid electrode of Q7 and the grid electrode of Q8 are connected with the drain electrode of the Q10 of the 2N7002 chip, the grid electrode of Q10 is connected with the SYSTEM _ EN end, and the source electrode of Q10 is connected with the GND end;
the drain of Q7 and the drain of Q8 are connected withpin 3 of U14,pin 1 of U14 is connected withpin 3 of U16, andpin 1 of U16 is connected with I _ OVER terminal.
The circuit is sampled through a 0.002R resistor R46, a high-end measuring current value is converted into a voltage value through a U14 amplifier, secondary amplification is carried out through U16, and when the current output exceeds a set output threshold value, the processor reduces an output signal to achieve short-circuit protection and can still output current.
The central processing unit adopts a stm32f103c8t6 chip U1, 20 pins of U1 are connected with the grid electrode of a 2N7002 tube Q6, and the drain electrode of Q6 is connected with an output relay;
the 43 pin of U1 is connected to the grid of Q9 of 2N7002 tube, the drain of Q9 is connected to connector J9, and the source of Q9 is grounded.
The analog-digital conversion part adopts a CS1237 chip U4, wherein 3 and 4 pins of U4 are correspondingly connected with a VL-end and a VL + end respectively, and 5 and 6 pins of U4 are correspondingly connected with a CS1237CK end and a CS1237D end respectively.
The sine wave generator adopts a PT8211 chip U7, pins 1, 2 and 3 of a U7 are correspondingly connected with a BCK end, a WS end and a DIN1 end respectively, and apin 8 of the U7 is connected with an IN + end through a resistor R22.
The switch trigger circuit comprises a CD4013B/SO chip U17, and apin 1 of U17 is connected with a SYSTEM _ EN terminal.
The linear voltage stabilizing circuit comprises an SGM2032-33 chip U12, an SGM2032-50 chip U13 and an SGM2032-33 chip U15, wherein apin 1 of U12 is connected with a VCC5V end, apin 5 of U12 is connected with a VCC3.3 end, apin 1 of U13 is connected with a VCC5V end, and apin 5 of U13 is connected with an AVCC5V end; the 1 pin of U15 is connected to VCC5V terminal, and the 5 pin of U15 is connected to AVCC3.3 terminal.
The startup and shutdown of the invention are realized by the combination of a hard switch and a soft switch (the hard switch is realized by connecting a battery and a circuit connecting end in series with a 20A air switch, and the soft switch is realized by a cd4013 RS trigger chip).
The sinusoidal alternating current (SOUT terminal of fig. 2) of the present invention is generated by modulating a rectangular square wave signal (PWMOUT of fig. 1).
The output relay in fig. 9 is used to completely disconnect the load.
It should be understood that the detailed description of the present invention is only for illustrating the present invention and is not limited by the technical solutions described in the embodiments of the present invention, and those skilled in the art should understand that the present invention can be modified or substituted equally to achieve the same technical effects; as long as the use requirements are met, the method is within the protection scope of the invention.
Claims (10)
1. The current protection tester comprises a central processing unit, a current acquisition part, a triangular wave generating circuit, an SPWM modulator, a half-bridge driving circuit, a filter circuit, a current output port, a switch voltage stabilizing circuit, an analog-to-digital conversion part, a sine wave generator, a switch trigger circuit and a linear voltage stabilizing circuit, and is characterized in that a signal output port of the sine wave generator and a signal output port of the triangular wave generating circuit are connected with a signal input port of the SPWM modulator;
the output port of the half-bridge driving circuit is connected with the current output port of the switching voltage stabilizing circuit through the filter circuit;
the input port of the linear voltage stabilizing circuit is connected with the voltage output port of the switch voltage stabilizing circuit;
the output port of the switch trigger circuit is connected with the control port of the switch voltage stabilizing circuit;
the input port of the analog-to-digital conversion part is connected with the output port of the current acquisition part, and the output port of the analog-to-digital conversion part is connected with the signal input port of the central processing unit;
the control signal output port of the central processing unit is respectively connected with the control signal input port of the switch voltage stabilizing circuit, the control signal input port of the switch trigger circuit, the control signal input port of the sine wave generator and the control signal input port of the triangular wave generating circuit.
2. The current protection tester of claim 1, wherein the current collection portion comprises an AD8552 chip UA2 and an AD8551 chip U8, wherein 2 pins of UA2 are respectively connected to 1 pin of a current collection interface J5, one end of a resistor R16 and one end of a resistor R21, the other end of the resistor R16 is respectively connected to the other end of R21, 1 pin of UA2 and one end of a resistor R20, 3 pins of UA2 are respectively connected to 2 pins of J5, 5 pins of UA2, 1 pin of U8 and 4 pins of U8, 3 pins of U8 are respectively connected to one end of a resistor R26, one end of a resistor R28 and one end of a capacitor C40, the other end of R26 is connected to an AVCC3.3 terminal, and the other ends of C40 and R28 are connected to AGND;
the 7 feet of UA2 are connected with the cathode of diode D10 and the anode of diode D11, the anode of D10 is connected with one end of resistor R24, one end of capacitor C34 and the VL-end, the other end of R24 is connected with the 6 feet of UA2, the other end of C34, one end of capacitor C30, one end of resistor R19 and the other end of R20, the other end of R19 is connected with the other end of C30, the cathode of D9 and one end of resistor R18, and the other end of R18 is connected with the VL + end.
3. The current protection tester as claimed in claim 1, wherein the input power source of the switching regulator circuit is a battery.
4. The current protection tester as claimed in claim 3, wherein the battery is a 12 volt lithium battery.
5. The current protection tester as claimed in claim 1, wherein the triangular wave generating circuit includes an AD8551 chip U9, wherein 3 pins of U9 are respectively connected to one end of a resistor R35, one end of a resistor R36, and one end of a capacitor C49, the other end of R35 is connected to an AVCC5V, and the other end of C49 is respectively connected to the other end of R36 and an AGND;
the 4 feet of U9 are connected with one end of a resistor R38 and one end of a resistor R39 respectively, the other end of R38 is connected with one end of a resistor R37 and one end of a capacitor C52 respectively through a capacitor C50, the other end of C52 is grounded, the other end of R37 is connected with a 200K end, and the other end of R39 is connected with the 1 foot and the T _ W end of U9 respectively.
6. The current protection tester as claimed IN claim 1, wherein the SPWM modulator includes an LM393 chip UA1, a 3-pin of UA1 is connected to an IN + terminal, a 2-pin of UA1 is connected to a T _ W terminal, a 4-pin of UA1 is connected to an 8-pin of UA1 and one end of a resistor R5 through a capacitor C16, and the other end of R5 is connected to a 1-pin of UA1 and an moput terminal.
7. The current protection tester as claimed in claim 1, wherein the half-bridge driving circuit comprises an EG3113 chip U3, pins 2 and 3 of U3 are connected to the PWMOUT terminal, pin 1 of U3 is connected to the anode of diode D3, the PVCC terminal, pin 2 of IPP048N12N Q1, pin 2 of PP048N12N Q2, and one end of resistor R8; a pin 1 of the Q1 is respectively connected with a pin 7 of the U3 and one end of a resistor R7 through a resistor R6, a pin 8 of the U3 is respectively connected with a cathode of the D3 and one end of a capacitor C18, and the other end of the C18 is respectively connected with a pin 6 of the U3, a pin 3 of the Q1, a pin 3 of the Q2 of the PP048N12N tube, a pin 2 of the Q4 of the PP048N12N tube, a pin 2 of the Q5 of the PP048N12N tube and one end of an inductor L1; the other end of R7 is connected with pin 1 of Q2;
pin 1 of Q4 is connected with pin 5 of U3 and one end of resistor R11 through resistor R10, the other end of R11 is connected with pin 1 of Q5, pin 3 of Q4, pin 3 of Q5 and the other end of R8 are grounded;
the other end of the L1 is respectively connected with the SOUT end and the anode of a capacitor C3, the cathode of the C3 is connected with the 4 pin of an SFK-112DM relay LS1, the 1 pin of the LS1 is connected with the cathode of a diode D5, the anode of the D5 is respectively connected with the 2 pin of the LS1 and the 3 pin of a 2N7002/SOT tube Q3, and the 1 pin of the Q3 is connected with the HRSEN1 end.
8. The current protection tester as claimed in claim 1, wherein the filter circuit comprises common mode inductors GL1, GL2 and GL3, wherein pin 1 of GL1 is connected to pin 3 of LS1, and pin 2 of GL1 is connected to pin 2 of Q3; pins 3 and 4 of GL1 are respectively connected to pins 2 and 1 of GL3, pins 3 and 4 of GL3 are respectively connected to pins 2 and 1 of GL2, and pins 3 and 4 of GL2 are respectively connected to pins 2 and 1 of current output port J2.
9. The current protection tester as claimed in claim 1, wherein the switching regulator circuit includes an AME5268 chip U10, an AME5268 chip U11, an INA194 chip U14, a common mode inductor GL4 and an AD8551 chip U16, wherein a pin 7 of the U10 is connected to the PVCCEN terminal, a pin 2 of the U10 is connected to a pin 4 and a pin VIN of the GL4 through L2, a pin 3 of the GL4 is connected to a pin 2 of the U11, and a pin 7 of the U11 is connected to the SYSTEM _ EN terminal;
the VIN end is respectively connected with the source electrode of the Q7 of the AOD403 tube and the source electrode of the Q8 of the AOD403 tube, the grid electrode of Q7 and the grid electrode of Q8 are connected with the drain electrode of the Q10 of the 2N7002 chip, the grid electrode of Q10 is connected with the SYSTEM _ EN end, and the source electrode of Q10 is connected with the GND end;
the drain of Q7 and the drain of Q8 are connected with pin 3 of U14, pin 1 of U14 is connected with pin 3 of U16, and pin 1 of U16 is connected with I _ OVER terminal.
10. The current protection tester as claimed in claim 1, wherein the cpu is a stm32f103c8t6 chip U1, U1 has its 20 pins connected to the gate of a 2N7002 transistor Q6, and Q6 has its drain connected to an output relay;
the 43 pin of U1 is connected to the grid of Q9 of 2N7002 tube, the drain of Q9 is connected to connector J9, and the source of Q9 is grounded.
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