CN110781117B - SPI expansion bus interface and system on chip based on FPGA - Google Patents

Abstract

The application discloses SPI expansion bus interface and system on chip based on FPGA, this SPI expansion bus interface includes: the functional interfaces are respectively connected with corresponding external equipment and are used for realizing SPI communication with the corresponding external equipment; the system bus interface is used for connecting a system bus of the MCU and mapping an external address sent by the MCU through the system bus into a corresponding register address, wherein the register address comprises an enabling register address; the controller comprises a control module and an enabling register, wherein the plurality of functional interfaces are respectively connected with the enabling register, and the control module operates the enabling register according to the address of the enabling register so as to control the plurality of functional interfaces. By the mode, the management control capability of the MUC on the external equipment is improved, and the expandability and the universality of the MCU function are enhanced.

Description

SPI expansion bus interface and system on chip based on FPGA

Technical Field

The present application relates to the field of bus interface technologies, and in particular, to an SPI expansion bus interface based on an FPGA (field programmable Gate Array) and a system on a chip.

Background

A Serial Peripheral Interface (SPI) is a high-speed, full-duplex, synchronous communication bus, which includes four ports, has simple and easy-to-use characteristics, and is generally used as an Interface for Serial communication between an external device and an off-chip system in the field of MCU (micro controller Unit).

However, the number of the existing SPI bus interfaces is limited, which results in poor expansibility and usability of the MCU.

Disclosure of Invention

In order to solve the problems, the application provides an SPI expansion bus interface based on an FPGA and a system on a chip, and the problems of poor MUC expansibility and usability in the prior art can be solved.

The technical scheme adopted by the application is as follows: the utility model provides a SPI expansion bus interface based on FPGA, this expansion bus interface is realized by FPGA logical resource to be used for connecting MCU and peripheral equipment, this expansion bus interface includes: the functional interfaces are respectively connected with corresponding external equipment and are used for realizing SPI communication with the corresponding external equipment; the system bus interface is used for connecting a system bus of the MCU and mapping an external address sent by the MCU through the system bus into a corresponding register address, wherein the register address comprises an enabling register address; the controller comprises a control module and an enabling register, wherein the plurality of functional interfaces are respectively connected with the enabling register, and the control module operates the enabling register according to the address of the enabling register so as to control the plurality of functional interfaces.

The control module operates the corresponding enable bit according to the address of the enable register, and then controls the enable state of the corresponding functional interface.

The control module is used for mapping the enabling pins of different functional interfaces to different enabling bits.

The controller further comprises a plurality of groups of function registers, each function interface is connected with one group of function registers, the register address comprises a function register address, the control module further operates the function registers according to the function register address, and the function interfaces realize SPI communication with corresponding external equipment based on the connected function registers.

The functional register addresses of the multiple groups of functional registers share the same address segment in the peripheral address space of the MCU.

The control module operates the multiple groups of functional registers simultaneously according to the addresses of the functional registers.

The control module determines a functional interface to be enabled according to the address of the enable register and operates a functional register connected with the functional interface to be enabled according to the address of the functional register.

And the MCU sets the offset addresses of the multiple groups of functional registers based on the same base address.

Each group of functional registers respectively comprises a control register, a state register, a read data register, a write data register and a slave address selection register.

Another technical scheme adopted by the application is as follows: a system on chip is provided, which comprises the expansion bus interface and an MCU connected with the expansion bus interface through a system bus.

The application provides SPI expansion bus interface based on FPGA is realized by FPGA logical resource to be used for connecting MCU and peripheral equipment, this expansion bus interface includes: the functional interfaces are respectively connected with corresponding external equipment and are used for realizing SPI communication with the corresponding external equipment; the system bus interface is used for connecting a system bus of the MCU and mapping an external address sent by the MCU through the system bus into a corresponding register address, wherein the register address comprises an enabling register address; the controller comprises a control module and an enabling register, wherein the plurality of functional interfaces are respectively connected with the enabling register, and the control module operates the enabling register according to the address of the enabling register so as to control the plurality of functional interfaces. In this way, based on FPGA logical resource and programmable characteristics, the SPI bus interface is expanded, the number and the function of the SPI functional interface can be dynamically adjusted, the problem of shortage of the SPI bus interface in the prior art is solved, in addition, the management and the control capacity of the MCU to external equipment are also mentioned, the expandability and the universality of the MCU are enhanced, and meanwhile, the design and the application complexity of the SPI interface are also reduced, and the SPI bus interface is convenient to use.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a block diagram of a system on a chip according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an SPI expansion bus interface provided in the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a controller provided in an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a functional interface provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of the connection between a control module and a functional interface according to an embodiment of the present application;

fig. 6 is a schematic workflow diagram of a system on chip according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a system on chip provided in an embodiment of the present application, where the system onchip 10 includes anMCU 11 and anFPGA 12, and theMCU 11 and theFPGA 12 are connected through asystem bus 13.

Logic resources inside theFPGA 12 form an SPIexpansion bus interface 20, and the SPIexpansion bus interface 20 is connected to theMCU 11 through thesystem bus 13. The logic resources inside theFPGA 12 mainly include an LCB (Logical Control Block) (including a display lookup table, an adder, a register, and a multiplexer), clock network resources, a clock processing unit, a Block random access memory (Block RAM), a DSP core, and interface resources. The SPIexpansion bus interface 20 in this embodiment is formed using logic resources inside theFPGA 12.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an SPI expansion bus interface provided in the embodiment of the present application, where the SPIexpansion bus interface 20 includes asystem bus interface 21, acontroller 22, and a plurality offunctional interfaces 23.

Thesystem bus interface 21 is configured to connect to thesystem bus 13 of theMCU 11, and map a peripheral address sent by theMCU 11 through thesystem bus 13 to a corresponding register address, so as to implement reading, writing, and controlling between theMCU 11 and a peripheral device, where the register address includes an enable register address. The plurality offunctional interfaces 23 are respectively connected to corresponding external devices, and are configured to implement SPI communication with the corresponding external devices.

Referring to fig. 3 again, fig. 3 is a schematic structural diagram of the controller according to the embodiment of the present application, where thecontroller 22 includes acontrol module 221 and aregister set 222, thecontrol module 221 is connected to thesystem bus interface 21 and each register in theregister set 222, and oneregister set 222 is connected to one of the plurality offunctional interfaces 23, that is, each register in oneregister set 222 is connected to one pin in onefunctional interface 23.

Theregister set 222 includes an enable register and a function register.

In an alternative embodiment, thecontrol module 221 may be implemented by a combinational logic circuit, and the logic function of the combinational logic circuit is characterized in that the output at any time is only dependent on the input at that time, and is independent of the original state of the circuit. Optionally, in an embodiment, the plurality ofregister sets 222 may respectively correspond to onecontrol module 221, and in another embodiment, the plurality ofregister sets 222 may correspond to thesame control module 221.

Theregister group 222 at least includes an enable register, wherein the plurality offunctional interfaces 23 are respectively connected to the enable register, and thecontrol module 221 operates the enable register according to an address of the enable register, thereby enabling and controlling the plurality offunctional interfaces 23.

Thecontroller 22 further comprises a plurality of sets of function registers, and eachfunction interface 23 is connected to a respective set of function registers.

The register address obtained by thecontroller 22 from thesystem bus interface 21 further includes a function register address, thecontrol module 221 further operates the function register according to the function register address, and thefunction interface 23 implements SPI communication with the corresponding external device based on the connected function register.

The functional register is a register for implementing a corresponding SPI function by performing read-write operations on the functional interface, and in an optional embodiment, the functional register includes a control register, a status register, a read data register, a write data register, and a slave address selection register.

The control register is used for controlling and determining the operation mode and the characteristics of the currently executed task; the status register is used to store two types of information: one type is various state information reflecting the execution result of the current instruction, and the other type is storage control information; the read data register is used for temporarily storing read data; the write data register is used for temporarily storing data to be written; the slave address selection register is used to store slave address information.

As shown in fig. 4, fig. 4 is a schematic structural diagram of a functional interface provided in the embodiment of the present application, where thefunctional interface 23 includes a plurality of pins.

The clock pin and the reset pin are connected to thesystem bus 13. Specifically, the clock pin is connected to a system bus clock, and the reset pin is connected to a system bus reset.

The system comprises an enabling pin, a control pin, a status pin, a data reading pin, a data writing pin and a slave address selection pin, wherein the enabling pin is connected with an enabling register, the control pin is connected with a control register, the status pin is connected with a status register, the data reading pin is connected with a data reading register, the data writing pin is connected with a data writing register, and the slave address selection pin is connected with.

Further, thefunctional interface 23 includes four ports, which are a signal output port (master output/slave input, MOSI), a signal input port (master input/slave output, MISO), a slave address selection port (SS), and a clock port (CK). Optionally, in another embodiment, an interrupt signal port (INT) may be further included, or there may be no signal output port (master output/slave input, MOSI).

With reference to fig. 1 to 4, thesystem bus 13 extends to the core of theFPGA 12 through the internal boundary of theFPGA 12, and is connected to thesystem bus interface 21, so as to realize the interaction between the core of theMCU 11 and the external device.

The enable register is provided with a plurality of enable bits capable of addressing through an address of the enable register, eachfunctional interface 23 corresponds to one enable bit, and thecontrol module 221 operates the corresponding enable bit according to the address of the enable register to further control the enable state of the correspondingfunctional interface 23. Further, the plurality offunctional interfaces 23 are respectively provided with an enable pin connected to the enable register, and thecontrol module 221 maps the enable pins of differentfunctional interfaces 23 to different enable bits.

Wherein the enable pins in eachfunctional interface 23 are mapped in combination as an enable register. Taking the example that theMCU 11 controls the threefunctional interfaces 23, the third bit of the enable register is mapped to the enable pins of the threefunctional interfaces 23, the enable register is set 1, thefunctional interface 23 is valid, otherwise, the functional interface is invalid. The number of thefunctional interfaces 23 is controlled in the manner of the enabling register, so that on one hand, the number of thefunctional interfaces 23 can be dynamically controlled, on the other hand, switching of base addresses can be avoided when a plurality of external devices are used, and the use complexity is reduced.

For example, thecontrol module 221 acquires the enable register address from thesystem bus interface 21, operates the corresponding enable bit of the enable register according to the enable register address, and controls the enable state of thefunction interface 23 corresponding to the enable bit.

In an alternative embodiment, the functional register addresses of the groups of functional registers share the same address segment in the peripheral address space of theMCU 11. Thecontrol module 221 operates on multiple sets of function registers simultaneously according to the function register addresses.

Taking write data as an example, thecontrol module 221 obtains the functional register address from thesystem bus interface 21, and since the functional register addresses of the plurality of functional registers share the same address segment in the peripheral address space of theMCU 11, thecontrol module 221 writes corresponding data into the write data register in eachregister group 222. Further, each write data register performs a write data operation on the external device through the correspondingfunctional interface 23.

In another alternative embodiment, thecontrol module 221 determines thefunctional interface 23 to be enabled according to the address of the enable register, and operates the functional register connected to thefunctional interface 23 to be enabled according to the address of the functional register.

Taking the read data as an example, thecontrol module 221 obtains an enable register address from thesystem bus interface 21, operates a corresponding enable bit of the enable register according to the enable register address, and controls the enable state of thefunction interface 23 corresponding to the enable bit. Further, thecontrol module 221 acquires the address of the function register from thesystem bus interface 21, and thecontrol module 221 determines thefunction interface 23 to be enabled according to the address of the enable register, and performs a data reading operation on the function register connected to thefunction interface 23 to be enabled according to the address of the function register.

In addition, theMCU 11 sets offset addresses of a plurality of sets of function registers based on the same base address. Taking the MCU as an example to control the threefunctional interfaces 23, the base address 0x10 is defined, and the offset addresses of the control register, the status register, the read data register, the write data register, the slave address selection register and the enable register are 0x0, 0x1, 0x2, 0x3, 0x4 and 0x5, respectively, which only need to occupy 6 address spaces. Compared to using three system buses to control threefunctional interfaces 23, each address includes 5 offset addresses, occupying 15 address spaces and saving 9 address spaces. In this way, the more the number of thefunctional interfaces 23 is, the more the number of the address spaces is saved, and the more the effect is obvious.

Referring to fig. 5 and fig. 6, fig. 5 is a schematic diagram illustrating a connection between a control module and a functional interface according to an embodiment of the present application, and fig. 6 is a schematic diagram illustrating a work flow of a system on chip according to an embodiment of the present application, where acontroller 22 according to this embodiment includes an enable register and a plurality of control modules, each control module corresponds to a group of functional registers, and each control module and a group of functional registers correspond to afunctional interface 23.

Further, the enable register is connected to an enable pin of eachfunctional interface 23, each control module is connected to the MCU interrupt vector table, a reset line in the system bus is connected to the reset pin of eachfunctional interface 23, and a clock line of the system bus is connected to the clock pin of eachfunctional interface 23.

Further, in the corresponding connection of one register group and onefunctional interface 23, the control register is connected to the control pin, the status register is connected to the status pin, the read data register is connected to the read data pin, the write data register is connected to the write data pin, and the slave address selection register is connected to the slave address selection pin.

The operation of the system-on-chip 10 in the above embodiment is described below with reference to fig. 1 to 6.

1) And judging whether the system bus is selected.

Specifically, when the MCU needs to perform read/write operations, the register address that needs to be read/written is sent to the address bus, and the control module can control the enable register to enable the corresponding functional interface according to the register address.

2) It is determined whether a read operation or a write operation.

Specifically, the MCU transmits a "read" or "write" signal to the control bus, and the control module adjusts the data transmission direction of the register to "read" or "write" according to the signal.

Furthermore, when reading operation is carried out, the control module controls the corresponding read data register, the control register and the state register to work; when writing operation is carried out, the control module controls the corresponding write data register, the control register and the state register to work.

The SPI expansion bus interface based on FPGA provided in this embodiment is implemented by FPGA logic resources, and is used to connect the MCU with an external device, and the expansion bus interface includes: the functional interfaces are respectively connected with corresponding external equipment and are used for realizing SPI communication with the corresponding external equipment; the system bus interface is used for connecting a system bus of the MCU and mapping an external address sent by the MCU through the system bus into a corresponding register address, wherein the register address comprises an enabling register address; the controller comprises a control module and an enabling register, wherein the plurality of functional interfaces are respectively connected with the enabling register, and the control module operates the enabling register according to the address of the enabling register so as to control the plurality of functional interfaces. In this way, based on FPGA logical resource and programmable characteristics, the SPI bus interface is expanded, the number and the function of the SPI functional interface can be dynamically adjusted, the problem of shortage of the SPI bus interface in the prior art is solved, in addition, the management and the control capacity of the MCU to external equipment are also mentioned, the expandability and the universality of the MCU are enhanced, and meanwhile, the design and the application complexity of the SPI interface are also reduced, and the SPI bus interface is convenient to use.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made according to the content of the present specification and the accompanying drawings, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. The utility model provides a SPI expansion bus interface based on FPGA which characterized in that, expansion bus interface is realized by FPGA logical resource to be used for connecting MCU and peripheral equipment, expansion bus interface includes:

the functional interfaces are respectively connected with corresponding external equipment and are used for realizing SPI communication with the corresponding external equipment;

the system bus interface is used for connecting a system bus of the MCU and mapping an external address sent by the MCU through the system bus into a corresponding register address, wherein the register address comprises an enabling register address;

the controller comprises a control module and an enabling register, wherein the plurality of functional interfaces are respectively connected with the enabling register, and the control module operates the enabling register according to the address of the enabling register so as to enable and control the plurality of functional interfaces corresponding to the address of the enabling register.

2. The expansion bus interface of claim 1,

the enabling register is provided with a plurality of enabling bits capable of addressing through the enabling register address, each functional interface corresponds to one enabling bit, and the control module operates the corresponding enabling bit according to the enabling register address so as to control the enabling state of the corresponding functional interface.

3. The expansion bus interface of claim 2,

the plurality of functional interfaces are respectively provided with an enabling pin connected to the enabling register, and the control module maps the enabling pins of different functional interfaces to different enabling bits.

4. The expansion bus interface of claim 1,

the controller further comprises a plurality of groups of function registers, each function interface is respectively connected with one group of function registers, the register address comprises a function register address, the control module further operates the function registers according to the function register address, and the function interfaces realize SPI communication with corresponding external equipment based on the connected function registers.

5. The expansion bus interface of claim 4,

and the functional register addresses of the multiple groups of functional registers share the same address segment in the peripheral address space of the MCU.

6. The expansion bus interface of claim 5,

and the control module operates the multiple groups of functional registers simultaneously according to the functional register addresses.

7. The expansion bus interface of claim 5,

and the control module determines the functional interface to be enabled according to the address of the enabling register and operates the functional register connected with the functional interface to be enabled according to the address of the functional register.

8. The expansion bus interface of claim 5,

and the MCU sets the offset addresses of the multiple groups of functional registers based on the same base address.

9. The expansion bus interface of claim 4,

each group of the function registers respectively comprises a control register, a state register, a read data register, a write data register and a slave address selection register.

10. A system on chip comprising an expansion bus interface according to any one of claims 1 to 9 and an MCU connected to the expansion bus interface via a system bus.

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