Disclosure of Invention
In view of the drawbacks of the prior art, a primary object of the present invention is to provide a control circuit and a control method for a compatible triac dimmer, which can solve the strobe problem and effectively reduce the duration of the bleeder current before the triac dimmer is turned on, thereby reducing the loss and improving the system efficiency.
To achieve the above and other objects, the present invention provides a control circuit compatible with a triac dimmer, configured to control a bleed current in an active modulation mode to balance a triac dimmer leakage current before the triac dimmer is turned on. The active modulation mode is distinguished from a control mode in which the predetermined pattern is varied and the bus voltage is constant at a predetermined value. Before the SCR dimmer is conducted, the on and off of the switch is controlled without the need of comparing the bus voltage signal with the reference threshold voltage. The system comprises a bus voltage sampling module, a signal conversion module, a TRIAC dimmer conduction judging module, a pulse generating module, a current discharging control module and a current discharging module.
The bus voltage sampling module is used for converting a bus voltage signal into a bus sampling signal. The signal conversion module is connected with the bus voltage sampling module and is used for comparing the bus sampling signal with a first reference voltage and outputting a bus square wave signal containing duty ratio information. The TRIAC dimmer conduction judging module is connected with the bus voltage sampling module and is used for comparing the bus sampling signal with a second reference voltage and outputting a conduction square wave signal containing the TRIAC dimmer conduction time information. The pulse generating module is used for generating a pulse square wave signal. The current leakage control module is connected with the pulse generation module, the signal conversion module and the TRIAC dimmer conduction judgment module and is used for generating a large current leakage control signal, a small current leakage control signal and a holding current leakage control signal according to the bus square wave signal, the conduction square wave signal and the pulse square wave signal. The current release module is connected with the current release control module and is used for adjusting the current value of the release current signal for controlling the bus voltage signal according to the large current release control signal, the small current release control signal and the holding current release control signal.
In an embodiment, the bus voltage sampling module includes a power tube, a first resistor and a second resistor connected in sequence.
In one embodiment, the power transistor is a HV NJFET.
In one embodiment, the signal conversion module includes a first comparator.
In one embodiment, the TRIAC dimmer conduction determination module includes a second comparator.
In one embodiment, the pulse generating module comprises an oscillator, a frequency divider and a monostable trigger which are connected in sequence.
In one embodiment, the current bleed module includes a transistor, a first switch, a second switch, and a third switch connected to the transistor, a first current connected to the first switch, a second current connected to the second switch, and a third current connected to the third switch.
In an embodiment, the current leakage control module includes a fourth switch, a first inverter, a second inverter, a third inverter, a first and gate, a second and gate, and a turn-on time window circuit, wherein the fourth switch is connected to an input terminal of the first and gate, an output terminal of the first inverter, the second inverter, and the third inverter is connected to an input terminal of the second and gate, an input terminal of the second inverter is connected to the fourth switch, and an input terminal of the third inverter is connected to the turn-on time window circuit.
In one embodiment, the pulse generating module is further configured to set a duty cycle of the pulse square wave signal to control the bleed current signal to accommodate the scr dimmers with different leakage currents.
The invention further provides a control method of the compatible silicon controlled rectifier dimmer, which comprises the steps of converting a bus voltage signal into a bus sampling signal through a bus voltage sampling module, comparing the bus sampling signal with a first reference voltage through a signal conversion module, outputting a bus square wave signal containing duty ratio information, comparing the bus sampling signal with a second reference voltage through a TRIAC dimmer conduction judging module, outputting a conduction square wave signal containing TRIAC dimmer conduction time information, generating a pulse square wave signal through a pulse generating module, generating a large current leakage control signal, a small current leakage control signal and a holding current leakage control signal through a current leakage control module according to the bus square wave signal, the conduction square wave signal and the pulse square wave signal, and adjusting the current value of the current signal for controlling the bus voltage signal through the current leakage control module according to the large current leakage control signal, the small current leakage control signal and the holding current leakage control signal.
The control method belongs to an active modulation mode, namely, a pulse generating circuit actively generates a pulse signal with a duty ratio, and different bleeder currents iBUS are controlled in a high-level stage and a low-level stage of the pulse signal to balance the leakage current of the silicon controlled rectifier dimmer. The active modulation mode is distinguished from a control mode in which the predetermined pattern is varied and the bus voltage is constant at a predetermined value. Before the SCR dimmer is conducted, the on and off of the switch is controlled without the need of comparing the bus voltage signal with the reference threshold voltage.
Compared with the prior art, the control circuit and the control method of the compatible silicon controlled rectifier dimmer belong to an active modulation mode, namely the pulse generating module actively generates a pulse square wave signal with a duty ratio, so that different bleeder current signals are controlled before the silicon controlled rectifier dimmer is conducted to balance the leakage current of the silicon controlled rectifier dimmer, thereby avoiding obvious delay of the conduction moment of the silicon controlled rectifier dimmer caused by excessive leakage current of the silicon controlled rectifier dimmer, and solving the problems of increased system power consumption, reduced efficiency and the like in the prior art.
Detailed Description
Further advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure, by describing embodiments of the present invention with specific examples. The invention is capable of other and different embodiments or of being practiced or of being carried out in various ways.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a control circuit compatible with a scr dimmer according to a first embodiment of the present invention. As shown in the drawings, the invention provides a control circuit compatible with a silicon controlled rectifier (scr) dimmer, which comprises a bus voltage sampling module 20, a signal conversion module 21, a TRIAC dimmer conduction judgment module 22, a pulse generation module 23, a current discharge control module 24 and a current discharge module 25.
The bus voltage sampling module 20 is used for converting a bus voltage signal VBUS into a bus sampling signal VBUS_IN. The signal conversion module 21 is connected to the bus voltage sampling module 20, and is configured to compare the bus sampling signal VBUS_IN with a first reference voltage VREF1 and output a bus square wave signal VBUS_ON containing duty cycle information. The TRIAC dimmer conduction judging module 22 is connected to the bus voltage sampling module 20, and is configured to compare the bus sampling signal VBUS_IN with a second reference voltage VREF2 and output a conduction square wave signal VBUS_TRIAC_ON containing the TRIAC dimmer conduction time information. The pulse generating module 23 is configured to generate a pulse square wave signal VS1. The current leakage control module 24 is connected to the pulse generation module 23, the signal conversion module 21 and the TRIAC dimmer conduction determination module 22, and is configured to generate a large current leakage control signal VS1A, a small current leakage control signal VS1B and a holding current leakage control signal VS2 according to the bus square wave signal VBUS_ON, the conduction square wave signal VBUS_TRIAC_ON and the pulse square wave signal VS1. The current leakage module 25 is connected to the current leakage control module 24, and is configured to adjust a current value of the leakage current signal iBUS for controlling the bus voltage signal VBUS according to the large current leakage control signal VS1A, the small current leakage control signal VS1B, and the holding current leakage control signal VS2.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a control circuit compatible with a scr dimmer according to a second embodiment of the present invention. In an embodiment, the bus voltage sampling module includes a power tube M2, a first resistor R1 and a second resistor R2 connected in sequence, for example, the power tube M2 may be, but not limited to, an HV NJFET.
In one embodiment, the signal conversion module 21 includes a first comparator CMP1.
In one embodiment, the TRIAC dimmer conduction determination module 22 includes a second comparator CMP2.
In one embodiment, the pulse generating module 23 includes an oscillator 230, a frequency divider 231, and a monostable 232 connected in sequence.
In one embodiment, the current leakage module 25 includes a transistor M1, a first switch S1, a second switch S2, and a third switch S3 connected to the transistor M1, and a first current i1, a second current i2, and a third current i3.
In one embodiment, the current leakage control module 24 includes a fourth switch S4, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first AND gate AND1, a second AND gate AND2, AND a turn-on time window circuit 240.
The bus voltage signal VBUS is adjusted to a bus sampling signal VBUS_IN with a lower voltage value through the power tube M2, the first resistor R1 and the second resistor R2. The positive electrode of the first comparator CMP1 is connected with the bus sampling signal VBUS_IN, the negative electrode of the first comparator CMP1 is connected with the reference voltage VREF1, the first comparator CMP1 outputs a bus square wave signal VBUS_ON which is connected with the control end of the fourth switch S4, AND the bus square wave signal VBUS_ON outputs a signal VBUS_OFF through the first inverter INV1 AND is connected with the input end of the second AND gate AND2. The bus square wave signal VBUS_ON controls the on or off of the fourth switch S4. One end of the fourth switch S4 receives the pulse VS1 output from the monostable 232, AND the other end of the fourth switch S4 outputs the pulse modulation signal VS1C to the second inverter INV2 AND the first AND gate AND1. The positive electrode of the second comparator CMP2 is connected to the bus sampling signal VBUS_IN, the negative electrode of the first comparator CMP1 is connected to the second reference voltage VREF2, and the first comparator CMP1 outputs the bus square wave signal VBUS_TRIAC_ON to the on-time window circuit 240. The on-time window circuit 240 outputs a signal of the current drain control signal VS2 to the control terminals of the third inverter INV3 and the third switch S3. The third inverter INV3 outputs a signal VS 2-to the first AND gate AND1 AND the second AND gate AND2. The first AND gate AND1 outputs the large current drain control signal VS1A, AND the second AND gate AND2 outputs the small current drain control signal VS1B.
The holding current bleed-off control signal VS2 controls the on and off of the third switch S3, the large current bleed-off control signal VS1A controls the on and off of the first switch S1, and the small current bleed-off control signal VS1B controls the on and off of the second switch S2.
The states of the first switch S1, the second switch S2, and the third switch S3 are adjusted to control the current value of the bleed current iBUS of the bus voltage signal VBUS.
When the first switch S1 is turned on, the second switch S2 and the third switch S3 are turned off, the bleeder current flowing through the MOS transistor M1 is switched to a current i1, i.e. a first current is output;
the second switch S2 is turned on, and the first switch S1 and the third switch S3 are turned off, so that the bleeder current flowing through the MOS transistor M1 is switched to a current i2, i.e. a second current is output;
When the third switch S3 is turned on and the first switch S1 and the second switch S2 are turned off, the bleed current flowing through the MOS transistor M1 is switched to a current i3, i.e. the output holding current.
Referring to fig. 4 and 5, fig. 4 is a schematic waveform diagram of a control circuit of a compatible scr dimmer according to a third embodiment of the present invention, and fig. 5 is a schematic waveform diagram of a control circuit of a compatible scr dimmer according to a fourth embodiment of the present invention.
In the interval from t1 to t2, the signal VBUS_OFF is at high level, the control circuit of the compatible scr dimmer of the present invention operates in an active modulation mode, i.e. the pulse generating module 23 actively generates a pulse square wave signal VS1 with duty ratio, the high current drain control signal VS1A and the low current drain control signal VS1B are modulated into mutually opposite pulse signals, and different drain current signals iBUS are controlled in the high level stage and the low level stage of the pulse signals to balance the leakage current of the scr dimmer. As shown in fig. 5, when the large current drain control signal VS1A is at a high level, the drain current signal iBUS flowing through the MOS transistor M1 is switched to the current i1, and when the small current drain control signal VS1B is at a low level, the drain current iBUS flowing through the MOS transistor M1 is switched to the current i2.
In the interval from t2 to t3, the current drain control signal VS2 is high, and the drain current iBUS flowing through the MOS transistor M1 is switched to the current i 3. the time t3 is determined by the on-time window circuit 240.
The leakage current of a thyristor dimmer is typically between a few mA and a few tens of mA. The current value of the holding current of the thyristor dimmer is typically in the order of tens of mA.
The holding current drain control signal VS2 outputs an enable control signal VS 2-through the inverter INV 3. The output of the first AND gate AND1 is the large current drain control signal VS1A. One input end of the first AND gate AND1 is connected with a signal obtained by passing the pulse square wave signal VS1 through the fourth switch S4, AND the other input end of the first AND gate AND1 is connected with an enabling control signal VS2-. The output of the second AND gate AND2 is the small current drain control signal VS1B. The input end of the second AND gate AND2 is connected with a signal passing through the second inverter INV2 after passing through the fourth switch S4 by the pulse square wave signal VS 1. The other end of the input of the second AND gate AND2 is connected with a signal passing through the first inverter INV1 by the bus square wave signal VBUS_ON. The other input of the second AND gate AND2 is terminated with an enable control signal VS2-.
The high current drain control signal VS1A is controlled by the high level pulse width of the pulse square wave signal VS 1. The small current drain control signal VS1B is controlled by the low level pulse width of the pulse square wave signal VS 1.
The on-time window circuit 240 enables the TRIAC dimmer to provide the bus voltage signal VBUS with a bleed current during a time window after turn-on to ensure that the dimmer can turn on normally. In the time window, the current drain control signal VS2 is high level, the third switch S3 is turned on, and beyond the time window, the current drain control signal VS2 is low level, and the third switch S3 is turned off.
In one embodiment, the pulse generating module 23 is further configured to set the duty cycle of the pulse square wave signal VS1 to control the bleed current signal iBUS to adapt to the scr dimmers with different leakage currents.
Preferably, when the duty cycle of the pulse square wave signal VS1 reaches a sufficiently large value, the main contribution of the bleed current signal iBUS flowing through the MOS transistor M1 comes from the first current. When the first current is set at a certain preset value, the leakage currents of the silicon controlled rectifier light modulator are balanced, and the compatibility of the silicon controlled rectifier light modulator is guaranteed to be optimal.
The control circuit compatible with the silicon controlled rectifier dimmer is configured to control the bleeder current signal iBUS in an active modulation mode before the silicon controlled rectifier dimmer is conducted so as to balance the leakage current of the silicon controlled rectifier dimmer, so that the leakage current of the silicon controlled rectifier dimmer flowing through an LED load is controllable, the problems of obviously delayed conduction time of the silicon controlled rectifier dimmer caused by excessive leakage current of the silicon controlled rectifier dimmer, increased system power consumption, reduced efficiency and the like in the prior art can be solved.
Further, the active modulation mode is to actively generate a pulse square wave signal VS1 with a duty ratio by the pulse generating module 23, and control different drain current signals iBUS to balance the leakage current of the scr dimmer in the high level stage and the low level stage of the pulse square wave signal VS 1. The active modulation mode is distinguished from the control mode in which the predetermined manner of the prior art is varied and the bus voltage is constant at a predetermined value. Before the silicon controlled rectifier dimmer is conducted by using the active modulation mode, the on and off of the switch is controlled without a comparison signal between a bus voltage signal and a reference threshold voltage.
Referring to fig. 6, fig. 6 is a flowchart illustrating a control method of a scr-compatible dimmer according to a fifth embodiment of the present invention. The invention also provides a control method of the compatible silicon controlled rectifier dimmer, which is used for controlling the release current to balance the leakage current of the silicon controlled rectifier dimmer, and comprises the following steps:
S61, converting a bus voltage signal into a bus sampling signal through a bus voltage sampling module.
S62, comparing the bus sampling signal with a first reference voltage through the signal conversion module, and outputting a bus square wave signal containing duty ratio information.
S63, comparing the bus sampling signal with a second reference voltage through the TRIAC dimmer conduction judging module, and outputting a conduction square wave signal containing the TRIAC dimmer conduction time information.
S64, generating a pulse square wave signal through a pulse generation module.
S65, generating a large-current discharge control signal, a small-current discharge control signal and a holding current discharge control signal through a current discharge control module according to the bus square wave signal, the conduction square wave signal and the pulse square wave signal.
S66, adjusting the current value of a bleeding current signal for controlling the bus voltage signal according to the large current bleeding control signal, the small current bleeding control signal and the holding current bleeding control signal through the current bleeding module.
The steps S62 to S64 may be performed in any order, or the steps S62 to S64 may be performed simultaneously.
In summary, the control circuit and the control method of the compatible scr dimmer of the present invention belong to an active modulation mode, that is, the pulse generating module actively generates a pulse square wave signal with a duty ratio, so that different bleed current signals are controlled to balance the leakage current of the scr dimmer before the scr dimmer is turned on, thereby avoiding the obvious delay of the turn-on time of the scr dimmer caused by excessive leakage current of the scr dimmer, and solving the problems of increased system power consumption, reduced efficiency, etc. in the prior art.
The features and spirit of the present invention will become apparent to those skilled in the art from the foregoing description of preferred embodiments, which is provided by way of illustration of the principles of the invention and its effectiveness, and not in limitation. Accordingly, any modifications and variations may be made to the above-described embodiments without departing from the spirit of the invention, and the scope of the invention is to be determined by the appended claims.