CN110727220B - Master-slave dual-redundancy FPGA switching control circuit - Google Patents

Abstract

The invention belongs to the field of digital circuit design, and relates to a master-slave dual-redundancy FPGA (field programmable gate array) switching control circuit which is composed of a watchdog reset module, an AND gate, two NOT gates, two groups of bus transceivers and two pull-up resistors. The circuit of the invention uses the watchdog reset module to carry out state monitoring by a core, and realizes FPGA redundancy switching control through the AND gate, the NOT gate and the bus transceiver, and the circuit is simple, has strong reliability and has higher practical value.

Description

Master-slave dual-redundancy FPGA switching control circuit

Technical Field

The invention belongs to the field of digital circuit design, and relates to a master-slave dual-redundancy FPGA switching control circuit.

Background

The FPGA has the advantages of flexible design, reconfiguration, strong parallelism and the like, and is widely applied to the fields of industry, military, medical electronics and the like. For equipment with higher reliability requirements, in order to avoid system function and even safety problems caused by single FPGA failure, a master-slave dual-redundancy FPGA design scheme is often adopted. The existing redundancy switching control is usually composed of devices such as a single chip microcomputer and a CPLD (complex programmable logic device) and related peripheral circuits, the working state of the FPGA is judged according to data interaction with the FPGA, and redundancy switching is performed when abnormality is found.

Disclosure of Invention

Object of the invention

The purpose of the invention is: aiming at the problems of complex control logic, poor reliability and the like of the existing master-slave dual-redundancy FPGA switching control mode, a simple and reliable master-slave dual-redundancy FPGA switching control circuit is provided.

(II) technical scheme

In order to solve the technical problem, the invention provides a master-slave dual-redundancy FPGA switching control circuit, which comprises a watchdog reset module, an AND gate, two NOT gates, two groups of bus transceivers and two pull-up resistors, wherein:

the watchdog module provides a watchdog input pin WDI, a low-effective watchdog output pin WDOn, a low-effective reset output pin RSTn and a low-effective manual reset input pin MRn;

the bus transceiver 1 provides a low effective output enable pin OEn, and reserves a data input end Ax (or Bx) and a corresponding data output end Bx (or Ax) for the switching control circuit, and the other data input and output ends are used for realizing data transceiving between the main redundancy FPGA and the bus.

The bus transceiver 2 provides a low effective output enable pin OEn, and a data input/output end of the bus transceiver is used for realizing data transceiving between the redundancy FPGA and the bus.

The parts have the following connection relationship:

a WDI pin of the watchdog reset module is connected with a general IO pin IOi of the main redundancy FPGA;

and a pin MRn of the watchdog reset module is connected with a CONF _ DONE of a configuration completion output pin of the main redundancy FPGA and is connected with a pull-up resistor.

A WDOn pin of the watchdog reset module is connected with an input of a NOT gate 1, and an output of the NOT gate 1 is connected with a data input end Ax (or Bx) of the bus transceiver 1;

a pin RSTn of the watchdog reset module is connected with a general IO pin IOj of the main redundancy FPGA to provide a reset signal for FPGA logic, and is simultaneously connected with the input of an AND gate, the other input end of the AND gate is connected with a data output end Bx (or Ax) of the bus transceiver 1 and is also connected with a pull-up resistor, and the pull-up resistor is used for maintaining the high level state of the signal in the non-enabled state of the output of the bus transceiver 1;

the output end of the AND gate is connected with an OEn pin of the bus transceiver 1 and is also connected with the input of the NOT gate 2;

the output of the not gate 2 is connected to the OEn pin of the bus transceiver 2.

The working flow of the master-slave dual-redundancy FPGA switching control circuit is as follows:

after the equipment is powered on, the main FPGA pulls down a CONF _ DONE output pin, so that the input of a MRn pin of a watchdog reset module is low, and the output of an RSTn pin is low;

since one input of the AND gate is low, the output is low, i.e., the OEn input of the bus transceiver 1 is low and the OEn input of the bus transceiver 2 is high, so that the bus transceiver 1 output is enabled and the bus transceiver 2 output is not enabled.

After the main redundancy FPGA receives all configuration data of the FPGA configuration chip, the CONF _ DONE pin is not pulled down any more, at the moment, due to the existence of a pull-up resistor, the input of the watchdog reset module MRn is high, and therefore the output of the RSTn pin is changed from low to high after a certain time.

After the CONF _ DONE pin output changes, the watchdog pulse output logic in the main redundancy FPGA works quickly, so that a pulse signal is output periodically through the IOi pin to avoid the watchdog action of the watchdog reset module, and the WDOn can maintain a high-level output state.

Since WDOn outputs high level, the not gate 1 outputs low level, and the low level enters the input end of the and gate through the bus transceiver 1, so that the and gate outputs low level, therefore, even if the watchdog reset module RSTn is changed from low to high, the state of enabling output of the bus transceiver 1 and disabling output of the bus transceiver 2 is still maintained, at this moment, the master redundancy FPGA can normally communicate with the bus, and the slave redundancy FPGA cannot transmit and receive bus data.

After the output of the pin RSTn of the watchdog reset module changes from low to high, if the FPGA works abnormally, a pulse signal cannot be periodically output through the pin IOi. When pulse interval time received by WDI exceeds a set threshold, the watchdog action of the watchdog reset module is triggered, so that the WDOn pin outputs low level, the NOT gate 1 outputs high level, and two input ends of the AND gate are both high level. And the AND gate outputs high level to make the bus transceiver 1 output non-enable, the bus transceiver 2 output enable to follow redundancy FPGA and can normally communicate with the bus, the main redundancy FPGA can not receive and send bus data, thus realizing redundancy switching.

(III) advantageous effects

The master-slave dual-redundancy FPGA switching control circuit provided by the technical scheme has the advantages that the watchdog reset module carries out state monitoring by using a core, the FPGA redundancy switching control is realized by using a AND gate, a NOT gate and a bus transceiver, the circuit is simple, the reliability is high, and the practical value is high.

Drawings

Fig. 1 is a schematic connection diagram of a master-slave dual-redundancy FPGA switching control circuit according to the present invention.

Detailed Description

In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

Referring to fig. 1, the specific implementation of the master-slave dual-redundancy FPGA switching control circuit of the present invention is as follows:

the master-slave redundancy FPGA adopts an EP3C55F484I7N chip of Altera corporation.

The utility model provides a master slaver dual-redundancy FPGA switches control circuit, by watchdog reset module, an AND gate, two NOT gates, two sets of bus transceiver and two pull-up resistance constitute, wherein:

the watchdog module is constructed by using a MAX706T chip and provides a watchdog input pin WDI, a low-effective watchdog output pin WDOn, a low-effective reset output pin RSTn and a low-effective manual reset input pin MRn;

the bus transceiver 1 is constructed by a bus transceiver from 3.3V to 3.3V, provides a low effective output enable pin OEn, reserves a data input end Ax (or Bx) and a corresponding data output end Bx (or Ax) for the switching control circuit, and the other data input and output ends are used for realizing data transceiving between the main redundancy FPGA and the bus.

The bus transceiver 2 provides a low effective output enable pin OEn, and a data input/output end of the bus transceiver is used for realizing data transceiving between the redundancy FPGA and the bus.

The parts have the following connection relationship:

a WDI pin of the MAX706T is connected with a general IO pin IOi of the main redundancy FPGA;

and an MRn pin of the MAX706T is connected with a CONF _ DONE output pin configured by a main redundancy FPGA, and is also connected with a 10k omega pull-up resistor R1.

The WDOn pin of the MAX706T is connected with the input of a NOT gate 1, and the output of the NOT gate 1 is connected with the data input end Ax (or Bx) of the bus transceiver 1;

the RSTn pin of the MAX706T is connected with a general IO pin IOj of the main redundancy FPGA to provide a reset signal for FPGA logic, and is simultaneously connected with the input of an AND gate, the other input end of the AND gate is connected with a data output end Bx (or Ax) of the bus transceiver 1 and is simultaneously connected with a 4.7k omega pull-up resistor R2, and the pull-up resistor is used for maintaining the high level state of the signal when the bus transceiver 1 outputs a non-enabled state;

the output end of the AND gate is connected with the OEn of the bus transceiver 1 and is also connected with the input of the NOT gate 2;

the output of the not gate 2 is connected to OEn of the bus transceiver 2.

The working flow of the master-slave dual-redundancy FPGA switching control circuit is as follows:

after the equipment is powered on, the main FPGA pulls down a CONF _ DONE output pin, so that the MRn pin input of MAX706T is low, and the RSTn pin output is low;

since one input of the and gate is low, the output is low, i.e. the OEn input of the bus transceiver 1 is low and the OEn input of the bus transceiver 2 is high, so that the bus transceiver 1 output is enabled and the bus transceiver 2 output is not enabled.

After the main redundancy FPGA receives all configuration data of the FPGA configuration chip, the CONF _ DONE pin is not pulled down any more, at the moment, due to the existence of the pull-up resistor R1 of 10k omega, the MRn input of the MAX706T is high, and therefore the RSTn pin output is changed from low to high after a certain time.

After the CONF _ DONE pin is output and changed, the watchdog pulse output logic in the main redundancy FPGA works quickly, so that a pulse signal is output periodically through the IOi pin to avoid the action of a watchdog of MAX706T, and the WDOn can maintain a high-level output state.

Since WDOn outputs high level, not gate 1 outputs low level, and this low level will enter the input end of and gate through bus transceiver 1, and make and gate output low level, therefore even if RSTn of MAX706T is changed from low to high, the state that bus transceiver 1 outputs enable and bus transceiver 2 outputs disable will be maintained, at this moment, the master redundancy FPGA can communicate with the bus normally, the slave redundancy FPGA can not receive and transmit bus data.

After the output of the pin RSTn of the watchdog reset module changes from low to high, if the FPGA works abnormally, a pulse signal cannot be periodically output through the pin IOi. When the pulse interval time received by the WDI is too long, the watchdog action of the watchdog reset module is triggered, so that the WDOn pin outputs low level, the NOT gate 1 outputs high level, and the two input ends of the AND gate are both high level. And the AND gate outputs high level to enable the bus transceiver 1 to output non-enable and the bus transceiver 2 to output enable, so that the slave redundancy FPGA can normally communicate with a bus, and the master redundancy FPGA cannot receive and transmit bus data, thereby realizing redundancy switching.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.

Claims (2)

1. A master-slave dual-redundancy FPGA switching control circuit is characterized by comprising: the watchdog reset module, an AND gate, two NOT gates, two groups of bus transceivers and two pull-up resistors; the two groups of bus transceivers comprise a bus transceiver 1 and a bus transceiver 2;

the watchdog reset module provides a watchdog input pin WDI, a low-effective watchdog output pin WDOn, a low-effective reset output pin RSTn and a low-effective manual reset input pin MRn;

the bus transceiver 1 provides a low effective output enable pin OEn, a data input end Ax or Bx and a corresponding data output end Bx or Ax are reserved for the switching control circuit, and the other data input and output ends are used for data transceiving between the main redundancy FPGA and the bus;

the bus transceiver 2 provides a low effective output enable pin OEn, and a data input/output end of the bus transceiver is used for receiving and transmitting data between the redundancy FPGA and the bus;

a WDI pin of the watchdog reset module is connected with a general IO pin IOi of the main redundancy FPGA;

a pin MRn of the watchdog reset module is connected with a CONF _ DONE of a configuration completion output pin of the main redundancy FPGA, and is connected with a pull-up resistor;

a WDOn pin of the watchdog reset module is connected with the input of a NOT gate 1, and the output of the NOT gate 1 is connected with a data input end Ax or Bx of the bus transceiver 1;

a pin RSTn of the watchdog reset module is connected with a general IO pin IOj of the main redundancy FPGA to provide a reset signal for FPGA logic, and is simultaneously connected with the input of an AND gate, the other input end of the AND gate is connected with a data output end Bx or Ax of the bus transceiver 1 and is simultaneously connected with a pull-up resistor, and the pull-up resistor is used for maintaining the high level state of the signal in the non-enabled state output by the bus transceiver 1;

the output end of the AND gate is connected with an OEn pin of the bus transceiver 1 and is also connected with the input of the NOT gate 2;

the output of the not gate 2 is connected to the OEn pin of the bus transceiver 2.

2. The master-slave dual-redundancy FPGA switching control circuit of claim 1, wherein after the switching control circuit is powered on, the master redundancy FPGA pulls down a configuration completion output pin CONF _ DONE of the master redundancy FPGA, the watchdog reset module active low manual reset input pin MRn input is low, and the active low reset output pin RSTn output is low; one input of the and gate is low, so the output is low, i.e. the low active output enable pin OEn input of the bus transceiver 1 is low and the low active output enable pin OEn input of the bus transceiver 2 is high, so that the bus transceiver 1 output enable and the bus transceiver 2 output are not enabled;

after the main redundancy FPGA receives all configuration data of the FPGA configuration chip, the output pin CONF _ DONE is completed without pulling down the configuration of the main redundancy FPGA, and at the moment, due to the existence of a pull-up resistor, the input of a low-effective manual reset input pin MRn of a watchdog reset module is high, so that the output of a low-effective reset output pin RSTn is changed from low to high after a certain time;

after the configuration of the main redundancy FPGA finishes the output change of the CONF _ DONE pin of the output pin, the watchdog pulse output logic in the main redundancy FPGA works, a pulse signal is periodically output through the IOi pin of the main redundancy FPGA to avoid the watchdog action of the watchdog reset module, and the WDOn pin of the low-effective watchdog maintains a high level output state;

the low effective watchdog output pin WDOn outputs high level, the NOT gate 1 outputs low level, the low level enters the input end of the AND gate through the bus transceiver 1 to enable the AND gate to output low level, even if the low effective reset output pin RSTn of the watchdog reset module changes from low to high, the states of enabling output of the bus transceiver 1 and disabling output of the bus transceiver 2 are continuously maintained, at the moment, the main redundancy FPGA and the bus normally communicate, and the slave redundancy FPGA cannot receive and transmit bus data;

when the pulse interval time received by the watchdog input pin WDI exceeds a set threshold, the watchdog action of the watchdog reset module is triggered, so that the low effective watchdog output pin WDOn outputs a low level, the NOT gate 1 outputs a high level, and the two input ends of the AND gate are both high levels; and the AND gate outputs high level to enable the bus transceiver 1 to output non-enable and the bus transceiver 2 to output enable, the slave redundancy FPGA and the bus normally communicate, and the master redundancy FPGA cannot receive and transmit bus data, so that redundancy switching is realized.

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