CN110677141A - Dynamic D flip-flops, data operation units, chips, computing power boards and computing equipment - Google Patents

Abstract

Translated fromChinese

本发明提供一种动态D触发器、数据运算单元、芯片、算力板及计算设备。动态D触发器，包括一输入端，一输出端，一时钟信号端；一第一数据传输单元；一第一锁存单元；一第二数据传输单元；一第二锁存单元；所述第一数据传输单元、所述第一锁存单元、所述第二数据传输单元、所述第二锁存单元依次串接在所述输入端和所述输出端之间，所述第一数据传输单元、所述第一锁存单元之间具有一第一节点，所述第二数据传输单元、所述第二锁存单元之间具有一第二节点；其中，还包括一漏电补偿单元，所述漏电补偿单元电性连接在所述第一节点、所述第二节点以及所述输出端之间。可以增加节点的等效电容，补偿节点的动态漏电流，提高数据的安全性和正确率。

The invention provides a dynamic D flip-flop, a data operation unit, a chip, a computing power board and a computing device. A dynamic D flip-flop, comprising an input end, an output end, a clock signal end; a first data transmission unit; a first latch unit; a second data transmission unit; a second latch unit; A data transmission unit, the first latch unit, the second data transmission unit, and the second latch unit are serially connected between the input end and the output end in sequence, and the first data transmission unit There is a first node between the unit and the first latch unit, and a second node between the second data transmission unit and the second latch unit; wherein, a leakage compensation unit is also included, so The leakage compensation unit is electrically connected between the first node, the second node and the output end. The equivalent capacitance of the node can be increased, the dynamic leakage current of the node can be compensated, and the security and accuracy of the data can be improved.

Description

Translated fromChinese

动态D触发器、数据运算单元、芯片、算力板及计算设备Dynamic D flip-flops, data operation units, chips, computing power boards and computing equipment

技术领域technical field

本发明涉及一种受时钟控制的存储器件，尤其涉及一种在大规模数据运算设备中应用的动态D触发器、数据运算单元、芯片、算力板及计算设备。The invention relates to a storage device controlled by a clock, in particular to a dynamic D flip-flop, a data operation unit, a chip, a computing power board and a computing device applied in large-scale data operation equipment.

背景技术Background technique

动态D触发器应用非常广泛，可用做数字信号的寄存。图1为现有动态D触发器的电路结构图。如图1所示，动态D触发器包括串联连接在输入端D及输出端Q之间的传输门101、反相器102、传输门103以及反相器104。传输门101与反相器102之间形成节点S0，传输门103与反相器104之间形成节点S1，数据通过反相器102以及反相器104中晶体管的寄生电容暂存在节点S0和/或节点S1。但是，节点S0和节点S1容易产生动态漏电，导致所暂存的数据丢失。Dynamic D flip-flops are widely used and can be used to register digital signals. FIG. 1 is a circuit structure diagram of a conventional dynamic D flip-flop. As shown in FIG. 1 , the dynamic D flip-flop includes atransmission gate 101 , aninverter 102 , atransmission gate 103 and aninverter 104 connected in series between the input terminal D and the output terminal Q. A node S0 is formed between thetransmission gate 101 and theinverter 102, a node S1 is formed between thetransmission gate 103 and theinverter 104, and the data is temporarily stored at the node S0 and/or the parasitic capacitance of the transistor in theinverter 102 and theinverter 104. or node S1. However, node S0 and node S1 are prone to dynamic leakage, resulting in the loss of temporarily stored data.

因此，如何有效减少动态D触发器的动态漏电实为需要解决的问题。Therefore, how to effectively reduce the dynamic leakage of the dynamic D flip-flop is a problem that needs to be solved.

发明内容SUMMARY OF THE INVENTION

为了解决上述问题，本发明提供一种动态D触发器，可以有效增加节点的等效电容，补偿节点的动态漏电流，提高数据的安全性和正确率。In order to solve the above problem, the present invention provides a dynamic D flip-flop, which can effectively increase the equivalent capacitance of the node, compensate the dynamic leakage current of the node, and improve the security and accuracy of data.

为了实现上述目的，本发明提供一种动态D触发器，包括一输入端，用于输入一数据；一输出端，用于输出所述数据；一时钟信号端，用于提供时钟信号；一第一数据传输单元，在所述时钟信号控制下传输所述数据；一第一锁存单元，用于锁存所述第一数据传输单元传输的数据；一第二数据传输单元，在所述时钟信号控制下传输所述第一锁存单元锁存的数据；一第二锁存单元，用于锁存所述第二数据传输单元传输的数据；所述第一数据传输单元、所述第一锁存单元、所述第二数据传输单元、所述第二锁存单元依次串接在所述输入端和所述输出端之间，所述第一数据传输单元、所述第一锁存单元之间具有一第一节点，所述第二数据传输单元、所述第二锁存单元之间具有一第二节点；其中，还包括一漏电补偿单元，所述漏电补偿单元电性连接在所述第一节点、所述第二节点以及所述输出端之间。In order to achieve the above object, the present invention provides a dynamic D flip-flop, which includes an input end for inputting a data; an output end for outputting the data; a clock signal end for providing a clock signal; a first a data transmission unit for transmitting the data under the control of the clock signal; a first latch unit for latching the data transmitted by the first data transmission unit; a second data transmission unit for transmitting the data latched by the first latch unit under signal control; a second latch unit for latching the data transmitted by the second data transmission unit; the first data transmission unit, the first The latch unit, the second data transmission unit, and the second latch unit are serially connected between the input end and the output end in sequence, and the first data transmission unit, the first latch unit There is a first node therebetween, and a second node is between the second data transmission unit and the second latch unit; wherein, a leakage compensation unit is also included, and the leakage compensation unit is electrically connected to the between the first node, the second node and the output terminal.

上述的动态D触发器，其中，所述漏电补偿单元具有一第一端、一第二端以及一控制端，所述第一端电性连接至所述输出端，所述第二端电性连接至所述第一节点，所述控制端电性连接至所述第二节点。The above dynamic D flip-flop, wherein the leakage compensation unit has a first end, a second end and a control end, the first end is electrically connected to the output end, and the second end is electrically connected is connected to the first node, and the control terminal is electrically connected to the second node.

上述的动态D触发器，其中，所述漏电补偿单元包括一PMOS晶体管及一NMOS晶体管，所述PMOS晶体管及所述NMOS晶体管串联连接在所述输出端与所述第一节点之间。In the above dynamic D flip-flop, wherein the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the output end and the first node.

上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述NMOS晶体管的所述漏极端，所述NMOS晶体管的所述源极端电性连接至所述第一节点，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述第二节点。The above dynamic D flip-flop, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, and the PMOS transistor has a source terminal, a drain terminal and a gate terminal. The source terminal is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, the source terminal of the NMOS transistor is electrically connected to the first node, and the A PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and is electrically connected to the second node.

上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述PMOS晶体管的所述漏极端，所述PMOS晶体管的所述源极端电性连接至所述第一节点，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述第二节点。The above dynamic D flip-flop, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, and the NMOS transistor has a source terminal, a drain terminal and a gate terminal. The source terminal is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, the source terminal of the PMOS transistor is electrically connected to the first node, the A PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and is electrically connected to the second node.

上述的动态D触发器，其中，所述时钟信号包括一第一时钟信号及一第二时钟信号，所述第一时钟信号与所述第二时钟信号反相。In the above dynamic D flip-flop, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are inverted.

上述的动态D触发器，其中，所述第一数据传输单元和/或所述第二数据传输单元为传输门。In the above dynamic D flip-flop, the first data transmission unit and/or the second data transmission unit are transmission gates.

上述的动态D触发器，其中，所述第一锁存单元和/或第二锁存单元为反相器。In the above dynamic D flip-flop, the first latch unit and/or the second latch unit are inverters.

使用本发明的动态D触发器，可以有效增加节点的等效电容，且能够从输出端反馈漏电电流到节点，补偿节点的动态漏电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。Using the dynamic D flip-flop of the present invention can effectively increase the equivalent capacitance of the node, and can feed back the leakage current from the output end to the node, compensate the dynamic leakage current of the node, improve the stability of data storage, and further enhance the security and safety of data. Correct rate.

为了更好地实现上述目的，本发明还提供了一种数据运算单元，包括互联连接的控制电路、运算电路、多个动态D触发器，所述多个动态D触发器为串联和/或并联连接；其中，所述多个动态D触发器为上述的任意一种动态D触发器。In order to better achieve the above purpose, the present invention also provides a data operation unit, comprising an interconnected control circuit, an operation circuit, and a plurality of dynamic D flip-flops, wherein the plurality of dynamic D flip-flops are connected in series and/or in parallel connection; wherein, the multiple dynamic D flip-flops are any of the above dynamic D flip-flops.

为了更好地实现上述目的，本发明还提供了一种芯片，其中，包括至少一个上述的数据运算单元。In order to better achieve the above object, the present invention also provides a chip, which includes at least one of the above data operation units.

为了更好地实现上述目的，本发明还提供了一种用于计算设备的算力板，其中，包括至少一个上述的芯片。In order to better achieve the above purpose, the present invention also provides a computing power board for a computing device, which includes at least one of the above-mentioned chips.

为了更好地实现上述目的，本发明还提供了一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其中，所述算力板为上述的算力板。In order to better achieve the above purpose, the present invention also provides a computing device, including a power board, a control board, a connecting board, a radiator and a plurality of computing power boards, the control board communicates with the computing power board through the connecting board The power board is connected, the radiator is arranged around the power board, and the power board is used to provide power to the connection board, the control board, the radiator and the power board, wherein, The computing power board is the aforementioned computing power board.

以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

附图说明Description of drawings

图1为现有动态D触发器的电路结构示意图；1 is a schematic diagram of the circuit structure of an existing dynamic D flip-flop;

图2为本发明一实施例动态D触发器的电路结构示意图；2 is a schematic diagram of a circuit structure of a dynamic D flip-flop according to an embodiment of the present invention;

图3为本发明又一实施例动态D触发器的电路结构示意图；3 is a schematic diagram of a circuit structure of a dynamic D flip-flop according to another embodiment of the present invention;

图4为本发明数据运算单元的结构示意图；Fig. 4 is the structural representation of the data operation unit of the present invention;

图5为本发明芯片的结构示意图；5 is a schematic structural diagram of a chip of the present invention;

图6为本发明算力板的结构示意图；6 is a schematic structural diagram of a computing power board of the present invention;

图7为本发明计算设备的结构示意图。FIG. 7 is a schematic structural diagram of a computing device of the present invention.

其中，附图标记：Among them, reference numerals:

100、200：动态D触发器100, 200: Dynamic D flip-flop

101、103：传输门101, 103: Transmission gate

102、104：反相器102, 104: Inverter

201：第一数据传输单元201: The first data transmission unit

202：第一锁存单元202: the first latch unit

203：第二数据传输单元203: second data transmission unit

204：第二锁存单元204: the second latch unit

205：漏电补偿单元205: Leakage compensation unit

201P、203P、205P：PMOS晶体管201P, 203P, 205P: PMOS transistors

201N、203N、205N：NMOS晶体管201N, 203N, 205N: NMOS transistors

400：数据运算单元400: Data operation unit

401：控制电路401: Control circuit

402：运算电路402: Operational circuit

500：芯片500: Chip

501：控制单元501: Control unit

600：算力板600: Hashboard

700：计算设备700: Computing Equipment

701：连接板701: Connection board

702：控制板702: Control Board

703：散热器703: Radiator

704：电源板704: Power Strip

D：输入端D: input terminal

Q：输出端Q: output terminal

CKP、CKN：时钟信号CKP, CKN: clock signal

S0、S1：节点S0, S1: Node

具体实施方式Detailed ways

下面结合附图对本发明的结构原理和工作原理作具体的描述：Below in conjunction with accompanying drawing, structure principle and working principle of the present invention are described in detail:

在说明书及后续的权利要求当中使用了某些词汇来指称特定组件。所属领域中具有通常知识者应可理解，制造商可能会用不同的名词来称呼同一个组件。本说明书及后续的权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。Certain terms are used in the specification and the claims that follow to refer to particular elements. It should be understood by those with ordinary knowledge in the art that manufacturers may refer to the same component by different nouns. The present specification and the following claims do not use the difference in name as a way of distinguishing components, but use the difference in function of the components as a criterion for distinguishing.

在通篇说明书及后续的权利要求当中所提及的“包括”和“包含”为一开放式的用语，故应解释成“包含但不限定于”。以外，“连接”一词在此为包含任何直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。References to "including" and "comprising" throughout the specification and the following claims are open-ended terms and should be interpreted as "including but not limited to". Otherwise, the term "connected" is used herein to include any direct and indirect means of electrical connection. Indirect electrical connection means include connection through other means.

实施例一：Example 1:

图2为本发明一实施例动态D触发器的电路结构示意图。如图2所示，动态D触发器200包括输入端D、输出端Q、时钟信号端CKN、时钟信号端CKP、第一数据传输单元201、第一锁存单元202、第二数据传输单元203、第二锁存单元204以及漏电补偿单元205。第一数据传输单元201、第一锁存单元202、第二数据传输单元203、第二锁存单元204依次串联连接在输入端D和输出端Q之间，第一数据传输单元201和第一锁存单元202之间形成第一节点S0，第二数据传输单元203和第二锁存单元204之间形成第二节点S1。漏电补偿单元205电性连接在第一节点S0、第二节点S1以及输出端Q之间。其中，输入端D用于输入数据，输出端用于输出数据，时钟信号端CKN以及时钟信号端CKP用于提供时钟信号CKN以及时钟信号CKP，时钟信号CKN与时钟信号CKP为反相时钟信号。FIG. 2 is a schematic diagram of a circuit structure of a dynamic D flip-flop according to an embodiment of the present invention. As shown in FIG. 2 , the dynamic D flip-flop 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a firstdata transmission unit 201 , afirst latch unit 202 , and a seconddata transmission unit 203 , thesecond latch unit 204 and theleakage compensation unit 205 . The firstdata transmission unit 201, thefirst latch unit 202, the seconddata transmission unit 203, and thesecond latch unit 204 are connected in series between the input end D and the output end Q in turn. The firstdata transmission unit 201 and the first A first node S0 is formed between thelatch units 202 , and a second node S1 is formed between the seconddata transmission unit 203 and thesecond latch unit 204 . Theleakage compensation unit 205 is electrically connected between the first node S0 , the second node S1 and the output terminal Q. The input terminal D is used for inputting data, the output terminal is used for outputting data, the clock signal terminal CKN and the clock signal terminal CKP are used for providing the clock signal CKN and the clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

具体的，如图2所示，动态D触发器200的第一数据传输单元201为传输门结构，数据传输单元201包括并联连接的PMOS晶体管201P以及NMOS晶体管201N。其中，PMOS晶体管201P的源极端与NMOS晶体管201N的源极端并联连接，并电性连接至动态D触发器200的输入端D，PMOS晶体管201P的漏极端与NMOS晶体管201N的漏极端并联连接，并电性连接至第一节点S0。NMOS晶体管201N的栅极端电性连接至时钟信号CKN，PMOS晶体管201P的栅极端电性连接至时钟信号CKP。当CKP为低电平时，CKN为高电平，PMOS晶体管201P与NMOS晶体管201N均为导通状态，动态D触发器200输入端D的数据通过第一数据传输单元201传送至第一节点S0。当CKP为高电平时，CKN为低电平，PMOS晶体管201P与NMOS晶体管201N均为不导通状态，动态D触发器200输入端D的数据不能通过第一数据传输单元201向第一节点S0进行传送。在本实施例中，第一数据传输单元201以传输门结构进行举例，当然，也可以是其他形式的数据传输单元，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。Specifically, as shown in FIG. 2 , the firstdata transmission unit 201 of the dynamic D flip-flop 200 is a transmission gate structure, and thedata transmission unit 201 includes aPMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of thePMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N, and is electrically connected to the input terminal D of the dynamic D flip-flop 200, and the drain terminal of thePMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N, and It is electrically connected to the first node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of thePMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is at low level, CKN is at high level,PMOS transistor 201P and NMOS transistor 201N are both on, and data at input D of dynamic D flip-flop 200 is transmitted to first node S0 through firstdata transmission unit 201 . When CKP is at a high level, CKN is at a low level, both thePMOS transistor 201P and the NMOS transistor 201N are in a non-conducting state, and the data at the input terminal D of the dynamic D flip-flop 200 cannot pass through the firstdata transmission unit 201 to the first node S0 to transmit. In this embodiment, the firstdata transmission unit 201 is exemplified by a transmission gate structure. Of course, it can also be other forms of data transmission units, as long as the switch function can be realized under the control of the clock signal. This is limited.

继续参照图2所示，动态D触发器200的第一锁存单元202为反相器结构，第一锁存单元202既可以利用其寄生电容暂存从第一数据传输单元201传输过来的数据，即第一节点S0处的数据，还可以将第一节点S0处的数据反相，并传送至第二数据传输单元203。Continuing to refer to FIG. 2 , thefirst latch unit 202 of the dynamic D flip-flop 200 is an inverter structure, and thefirst latch unit 202 can temporarily store the data transmitted from the firstdata transmission unit 201 by using its parasitic capacitance. , that is, the data at the first node S0 , the data at the first node S0 may also be inverted and transmitted to the seconddata transmission unit 203 .

如图2所示，动态D触发器200的第二数据传输单元202为传输门结构，第二数据传输单元203包括并联连接的PMOS晶体管203P以及NMOS晶体管203N。其中，PMOS晶体管203P的源极端与NMOS晶体管203N的源极端并联连接，并电性连接至第一锁存单元202，PMOS晶体管203P的漏极端与NMOS晶体管203N的漏极端并联连接，并电性连接至第二节点S1。NMOS晶体管203N的栅极端电性连接至时钟信号CKP，PMOS晶体管203P的栅极端电性连接至时钟信号CKN。当CKN为低电平时，CKP为高电平，PMOS晶体管203P与NMOS晶体管203N均为导通状态，第一锁存单元202输出的数据通过第二数据传输单元203传送至第二节点S1。当CKN为高电平时，CKP为低电平，PMOS晶体管203P与NMOS晶体管203N均为不导通状态，动态D触发器200输入端D的数据不能通过第二数据传输单元203向第二节点S1进行传送。在本实施例中，第二数据传输单元203以传输门结构进行举例，当然，也可以是其他形式的数据传输单元，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。As shown in FIG. 2 , the seconddata transmission unit 202 of the dynamic D flip-flop 200 is a transmission gate structure, and the seconddata transmission unit 203 includes a PMOS transistor 203P and anNMOS transistor 203N connected in parallel. The source terminal of the PMOS transistor 203P is connected in parallel with the source terminal of theNMOS transistor 203N, and is electrically connected to thefirst latch unit 202, and the drain terminal of the PMOS transistor 203P is connected in parallel with the drain terminal of theNMOS transistor 203N, and is electrically connected to the second node S1. The gate terminal of theNMOS transistor 203N is electrically connected to the clock signal CKP, and the gate terminal of the PMOS transistor 203P is electrically connected to the clock signal CKN. When CKN is low and CKP is high, both the PMOS transistor 203P and theNMOS transistor 203N are turned on, and the data output by thefirst latch unit 202 is transmitted to the second node S1 through the seconddata transmission unit 203 . When CKN is at a high level, CKP is at a low level, both the PMOS transistor 203P and theNMOS transistor 203N are in a non-conducting state, and the data at the input terminal D of the dynamic D flip-flop 200 cannot pass through the seconddata transmission unit 203 to the second node S1 to transmit. In this embodiment, the seconddata transmission unit 203 is exemplified by a transmission gate structure. Of course, it can also be other forms of data transmission units, as long as the switching function can be realized under the control of the clock signal. This is limited.

继续参照图2所示，动态D触发器200的第二锁存单元204为反相器结构，第二锁存单元204与第一锁存单元202一样，既可以利用其寄生电容暂存从第二数据传输单元203传输过来的数据，即第二节点S1处的数据，还可以将第二节点S1处的数据反相，并传送至动态D触发器200的输出端Q。Continuing to refer to FIG. 2 , thesecond latch unit 204 of the dynamic D flip-flop 200 is an inverter structure. Like thefirst latch unit 202 , thesecond latch unit 204 can use its parasitic capacitance to temporarily store The data transmitted from the seconddata transmission unit 203 , that is, the data at the second node S1 , can also invert the data at the second node S1 and transmit it to the output Q of the dynamic D flip-flop 200 .

由此可见，第一数据传输单元201以及第二数据传输单元203受到反相时钟信号的控制，即第一数据传输单元201以及第二数据传输单元203不会同时导通和/或截止，动态D触发器200中的第一锁存单元202和第二锁存单元204根据时钟信号起到数据寄存的作用。且，动态D触发器200输入端D的数据经过第一锁存单元202和第二锁存单元204的反相，使得输出端Q的数据与输入端D的数据同相。同时，第一锁存单元202和第二锁存单元204还可以起到提高数据驱动能力的作用。It can be seen that the firstdata transmission unit 201 and the seconddata transmission unit 203 are controlled by the inverted clock signal, that is, the firstdata transmission unit 201 and the seconddata transmission unit 203 will not be turned on and/or turned off at the same time, and the dynamic Thefirst latch unit 202 and thesecond latch unit 204 in the D flip-flop 200 play the role of data registration according to the clock signal. In addition, the data at the input terminal D of the dynamic D flip-flop 200 is inverted by thefirst latch unit 202 and thesecond latch unit 204, so that the data at the output terminal Q is in phase with the data at the input terminal D. At the same time, thefirst latch unit 202 and thesecond latch unit 204 can also play a role in improving the data driving capability.

如图2所示，动态D触发器200还包括漏电补偿单元205。在本实施例中，漏电补偿单元205包括PMOS晶体管205P以及NMOS晶体管205N，PMOS晶体管205P以及NMOS晶体管205N串联连接在输出端Q以及第一节点S0之间。PMOS晶体管205P的源极端电性连接至输出端Q，PMOS晶体管205P的漏极端电性连接至NMOS晶体管205N的漏极端，NMOS晶体管205N的源极端电性连接至第一节点S0，PMOS晶体管205P以及NMOS晶体管205N的栅极端并联连接在一起，并电性连接至第二节点S1。As shown in FIG. 2 , the dynamic D flip-flop 200 further includes aleakage compensation unit 205 . In this embodiment, theleakage compensation unit 205 includes a PMOS transistor 205P and anNMOS transistor 205N, and the PMOS transistor 205P and theNMOS transistor 205N are connected in series between the output end Q and the first node S0 . The source terminal of the PMOS transistor 205P is electrically connected to the output terminal Q, the drain terminal of the PMOS transistor 205P is electrically connected to the drain terminal of theNMOS transistor 205N, the source terminal of theNMOS transistor 205N is electrically connected to the first node S0, the PMOS transistor 205P and Gate terminals of theNMOS transistors 205N are connected together in parallel and are electrically connected to the second node S1.

由于PMOS晶体管205P以及NMOS晶体管205N的栅极端同样都电性连接至第二节点S1，在相同电平的信号驱动下，PMOS晶体管205P以及NMOS晶体管205N不会同时导通，只能有一个处于导通状态，另一个处于截止状态。例如，当第二节点S1处的电位为高电平时，PMOS晶体管205P处于截止状态，而NMOS晶体管205N处于导通状态；当第二节点S1处的电位为低电平时，PMOS晶体管205P处于导通状态，而NMOS晶体管205N处于截止状态。因此，漏电补偿单元205可以将输出端Q的漏电电流反馈至第一节点S0处的同时，增加第二节点S1处的寄生电容，既可以补偿第一节点S0处的漏电电流，又可以增加第二节点S1处的寄生电容，从而提高第一节点S0及第二节点S1处数据存储的稳定性，增强数据的正确性和安全性。Since the gate terminals of the PMOS transistor 205P and theNMOS transistor 205N are also electrically connected to the second node S1, under the same level of signal driving, the PMOS transistor 205P and theNMOS transistor 205N will not be turned on at the same time, and only one of them can be turned on. On state, the other is off state. For example, when the potential at the second node S1 is at a high level, the PMOS transistor 205P is in an off state, and theNMOS transistor 205N is in an on state; when the potential at the second node S1 is at a low level, the PMOS transistor 205P is in an on state state, while theNMOS transistor 205N is in an off state. Therefore, theleakage compensation unit 205 can increase the parasitic capacitance at the second node S1 while feeding back the leakage current of the output terminal Q to the first node S0, which can not only compensate the leakage current at the first node S0, but also increase the first node S0. Two parasitic capacitances at the nodes S1, thereby improving the stability of data storage at the first node S0 and the second node S1, and enhancing the correctness and security of the data.

实施例二：Embodiment 2:

图3为本发明又一实施例动态D触发器的电路结构示意图。图3为本发明一实施例动态D触发器的电路结构示意图。如图3所示，动态D触发器200包括输入端D、输出端Q、时钟信号端CKN、时钟信号端CKP、第一数据传输单元201、第一锁存单元202、第二数据传输单元203、第二锁存单元204以及漏电补偿单元205。第一数据传输单元201、第一锁存单元202、第二数据传输单元203、第二锁存单元204依次串联连接在输入端D和输出端Q之间，第一数据传输单元201和第一锁存单元202之间形成第一节点S0，第二数据传输单元203和第二锁存单元204之间形成第二节点S1。漏电补偿单元205电性连接在第一节点S0、第二节点S1以及输出端Q之间。其中，输入端D用于输入数据，输出端用于输出数据，时钟信号端CKN以及时钟信号端CKP用于提供时钟信号CKN以及时钟信号CKP，时钟信号CKN与时钟信号CKP为反相时钟信号。FIG. 3 is a schematic diagram of a circuit structure of a dynamic D flip-flop according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a circuit structure of a dynamic D flip-flop according to an embodiment of the present invention. As shown in FIG. 3 , the dynamic D flip-flop 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a firstdata transmission unit 201 , afirst latch unit 202 , and a seconddata transmission unit 203 , thesecond latch unit 204 and theleakage compensation unit 205 . The firstdata transmission unit 201, thefirst latch unit 202, the seconddata transmission unit 203, and thesecond latch unit 204 are connected in series between the input end D and the output end Q in turn. The firstdata transmission unit 201 and the first A first node S0 is formed between thelatch units 202 , and a second node S1 is formed between the seconddata transmission unit 203 and thesecond latch unit 204 . Theleakage compensation unit 205 is electrically connected between the first node S0 , the second node S1 and the output terminal Q. The input terminal D is used for inputting data, the output terminal is used for outputting data, the clock signal terminal CKN and the clock signal terminal CKP are used for providing the clock signal CKN and the clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

具体的，如图3所示，动态D触发器200的第一数据传输单元201为传输门结构，数据传输单元201包括并联连接的PMOS晶体管201P以及NMOS晶体管201N。其中，PMOS晶体管201P的源极端与NMOS晶体管201N的源极端并联连接，并电性连接至动态D触发器200的输入端D，PMOS晶体管201P的漏极端与NMOS晶体管201N的漏极端并联连接，并电性连接至第一节点S0。NMOS晶体管201N的栅极端电性连接至时钟信号CKN，PMOS晶体管201P的栅极端电性连接至时钟信号CKP。当CKP为低电平时，CKN为高电平，PMOS晶体管201P与NMOS晶体管201N均为导通状态，动态D触发器200输入端D的数据通过第一数据传输单元201传送至第一节点S0。当CKP为高电平时，CKN为低电平，PMOS晶体管201P与NMOS晶体管201N均为不导通状态，动态D触发器200输入端D的数据不能通过第一数据传输单元201向第一节点S0进行传送。在本实施例中，第一数据传输单元201以传输门结构进行举例，当然，也可以是其他形式的数据传输单元，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。Specifically, as shown in FIG. 3 , the firstdata transmission unit 201 of the dynamic D flip-flop 200 is a transmission gate structure, and thedata transmission unit 201 includes aPMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of thePMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N, and is electrically connected to the input terminal D of the dynamic D flip-flop 200, and the drain terminal of thePMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N, and It is electrically connected to the first node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of thePMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is at low level, CKN is at high level,PMOS transistor 201P and NMOS transistor 201N are both on, and data at input D of dynamic D flip-flop 200 is transmitted to first node S0 through firstdata transmission unit 201 . When CKP is at a high level, CKN is at a low level, both thePMOS transistor 201P and the NMOS transistor 201N are in a non-conducting state, and the data at the input terminal D of the dynamic D flip-flop 200 cannot pass through the firstdata transmission unit 201 to the first node S0 to transmit. In this embodiment, the firstdata transmission unit 201 is exemplified by a transmission gate structure. Of course, it can also be other forms of data transmission units, as long as the switch function can be realized under the control of the clock signal. This is limited.

继续参照图3所示，动态D触发器200的第一锁存单元202为反相器结构，第一锁存单元202既可以利用其寄生电容暂存从第一数据传输单元201传输过来的数据，即第一节点S0处的数据，还可以将第一节点S0处的数据反相，并传送至第二数据传输单元203。Continuing to refer to FIG. 3 , thefirst latch unit 202 of the dynamic D flip-flop 200 is an inverter structure, and thefirst latch unit 202 can temporarily store the data transmitted from the firstdata transmission unit 201 by using its parasitic capacitance , that is, the data at the first node S0 , the data at the first node S0 may also be inverted and transmitted to the seconddata transmission unit 203 .

如图3所示，动态D触发器200的第二数据传输单元202为传输门结构，第二数据传输单元203包括并联连接的PMOS晶体管203P以及NMOS晶体管203N。其中，PMOS晶体管203P的源极端与NMOS晶体管203N的源极端并联连接，并电性连接至第一锁存单元202，PMOS晶体管203P的漏极端与NMOS晶体管203N的漏极端并联连接，并电性连接至第二节点S1。NMOS晶体管203N的栅极端电性连接至时钟信号CKP，PMOS晶体管203P的栅极端电性连接至时钟信号CKN。当CKN为低电平时，CKP为高电平，PMOS晶体管203P与NMOS晶体管203N均为导通状态，第一锁存单元202输出的数据通过第二数据传输单元203传送至第二节点S1。当CKN为高电平时，CKP为低电平，PMOS晶体管203P与NMOS晶体管203N均为不导通状态，动态D触发器200输入端D的数据不能通过第二数据传输单元203向第二节点S1进行传送。在本实施例中，第二数据传输单元203以传输门结构进行举例，当然，也可以是其他形式的数据传输单元，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。As shown in FIG. 3 , the seconddata transmission unit 202 of the dynamic D flip-flop 200 is a transmission gate structure, and the seconddata transmission unit 203 includes a PMOS transistor 203P and anNMOS transistor 203N connected in parallel. The source terminal of the PMOS transistor 203P is connected in parallel with the source terminal of theNMOS transistor 203N, and is electrically connected to thefirst latch unit 202, and the drain terminal of the PMOS transistor 203P is connected in parallel with the drain terminal of theNMOS transistor 203N, and is electrically connected to the second node S1. The gate terminal of theNMOS transistor 203N is electrically connected to the clock signal CKP, and the gate terminal of the PMOS transistor 203P is electrically connected to the clock signal CKN. When CKN is low and CKP is high, both the PMOS transistor 203P and theNMOS transistor 203N are turned on, and the data output by thefirst latch unit 202 is transmitted to the second node S1 through the seconddata transmission unit 203 . When CKN is at a high level, CKP is at a low level, both the PMOS transistor 203P and theNMOS transistor 203N are in a non-conducting state, and the data at the input terminal D of the dynamic D flip-flop 200 cannot pass through the seconddata transmission unit 203 to the second node S1 to transmit. In this embodiment, the seconddata transmission unit 203 is exemplified by a transmission gate structure. Of course, it can also be other forms of data transmission units, as long as the switching function can be realized under the control of the clock signal. This is limited.

继续参照图3所示，动态D触发器200的第二锁存单元204为反相器结构，第二锁存单元204与第一锁存单元202一样，既可以利用其寄生电容暂存从第二数据传输单元203传输过来的数据，即第二节点S1处的数据，还可以将第二节点S1处的数据反相，并传送至动态D触发器200的输出端Q。3, thesecond latch unit 204 of the dynamic D flip-flop 200 is an inverter structure. Like thefirst latch unit 202, thesecond latch unit 204 can use its parasitic capacitance to temporarily store the The data transmitted from the seconddata transmission unit 203 , that is, the data at the second node S1 , can also invert the data at the second node S1 and transmit it to the output Q of the dynamic D flip-flop 200 .

由此可见，第一数据传输单元201以及第二数据传输单元203受到反相时钟信号的控制，即第一数据传输单元201以及第二数据传输单元203不会同时导通和/或截止，动态D触发器200中的第一锁存单元202和第二锁存单元204根据时钟信号起到数据寄存的作用。且，动态D触发器200输入端D的数据经过第一锁存单元202和第二锁存单元204的反相，使得输出端Q的数据与输入端D的数据同相。同时，第一锁存单元202和第二锁存单元204还可以起到提高数据驱动能力的作用。It can be seen that the firstdata transmission unit 201 and the seconddata transmission unit 203 are controlled by the inverted clock signal, that is, the firstdata transmission unit 201 and the seconddata transmission unit 203 will not be turned on and/or turned off at the same time, and the dynamic Thefirst latch unit 202 and thesecond latch unit 204 in the D flip-flop 200 play the role of data registration according to the clock signal. In addition, the data at the input terminal D of the dynamic D flip-flop 200 is inverted by thefirst latch unit 202 and thesecond latch unit 204, so that the data at the output terminal Q is in phase with the data at the input terminal D. At the same time, thefirst latch unit 202 and thesecond latch unit 204 can also play a role in improving the data driving capability.

如图3所示，动态D触发器200还包括漏电补偿单元205。与图3所示实施例不同之处在于，在本实施例中，漏电补偿单元205包括PMOS晶体管205P以及NMOS晶体管205N，PMOS晶体管205P以及NMOS晶体管205N串联连接在输出端Q以及第一节点S0之间。PMOS晶体管205P的源极端电性连接至第一节点S0，PMOS晶体管205P的漏极端电性连接至NMOS晶体管205N的漏极端，NMOS晶体管205N的源极端电性连接至输出端Q，PMOS晶体管205P以及NMOS晶体管205N的栅极端并联连接在一起，并电性连接至第二节点S1。As shown in FIG. 3 , the dynamic D flip-flop 200 further includes aleakage compensation unit 205 . The difference from the embodiment shown in FIG. 3 is that, in this embodiment, theleakage compensation unit 205 includes a PMOS transistor 205P and anNMOS transistor 205N, and the PMOS transistor 205P and theNMOS transistor 205N are connected in series between the output end Q and the first node S0. between. The source terminal of the PMOS transistor 205P is electrically connected to the first node S0, the drain terminal of the PMOS transistor 205P is electrically connected to the drain terminal of theNMOS transistor 205N, the source terminal of theNMOS transistor 205N is electrically connected to the output terminal Q, the PMOS transistor 205P and Gate terminals of theNMOS transistors 205N are connected together in parallel and are electrically connected to the second node S1.

由于PMOS晶体管205P以及NMOS晶体管205N的栅极端同样都电性连接至第二节点S1，在相同电平的信号驱动下，PMOS晶体管205P以及NMOS晶体管205N不会同时导通，只能有一个处于导通状态，另一个处于截止状态。例如，当第二节点S1处的电位为高电平时，PMOS晶体管205P处于截止状态，而NMOS晶体管205N处于导通状态；当第二节点S1处的电位为低电平时，PMOS晶体管205P处于导通状态，而NMOS晶体管205N处于截止状态。因此，漏电补偿单元205可以将输出端Q的漏电电流反馈至第一节点S0处的同时，增加第二节点S1处的寄生电容，既可以补偿第一节点S0处的漏电电流，又可以增加第二节点S1处的寄生电容，从而提高第一节点S0及第二节点S1处数据存储的稳定性，增强数据的正确性和安全性。Since the gate terminals of the PMOS transistor 205P and theNMOS transistor 205N are also electrically connected to the second node S1, under the same level of signal driving, the PMOS transistor 205P and theNMOS transistor 205N will not be turned on at the same time, and only one of them can be turned on. On state, the other is off state. For example, when the potential at the second node S1 is at a high level, the PMOS transistor 205P is in an off state, and theNMOS transistor 205N is in an on state; when the potential at the second node S1 is at a low level, the PMOS transistor 205P is in an on state state, while theNMOS transistor 205N is in an off state. Therefore, theleakage compensation unit 205 can increase the parasitic capacitance at the second node S1 while feeding back the leakage current of the output terminal Q to the first node S0, which can not only compensate the leakage current at the first node S0, but also increase the first node S0. Two parasitic capacitances at the nodes S1, thereby improving the stability of data storage at the first node S0 and the second node S1, and enhancing the correctness and security of the data.

本发明还提供一种数据运算单元，图4为本发明数据运算单元的结构示意图。如图4所示，数据运算单元400包括控制电路401、运算电路402以及多个动态寄存200。控制电路401对动态寄存200中的数据进行刷新并从动态寄存200中读取数据，运算电路402对读取的数据进行运算，再由控制电路401将运算结果输出。The present invention also provides a data operation unit, and FIG. 4 is a schematic structural diagram of the data operation unit of the present invention. As shown in FIG. 4 , thedata operation unit 400 includes a control circuit 401 , an operation circuit 402 and a plurality ofdynamic registers 200 . The control circuit 401 refreshes the data in thedynamic register 200 and reads the data from thedynamic register 200, the operation circuit 402 performs operation on the read data, and the control circuit 401 outputs the operation result.

本发明还提供一种芯片，图5为本发明芯片的结构示意图。如图5所示，芯片500包括控制单元501，以及一个或多个数据运算单元400。控制单元501向数据运算单元400输入数据并将数据运算单元400输出的数据进行处理。The present invention also provides a chip, and FIG. 5 is a schematic structural diagram of the chip of the present invention. As shown in FIG. 5 , thechip 500 includes acontrol unit 501 and one or moredata operation units 400 . Thecontrol unit 501 inputs data to thedata operation unit 400 and processes the data output from thedata operation unit 400 .

本发明还提供一种算力板，图6为本发明算力板的结构示意图。如图6所示，每一个算力板600上包括一个或多个芯片500，对计算设备下发的工作数据进行大规模运算。The present invention also provides a computing power board, and FIG. 6 is a schematic structural diagram of the computing power board of the present invention. As shown in FIG. 6 , eachcomputing power board 600 includes one ormore chips 500 to perform large-scale operations on the work data sent by the computing device.

本发明还提供一种计算设备，所述计算设备优选用于挖掘虚拟数字货币的运算，当然所述计算设备也可以用于其他任何海量运算。图7为本发明计算设备的结构示意图。如图7所示，每一个计算设备700包括连接板701、控制板702、散热器703、电源板704，以及一个或多个算力板600。控制板702通过连接板701与算力板600连接，散热器703设置在算力板600的周围。电源板704用于向所述连接板701、控制板702、散热器703以及算力板600提供电源。The present invention also provides a computing device. The computing device is preferably used for mining virtual digital currency. Of course, the computing device can also be used for any other massive computing. FIG. 7 is a schematic structural diagram of a computing device of the present invention. As shown in FIG. 7 , eachcomputing device 700 includes aconnection board 701 , acontrol board 702 , aheat sink 703 , apower board 704 , and one or morecomputing power boards 600 . Thecontrol board 702 is connected to thecomputing power board 600 through the connectingboard 701 , and theradiator 703 is arranged around thecomputing power board 600 . Thepower board 704 is used to provide power to theconnection board 701 , thecontrol board 702 , theheat sink 703 and thecomputing power board 600 .

需要说明的是，在本发明的描述中，术语“横向”、“纵向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，并不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。It should be noted that in the description of the present invention, the terms "horizontal", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", The orientation or positional relationship indicated by "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, and It is not indicated or implied that the indicated device or element must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention.

换言之，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。In other words, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should belong to the protection scope of the appended claims of the present invention.

Claims (12)

Translated fromChinese

1.一种动态D触发器，其特征在于，包括：1. a dynamic D flip-flop, is characterized in that, comprises:一输入端，用于输入一数据；an input terminal for inputting a data;一输出端，用于输出所述数据；an output terminal for outputting the data;一时钟信号端，用于提供时钟信号；a clock signal terminal for providing a clock signal;一第一数据传输单元，在所述时钟信号控制下传输所述数据；a first data transmission unit, which transmits the data under the control of the clock signal;一第一锁存单元，用于锁存所述第一数据传输单元传输的数据；a first latching unit for latching the data transmitted by the first data transmission unit;一第二数据传输单元，在所述时钟信号控制下传输所述第一锁存单元锁存的数据；a second data transmission unit, which transmits the data latched by the first latch unit under the control of the clock signal;一第二锁存单元，用于锁存所述第二数据传输单元传输的数据；a second latching unit for latching the data transmitted by the second data transmission unit;所述第一数据传输单元、所述第一锁存单元、所述第二数据传输单元、所述第二锁存单元依次串接在所述输入端和所述输出端之间，所述第一数据传输单元、所述第一锁存单元之间具有一第一节点，所述第二数据传输单元、所述第二锁存单元之间具有一第二节点；The first data transmission unit, the first latch unit, the second data transmission unit, and the second latch unit are serially connected between the input end and the output end in sequence, and the first data transmission unit and the output end are connected in series. A first node is arranged between a data transmission unit and the first latch unit, and a second node is arranged between the second data transmission unit and the second latch unit;其中，还包括一漏电补偿单元，所述漏电补偿单元电性连接在所述第一节点、所述第二节点以及所述输出端之间。Wherein, a leakage compensation unit is further included, and the leakage compensation unit is electrically connected between the first node, the second node and the output end.2.如权利要求1所述的动态D触发器，其特征在于：所述漏电补偿单元具有一第一端、一第二端以及一控制端，所述第一端电性连接至所述输出端，所述第二端电性连接至所述第一节点，所述控制端电性连接至所述第二节点。2 . The dynamic D flip-flop of claim 1 , wherein the leakage compensation unit has a first terminal, a second terminal and a control terminal, and the first terminal is electrically connected to the output. 3 . terminal, the second terminal is electrically connected to the first node, and the control terminal is electrically connected to the second node.3.如权利要求2所述的动态D触发器，其特征在于：所述漏电补偿单元包括一PMOS晶体管及一NMOS晶体管，所述PMOS晶体管及所述NMOS晶体管串联连接在所述输出端与所述第一节点之间。3. The dynamic D flip-flop of claim 2, wherein the leakage compensation unit comprises a PMOS transistor and an NMOS transistor, the PMOS transistor and the NMOS transistor are connected in series at the output end and the between the first nodes.4.如权利要求3所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述NMOS晶体管的所述漏极端，所述NMOS晶体管的所述源极端电性连接至所述第一节点，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述第二节点。4. The dynamic D flip-flop of claim 3, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, and the NMOS transistor has a source terminal, a drain terminal and a gate terminal terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected To the first node, the PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and is electrically connected to the second node.5.如权利要求3所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述PMOS晶体管的所述漏极端，所述PMOS晶体管的所述源极端电性连接至所述第一节点，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述第二节点。5. The dynamic D flip-flop of claim 3, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, and the NMOS transistor has a source terminal, a drain terminal and a gate terminal terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected To the first node, the PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and is electrically connected to the second node.6.如权利要求1所述的动态D触发器，其特征在于：所述时钟信号包括一第一时钟信号及一第二时钟信号，所述第一时钟信号与所述第二时钟信号反相。6. The dynamic D flip-flop of claim 1, wherein the clock signal comprises a first clock signal and a second clock signal, and the first clock signal and the second clock signal are inverted .7.如权利要求1所述的动态D触发器，其特征在于：所述第一数据传输单元和/或所述第二数据传输单元为传输门。7. The dynamic D flip-flop according to claim 1, wherein the first data transmission unit and/or the second data transmission unit are transmission gates.8.如权利要求1所述的动态D触发器，其特征在于：所述第一锁存单元和/或第二锁存单元为反相器。8. The dynamic D flip-flop of claim 1, wherein the first latch unit and/or the second latch unit are inverters.9.一种数据运算单元，包括互联连接的控制电路、运算电路、多个动态D触发器，所述多个动态D触发器为串联和/或并联连接；其特征在于：所述多个动态D触发器为权利要求1-8中任意一种所述的动态D触发器。9. A data operation unit, comprising a control circuit, an operation circuit, and a plurality of dynamic D flip-flops connected to each other, wherein the plurality of dynamic D flip-flops are connected in series and/or in parallel; it is characterized in that: the plurality of dynamic D flip-flops are connected in parallel. The D flip-flop is the dynamic D flip-flop described in any one of claims 1-8.10.一种芯片，其特征在于，包括至少一个如权利要求9所述的数据运算单元。10. A chip, characterized by comprising at least one data operation unit as claimed in claim 9.11.一种用于计算设备的算力板，其特征在于，包括至少一个如权利要求10所述的芯片。11. A computing power board for computing equipment, comprising at least one chip as claimed in claim 10.12.一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其特征在于：所述算力板为如权利要求11所述的算力板。12. A computing device, comprising a power supply board, a control board, a connecting board, a radiator, and a plurality of computing power boards, the control board is connected to the computing power board through the connecting board, and the radiator is provided at the Around the computing power board, the power board is used to provide power to the connection board, the control board, the radiator and the computing power board, and it is characterized in that: the computing power board is as claimed in the claim The hash board described in 11.

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