CN110600362B - Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device - Google Patents
Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor deviceDownload PDFInfo
- Publication number
- CN110600362B CN110600362BCN201910708203.9ACN201910708203ACN110600362BCN 110600362 BCN110600362 BCN 110600362BCN 201910708203 ACN201910708203 ACN 201910708203ACN 110600362 BCN110600362 BCN 110600362B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon
- ingap
- nanometers
- algaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本申请涉及微电子技术领域，具体涉及一种硅基异构集成材料及其制备方法、半导体器件。The present application relates to the technical field of microelectronics, in particular to a silicon-based heterogeneous integrated material, a preparation method thereof, and a semiconductor device.
背景技术Background technique
基于硅基互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)技术的现代集成电路，随着CMOS器件特征尺寸的不断缩小，在集成度、功耗和器件特性方面不断进步。Modern integrated circuits based on silicon-based complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) technology continue to improve in terms of integration, power consumption and device characteristics as the feature size of CMOS devices continues to shrink.
而另一方面，化合物半导体器件与集成电路在超高速电路、微波电路、太赫兹电路、光电集成电路等领域也获得了长足发展。On the other hand, compound semiconductor devices and integrated circuits have also made great progress in the fields of ultra-high-speed circuits, microwave circuits, terahertz circuits, and optoelectronic integrated circuits.
由于硅基CMOS芯片与化合物半导体芯片很难在同一晶圆厂生产，无法实现工艺兼容，但是如果将两者有机结合，进而突破集成电路设计领域存在的器件选型有限及各种不同材料器件不能混合集成的难题，可实现集成电路设计、性能的大幅度提升。Since it is difficult to produce silicon-based CMOS chips and compound semiconductor chips in the same fab, it is impossible to achieve process compatibility. However, if the two are organically combined, it will break through the limited selection of devices in the field of integrated circuit design and the inability of devices of various materials. The problem of hybrid integration can greatly improve the design and performance of integrated circuits.
发明内容SUMMARY OF THE INVENTION
本申请的目的是提供一种硅基异构集成材料及其制备方法、半导体器件，用以实现集成电路设计、性能的提升。The purpose of the present application is to provide a silicon-based heterogeneous integrated material, a preparation method thereof, and a semiconductor device, so as to realize the improvement of integrated circuit design and performance.
本申请第一方面提供一种硅基异构集成材料制备方法，包括：A first aspect of the present application provides a method for preparing a silicon-based heterogeneous integrated material, comprising:
提供硅基半导体衬底；Provide silicon-based semiconductor substrates;
在所述硅基半导体衬底上形成二氧化硅SiO2介质层；forming a silicon dioxideSiO2 dielectric layer on the silicon-based semiconductor substrate;
在所述SiO2介质层上形成砷化铝镓AlGaAs保护层；forming an aluminum gallium arsenide AlGaAs protective layer on the SiO2 dielectric layer;
在所述AlGaAs保护层上形成磷化铟镓InGaP缓冲层；forming an indium gallium phosphide InGaP buffer layer on the AlGaAs protective layer;
在所述InGaP缓冲层上形成砷化铟镓InGaAs沟道层；forming an indium gallium arsenide InGaAs channel layer on the InGaP buffer layer;
在所述InGaAs沟道层上形成磷化铟镓InGaP势垒层；forming an indium gallium phosphide InGaP barrier layer on the InGaAs channel layer;
在所述InGaP势垒层上形成砷化镓GaAs帽层。A gallium arsenide GaAs cap layer is formed on the InGaP barrier layer.
在一种可能的实现方式中，在本申请提供的上述方法中，所述SiO2介质层的厚度为200纳米。In a possible implementation manner, in the above method provided in this application, the thickness of the SiO2 dielectric layer is 200 nanometers.
在一种可能的实现方式中，在本申请提供的上述方法中，所述AlGaAs保护层的厚度范围为100纳米到300纳米，AlGaAs材料中Al组分范围为0.1到0.3。In a possible implementation manner, in the above method provided in this application, the thickness of the AlGaAs protective layer ranges from 100 nanometers to 300 nanometers, and the Al composition in the AlGaAs material ranges from 0.1 to 0.3.
在一种可能的实现方式中，在本申请提供的上述方法中，所述InGaP缓冲层的厚度范围为200纳米到400纳米，InGaP材料中In的组分为0.49。In a possible implementation manner, in the above method provided in the present application, the thickness of the InGaP buffer layer ranges from 200 nanometers to 400 nanometers, and the composition of In in the InGaP material is 0.49.
在一种可能的实现方式中，在本申请提供的上述方法中，所述InGaAs沟道层的厚度范围为10纳米到100纳米，InGaAs材料中In的组分范围为0到0.4。In a possible implementation manner, in the above method provided in the present application, the thickness of the InGaAs channel layer is in the range of 10 nanometers to 100 nanometers, and the composition of In in the InGaAs material is in the range of 0 to 0.4.
在一种可能的实现方式中，在本申请提供的上述方法中，所述InGaP势垒层的厚度范围为30纳米到100纳米，InGaP材料中In的组分为0.49。In a possible implementation manner, in the above method provided in the present application, the thickness of the InGaP barrier layer ranges from 30 nanometers to 100 nanometers, and the composition of In in the InGaP material is 0.49.
在一种可能的实现方式中，在本申请提供的上述方法中，所述GaAs帽层的厚度范围为100纳米到200纳米，其掺杂类型为N型，掺杂浓度大于5×1018cm-3。In a possible implementation manner, in the above method provided in this application, the thickness of the GaAs cap layer ranges from 100 nanometers to 200 nanometers, its doping type is N-type, and the doping concentration is greater than 5×1018 cm-3 .
本申请第二方面提供一种硅基异构集成材料，所述硅基异构集成材料采用上述第一方面所述的方法制作而成，所述硅基异构集成材料包括：A second aspect of the present application provides a silicon-based heterogeneous integrated material, the silicon-based heterogeneous integrated material is fabricated by using the method described in the first aspect, and the silicon-based heterogeneous integrated material includes:
硅基半导体衬底；Silicon-based semiconductor substrate;
在所述硅基半导体衬底上形成的二氧化硅SiO2介质层；a silicon dioxideSiO2 dielectric layer formed on the silicon-based semiconductor substrate;
在所述SiO2介质层上形成的砷化铝镓AlGaAs保护层；an aluminum gallium arsenide AlGaAs protective layer formed on the SiO2 dielectric layer;
在所述AlGaAs保护层上形成的磷化铟镓InGaP缓冲层；an indium gallium phosphide InGaP buffer layer formed on the AlGaAs protective layer;
在所述InGaP缓冲层上形成的砷化铟镓InGaAs沟道层；an indium gallium arsenide InGaAs channel layer formed on the InGaP buffer layer;
在所述InGaAs沟道层上形成的磷化铟镓InGaP势垒层；an indium gallium phosphide InGaP barrier layer formed on the InGaAs channel layer;
在所述InGaP势垒层上形成的砷化镓GaAs帽层。A gallium arsenide GaAs cap layer is formed on the InGaP barrier layer.
本申请第三方面提供一种半导体器件，所述半导体器件的材料为上述第二方面所述的硅基异构集成材料。A third aspect of the present application provides a semiconductor device, where the material of the semiconductor device is the silicon-based heterogeneous integrated material described in the second aspect.
相较于现有技术，本申请提供的硅基异构集成材料及其制备方法、半导体器件，通过在硅半导体衬底上形成二氧化硅SiO2介质层；在所述SiO2介质层上形成砷化铝镓AlGaAs保护层，再在所述AlGaAs保护层上形成磷化铟镓InGaP缓冲层，再在所述InGaP缓冲层上形成砷化铟镓InGaAs沟道层，再在所述InGaAs沟道层上形成磷化铟镓InGaP势垒层，再在所述InGaP势垒层上形成砷化镓GaAs帽层，本申请采用SiO2作为介质层，并采用了AlGaAs材料作为整个材料的中间绝缘材料和保护材料，整体提高了器件衬底防止漏电的能力，对于提高所做的器件和集成电路的噪声特性非常有益处，可以实现异构集成电路设计和性能的提升。Compared with the prior art, the silicon-based heterogeneous integrated material, the preparation method thereof, and the semiconductor device provided by the present application are formed by forming a silicon dioxideSiO2 dielectric layer on a silicon semiconductor substrate; forming an AlGaAs AlGaAs protective layer, forming an InGaP InGaP buffer layer on the AlGaAs protective layer, forming an InGaAs InGaAs channel layer on the InGaP buffer layer, and forming an InGaAs channel layer on the InGaAs channel An indium gallium phosphide InGaP barrier layer is formed on the layer, and then a gallium arsenide GaAs cap layer is formed on the InGaP barrier layer. In this application, SiO2 is used as the dielectric layer, and AlGaAs material is used as the intermediate insulating material of the whole material. and protective materials, which improve the ability of the device substrate to prevent leakage as a whole, which is very beneficial for improving the noise characteristics of the fabricated devices and integrated circuits, and can realize the improvement of the design and performance of heterogeneous integrated circuits.
附图说明Description of drawings
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本申请的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for purposes of illustrating preferred embodiments only and are not to be considered limiting of the application. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:
图1示出了本申请的一些实施方式所提供的一种硅基异构集成材料制备方法的流程图；FIG. 1 shows a flow chart of a method for preparing a silicon-based heterogeneous integrated material provided by some embodiments of the present application;
图2示出了本申请的一些实施方式所提供的一种硅基异构集成材料的结构图。FIG. 2 shows a structural diagram of a silicon-based heterogeneous integrated material provided by some embodiments of the present application.
具体实施方式Detailed ways
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.
需要注意的是，除非另有说明，本申请使用的技术术语或者科学术语应当为本申请所属领域技术人员所理解的通常意义。It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art to which this application belongs.
另外，术语“第一”和“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。In addition, the terms "first" and "second" and the like are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.
本申请实施例提供一种硅基异构集成材料制备方法、一种硅基异构集成材料、一种半导体器件，下面结合附图进行说明。Embodiments of the present application provide a method for preparing a silicon-based heterogeneous integrated material, a silicon-based heterogeneous integrated material, and a semiconductor device, which are described below with reference to the accompanying drawings.
请参考图1和图2，图1示出了本申请的一些实施方式所提供的一种硅基异构集成材料制备方法的流程图，图2示出了本申请的一些实施方式所提供的一种硅基异构集成材料的结构图，图2中的硅基异构集成材料通过图1中硅基异构集成材料制备方法制备，如图所示，所述方法，可以包括以下步骤：Please refer to FIG. 1 and FIG. 2 , FIG. 1 shows a flow chart of a method for preparing a silicon-based heterogeneous integrated material provided by some embodiments of the present application, and FIG. 2 shows some embodiments of the present application. A structural diagram of a silicon-based heterogeneous integrated material. The silicon-based heterogeneous integrated material in FIG. 2 is prepared by the preparation method of the silicon-based heterogeneous integrated material in FIG. 1. As shown in the figure, the method may include the following steps:
步骤S101：提供硅基半导体衬底101；Step S101: providing a silicon-based
步骤S102：在所述硅基半导体衬底101上形成二氧化硅SiO2介质层102；Step S102 : forming a silicon dioxide SiO2
步骤S103：在所述SiO2介质层102上形成砷化铝镓AlGaAs保护层103；Step S103 : forming an AlGaAs AlGaAs
步骤S104：在所述AlGaAs保护层103上形成磷化铟镓InGaP缓冲层104；Step S104 : forming an indium gallium phosphide
步骤S105：在所述InGaP缓冲层104上形成砷化铟镓InGaAs沟道层105；Step S105 : forming an InGaAs InGaAs
步骤S106：在所述InGaAs沟道层105上形成磷化铟镓InGaP势垒层106；Step S106 : forming an indium gallium phosphide
步骤S107：在所述InGaP势垒层106上形成砷化镓GaAs帽层107。Step S107 : forming a GaAs
具体的，在硅基半导体上实现砷化镓(GaAs)材料的外延，是实现硅基半导体器件和磷化铟基(InP)半导体器件集成的重要途径，良好的硅基化合物半导体结构必然可以提升异构集成电路的性能。通过在硅基半导体上形成SiO2介质上的GaAs基材料结构，充分利用了GaAs材料可实现较大尺寸生长和工业化生产的优点，GaAs材料也是目前最为成熟的化合物半导体材料。另一方面采用SiO2作为介质层，并采用了AlGaAs材料作为整个材料的中间绝缘材料和保护材料，实现了高性能硅基化合物半导体材料特性，最终可以实现异构集成电路设计和性能的提升。Specifically, the epitaxy of gallium arsenide (GaAs) materials on silicon-based semiconductors is an important way to realize the integration of silicon-based semiconductor devices and indium phosphide-based (InP) semiconductor devices. A good silicon-based compound semiconductor structure can certainly improve the Performance of Heterogeneous Integrated Circuits. By forming a GaAs-based material structure on a SiO2 medium on a silicon-based semiconductor, the advantages of the GaAs material for large-scale growth and industrial production are fully utilized, and the GaAs material is also the most mature compound semiconductor material at present. On the other hand, SiO2 is used as the dielectric layer, and AlGaAs material is used as the intermediate insulating material and protective material of the whole material, which realizes the characteristics of high-performance silicon-based compound semiconductor materials, and finally realizes the improvement of the design and performance of heterogeneous integrated circuits.
为了保证最佳成膜质量，本申请还提供了硅基异构集成材料中各膜层的成膜厚度和组分。In order to ensure the best film-forming quality, the present application also provides the film-forming thickness and composition of each film layer in the silicon-based heterogeneous integrated material.
在一些实施方式中，基于上述实施例，所述SiO2介质层的厚度可以为200纳米。In some embodiments, based on the above embodiments, the thickness of the SiO2 dielectric layer may be 200 nanometers.
在一些实施方式中，基于上述实施例，所述AlGaAs保护层的厚度范围为100纳米到300纳米，AlGaAs材料中Al组分范围为0.1到0.3。In some embodiments, based on the above embodiments, the thickness of the AlGaAs protective layer ranges from 100 nanometers to 300 nanometers, and the Al composition in the AlGaAs material ranges from 0.1 to 0.3.
在一些实施方式中，基于上述实施例，所述InGaP缓冲层的厚度范围为200纳米到400纳米，InGaP材料中In的组分为0.49。In some embodiments, based on the above embodiments, the thickness of the InGaP buffer layer ranges from 200 nanometers to 400 nanometers, and the composition of In in the InGaP material is 0.49.
在一些实施方式中，基于上述实施例，所述InGaAs沟道层的厚度范围为10纳米到100纳米，InGaAs材料中In的组分范围为0到0.4。In some embodiments, based on the above embodiments, the thickness of the InGaAs channel layer ranges from 10 nanometers to 100 nanometers, and the composition of In in the InGaAs material ranges from 0 to 0.4.
在一些实施方式中，基于上述实施例，所述InGaP势垒层的厚度范围为30纳米到100纳米，InGaP材料中In的组分为0.49。In some embodiments, based on the above embodiments, the thickness of the InGaP barrier layer ranges from 30 nanometers to 100 nanometers, and the composition of In in the InGaP material is 0.49.
在一些实施方式中，基于上述实施例，所述GaAs帽层的厚度范围为100纳米到200纳米，其掺杂类型为N型，掺杂浓度大于5×1018cm-3。In some embodiments, based on the above embodiments, the thickness of the GaAs cap layer ranges from 100 nanometers to 200 nanometers, the doping type is N-type, and the doping concentration is greater than 5×1018 cm−3 .
本申请提供的硅基异构集成材料制备方法，通过在硅半导体衬底上形成二氧化硅SiO2介质层；在所述SiO2介质层上形成砷化铝镓AlGaAs保护层，再在所述AlGaAs保护层上形成磷化铟镓InGaP缓冲层，再在所述InGaP缓冲层上形成砷化铟镓InGaAs沟道层，再在所述InGaAs沟道层上形成磷化铟镓InGaP势垒层，再在所述InGaP势垒层上形成砷化镓GaAs帽层，本申请采用SiO2作为介质层，并采用了AlGaAs材料作为整个材料的中间绝缘材料和保护材料，整体提高了器件衬底防止漏电的能力，对于提高所做的器件和集成电路的噪声特性非常有益处，可以实现异构集成电路设计和性能的提升。The method for preparing a silicon-based heterogeneous integrated material provided by the present application includes forming a silicon dioxideSiO2 dielectric layer on a silicon semiconductor substrate; forming an aluminum gallium arsenide AlGaAs protective layer on theSiO2 dielectric layer; An indium gallium phosphide InGaP buffer layer is formed on the AlGaAs protective layer, an indium gallium arsenide InGaAs channel layer is formed on the InGaP buffer layer, and an indium gallium phosphide InGaP barrier layer is formed on the InGaAs channel layer, Then, a gallium arsenide GaAs cap layer is formed on the InGaP barrier layer. In this application, SiO2 is used as the dielectric layer, and AlGaAs material is used as the intermediate insulating material and protective material of the whole material, which improves the overall protection of the device substrate against leakage. It is very beneficial to improve the noise characteristics of the devices and integrated circuits made, and can realize the improvement of the design and performance of heterogeneous integrated circuits.
基于同一发明构思，本申请实施例还提供了一种硅基异构集成材料，由于该硅基异构集成材料解决问题的原理与前述一种制作方法相似，因此该硅基异构集成材料的实施可以参见制作方法的实施，重复之处不再赘述。Based on the same inventive concept, the embodiment of the present application also provides a silicon-based heterogeneous integrated material. Since the principle of solving the problem of the silicon-based heterogeneous integrated material is similar to that of the aforementioned manufacturing method, the silicon-based heterogeneous integrated material has a For the implementation, please refer to the implementation of the manufacturing method, and the repetition will not be repeated.
具体的，请参考图2，本申请的一些实施方式所提供的一种硅基异构集成材料包括：Specifically, please refer to FIG. 2, a silicon-based heterogeneous integrated material provided by some embodiments of the present application includes:
硅基半导体衬底101；silicon-based
在所述硅基半导体101衬底上形成的二氧化硅SiO2介质层102；A silicon dioxideSiO2 dielectric layer 102 formed on the silicon-based
在所述SiO2介质层102上形成的砷化铝镓AlGaAs保护层103；an aluminum gallium arsenide AlGaAs
在所述AlGaAs保护层103上形成的磷化铟镓InGaP缓冲层104；an indium gallium phosphide
在所述InGaP缓冲层104上形成的砷化铟镓InGaAs沟道层105；an indium gallium arsenide
在所述InGaAs沟道层105上形成的磷化铟镓InGaP势垒层106；an indium gallium phosphide
在所述InGaP势垒层106上形成的砷化镓GaAs帽层107。A GaAs
可选的，所述SiO2介质层的厚度为200纳米。Optionally, the thickness of the SiO2 dielectric layer is 200 nanometers.
可选的，所述AlGaAs保护层的厚度范围为100纳米到300纳米，AlGaAs材料中Al组分范围为0.1到0.3。Optionally, the thickness of the AlGaAs protective layer ranges from 100 nanometers to 300 nanometers, and the Al composition in the AlGaAs material ranges from 0.1 to 0.3.
可选的，所述InGaP缓冲层的厚度范围为200纳米到400纳米，InGaP材料中In的组分为0.49。Optionally, the thickness of the InGaP buffer layer ranges from 200 nanometers to 400 nanometers, and the composition of In in the InGaP material is 0.49.
可选的，所述InGaAs沟道层的厚度范围为10纳米到100纳米，InGaAs材料中In的组分范围为0到0.4。Optionally, the thickness of the InGaAs channel layer ranges from 10 nanometers to 100 nanometers, and the composition of In in the InGaAs material ranges from 0 to 0.4.
可选的，所述InGaP势垒层的厚度范围为30纳米到100纳米，InGaP材料中In的组分为0.49。Optionally, the thickness of the InGaP barrier layer ranges from 30 nanometers to 100 nanometers, and the composition of In in the InGaP material is 0.49.
可选的，所述GaAs帽层的厚度范围为100纳米到200纳米，其掺杂类型为N型，掺杂浓度大于5×1018cm-3。Optionally, the thickness of the GaAs cap layer ranges from 100 nanometers to 200 nanometers, the doping type is N-type, and the doping concentration is greater than 5×1018 cm−3 .
基于同一发明构思，本申请实施例还提供了一种半导体器件，该半导体器件的材料为上述实施例提供的硅基异构集成材料。该半导体器件的实施可以参见上述硅基异构集成材料的实施例，重复之处不再赘述。Based on the same inventive concept, an embodiment of the present application further provides a semiconductor device, and the material of the semiconductor device is the silicon-based heterogeneous integrated material provided in the above-mentioned embodiments. For the implementation of the semiconductor device, reference may be made to the above-mentioned embodiment of the silicon-based heterogeneous integrated material, and repeated details will not be repeated.
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围，其均应涵盖在本申请的权利要求和说明书的范围当中。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application. scope, which shall be included in the scope of the claims and description of the present application.
Claims (3)
Translated fromChinesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910708203.9ACN110600362B (en) | 2019-08-01 | 2019-08-01 | Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910708203.9ACN110600362B (en) | 2019-08-01 | 2019-08-01 | Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110600362A CN110600362A (en) | 2019-12-20 |
| CN110600362Btrue CN110600362B (en) | 2022-05-20 |
Family
ID=68853283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910708203.9AExpired - Fee RelatedCN110600362B (en) | 2019-08-01 | 2019-08-01 | Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110600362B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416591A (en)* | 2000-02-10 | 2003-05-07 | 摩托罗拉公司 | Semiconductor structure |
| WO2004059744A1 (en)* | 2002-12-25 | 2004-07-15 | Sumitomo Chemical Company, Limited | Compound semiconductor epitaxial substrate and method for manufacturing same |
| CN102569364A (en)* | 2010-12-08 | 2012-07-11 | 中国科学院微电子研究所 | High-mobility substrate structure and preparation method thereof |
| CN205159336U (en)* | 2015-12-16 | 2016-04-13 | 成都嘉石科技有限公司 | Silica -based heterogeneous integrated MHEMT structure |
| CN205670542U (en)* | 2016-06-17 | 2016-11-02 | 成都海威华芯科技有限公司 | A kind of silica-based heterogeneous integrated P-channel HFET device |
| US20160327737A1 (en)* | 2014-01-14 | 2016-11-10 | Massachusetts Institute Of Technology | Method of forming an integrated circuit and related integrated circuit |
- 2019
- 2019-08-01CNCN201910708203.9Apatent/CN110600362B/ennot_activeExpired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416591A (en)* | 2000-02-10 | 2003-05-07 | 摩托罗拉公司 | Semiconductor structure |
| WO2004059744A1 (en)* | 2002-12-25 | 2004-07-15 | Sumitomo Chemical Company, Limited | Compound semiconductor epitaxial substrate and method for manufacturing same |
| CN102569364A (en)* | 2010-12-08 | 2012-07-11 | 中国科学院微电子研究所 | High-mobility substrate structure and preparation method thereof |
| US20160327737A1 (en)* | 2014-01-14 | 2016-11-10 | Massachusetts Institute Of Technology | Method of forming an integrated circuit and related integrated circuit |
| CN205159336U (en)* | 2015-12-16 | 2016-04-13 | 成都嘉石科技有限公司 | Silica -based heterogeneous integrated MHEMT structure |
| CN205670542U (en)* | 2016-06-17 | 2016-11-02 | 成都海威华芯科技有限公司 | A kind of silica-based heterogeneous integrated P-channel HFET device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110600362A (en) | 2019-12-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109860022B (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN103390591B (en) | The CMOS preparation method of silica-based high mobility III-V/Ge raceway groove | |
| US20130264609A1 (en) | Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof | |
| Yan et al. | High performance amplifier element realization via MoS2/GaTe heterostructures | |
| CN105340074B (en) | SOI substrate preparation method and SOI substrate | |
| CN102263015B (en) | Method for preparing silica-based gallium arsenide material structure applied to n-channel metal oxide semiconductor (nMOS) | |
| CN102790084A (en) | Germanium and III-V mixed coplanar silicon on insulator (SOI) semi-conductor structure and preparation method thereof | |
| CN113224214B (en) | Red light emitting diode epitaxial wafer and preparation method thereof | |
| CN107039587A (en) | Negative differential resistance and preparation method based on black phosphorus/rhenium disulfide hetero-junctions | |
| CN107195534A (en) | Ge compound substrates, substrate epitaxial structure and preparation method thereof | |
| CN103107096A (en) | Method for producing silicon-based III-V group nMOS device | |
| CN103117222B (en) | The method of growth GaAs material HEMT device in ART structured channel | |
| CN110600362B (en) | Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device | |
| CN111755529B (en) | A bidirectional symmetrical TVS diode and a manufacturing method thereof | |
| CN102534768B (en) | Method for preparing silicon-based gallium arsenide material | |
| CN105047719B (en) | Staggered hetero-junctions tunneling field-effect transistor based on InAsN GaAsSb materials | |
| CN103065973B (en) | Si base is prepared the method for InP-base n-MOS device | |
| CN105448978A (en) | Epitaxial layer structure for silicon base integrated mHEMT devices and growing method of epitaxial layer structure | |
| CN103177971A (en) | NMOS (N-channel metal oxide semiconductor) device, with GaAs material growing in silicon grooves, based on ART (aspect radio trapping ) structure | |
| CN107123668B (en) | InAs/AlSb HEMT epitaxial structure and preparation method thereof | |
| CN108878368A (en) | The epitaxial structure and preparation method of the compound integrated HBT and CMOS of SOI base | |
| CN115831968A (en) | Hydrogen terminal diamond/gallium oxide heterogeneous integrated complementary device and preparation method thereof | |
| CN102543693A (en) | Method for preparing germanium-based pseudo gallium arsenide (GaAs) substrate | |
| CN103077892B (en) | The method of integrated HEMT device on silicon | |
| CN104576727A (en) | GaAs and PHEMT-PIN compound epitaxial material structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee | Granted publication date:20220520 |