技术领域technical field
本申请涉及显示技术领域，尤其涉及一种显示面板、显示装置和驱动方法。The present application relates to the field of display technology, and in particular to a display panel, a display device and a driving method.
背景技术Background technique
随着显示技术的发展，显示装置的应用场景也越来越多，例如，在VR(VirtualReality，虚拟现实)或者AR(Augmented Reality，增强现实)显示装置中，有些区域需要较高刷新率来防止闪烁等现象，有些区域需要较低刷新率来降低功耗，然而，目前的显示面板在实现上述分区域的刷新率控制时，需要较为复杂的结构设计。With the development of display technology, there are more and more application scenarios for display devices. For example, in VR (Virtual Reality, virtual reality) or AR (Augmented Reality, augmented reality) display devices, some areas require a higher refresh rate to prevent Flickering and other phenomena, some areas require a lower refresh rate to reduce power consumption, however, the current display panel needs a more complicated structural design when realizing the refresh rate control of the above sub-regions.
发明内容Contents of the invention
本申请实施例提供一种显示面板、显示装置和驱动方法，可以通过较为简单的结构实现分区域的刷新率控制。Embodiments of the present application provide a display panel, a display device, and a driving method, which can implement region-by-region refresh rate control through a relatively simple structure.
一方面，本申请实施例提供一种显示面板，包括：On the one hand, an embodiment of the present application provides a display panel, including:
多行子像素；Multiple rows of sub-pixels;
与每行所述子像素对应电连接的扫描线；Scanning lines electrically connected to the sub-pixels in each row;
与每条所述扫描线对应的选通单元，所述选通单元包括第一输入端、输出端和控制端，所述选通单元的输出端电连接于对应的所述扫描线，所述选通单元用于在其控制端的信号控制下，使所述第一输入端和所述输出端之间导通或截止。a gating unit corresponding to each of the scanning lines, the gating unit includes a first input terminal, an output terminal and a control terminal, the output terminal of the gating unit is electrically connected to the corresponding scanning line, the The gating unit is used to switch on or off between the first input terminal and the output terminal under the control of the signal at the control terminal.
另一方面，本申请实施例还提供一种显示装置，包括：On the other hand, the embodiment of the present application also provides a display device, including:
驱动芯片和上述的显示面板，所述驱动芯片电连接于每个所述选通单元的控制端。The driving chip and the above display panel, the driving chip is electrically connected to the control terminal of each gate unit.
另一方面，本申请实施例还提供一种驱动方法，用于上述的显示面板，所述驱动方法包括：On the other hand, the embodiment of the present application also provides a driving method for the above-mentioned display panel, the driving method comprising:
在所述单位时间内，控制部分所述选通单元使第一输入端和输出端之间导通于第一时长，控制另外一部分所述选通单元使第一输入端和输出端之间导通于第二时长，所述第一时长不等于所述第二时长。In the unit time, the control part of the gating unit makes the conduction between the first input end and the output end last for a first duration, and controls the other part of the gating unit to make the conduction between the first input end and the output end Due to the second duration, the first duration is not equal to the second duration.
本申请实施例中的显示面板、显示装置和驱动方法，设置与每条扫描线对应的选通单元，通过较为简单的结构改进即可可以单独控制每条扫描线与对应的第一输入端之间导通还是截止，第一输入端用于提供电平，当扫描线与对应的第一输入端之间导通时，第一输入端处的电平才会传输至对应的扫描线上，以此来实现为扫描线提供扫描信号，因此，可以分区域通过控制不同区域对应的选通单元的导通时长，使不同区域具有不同的画面刷新率，例如，使部分区域具有较高刷新率来防止闪烁等现象，提高显示效果，使另一部分区域具有较低刷新率，以降低功耗。另外，由于每个选通单元均可以实现单独的控制，因此可以根据需要动态选择不同的区域以实现画面刷新率的调节，并且，可以任意改变选通单元的导通时长，从而实现画面刷新率的动态调节。In the display panel, display device, and driving method in the embodiments of the present application, a gate unit corresponding to each scanning line is provided, and the connection between each scanning line and the corresponding first input terminal can be individually controlled through a relatively simple structural improvement. Whether it is turned on or off, the first input terminal is used to provide the level. When the scan line is turned on with the corresponding first input terminal, the level at the first input terminal will be transmitted to the corresponding scan line. In this way, the scan signal is provided for the scan line. Therefore, by controlling the conduction duration of the gate units corresponding to different areas, different areas have different picture refresh rates, for example, some areas have higher refresh rates. To prevent flickering and other phenomena, improve the display effect, and make another part of the area have a lower refresh rate to reduce power consumption. In addition, since each gating unit can be individually controlled, different regions can be dynamically selected to adjust the screen refresh rate according to needs, and the on-time duration of the gating unit can be changed arbitrarily to achieve a higher screen refresh rate. dynamic adjustment.
附图说明Description of drawings
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without any creative effort.
图1为本申请实施例中一种显示面板的结构示意图；FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the present application;
图2为本申请实施例中另一种显示面板的结构示意图；FIG. 2 is a schematic structural diagram of another display panel in an embodiment of the present application;
图3为图2中显示面板对应的一种信号时序图；FIG. 3 is a timing diagram of a signal corresponding to the display panel in FIG. 2;
图4为本申请实施例中另一种显示面板的结构示意图；FIG. 4 is a schematic structural diagram of another display panel in an embodiment of the present application;
图5为图4中显示面板对应的一种信号时序图；FIG. 5 is a timing diagram of a signal corresponding to the display panel in FIG. 4;
图6为本申请实施例中另一种显示面板的结构示意图；FIG. 6 is a schematic structural diagram of another display panel in the embodiment of the present application;
图7为图6中显示面板对应的一种信号时序图；FIG. 7 is a timing diagram of a signal corresponding to the display panel in FIG. 6;
图8为本申请实施例中一种选通单元的等效电路图；FIG. 8 is an equivalent circuit diagram of a gating unit in an embodiment of the present application;
图9为本申请实施例中一种显示装置的结构示意图。FIG. 9 is a schematic structural diagram of a display device in an embodiment of the present application.
具体实施方式Detailed ways
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。Terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of this application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.
如图1所示，图1为本申请实施例中一种显示面板的结构示意图，本申请实施例提供一种显示面板，包括：多行子像素1，其中，子像素1在显示区域10内呈阵列排布，沿第一方向h1排列为为多列，沿第二方向h2排列为多行，每个子像素1为一个最小显示单元，多个子像素1组成一个像素，例如，每个像素包括红色子像素、绿色子像素和蓝色子像素，通过三种颜色的组合实现彩色显示，多个像素共同实现整个画面的显示；与每行子像素1对应电连接的扫描线2以及与每列子像素1对应电连接的数据线3，在画面显示过程中，需要通过行扫描的方式来实现数据写入，即通过扫描线2为子像素1提供扫描信号，数据线3上的数据电压响应于扫描信号传输至对应的子像素1，以实现数据写入，例如，当扫描第一行子像素1时，第一行子像素1对应的扫描线2提供导通电平，其他行子像素1对应的扫描线2提供截止电平，数据线3上的数据电压传输至第一行子像素1；然后进行第二行子像素1的扫描，第二行子像素1对应的扫描线2提供导通电平，其他行子像素1对应的扫描线2提供截止电平，数据线3上的数据电压传输至第二行子像素1，以此类推，逐行进行画面的刷新，每个子像素1根据数据电压显示对应的灰度，显示刷新率表示每秒钟画面的扫描次数，刷新率越高，则扫描速度越快，画面显示效果越好，不容易出现闪烁现象，但是相应的功耗越高；与每条扫描线2对应的选通单元4，选通单元4包括第一输入端401、输出端41和控制端42，选通单元4的输出端41电连接于对应的扫描线2，选通单元4用于在其控制端42的信号控制下，使第一输入端401和输出端41之间导通或截止。As shown in FIG. 1 , FIG. 1 is a schematic structural diagram of a display panel in the embodiment of the present application. The embodiment of the present application provides a display panel, including: multiple rows of sub-pixels 1 , wherein the sub-pixels 1 are in the display area 10 Arranged in an array, arranged in multiple columns along the first direction h1, and arranged in multiple rows along the second direction h2, each sub-pixel 1 is a minimum display unit, and multiple sub-pixels 1 form a pixel, for example, each pixel includes The red sub-pixel, green sub-pixel and blue sub-pixel realize color display through the combination of three colors, and multiple pixels jointly realize the display of the entire screen; the scanning line 2 electrically connected to the sub-pixel 1 in each row and the sub-pixel in each column The pixel 1 corresponds to the data line 3 that is electrically connected. During the screen display process, data writing needs to be realized by row scanning, that is, the scanning signal is provided for the sub-pixel 1 through the scanning line 2, and the data voltage on the data line 3 responds to The scanning signal is transmitted to the corresponding sub-pixel 1 to realize data writing. For example, when scanning the sub-pixel 1 in the first row, the scanning line 2 corresponding to the sub-pixel 1 in the first row provides a conduction level, and the sub-pixel 1 in other rows The corresponding scan line 2 provides the cut-off level, and the data voltage on the data line 3 is transmitted to the first row of sub-pixels 1; then, the second row of sub-pixels 1 is scanned, and the corresponding scan line 2 of the second row of sub-pixels 1 provides the conduction voltage. On level, the scanning line 2 corresponding to the sub-pixel 1 in other rows provides the off-level, the data voltage on the data line 3 is transmitted to the sub-pixel 1 in the second row, and so on, the screen is refreshed row by row, each sub-pixel 1 According to the corresponding gray level of the data voltage display, the display refresh rate indicates the number of screen scans per second. The higher the refresh rate, the faster the scan speed, the better the screen display effect, and less likely to flicker, but the corresponding power consumption is higher. High; the gate unit 4 corresponding to each scan line 2, the gate unit 4 includes a first input terminal 401, an output terminal 41 and a control terminal 42, and the output terminal 41 of the gate unit 4 is electrically connected to the corresponding scan line 2 , the gating unit 4 is used to switch on or off the first input terminal 401 and the output terminal 41 under the control of the signal of the control terminal 42 .
具体地，通过设置选通单元4，使得可以单独控制每条扫描线2与对应的第一输入端401之间导通还是截止，第一输入端401用于提供电平，当扫描线2与对应的第一输入端401之间导通时，第一输入端401处的电平才会传输至对应的扫描线2上，以此来实现为扫描线2提供扫描信号，因此，可以分区域通过控制不同区域对应的选通单元4的导通时长，使不同区域具有不同的画面刷新率，例如，显示区域10包括第一显示区域11和第二显示区域12，第一显示区域11包括第1至第300行子像素1，第二显示区域12包括第301至第600行子像素1，第i个选通单元4的输出端41第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、600，显示面板周期性进行驱动扫描，每个周期包括第一阶段和第二阶段，在每个阶段，第1至第600个选通单元4的输入端401提供一次完整的扫描信号，一次完整的扫描信号是指，每个选通单元4的输入端401提供一次导通电平，且在同一时刻，仅有一个选通单元4的输入端401提供导通电平，其他选通单元4的输入端401均提供截止电平，在第一阶段，控制第1至第600个选通单元4均导通，即在第一阶段，第一显示区域11和第二显示区域12中的所有行子像素1进行一次刷新，在第二阶段，控制第1至第300个选通单元4导通，控制第301至第600个选通单元4截止，即在第二阶段，第一显示区域11中的子像素1进行一次刷新，第二显示区域12中的子像素1不进行刷新。也就是说，在每个周期中，第一显示区域11进行两次刷新，第二显示区域12进行一次刷新，即实现了分区域的刷新率控制。可以理解地，以上仅以各选通单元4的输入端401所提供的一种时序为例说明通过控制不同区域对应的选通单元4的导通时长，可以使不同区域具有不同的画面刷新率，本申请实施例对于各选通单元4的输入端401所提供的时序不作限定，在后文中会以其他时序为例进行说明，即会在后文介绍各选通单元4的输入端401的信号具体提供方式。选通单元4的控制端42具体可以由驱动芯片来提供信号实现控制。Specifically, by setting the gating unit 4, it is possible to individually control whether each scanning line 2 is turned on or off with the corresponding first input terminal 401. The first input terminal 401 is used to provide a level. When the scanning line 2 and the corresponding first input terminal 401 When the corresponding first input terminals 401 are turned on, the level at the first input terminal 401 will be transmitted to the corresponding scanning line 2, so as to provide scanning signals for the scanning line 2. Therefore, it can be divided into regions By controlling the conduction duration of the gate units 4 corresponding to different areas, different areas have different screen refresh rates. For example, the display area 10 includes a first display area 11 and a second display area 12, and the first display area 11 includes a second display area. 1 to the 300th row of sub-pixels 1, the second display area 12 includes the 301st to 600th row of sub-pixels 1, the output terminal 41 of the i-th gating unit 41 of the i-th scanning line 2, the i-th scanning line 2 Connected to the sub-pixel 1 in the i-th row, the value of i is 1, 2, 3, ..., 600, and the display panel is periodically driven and scanned, and each cycle includes the first stage and the second stage. In each stage, the first The input terminal 401 of the 1st to the 600th gating unit 4 provides a complete scanning signal. A complete scanning signal means that the input terminal 401 of each gating unit 4 provides a conduction level, and at the same time, The input terminal 401 of only one gating unit 4 provides a turn-on level, and the input terminals 401 of other gating units 4 provide a cut-off level. In the first stage, the first to 600th gating units 4 are controlled to be turned on. In the first stage, all rows of sub-pixels 1 in the first display area 11 and the second display area 12 are refreshed once; in the second stage, the first to 300th gate units 4 are controlled to be turned on, and The 301st to 600th gate units 4 are turned off, that is, in the second stage, the sub-pixels 1 in the first display area 11 are refreshed once, and the sub-pixels 1 in the second display area 12 are not refreshed. That is to say, in each period, the first display area 11 is refreshed twice, and the second display area 12 is refreshed once, that is, the refresh rate control by area is realized. Understandably, the above only takes a timing provided by the input terminal 401 of each gating unit 4 as an example to illustrate that by controlling the conduction duration of the gating units 4 corresponding to different regions, different regions can have different screen refresh rates. , the embodiment of the present application does not limit the timing provided by the input terminal 401 of each gating unit 4, and other timings will be used as examples to illustrate in the following, that is, the input terminal 401 of each gating unit 4 will be introduced later. The specific way to provide the signal. Specifically, the control terminal 42 of the gating unit 4 can be controlled by providing signals from the driver chip.
本申请实施例中的显示面板，设置与每条扫描线对应的选通单元，通过较为简单的结构改进即可可以单独控制每条扫描线与对应的第一输入端之间导通还是截止，第一输入端用于提供电平，当扫描线与对应的第一输入端之间导通时，第一输入端处的电平才会传输至对应的扫描线上，以此来实现为扫描线提供扫描信号，因此，可以分区域通过控制不同区域对应的选通单元的导通时长，使不同区域具有不同的画面刷新率，例如，使部分区域具有较高刷新率来防止闪烁等现象，提高显示效果，使另一部分区域具有较低刷新率，以降低功耗。另外，由于每个选通单元均可以实现单独的控制，因此可以根据需要动态选择不同的区域以实现画面刷新率的调节，并且，可以任意改变选通单元的导通时长，从而实现画面刷新率的动态调节。In the display panel in the embodiment of the present application, a gate unit corresponding to each scanning line is provided, and through a relatively simple structural improvement, it is possible to individually control whether each scanning line is turned on or off with the corresponding first input terminal. The first input terminal is used to provide a level. When the scan line is connected to the corresponding first input terminal, the level at the first input terminal will be transmitted to the corresponding scan line, so as to realize scanning Lines provide scanning signals. Therefore, different regions can have different screen refresh rates by controlling the conduction duration of the gate units corresponding to different regions in different regions. For example, some regions have higher refresh rates to prevent flickering and other phenomena. Improve the display effect and make another part of the area have a lower refresh rate to reduce power consumption. In addition, since each gating unit can be individually controlled, different regions can be dynamically selected to adjust the screen refresh rate according to needs, and the on-time duration of the gating unit can be changed arbitrarily to achieve a higher screen refresh rate. dynamic adjustment.
可选地，如图2所示，图2为本申请实施例中另一种显示面板的结构示意图，显示面板还包括扫描驱动电路50，扫描驱动电路50包括级联的多个移位寄存器5，每个移位寄存器5对应一个选通单元4；移位寄存器5的输出端电连接于对应的选通单元4的第一输入端401。Optionally, as shown in FIG. 2, FIG. 2 is a schematic structural diagram of another display panel in the embodiment of the present application. The display panel also includes a scanning driving circuit 50, and the scanning driving circuit 50 includes a plurality of cascaded shift registers 5 , each shift register 5 corresponds to a gating unit 4 ; the output end of the shift register 5 is electrically connected to the first input end 401 of the corresponding gating unit 4 .
具体地，扫描驱动电路50用于输出扫描信号，如图2和图3所示，图3为图2中显示面板对应的一种信号时序图，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。V1、V2、V3、…、Vn分别表示第1至第n个移位寄存器5的输出端的信号波形，Vn+1、Vn+2、…、Vn+m分别表示第n+1至第n+m个移位寄存器5的输出端的信号波形，G1、G2、G3、…、Gn分别表示第1至第n个选通单元4的输出端41的信号波形，Gn+1、Gn+2、…、Gn+m分别表示第n+1至第n+m个选通单元2的输出端41的信号波形，C1表示第1至第n个选通单元4的控制端42的信号波形，C2表示第n+1至第n+m个选通单元4的控制端42的信号波形，即第1至第n个选通单元4的控制端42由相同的信号控制，第n+1至第n+m个选通单元4的控制端42由相同的信号控制，对于选通单元4的控制端42，当其为高电平时控制选通单元4的第一输入端401和输出端41之间导通，当其为低电平用于控制选通单元4的第一输入端401和输出端41之间截止。显示面板以单位时间T为周期进行驱动，单位时间T包括第a帧和第b帧，扫描驱动电路50以帧为周期输出扫描信号，在每帧中，第1至第n+m个移位寄存器5的输出端依次输出导通电平，例如，在每帧的第1时刻，第1个移位寄存器5的输出端输出导通电平，其他移位寄存器5的输出端输出截止电平；在每帧的第2时刻，第2个移位寄存器5的输出端输出导通电平，其他移位寄存器5的输出端输出截止电平；依次类推，在每帧的第n+m时刻，第n+m个移位寄存器5的输出端输出导通电平，其他移位寄存器5的输出端输出截止电平。本申请实施例中以高电平为导通电平、低电平为截止电平为例进行说明，在第a帧，C1和C2均为高电平，控制第1至第n+m个选通单元4的第一输入端401和输出端41之间导通，即在第a帧，每个选通单元4的输出端41的信号均和对应的移位寄存器5的输出端的信号相同，使得在第a帧，第一显示区域11和第二显示区域12完成一次画面刷新；在第b帧，C1为高电平，控制第1至第n个选通单元4的第一输入端401和输出端41之间导通，即在第b帧，第一显示区域11对应的选通单元4的输出端41的信号均和对应的移位寄存器5的输出端的信号相同，使得第一显示区域11完成一次画面刷新，C2为低电平，控制第n+1至第n+m个选通单元4的第一输入端401和输出端41之间截止，即第二显示区域12对应的移位寄存器5的输出端的信号无法传输至对应的扫描线2，使得第二显示区域12无画面刷新。也就是说，在单位时间T内，第一显示区域11进行了两次画面刷新而第二显示区域12进行了一次画面刷新，即通过控制不同区域对应的选通单元4的导通时长，使不同区域具有不同的画面刷新率，与常规的显示面板相比，通过在原本的移位寄存器和扫描线之间增加串联选通单元，无需改变扫描驱动电路的结构和相应时序，通过对选通单元的控制，即可改变不同区域的画面刷新率。Specifically, the scanning driving circuit 50 is used to output scanning signals, as shown in FIG. 2 and FIG. 3 , and FIG. 3 is a signal timing diagram corresponding to the display panel in FIG. n rows of sub-pixels 1, the second display area 12 includes sub-pixels 1 in rows n+1 to n+m, and the output end of the i-th shift register 5 is electrically connected to the first input of the i-th gating unit 4 Terminal 401, the output terminal 41 of the i-th gate unit 2 is connected to the i-th scan line 2, the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2, 3, ..., n+m. V1 , V2 , V3 , ..., Vn represent the signal waveforms at the output terminals of the first to nth shift registers 5 respectively, and Vn+1 , Vn+2 , ..., Vn+m respectively represent the The signal waveforms of the output terminals of n+1 to n+m shift registers 5, G1 , G2 , G3 ,..., Gn respectively represent the signals of the output terminals 41 of the 1st to nth gating units 4 Waveforms, Gn+1 , Gn+2 , ..., Gn+m represent the signal waveforms of the output terminals 41 of the n+1th to n+mth gating units 2 respectively, and C1 represents the 1st to nth The signal waveform of the control terminal 42 of the gating unit 4, C2 represents the signal waveform of the control terminal 42 of the n+1 to n+m gating unit 4, that is, the control terminal of the 1st to nth gating unit 4 42 is controlled by the same signal, and the control terminal 42 of the n+1th to n+m gating unit 4 is controlled by the same signal. For the control terminal 42 of the gating unit 4, when it is high level, it controls the gating The connection between the first input terminal 401 and the output terminal 41 of the unit 4 is conducted, and when it is at a low level, it is used to control the cut-off between the first input terminal 401 and the output terminal 41 of the gating unit 4 . The display panel is driven with a unit time T as a period, and the unit time T includes the a-th frame and the b-th frame, and the scanning driving circuit 50 outputs a scanning signal with a frame as a period, and in each frame, the 1st to n+mth shifts The output terminals of the register 5 output the conduction level sequentially, for example, at the first moment of each frame, the output terminal of the first shift register 5 outputs the conduction level, and the output terminals of the other shift register 5 output the cut-off level ; At the second moment of each frame, the output terminal of the second shift register 5 outputs the conduction level, and the output terminals of other shift registers 5 output the cut-off level; and so on, at the n+m moment of each frame , the output terminal of the n+mth shift register 5 outputs the on-level, and the output terminals of the other shift registers 5 output the off-level. In the embodiment of this application, the high level is used as the on-level and the low level is used as the cut-off level as an example. In the a-th frame, both C1 and C2 are high-level, and control the first to n+ The conduction between the first input terminal 401 and the output terminal 41 of the m gating units 4, that is, in the ath frame, the signal of the output terminal 41 of each gating unit 4 is equal to the signal of the output terminal of the corresponding shift register 5 The signals are the same, so that in frame a, thefirst display area 11 and the second display area 12 complete a picture refresh; A conduction between the input terminal 401 and the output terminal 41, that is, in the b-th frame, the signal of the output terminal 41 of the gate unit 4 corresponding to the first display area 11 is the same as the signal of the output terminal of the corresponding shift register 5, Make the first display area 11 complete a picture refresh,C2 is low level, control the cut-off between the first input terminal 401 and the output terminal 41 of the n+1th to n+mth gating unit 4, that is, the second The signal at the output end of the shift register 5 corresponding to the display area 12 cannot be transmitted to the corresponding scan line 2 , so that the second display area 12 has no screen refresh. That is to say, within the unit time T, the first display area 11 has performed two screen refreshes and the second display area 12 has performed one screen refresh, that is, by controlling the conduction duration of the gate units 4 corresponding to different areas, so that Different areas have different screen refresh rates. Compared with conventional display panels, by adding a series gate unit between the original shift register and the scan line, there is no need to change the structure and corresponding timing of the scan drive circuit. The control of the unit can change the screen refresh rate of different areas.
可选地，如图4所示，图4为本申请实施例中另一种显示面板的结构示意图，显示面板还包括：第一时钟信号线CK1和第二时钟信号线CK2；第一时钟信号线CK1电连接于每个奇数行扫描线2对应的选通单元4的第一输入端401，第二时钟信号线CK2电连接于每个偶数行扫描线2对应的选通单元4的第一输入端401。Optionally, as shown in FIG. 4, FIG. 4 is a schematic structural diagram of another display panel in the embodiment of the present application. The display panel further includes: a first clock signal line CK1 and a second clock signal line CK2; The line CK1 is electrically connected to the first input terminal 401 of the gate unit 4 corresponding to each odd-numbered scanning line 2, and the second clock signal line CK2 is electrically connected to the first input terminal 401 of the gate unit 4 corresponding to each even-numbered scanning line 2. input 401 .
具体地，如图4和图5所示，图5为图4中显示面板对应的一种信号时序图，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。C1、C2、C3、…、Cn+m分别表示第1至第n+m个选通单元4的控制端42的信号波形，G1、G2、G3、…、Gn分别表示第1至第n个选通单元4的输出端41的信号波形，Gn+1、Gn+2、…、Gn+m分别表示第n+1至第n+m个选通单元2的输出端41的信号波形，第一时钟信号线CK1和第二时钟信号线CK2分别输出相反极性的时钟信号，VCK1表示第一时钟信号线CK1的信号波形，VCK2表示第二时钟信号线CK2的信号波形，对于选通单元4的控制端42，当其为高电平时控制选通单元4的第一输入端401和输出端41之间导通，当其为低电平用于控制选通单元4的第一输入端401和输出端41之间截止。显示面板以单位时间T为周期进行驱动，单位时间T包括第a帧和第b帧，在第a帧，第1至第n+m个选通单元4的第一输入端401和输出端41之间依次导通，其中，在奇数选通单元4的第一输入端401和输出端41之间导通时，恰好使第一时钟信号线CK1上的导通电平通过选通单元4传输至对应的扫描线2，在偶数选通单元4的第一输入端401和输出端41之间导通时，恰好使第二时钟信号线CK2上的导通电平通过选通单元4传输至对应的扫描线2，使得第1至第n+m条扫描线2上产生扫描信号，第1至第n+m条扫描线2上的信号波形即G1至Gn+m的信号波形，使得在第a帧，第一显示区域11和第二显示区域12完成一次画面刷新；在第b帧，第1至第n个选通单元4的第一输入端401和输出端41之间依次导通，使得对应的扫描线2上产生扫描信号，即在第b帧，第一显示区域11对应的扫描线2上产生扫描信号，第一显示区域11完成一次画面刷新，第n+1至第n+m个选通单元4的第一输入端401和输出端41之间保持截止，使得对应的扫描线2上不会产生扫描信号，第二显示区域12无画面刷新。也就是说，在单位时间T内，第一显示区域11进行了两次画面刷新而第二显示区域12进行了一次画面刷新，即通过控制不同区域对应的选通单元4的导通时长，使不同区域具有不同的画面刷新率，与常规的显示面板相比，无需设置扫描驱动电路，只需要两条时钟信号线配合选通单元4，即可改变不同区域的画面刷新率，两条时钟信号线可以复用显示面板中本身所需要的时钟信号线，例如，有机发光显示面板还包括发光控制电路，发光控制电路用于提供扫描信号控制每个子像素的发光时间，发光控制电路需要使用时钟信号，因此，发光控制电路可以复用上述第一时钟信号线CK1和第二时钟信号线CK2。Specifically, as shown in FIG. 4 and FIG. 5, FIG. 5 is a signal timing diagram corresponding to the display panel in FIG. 12 includes the n+1 to n+m rows of sub-pixels 1, the output end of the i-th shift register 5 is electrically connected to the first input end 401 of the i-th gating unit 4, and the i-th gating unit 2 The output terminal 41 of the i-th scan line 2 is connected to the i-th scan line 2, and the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2, 3, . . . , n+m. C1 , C2 , C3 , ..., Cn+m represent the signal waveforms of the control terminals 42 of the first to n+m gating units 4 respectively, G1 , G2 , G3 , ..., Gn Represent the signal waveforms of the output terminals 41 of the 1st to nth gating units 4,Gn+1 , Gn+2 , ..., Gn+m respectively represent the n+1th to n+mth gating units The signal waveform of the output terminal 41 of the unit 2, the first clock signal line CK1 and the second clock signal line CK2 respectively output clock signals of opposite polarities, VCK1 represents the signal waveform of the first clock signal line CK1, VCK2 represents the second The signal waveform of the clock signal line CK2, for the control terminal 42 of the gating unit 4, when it is at a high level, controls the conduction between the first input terminal 401 and the output terminal 41 of the gating unit 4, and when it is at a low level It is used to control the cut-off between the first input terminal 401 and the output terminal 41 of the gating unit 4 . The display panel is driven with a unit time T as a cycle, and the unit time T includes the a-th frame and the b-th frame, and in the a-th frame, the first input terminal 401 and the output terminal 41 of the first to n+mth gate units 4 between the first input terminal 401 and the output terminal 41 of the odd-numbered gate unit 4, and the conduction level on the first clock signal line CK1 is just transmitted through the gate unit 4 To the corresponding scanning line 2, when conducting between the first input terminal 401 and the output terminal 41 of the even-numbered gate unit 4, the conduction level on the second clock signal line CK2 is transmitted to the The corresponding scanning line 2 makes scanning signals generated on the 1st to n+m scanning lines 2, and the signal waveforms on the 1st to n+m scanning lines 2 are the signal waveforms ofG1 to Gn+m , So that in frame a, the first display area 11 and the second display area 12 complete a picture refresh; turn on, so that the scanning signal is generated on the corresponding scanning line 2, that is, in the bth frame, the scanning signal is generated on the scanning line 2 corresponding to the first display area 11, and the first display area 11 completes a screen refresh, and the n+1 to The first input terminal 401 and the output terminal 41 of the n+m gate unit 4 are kept cut off, so that no scanning signal is generated on the corresponding scanning line 2 , and the second display area 12 has no screen refresh. That is to say, within the unit time T, the first display area 11 has performed two screen refreshes and the second display area 12 has performed one screen refresh, that is, by controlling the conduction duration of the gate units 4 corresponding to different areas, so that Different areas have different picture refresh rates. Compared with conventional display panels, there is no need to set up a scanning drive circuit, and only two clock signal lines are needed to cooperate with the gating unit 4 to change the picture refresh rates of different areas. The two clock signals The line can multiplex the clock signal line required by the display panel itself. For example, the organic light-emitting display panel also includes a light-emitting control circuit. The light-emitting control circuit is used to provide scanning signals to control the light-emitting time of each sub-pixel. The light-emitting control circuit needs to use clock signals Therefore, the light emission control circuit can multiplex the first clock signal line CK1 and the second clock signal line CK2.
可选地，如图6所示，图6为本申请实施例中另一种显示面板的结构示意图，显示面板还包括：导通电平信号线VGH，导通电平信号线VGH电连接于每个选通单元4的第一输入端401。Optionally, as shown in FIG. 6, FIG. 6 is a schematic structural diagram of another display panel in the embodiment of the present application. The display panel further includes: a conduction level signal line VGH, and the conduction level signal line VGH is electrically connected to The first input terminal 401 of each gating unit 4 .
具体地，如图6和图7所示，图7为图6中显示面板对应的一种信号时序图，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。C1、C2、C3、…、Cn+m分别表示第1至第n+m个选通单元4的控制端42的信号波形，G1、G2、G3、…、Gn分别表示第1至第n个选通单元4的输出端41的信号波形，Gn+1、Gn+2、…、Gn+m分别表示第n+1至第n+m个选通单元2的输出端41的信号波形，第一时钟信号线CK1和第二时钟信号线CK2分别输出相反极性的时钟信号，VGH表示导通电平信号线VGH的信号波形，导通电平信号线VGH提供持续的导通电平，例如高电平，对于选通单元4的控制端42，当其为高电平时控制选通单元4的第一输入端401和输出端41之间导通，当其为低电平用于控制选通单元4的第一输入端401和输出端41之间截止。显示面板以单位时间T为周期进行驱动，单位时间T包括第a帧和第b帧，在第a帧，第1至第n+m个选通单元4的第一输入端401和输出端41之间依次导通，其中，当某个选通单元4的第一输入端401和输出端41之间导通时，使导通电平信号线VGH上的导通电平通过该选通单元4传输至对应的扫描线2上，使得第1至第n+m条扫描线2上产生扫描信号，第1至第n+m条扫描线2上的信号波形即G1至Gn+m的信号波形，使得在第a帧，第一显示区域11和第二显示区域12完成一次画面刷新；在第b帧，第1至第n个选通单元4的第一输入端401和输出端41之间依次导通，使得对应的扫描线2上产生扫描信号，即在第b帧，第一显示区域11对应的扫描线2上产生扫描信号，第一显示区域11完成一次画面刷新，第n+1至第n+m个选通单元4的第一输入端401和输出端41之间保持截止，使得对应的扫描线2上不会产生扫描信号，第二显示区域12无画面刷新。也就是说，在单位时间T内，第一显示区域11进行了两次画面刷新而第二显示区域12进行了一次画面刷新，即通过控制不同区域对应的选通单元4的导通时长，使不同区域具有不同的画面刷新率，与常规的显示面板相比，无需设置扫描驱动电路，只需要导通电平信号线VGH配合选通单元4，即可改变不同区域的画面刷新率，导通电平信号线VGH可以复用显示面板中本身所需要的信号线。Specifically, as shown in FIG. 6 and FIG. 7, FIG. 7 is a signal timing diagram corresponding to the display panel in FIG. 12 includes the n+1 to n+m rows of sub-pixels 1, the output end of the i-th shift register 5 is electrically connected to the first input end 401 of the i-th gating unit 4, and the i-th gating unit 2 The output terminal 41 of the i-th scan line 2 is connected to the i-th scan line 2, and the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2, 3, . . . , n+m. C1 , C2 , C3 , ..., Cn+m represent the signal waveforms of the control terminals 42 of the first to n+m gating units 4 respectively, G1 , G2 , G3 , ..., Gn Represent the signal waveforms of the output terminals 41 of the 1st to nth gating units 4,Gn+1 , Gn+2 , ..., Gn+m respectively represent the n+1th to n+mth gating units The signal waveform of the output terminal 41 of the unit 2, the first clock signal line CK1 and the second clock signal line CK2 respectively output clock signals of opposite polarities, VGH represents the signal waveform of the conduction level signal line VGH, and the conduction level The signal line VGH provides a continuous conduction level, such as a high level. For the control terminal 42 of the gating unit 4, when it is at a high level, it controls the conduction between the first input terminal 401 and the output terminal 41 of the gating unit 4. When it is at low level, it is used to control the cut-off between the first input terminal 401 and the output terminal 41 of the gating unit 4 . The display panel is driven with a unit time T as a cycle, and the unit time T includes the a-th frame and the b-th frame, and in the a-th frame, the first input terminal 401 and the output terminal 41 of the first to n+mth gate units 4 between the first input terminal 401 and the output terminal 41 of a certain gating unit 4, and the conduction level on the conduction level signal line VGH passes through the gate unit 4 4 is transmitted to the corresponding scanning line 2, so that scanning signals are generated on the 1st to n+m scanning lines 2, and the signal waveforms on the 1st to n+m scanning lines 2 are G1 to Gn+m signal waveform, so that in the ath frame, the first display area 11 and the second display area 12 complete a screen refresh; 41 are sequentially turned on, so that a scanning signal is generated on the corresponding scanning line 2, that is, in the b-th frame, a scanning signal is generated on the scanning line 2 corresponding to the first display area 11, and the first display area 11 completes a screen refresh, and the second The first input terminal 401 and the output terminal 41 of the n+1 to n+mth gate units 4 are kept cut off, so that no scanning signal is generated on the corresponding scanning line 2 , and the second display area 12 has no screen refresh. That is to say, within the unit time T, the first display area 11 has performed two screen refreshes and the second display area 12 has performed one screen refresh, that is, by controlling the conduction duration of the gate units 4 corresponding to different areas, so that Different areas have different picture refresh rates. Compared with conventional display panels, there is no need to set up a scanning drive circuit, and only need to turn on the level signal line VGH and cooperate with the gating unit 4 to change the picture refresh rate in different areas. The level signal line VGH can multiplex the signal lines required in the display panel itself.
可选地，如图2、图4和图6所示，显示面板还包括：截止电平信号线VGL；选通单元4还包括第二输入端402，第二输入端402电连接于截止电平信号线VGL，选通单元4用于在其控制端42的信号控制下，控制第一输入端401和第二输入端402中的一者与其输出端41之间导通，在选通单元4中，当第一输入端401和输出端41之间导通时，第二输入端402和输出端41之间截止，当第二输入端402和输出端41之间导通时，第一输入端401和输出端41之间截止。Optionally, as shown in FIG. 2 , FIG. 4 and FIG. 6 , the display panel further includes: an off-level signal line VGL; Flat signal line VGL, the gating unit 4 is used to control the conduction between one of the first input end 401 and the second input end 402 and its output end 41 under the signal control of its control end 42, and the gating unit 4 4, when the conduction between the first input terminal 401 and the output terminal 41, the cutoff between the second input terminal 402 and the output terminal 41, when the conduction between the second input terminal 402 and the output terminal 41, the first The connection between the input terminal 401 and the output terminal 41 is cut off.
具体地，截止电平信号线VGL用于输出截止电平，在控制选通单元4的第一输入端401和输出端41之间截止时，是用于防止在对应的扫描线2上产生扫描信号，同时，为了维持扫描线2上的电位稳定，即使第二输入端402和输出端41之间导通，使截止电平传输至对应的扫描线2上。Specifically, the cut-off level signal line VGL is used to output the cut-off level, and when the first input terminal 401 and the output terminal 41 of the control gating unit 4 are cut off, it is used to prevent scanning from being generated on the corresponding scanning line 2. At the same time, in order to keep the potential on the scanning line 2 stable, even if the second input terminal 402 and the output terminal 41 are conducting, the cut-off level is transmitted to the corresponding scanning line 2 .
可选地，如图8所示，图8为本申请实施例中一种选通单元的等效电路图，选通单元4包括：第一开关晶体管M1，其第一端电连接于第一输入端401，其第二端电连接于选通单元4的输出端41，其控制端电连接于选通单元4的控制端42；第二开关晶体管M2，其第一端电连接于选通单元4的输出端41，其第二端电连接于第二输入端402，其控制端电连接于选通单元4的控制端42；第一开关晶体管M1为N型晶体管，第二开关晶体管M2为P型晶体管；或者，第一开关晶体管M1为P型晶体管，第二开关晶体管M2为N型晶体管。即，第一开关晶体管M1和第二开关晶体管M2的控制类型相反，这样，例如，当选通单元4的控制端42为高电平时，控制第一开关晶体管M1导通、第二开关晶体管M2截止，当选通单元4的控制端42为低电平时，控制第一开关晶体管M1截止、第二开关晶体管M2导通，即通过同一个信号实现两个开关管的控制，且实现了信号选通的功能，结构简单。Optionally, as shown in FIG. 8, FIG. 8 is an equivalent circuit diagram of a gating unit in the embodiment of the present application. The gating unit 4 includes: a first switch transistor M1, the first end of which is electrically connected to the first input End 401, its second end is electrically connected to the output end 41 of the gating unit 4, its control end is electrically connected to the control end 42 of the gating unit 4; the second switching transistor M2, its first end is electrically connected to the gating unit The output terminal 41 of 4, its second terminal is electrically connected to the second input terminal 402, and its control terminal is electrically connected to the control terminal 42 of the gating unit 4; the first switch transistor M1 is an N-type transistor, and the second switch transistor M2 is A P-type transistor; or, the first switch transistor M1 is a P-type transistor, and the second switch transistor M2 is an N-type transistor. That is, the control types of the first switch transistor M1 and the second switch transistor M2 are opposite, so, for example, when the control terminal 42 of the gating unit 4 is at a high level, the first switch transistor M1 is controlled to be turned on and the second switch transistor M2 is turned off. , when the control terminal 42 of the gating unit 4 is at a low level, the first switching transistor M1 is controlled to be turned off and the second switching transistor M2 is turned on, that is, the control of the two switching transistors is realized through the same signal, and the signal gating is realized. Function, simple structure.
另外，在上述各实施例中，由于每个选通单元均可以实现单独的控制，因此可以根据需要动态选择不同的区域以实现画面刷新率的调节，图1、图2、图4和图6中不同显示区域的划分仅为举例，在其他可实现的实施方式中，还可以设置更多的显示区域，例如设置三个显示区域，任意两个显示区域的画面刷新率均不同，并且，可以任意改变选通单元的导通时长，从而实现画面刷新率的动态调节，例如，在某些场景下，控制不同的显示区域具有不同的画面刷新率，而在另外一些场景下，控制所有的显示区域具有相同的画面刷新率。In addition, in the above-mentioned embodiments, since each gating unit can be individually controlled, different regions can be dynamically selected according to needs to realize the adjustment of the screen refresh rate, as shown in Fig. 1, Fig. 2, Fig. 4 and Fig. 6 The division of different display areas in the above is only an example. In other feasible implementation manners, more display areas can be set, for example, three display areas can be set, and the screen refresh rates of any two display areas are different, and can be Arbitrarily change the conduction time of the gating unit, so as to realize the dynamic adjustment of the screen refresh rate, for example, in some scenarios, control different display areas to have different screen refresh rates, and in other scenarios, control all display Zones have the same frame rate.
如图9所示，图9为本申请实施例中一种显示装置的结构示意图，本申请实施例还提供一种显示装置，包括：驱动芯片100和上述任意实施例中的显示面板200，驱动芯片100电连接于每个选通单元(图9中未示意)的控制端。As shown in FIG. 9, FIG. 9 is a schematic structural diagram of a display device in an embodiment of the present application. The embodiment of the present application also provides a display device, including: a driving chip 100 and a display panel 200 in any of the above-mentioned embodiments, driving The chip 100 is electrically connected to the control terminal of each gating unit (not shown in FIG. 9 ).
其中，显示面板200的具体结构和工作原理与上述实施例相同，在此不再赘述。Wherein, the specific structure and working principle of the display panel 200 are the same as those of the above-mentioned embodiments, and will not be repeated here.
本申请实施例中的显示装置，设置与每条扫描线对应的选通单元，通过较为简单的结构改进即可可以单独控制每条扫描线与对应的第一输入端之间导通还是截止，第一输入端用于提供电平，当扫描线与对应的第一输入端之间导通时，第一输入端处的电平才会传输至对应的扫描线上，以此来实现为扫描线提供扫描信号，因此，可以分区域通过控制不同区域对应的选通单元的导通时长，使不同区域具有不同的画面刷新率，例如，使部分区域具有较高刷新率来防止闪烁等现象，提高显示效果，使另一部分区域具有较低刷新率，以降低功耗。In the display device in the embodiment of the present application, a gating unit corresponding to each scanning line is provided, and through a relatively simple structural improvement, it is possible to individually control whether each scanning line is turned on or off with the corresponding first input terminal. The first input terminal is used to provide a level. When the scan line is connected to the corresponding first input terminal, the level at the first input terminal will be transmitted to the corresponding scan line, so as to realize scanning Lines provide scanning signals. Therefore, different regions can have different screen refresh rates by controlling the conduction duration of the gate units corresponding to different regions in different regions. For example, some regions have higher refresh rates to prevent flickering and other phenomena. Improve the display effect and make another part of the area have a lower refresh rate to reduce power consumption.
如图1至图7所示，本申请实施例还提供一种驱动方法，用于上述的显示面板，驱动方法包括：在单位时间T内，控制部分选通单元4使第一输入端401和输出端41之间导通于第一时长，控制另外一部分选通单元4使第一输入端401和输出端41之间导通于第二时长，第一时长不等于第二时长。As shown in FIG. 1 to FIG. 7 , the embodiment of the present application also provides a driving method for the above-mentioned display panel. The driving method includes: within a unit time T, controlling part of the gate unit 4 to make the first input terminal 401 and the first input terminal 401 The conduction between the output terminals 41 is at the first duration, and another part of the gating units 4 are controlled to conduct the conduction between the first input terminal 401 and the output terminal 41 at the second duration, and the first duration is not equal to the second duration.
具体地，部分选通单元4可以为上述第一显示区域11对应的选通单元4，另一部分选通单元4可以为上述第二显示区域12对应的选通单元4，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。部分选通单元4为第1至第n个选通单元4，另一部分选通单元4为第n+1至第n+m个选通单元4。例如在图2和图3所示的结构及对应的时序中，第一显示区域11对应的每个选通单元4的第一输入端401和输出端41在第a帧导通和第b帧均持续导通，第二显示区域12对应的每个选通单元4的第一输入端401和输出端41在第a帧中持续导通，在第b帧中不导通，即在单位时间T内，第一显示区域11对应的每个选通单元4的第一输入端401和输出端41的导通时长是第二显示区域12对应的每个选通单元4的第一输入端401和输出端41的导通时长的两倍。例如在图4至图7所示的结构及对应的时序中，第一显示区域11对应的每个选通单元4的第一输入端401和输出端41在第a帧导通一次、在第b帧中导通一次，第二显示区域12对应的每个选通单元4的第一输入端401和输出端41在第a帧中导通一次，在第b帧中不导通，每个选通单元4的第一输入端401和输出端41每次导通的时长相同，即在单位时间T内，第一显示区域11对应的每个选通单元4的第一输入端401和输出端41的导通时长是第二显示区域12对应的每个选通单元4的第一输入端401和输出端41的导通时长的两倍。显示面板的具体结构和工作原理以及驱动方法的具体过程与上述实施例相同，在此不再赘述。Specifically, part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned first display area 11, and another part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned second display area 12, for example, the first display area 11 includes the sub-pixels 1 in the 1st to nth rows, the second display area 12 includes the sub-pixels 1 in the n+1 to n+mth rows, and the output end of the i-th shift register 5 is electrically connected to the i-th gate The first input terminal 401 of the unit 4, the output terminal 41 of the i-th gate unit 2 is connected to the i-th scan line 2, the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2, 3, ..., n+m. Some of the gating units 4 are the 1st to nth gating units 4 , and the other part of the gating units 4 are the n+1th to n+mth gating units 4 . For example, in the structures and corresponding timings shown in FIG. 2 and FIG. 3 , the first input terminal 401 and output terminal 41 of each gate unit 4 corresponding to the first display area 11 are turned on in frame a and frame b. are continuously conducted, the first input terminal 401 and the output terminal 41 of each gating unit 4 corresponding to the second display area 12 are continuously conducted in the first frame, and are not conducted in the b-th frame, that is, in the unit time In T, the conduction duration of the first input terminal 401 and the output terminal 41 of each gate unit 4 corresponding to the first display area 11 is the first input terminal 401 of each gate unit 4 corresponding to the second display area 12 and twice the on-time of the output terminal 41. For example, in the structures and corresponding timings shown in FIG. 4 to FIG. Once conducted in frame b, the first input terminal 401 and output terminal 41 of each gate unit 4 corresponding to the second display area 12 are conducted once in frame a, and not conducted in frame b, each The first input terminal 401 and the output terminal 41 of the gating unit 4 are turned on for the same duration each time, that is, within the unit time T, the first input terminal 401 and the output terminal 401 of each gating unit 4 corresponding to the first display area 11 The conduction duration of the terminal 41 is twice the conduction period of the first input terminal 401 and the output terminal 41 of each gate unit 4 corresponding to the second display area 12 . The specific structure and working principle of the display panel and the specific process of the driving method are the same as those of the above-mentioned embodiments, and will not be repeated here.
本申请实施例中的驱动方法，设置与每条扫描线对应的选通单元，通过较为简单的结构改进即可可以单独控制每条扫描线与对应的第一输入端之间导通还是截止，第一输入端用于提供电平，当扫描线与对应的第一输入端之间导通时，第一输入端处的电平才会传输至对应的扫描线上，以此来实现为扫描线提供扫描信号，因此，可以分区域通过控制不同区域对应的选通单元的导通时长，使不同区域具有不同的画面刷新率，例如，使部分区域具有较高刷新率来防止闪烁等现象，提高显示效果，使另一部分区域具有较低刷新率，以降低功耗。In the driving method in the embodiment of the present application, a gating unit corresponding to each scanning line is set, and through a relatively simple structural improvement, it is possible to individually control whether each scanning line is turned on or off with the corresponding first input terminal. The first input terminal is used to provide a level. When the scan line is connected to the corresponding first input terminal, the level at the first input terminal will be transmitted to the corresponding scan line, so as to realize scanning Lines provide scanning signals. Therefore, different regions can have different screen refresh rates by controlling the conduction duration of the gate units corresponding to different regions in different regions. For example, some regions have higher refresh rates to prevent flickering and other phenomena. Improve the display effect and make another part of the area have a lower refresh rate to reduce power consumption.
可选地，驱动方法用于如图2所示的显示面板，如图3所示，驱动方法包括：扫描驱动电路50以帧为周期输出扫描信号，单位时间T包括第a帧和第b帧；在单位时间T内，控制部分选通单元4的第一输入端401和输出端41在第a帧和在b帧中均导通，控制另外一部分选通单元4的第一输入端401和输出端41在第a帧中导通、在第b帧中截止。Optionally, the driving method is used for the display panel as shown in FIG. 2. As shown in FIG. 3, the driving method includes: the scan driving circuit 50 outputs the scan signal in a frame cycle, and the unit time T includes the ath frame and the bth frame ; In the unit time T, the first input terminal 401 and the output terminal 41 of the control part of the gate unit 4 are all turned on in the first frame a and in the b frame, and the first input terminal 401 and the first input terminal 401 of the other part of the gate unit 4 are controlled. The output terminal 41 is turned on in the a-th frame and turned off in the b-th frame.
具体地，部分选通单元4可以为上述第一显示区域11对应的选通单元4，另一部分选通单元4可以为上述第二显示区域12对应的选通单元4，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。部分选通单元4为第1至第n个选通单元4，另一部分选通单元4为第n+1至第n+m个选通单元4。在第a帧的第1时刻，第1个移位寄存器5的输出端输出导通电平，并通过第1个选通单元4传输至第1行子像素1，以使第1行子像素1进行数据写入，其他移位寄存器5的输出端输出截止电平，并通过其他选通单元4传输至其他行子像素1；在第a帧的第2时刻，第2个移位寄存器5的输出端输出导通电平，并通过第2个选通单元4传输至第2行子像素1，以使第2行子像素1进行数据写入，其他移位寄存器5的输出端输出截止电平并传输至其他行子像素1；依次类推，直到第a帧的第n+m时刻，在第n+m个移位寄存器5的输出端输出导通电平，并通过第n+m个选通单元传输至第n+m行子像素1，其他移位寄存器5输出截止电平，并传输至其他行子像素1。即使第一显示区域11和第二显示区域12在第a帧均进行一次画面刷新。在第b帧的第1至第n时刻，与第a帧的第1至第n时刻的驱动方式相同，第一显示区域11进行一次画面刷新，在第b帧的第n+1至第n+m时刻，由于第n+1至第n+m个选通单元4的第一输入端401和输出端41截止，因此，即便移位寄存器5仍输出扫描信号，但是也无法通过传输至第二显示区域12中的子像素1，因此，第二显示区域12不进行画面刷新。Specifically, part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned first display area 11, and another part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned second display area 12, for example, the first display area 11 includes the sub-pixels 1 in the 1st to nth rows, the second display area 12 includes the sub-pixels 1 in the n+1 to n+mth rows, and the output end of the i-th shift register 5 is electrically connected to the i-th gate The first input terminal 401 of the unit 4, the output terminal 41 of the i-th gate unit 2 is connected to the i-th scan line 2, the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2, 3, ..., n+m. Some of the gating units 4 are the 1st to nth gating units 4 , and the other part of the gating units 4 are the n+1th to n+mth gating units 4 . At the first moment of frame a, the output terminal of the first shift register 5 outputs a conduction level, which is transmitted to the sub-pixels 1 of the first row through the first gating unit 4, so that the sub-pixels of the first row 1 to write data, the output terminals of other shift registers 5 output cut-off levels, and transmit to sub-pixels 1 of other rows through other gating units 4; at the second moment of frame a, the second shift register 5 The output end of the shift register 5 outputs a conduction level, and is transmitted to the sub-pixel 1 of the second row through the second gating unit 4, so that the sub-pixel 1 of the second row can write data, and the output of the other shift register 5 is cut off level and transmit it to the sub-pixels 1 in other rows; and so on, until the n+mth moment of the ath frame, the output terminal of the n+mth shift register 5 outputs the conduction level, and passes through the n+mth The gate units are transmitted to the sub-pixels 1 in the n+mth row, and the other shift registers 5 output cut-off levels, and are transmitted to the sub-pixels 1 in other rows. Even if the first display area 11 and the second display area 12 both perform an image refresh at frame a. From the 1st to the nth moment of the b frame, the driving method is the same as that of the ath frame from the 1st to the nth moment, the first display area 11 performs a screen refresh, and at the n+1th to the nth At +m moment, since the first input terminal 401 and the output terminal 41 of the n+1th to n+mth gate unit 4 are cut off, even if the shift register 5 still outputs the scanning signal, it cannot be transmitted to the first gate unit 4 The sub-pixels 1 in the second display area 12, therefore, the second display area 12 does not perform screen refresh.
可选地，驱动方法用于如图4所示的显示面板，如图5所示，驱动方法包括：第一时钟信号线CK1和第二时钟信号线CK2分别输出相反极性的时钟信号；单位时间T包括第a帧和第b帧，在单位时间T内，在第a帧中，控制每个选通单元4的第一输入端401和输出端41之间导通一次，且在同一时间，最多有一个选通单元4的第一输入端401和输出端41之间导通，在第b帧中，控制部分选通单元4的第一输入端401和输出端41之间导通一次，且在同一时间，最多有一个选通单元4的第一输入端401和输出端41之间导通，控制另一部分选通单元4的第一输入端401和输出端41之间截止。Optionally, the driving method is used for the display panel shown in FIG. 4. As shown in FIG. 5, the driving method includes: the first clock signal line CK1 and the second clock signal line CK2 respectively output clock signals of opposite polarities; the unit The time T includes the ath frame and the bth frame. Within the unit time T, in the ath frame, the conduction between the first input terminal 401 and the output terminal 41 of each gating unit 4 is controlled once, and at the same time , there is at most one conduction between the first input terminal 401 and the output terminal 41 of the gating unit 4, and in the bth frame, the conduction between the first input terminal 401 and the output terminal 41 of the control part of the gating unit 4 is conducted once , and at the same time, at most one gating unit 4 is conducted between the first input terminal 401 and the output terminal 41 , and the other part of gating units 4 is controlled to be cut off between the first input terminal 401 and the output terminal 41 .
具体地，部分选通单元4可以为上述第一显示区域11对应的选通单元4，另一部分选通单元4可以为上述第二显示区域12对应的选通单元4，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。部分选通单元4为第1至第n个选通单元4，另一部分选通单元4为第n+1至第n+m个选通单元4。在第a帧中，第一显示区域11和第二显示区域12对应的第1至第n+m个选通单元4的第一输入端401和输出端41依次导通。例如，在第a帧的第1时刻，第1个选通单元4的第一输入端401和输出端41导通，第2至第n+m个选通单元4的第一输入端401和输出端41截止，第一时钟信号线CK1的导通电平传输至第1行子像素1，使第1行子像素1进行数据写入；在第a帧的第2时刻，第2个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，第二时钟信号线CK2的导通电平传输至第2行子像素1，使第2行子像素1进行数据写入；依次类推，直到第a帧的第n+m时刻，第n+m个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，使第n+m行子像素1进行数据写入。在第b帧中，第一显示区域11对应的第1至第n个选通单元4的第一输入端401和输出端41依次导通，第二显示区域12对应的第n+1至第n+m个选通单元4的第一输入端401和输出端41保持截止。例如，在第b帧的第1时刻，第1个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，第一时钟信号线CK1的导通电平传输至第1行子像素1，使第1行子像素1进行数据写入；在第b帧的第2时刻，第2个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，第二时钟信号线CK2的导通电平传输至第2行子像素1，使第2行子像素1进行数据写入；依次类推，直到第b帧的第n时刻，第n个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，第n行子像素1进行数据写入；在第b帧的第n+1至第n+m时刻，每个选通单元4的第一输入端401和输出端41之间截止，即第n+1至第n+m行子像素1不进行数据写入。Specifically, part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned first display area 11, and another part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned second display area 12, for example, the first display area 11 includes the sub-pixels 1 in the 1st to nth rows, the second display area 12 includes the sub-pixels 1 in the n+1 to n+mth rows, and the output end of the i-th shift register 5 is electrically connected to the i-th gate The first input terminal 401 of the unit 4, the output terminal 41 of the i-th gate unit 2 is connected to the i-th scan line 2, the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2, 3, ..., n+m. Some of the gating units 4 are the 1st to nth gating units 4 , and the other part of the gating units 4 are the n+1th to n+mth gating units 4 . In frame a, the first input terminals 401 and output terminals 41 of the first to n+m gate units 4 corresponding to the first display area 11 and the second display area 12 are sequentially turned on. For example, at the first moment of frame a, the first input terminal 401 and output terminal 41 of the first gating unit 4 are turned on, and the first input terminals 401 and The output terminal 41 is turned off, and the conduction level of the first clock signal line CK1 is transmitted to the sub-pixel 1 in the first row, so that the sub-pixel 1 in the first row performs data writing; at the second moment of frame a, the second selected The first input terminal 401 and the output terminal 41 of the pass unit 4 are turned on, the first input terminal 401 and the output terminal 41 of the other pass unit 4 are turned off, and the conduction level of the second clock signal line CK2 is transmitted to the second row Pixel 1, so that the sub-pixel 1 in the second row performs data writing; and so on, until the n+mth moment of the ath frame, the first input terminal 401 and the output terminal 41 of the n+mth gating unit 4 are turned on , the first input terminal 401 and the output terminal 41 of the other gating unit 4 are turned off, so that the sub-pixel 1 in the n+mth row performs data writing. In the b-th frame, the first input terminal 401 and the output terminal 41 of the first to nth gate units 4 corresponding to the first display area 11 are sequentially turned on, and the n+1th to nth gate units 4 corresponding to the second display area 12 are The first input terminals 401 and output terminals 41 of the n+m gating units 4 are kept cut off. For example, at the first moment of frame b, the first input terminal 401 and output terminal 41 of the first gating unit 4 are turned on, and the first input terminals 401 and output terminals 41 of other gating units 4 are turned off. The conduction level of the clock signal line CK1 is transmitted to the sub-pixel 1 in the first row, so that the sub-pixel 1 in the first row performs data writing; at the second moment of the b frame, the first input of the second gating unit 4 Terminal 401 and output terminal 41 are turned on, the first input terminal 401 and output terminal 41 of other gating units 4 are turned off, and the conduction level of the second clock signal line CK2 is transmitted to the second row of sub-pixels 1, so that the second row Sub-pixel 1 performs data writing; and so on, until the nth moment of the bth frame, the first input terminal 401 and the output terminal 41 of the nth gating unit 4 are turned on, and the first input terminals of other gating units 4 401 and the output terminal 41 are turned off, and the sub-pixel 1 in the nth row performs data writing; the first input terminal 401 and the output terminal 41 of each gating unit 4 are The data is not written into the sub-pixels 1 in the n+1th to n+mth rows.
可选地，驱动方法用于如图6所示的显示面板，如图7所示，驱动方法包括：导通电平信号线VGH输出持续的导通电平；单位时间T包括第a帧和第b帧，在单位时间T内，在第a帧中，控制每个选通单元4的第一输入端401和输出端41之间导通一次，且在同一时间，最多有一个选通单元4的第一输入端401和输出端41之间导通，在第b帧中，控制部分选通单元4的第一输入端401和输出端41之间导通一次，且在同一时间，最多有一个选通单元4的第一输入端401和输出端41之间导通，控制另一部分选通单元4的第一输入端401和输出端41之间截止。Optionally, the driving method is used for the display panel shown in FIG. 6. As shown in FIG. 7, the driving method includes: the conduction level signal line VGH outputs a continuous conduction level; the unit time T includes the ath frame and In the b-th frame, within the unit time T, in the a-th frame, the conduction between the first input terminal 401 and the output terminal 41 of each gating unit 4 is controlled once, and at the same time, there is at most one gating unit The conduction between the first input terminal 401 and the output terminal 41 of 4, in the b-th frame, the conduction between the first input terminal 401 and the output terminal 41 of the control part of the gating unit 4 is conducted once, and at the same time, at most The conduction between the first input terminal 401 and the output terminal 41 of one gating unit 4 is controlled, and the cutoff between the first input terminal 401 and the output terminal 41 of another part of the gating units 4 is controlled.
具体地，图6中所示的显示面板中，对于选通单元4的控制方法可以与图3中所示的显示面板中对于选通单元4的控制方法相同，区别在于，图4所示的结构由两条时钟信号线提供信号至选通单元4的第一输入端401，而图6中所示的结构由一条导通电平信号线VGH提供信号至选通单元4的第一输入端401。在单位时间T的第a帧和第b帧，导通电平信号线VGH提供持续的导通电平(例如高电平)。部分选通单元4可以为上述第一显示区域11对应的选通单元4，另一部分选通单元4可以为上述第二显示区域12对应的选通单元4，例如，第一显示区域11包括第1至第n行子像素1，第二显示区域12包括第n+1至第n+m行子像素1，第i个移位寄存器5的输出端电连接于第i个选通单元4的第一输入端401，第i个选通单元2的输出端41连接于第i条扫描线2，第i条扫描线2电连接于第i行子像素1，i的取值为1、2、3、…、n+m。部分选通单元4为第1至第n个选通单元4，另一部分选通单元4为第n+1至第n+m个选通单元4。在第a帧中，第一显示区域11和第二显示区域12对应的第1至第n+m个选通单元4的第一输入端401和输出端41依次导通。例如，在第a帧的第1时刻，第1个选通单元4的第一输入端401和输出端41导通，第2至第n+m个选通单元4的第一输入端401和输出端41截止，导通电平信号线VGH的导通电平传输至第1行子像素1，使第1行子像素1进行数据写入；在第a帧的第2时刻，第2个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，导通电平信号线VGH的导通电平传输至第2行子像素1，使第2行子像素1进行数据写入；依次类推，直到第a帧的第n+m时刻，第n+m个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，导通电平信号线VGH的导通电平传输至第n+m行子像素1，使第n+m行子像素1进行数据写入。在第b帧中，第一显示区域11对应的第1至第n个选通单元4的第一输入端401和输出端41依次导通，第二显示区域12对应的第n+1至第n+m个选通单元4的第一输入端401和输出端41保持截止。例如，在第b帧的第1时刻，第1个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，导通电平信号线VGH的导通电平传输至第1行子像素1，使第1行子像素1进行数据写入；在第b帧的第2时刻，第2个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，导通电平信号线VGH的导通电平传输至第2行子像素1，使第2行子像素1进行数据写入；依次类推，直到第b帧的第n时刻，第n个选通单元4的第一输入端401和输出端41导通，其他选通单元4的第一输入端401和输出端41截止，导通电平信号线VGH的导通电平传输至第n行子像素1，使第n行子像素1进行数据写入；在第b帧的第n+1至第n+m时刻，每个选通单元4的第一输入端401和输出端41之间截止，即第n+1至第n+m行子像素1不进行数据写入。Specifically, in the display panel shown in FIG. 6, the control method for the gating unit 4 can be the same as the control method for the gating unit 4 in the display panel shown in FIG. The structure provides signals to the first input terminal 401 of the gating unit 4 by two clock signal lines, while the structure shown in FIG. 6 provides signals to the first input terminal of the gating unit 4 by one conduction level signal line VGH 401. In the a-th frame and the b-th frame of the unit time T, the conduction level signal line VGH provides a continuous conduction level (for example, a high level). Part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned first display area 11, and another part of the gate unit 4 can be the gate unit 4 corresponding to the above-mentioned second display area 12. For example, the first display area 11 includes the first display area 11. 1 to the nth row of sub-pixels 1, the second display area 12 includes the n+1 to n+mth row of sub-pixels 1, the output end of the i-th shift register 5 is electrically connected to the i-th gating unit 4 The first input terminal 401, the output terminal 41 of the i-th gate unit 2 is connected to the i-th scan line 2, the i-th scan line 2 is electrically connected to the i-th row of sub-pixels 1, and the value of i is 1, 2 , 3, ..., n+m. Some of the gating units 4 are the 1st to nth gating units 4 , and the other part of the gating units 4 are the n+1th to n+mth gating units 4 . In frame a, the first input terminals 401 and output terminals 41 of the first to n+m gate units 4 corresponding to the first display area 11 and the second display area 12 are sequentially turned on. For example, at the first moment of frame a, the first input terminal 401 and output terminal 41 of the first gating unit 4 are turned on, and the first input terminals 401 and The output terminal 41 is turned off, and the conduction level of the conduction level signal line VGH is transmitted to the sub-pixel 1 of the first row, so that the sub-pixel 1 of the first row performs data writing; at the second moment of frame a, the second The first input end 401 and output end 41 of the gating unit 4 are turned on, the first input end 401 and the output end 41 of other gating units 4 are turned off, and the conduction level of the conduction level signal line VGH is transmitted to the second row sub-pixel 1, so that the second row sub-pixel 1 performs data writing; and so on, until the n+mth moment of the a-th frame, the first input terminal 401 and the output terminal 41 of the n+mth gating unit 4 turn on, the first input terminal 401 and the output terminal 41 of other gating units 4 are cut off, and the conduction level of the conduction level signal line VGH is transmitted to the sub-pixel 1 in the n+mth row, so that the sub-pixels in the n+mth row Pixel 1 performs data writing. In the b-th frame, the first input terminal 401 and the output terminal 41 of the first to nth gate units 4 corresponding to the first display area 11 are sequentially turned on, and the n+1th to nth gate units 4 corresponding to the second display area 12 are The first input terminals 401 and output terminals 41 of the n+m gating units 4 are kept cut off. For example, at the first moment of frame b, the first input terminal 401 and output terminal 41 of the first gating unit 4 are turned on, and the first input terminals 401 and output terminals 41 of other gating units 4 are turned off and turned on The conduction level of the level signal line VGH is transmitted to the sub-pixel 1 in the first row, so that the sub-pixel 1 in the first row performs data writing; at the second moment of the b frame, the first The input end 401 and the output end 41 are turned on, and the first input end 401 and the output end 41 of other gating units 4 are turned off, and the conduction level of the conduction level signal line VGH is transmitted to the second row of sub-pixels 1, so that the second row of sub-pixels 1 Two rows of sub-pixels 1 perform data writing; and so on, until the nth moment of the bth frame, the first input terminal 401 and the output terminal 41 of the nth gating unit 4 are turned on, and the first input terminal 401 and the output terminal 41 of the other gating units 4 The input terminal 401 and the output terminal 41 are cut off, and the conduction level of the conduction level signal line VGH is transmitted to the sub-pixel 1 in the nth row, so that the subpixel 1 in the nth row can perform data writing; in the n+th row of the b frame From the 1st to the (n+m)th moment, the connection between the first input terminal 401 and the output terminal 41 of each gating unit 4 is cut off, that is, the sub-pixels 1 in the (n+1) to (n+m)th rows do not write data.
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。The above is only a preferred embodiment of the application, and is not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the application should be included in the application. within the scope of protection.
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910801615.7ACN110517633B (en) | 2019-08-28 | 2019-08-28 | Display panel, display device, and driving method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910801615.7ACN110517633B (en) | 2019-08-28 | 2019-08-28 | Display panel, display device, and driving method |
| Publication Number | Publication Date |
|---|---|
| CN110517633Atrue CN110517633A (en) | 2019-11-29 |
| CN110517633B CN110517633B (en) | 2021-08-31 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910801615.7AActiveCN110517633B (en) | 2019-08-28 | 2019-08-28 | Display panel, display device, and driving method |
| Country | Link |
|---|---|
| CN (1) | CN110517633B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564135A (en)* | 2020-06-24 | 2020-08-21 | 厦门天马微电子有限公司 | Display panel driving method, display panel and display device |
| CN113066451A (en)* | 2021-03-26 | 2021-07-02 | 联想(北京)有限公司 | Display control method and display device |
| CN113689825A (en)* | 2021-08-20 | 2021-11-23 | 京东方科技集团股份有限公司 | Driving circuit, driving method and display device |
| CN113851086A (en)* | 2020-06-26 | 2021-12-28 | 三星显示有限公司 | Scan driving circuit and display device including the same |
| CN113870776A (en)* | 2020-06-30 | 2021-12-31 | 三星显示有限公司 | Display device |
| WO2022134207A1 (en)* | 2020-12-21 | 2022-06-30 | 京东方科技集团股份有限公司 | Display panel driving method, display panel, and display device |
| CN114927113A (en)* | 2022-05-31 | 2022-08-19 | 长沙惠科光电有限公司 | Scanning drive circuit and display panel |
| CN115250633A (en)* | 2021-02-26 | 2022-10-28 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
| CN115775547A (en)* | 2022-12-26 | 2023-03-10 | 京东方科技集团股份有限公司 | Display panel, driving method thereof, and display device |
| CN115798414A (en)* | 2022-12-26 | 2023-03-14 | 京东方科技集团股份有限公司 | Gate drive circuit and drive method thereof, panel drive circuit and panel |
| CN117012126A (en)* | 2022-04-27 | 2023-11-07 | 荣耀终端有限公司 | Shifting register, grid driving circuit, display panel and electronic equipment |
| WO2024037465A1 (en)* | 2022-08-19 | 2024-02-22 | 华为技术有限公司 | Display driving chip, display screen and display apparatus |
| WO2024078150A1 (en)* | 2022-10-11 | 2024-04-18 | 荣耀终端有限公司 | Display panel and electronic device |
| WO2024130557A1 (en)* | 2022-12-20 | 2024-06-27 | 京东方科技集团股份有限公司 | Shift register, driving method, gate driving circuit, and display device |
| WO2024250389A1 (en)* | 2023-06-06 | 2024-12-12 | 武汉华星光电半导体显示技术有限公司 | Gate drive module and display panel |
| CN119785712A (en)* | 2025-01-22 | 2025-04-08 | 合肥维信诺科技有限公司 | Display panel and display device |
| US12431058B2 (en) | 2023-04-24 | 2025-09-30 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel, method for display control therefor, and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103218964A (en)* | 2012-01-20 | 2013-07-24 | 刘鸿达 | Driving method and display device using same |
| CN106328081A (en)* | 2016-10-09 | 2017-01-11 | 武汉华星光电技术有限公司 | Flexible display and drive method thereof |
| CN107195269A (en)* | 2017-05-26 | 2017-09-22 | 上海天马有机发光显示技术有限公司 | A kind of driving method of the multi-channel gating switch circuit of display panel, display device and display panel |
| CN107293264A (en)* | 2016-04-04 | 2017-10-24 | 株式会社半导体能源研究所 | Display device, display module and electronic equipment |
| CN107742502A (en)* | 2017-11-30 | 2018-02-27 | 武汉天马微电子有限公司 | Display panel, display method and display device |
| CN109256099A (en)* | 2018-09-30 | 2019-01-22 | 惠科股份有限公司 | Driving circuit and driving method of display panel |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103218964A (en)* | 2012-01-20 | 2013-07-24 | 刘鸿达 | Driving method and display device using same |
| CN107293264A (en)* | 2016-04-04 | 2017-10-24 | 株式会社半导体能源研究所 | Display device, display module and electronic equipment |
| CN106328081A (en)* | 2016-10-09 | 2017-01-11 | 武汉华星光电技术有限公司 | Flexible display and drive method thereof |
| CN107195269A (en)* | 2017-05-26 | 2017-09-22 | 上海天马有机发光显示技术有限公司 | A kind of driving method of the multi-channel gating switch circuit of display panel, display device and display panel |
| CN107742502A (en)* | 2017-11-30 | 2018-02-27 | 武汉天马微电子有限公司 | Display panel, display method and display device |
| CN109256099A (en)* | 2018-09-30 | 2019-01-22 | 惠科股份有限公司 | Driving circuit and driving method of display panel |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564135A (en)* | 2020-06-24 | 2020-08-21 | 厦门天马微电子有限公司 | Display panel driving method, display panel and display device |
| CN113851086A (en)* | 2020-06-26 | 2021-12-28 | 三星显示有限公司 | Scan driving circuit and display device including the same |
| CN113851086B (en)* | 2020-06-26 | 2025-09-12 | 三星显示有限公司 | Scan driving circuit and display device including the same |
| US12277911B2 (en) | 2020-06-26 | 2025-04-15 | Samsung Display Co., Ltd. | Scan driving circuit and display device including the same |
| CN113870776A (en)* | 2020-06-30 | 2021-12-31 | 三星显示有限公司 | Display device |
| US11837149B2 (en) | 2020-12-21 | 2023-12-05 | Boe Technology Group Co., Ltd. | Driving method for display panel, display panel and display apparatus |
| WO2022134207A1 (en)* | 2020-12-21 | 2022-06-30 | 京东方科技集团股份有限公司 | Display panel driving method, display panel, and display device |
| CN115250633A (en)* | 2021-02-26 | 2022-10-28 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
| CN113066451A (en)* | 2021-03-26 | 2021-07-02 | 联想(北京)有限公司 | Display control method and display device |
| CN113689825A (en)* | 2021-08-20 | 2021-11-23 | 京东方科技集团股份有限公司 | Driving circuit, driving method and display device |
| US12236891B2 (en) | 2022-04-27 | 2025-02-25 | Honor Device Co., Ltd. | Shift register for display gate driver with silicon and oxide semiconductor transistors |
| CN117012126A (en)* | 2022-04-27 | 2023-11-07 | 荣耀终端有限公司 | Shifting register, grid driving circuit, display panel and electronic equipment |
| CN114927113B (en)* | 2022-05-31 | 2023-08-04 | 长沙惠科光电有限公司 | Scan driving circuit and display panel |
| CN114927113A (en)* | 2022-05-31 | 2022-08-19 | 长沙惠科光电有限公司 | Scanning drive circuit and display panel |
| WO2024037465A1 (en)* | 2022-08-19 | 2024-02-22 | 华为技术有限公司 | Display driving chip, display screen and display apparatus |
| WO2024078150A1 (en)* | 2022-10-11 | 2024-04-18 | 荣耀终端有限公司 | Display panel and electronic device |
| WO2024130557A1 (en)* | 2022-12-20 | 2024-06-27 | 京东方科技集团股份有限公司 | Shift register, driving method, gate driving circuit, and display device |
| CN115798414A (en)* | 2022-12-26 | 2023-03-14 | 京东方科技集团股份有限公司 | Gate drive circuit and drive method thereof, panel drive circuit and panel |
| CN115775547A (en)* | 2022-12-26 | 2023-03-10 | 京东方科技集团股份有限公司 | Display panel, driving method thereof, and display device |
| US12431058B2 (en) | 2023-04-24 | 2025-09-30 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel, method for display control therefor, and display device |
| WO2024250389A1 (en)* | 2023-06-06 | 2024-12-12 | 武汉华星光电半导体显示技术有限公司 | Gate drive module and display panel |
| US12315458B2 (en) | 2023-06-06 | 2025-05-27 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate drivings module and display panels |
| CN119785712A (en)* | 2025-01-22 | 2025-04-08 | 合肥维信诺科技有限公司 | Display panel and display device |
| Publication number | Publication date |
|---|---|
| CN110517633B (en) | 2021-08-31 |
| Publication | Publication Date | Title |
|---|---|---|
| CN110517633A (en) | Display panel, display device and driving method | |
| CN110517636B (en) | Organic light emitting display panel, display device and driving method | |
| CN106444137B (en) | A display panel, liquid crystal display and driving method thereof | |
| CN110447062B (en) | Driving device and display apparatus | |
| KR101385225B1 (en) | Liquid crystal display and method for driving the same | |
| JP4419369B2 (en) | Liquid crystal display device and driving method thereof | |
| EP3327715B1 (en) | Display device | |
| US20240274051A1 (en) | Display driving method and display device | |
| CN110706653A (en) | Driving circuit, display panel, driving method and display device | |
| JP4501525B2 (en) | Display device and drive control method thereof | |
| KR100561946B1 (en) | LCD and its driving method | |
| US8963912B2 (en) | Display device and display device driving method | |
| KR20080054190A (en) | Display device and driving method thereof | |
| US20090102777A1 (en) | Method for driving liquid crystal display panel with triple gate arrangement | |
| JP2011018020A (en) | Display panel driving method, gate driver and display apparatus | |
| CN101266767A (en) | LCD Monitor | |
| JP2003255915A5 (en) | ||
| CN114743493B (en) | Display panel and display device | |
| US20080180462A1 (en) | Liquid crystal display device and method of driving liquid crystal display device | |
| CN100410997C (en) | Liquid crystal display device | |
| TWI408648B (en) | Field sequential lcd driving method | |
| US7042429B2 (en) | Display device and method of driving same | |
| KR20080049445A (en) | Liquid crystal display device and driving method thereof | |
| CN116434700A (en) | Display panel, driving method thereof, and display device | |
| JP2003271110A (en) | Active matrix display device and driving method thereof |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |