Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a high-reliability printed circuit board suitable for intelligent wearable equipment.
The technical scheme includes that the high-reliability printed circuit board suitable for intelligent wearable equipment is designed and comprises a first power ply, a signal ply, a first grounding ply, a second power ply, a second grounding ply, an electromagnetic shielding ply, an impedance ply and a third grounding ply which are sequentially overlapped from top to bottom, wherein the first power ply is used for installing a CPU chip, a memory chip, a Beidou chip, a GPS chip, a power chip, a WIFI chip, a gravity sensor and a crystal oscillator, the signal ply is used for setting a ground wire of the memory chip and the crystal oscillator and a signal control wire of the CPU chip, the GPS chip, the power chip, the WIFI chip and the gravity sensor, the first grounding ply is used for setting a ground wire of the CPU chip and the memory chip, a signal control wire of the WIFI chip, the GPS chip and the signal control wire of the gravity sensor, the second grounding ply is used for setting a ground wire of the CPU chip and the crystal oscillator, the signal control wire of the Beidou chip, the GPS chip and the power chip, the signal control wire of the GPS chip, the GPS chip and the power chip.
The first power ply board, signal ply board, first earth ply board, second power ply board, second earth ply board, electromagnetic shield ply board, impedance ply board, third earth ply board all offer the through-hole, the through-hole includes about two separately at least, and the wiring between each ply board accessible the through-hole is connected.
The WIFI chip, the Beidou chip, the GPS chip and the gravity sensor adopt power supplies with the same voltage level.
The CPU chip is arranged in the middle of the printed circuit board, and the storage chip, the Beidou chip, the GPS chip, the power chip, the WIFI chip, the gravity sensor and the crystal oscillator surround the CPU chip.
The first power ply board, the signal ply board, the first grounding ply board, the second power ply board, the second grounding ply board, the electromagnetic shielding ply board, the impedance ply board and the third grounding ply board adopt electroless nickel-gold OSP boards.
The thickness of the nickel plating layer of the first power ply, the signal ply, the first grounding ply, the second power ply, the second grounding ply, the electromagnetic shielding ply, the impedance ply and the third grounding ply is larger than 100 mu m, the thickness of the electroless gold plating layer ranges from 0.03 mu m to 1.2 mu m, the thickness of the surface copper layer ranges from 0.5OZ and the thickness of the OSP plating layer ranges from 0.2 mu m to 0.5 mu m.
The first power ply, the signal ply, the first grounding ply, the second power ply, the second grounding ply, the electromagnetic shielding ply, the impedance ply and the third grounding ply all adopt a mounting structure with single-sided placed components.
The intelligent wearable device has the advantages that under the actual demand that the intelligent wearable device is more and more favored by users and has more and more complex functions, the complicated and more components and wirings are placed on the circuit board of the multi-layer board, the wiring planning of the ground wires and the signal control wires is reasonably carried out, the electromagnetic interference among the components is restrained, the performance stability of the components is enhanced, the environment adaptability is improved, better effects are achieved in the aspects of electromagnetic compatibility, dropping, dipping and the like, the reliability and the stability of the product are improved, the intelligent wearable device can integrate more sensors and components, the functions of the intelligent wearable device are increased, the satisfaction degree of the user on the intelligent wearable device is improved, the number of the sensors of the electronic product of the intelligent wearable device is greatly increased by placing the components on 8 layers of single sides, meanwhile, the sensor components of each layer are reasonably arranged, the signal wires and the ground wires are arranged in different adjacent layers, the electromagnetic interference is greatly reduced, the reliability and the stability of the electronic signal are improved, and the intelligent wearable device can be applied to the intelligent wearable device flexibly.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention discloses a high-reliability printed circuit board suitable for intelligent wearable equipment, and aims to solve the problems of few integrated sensors and weak electromagnetic interference resistance caused by the prior art and ensure the reliability, stability and safety of the circuit board.
Referring to the structural schematic diagram of the preferred embodiment of the invention shown in fig. 1, the invention comprises a first power ply 1, a signal ply 2, a first grounding ply 3, a second power ply 4, a second grounding ply 5, an electromagnetic shielding ply 6, an impedance ply 7 and a third grounding ply 8 which are sequentially overlapped from top to bottom, wherein the first power ply 1 is used for installing a CPU chip 9, a memory chip 10, a Beidou chip 11, a GPS chip 12, a power chip 13, a WIFI chip 14, a gravity sensor 18 and a crystal oscillator 19, the signal ply 2 is used for setting the ground wire of the memory chip and the crystal oscillator and the signal control wire of the CPU chip, which is connected with the ground wire of the Beidou chip, the GPS chip, the power chip, the WIFI chip and the ground wire of the gravity sensor, the first grounding ply 3 is used for setting the ground wire of the CPU chip and the power chip, the second grounding ply 4 is used for setting the ground wire of the CPU chip and the memory chip, and the signal control wire of the WIFI chip, the Beidou chip, the GPS chip and the signal control wire of the gravity sensor, the second grounding ply 5 is used for setting the CPU chip and the signal control wire of the WIFI chip, the ground wire of the power chip, the Beidou chip, the GPS chip and the signal control wire of the GPS chip, the ground wire of the GPS chip and the power chip, the signal control wire of the GPS chip and the third grounding ply 8.
Referring to the schematic plan view of the first power plane shown in fig. 2, the plane is provided with the necessary components and other sensors. Referring to the schematic plan view of the signal plane shown in fig. 3, the plane is provided with the ground line of the memory chip and the signal control line of the CPU chip, so that a wider electrical isolation area is provided between the signal control line of the CPU chip and other low-voltage components. Referring to the schematic plan view of the first ground plane shown in fig. 4, the plane is provided with a power chip and a memory chip ground line, no other signal control lines are placed, the area of the high frequency ac loop is reduced, and the analog signal layer and the digital ground layer are not overlapped. Referring to the plan schematic diagram of the second power ply shown in fig. 5, the ply is provided with the ground wires of the CPU chip and the memory chip, and the signal control wires of the WIFI chip, the Beidou chip, the GPS chip and the gravity sensor, and the components with the same power grade and the same type are put together as much as possible, so that for the layout of the multi-layer PCB, the components with different power and ground types are reasonably arranged for use, great convenience is brought to the segmentation of the inner electric layer, and the anti-interference capability among the components can be effectively improved. Referring to the schematic plan view of the second grounding layer board shown in fig. 6, the layer board is provided with the CPU chip and the ground wire of the crystal oscillator, and the ground wire and the signal wire are alternately distributed, so that the signal layer is prevented from being close to the ground wire, and the signal isolation is poor. Referring to the schematic plan view of the electromagnetic shielding laminate shown in fig. 7, the laminate is provided with the ground wire of the CPU chip, and the signal control wires of the power chip, the GPS chip, the beidou chip and the WIFI chip, each signal layer is directly adjacent to the inner electric layer, is effectively isolated from other signal layers, and is not easy to generate crosstalk. The interference of the outside on the signal layer can be effectively shielded. Referring to the schematic plan view of the impedance laminate shown in fig. 8, the laminate is provided with a CPU chip, a memory chip, a beidou chip, a GPS chip, a power chip, a WIFI chip, and a power line of a gravity sensor, so that the ground line protection of the laminate and the third grounding laminate are tightly coupled, and the interference of the printed conductors mainly includes the interference introduced between the conductors and the interference introduced by the power line, so that the interference sources can be effectively reduced by reasonably arranging and arranging the wiring and grounding modes. Referring to the schematic plan view of the third ground plane shown in fig. 9, the plane has a large block of protective ground lines, which can effectively reduce interference.
In the preferred embodiment, the first power board 1, the signal board 2, the first grounding board 3, the second power board 4, the second grounding board 5, the electromagnetic shielding board 6, the impedance board 7 and the third grounding board 8 are all provided with through holes 16, and the through holes at least comprise two left and right separated boards, and the connecting lines between the boards can be connected through the through holes.
In a preferred embodiment, the WIFI chip, the beidou chip, the GPS chip and the gravity sensor adopt power sources with the same voltage level. The CPU chip 9 is arranged in the middle of the printed circuit board, and the storage chip 10, the Beidou chip 11, the GPS chip 12, the power chip 13, the WIFI chip 14, the gravity sensor and the crystal oscillator are arranged around the CPU chip, so that the total length of various circuits is reduced.
In the invention, the first power ply 1, the signal ply 2, the first grounding ply 3, the second power ply 4, the second grounding ply 5, the electromagnetic shielding ply 6, the impedance ply 7 and the third grounding ply 8 are made of electroless nickel-gold OSP. The total design of 8 layers is that the finished product is a connecting piece, the thickness of the whole plate is 1.0mm plus or minus 10%, all BGA pads must adopt OSP technology, and the connecting rib must use stamp hole mode.
In a preferred embodiment, the thicknesses of the nickel plating layers of the first power ply 1, the signal ply 2, the first grounding ply 3, the second power ply 4, the second grounding ply 5, the electromagnetic shielding ply 6, the impedance ply 7 and the third grounding ply 8 are greater than 100 μm (standard), the thickness of the electroless gold plating layer is in the range of 0.03 μm to 1.2 μm, the thinnest part is not less than 0.03 μm, the thicknesses of the hole copper are respectively greater than 0.7mil, the copper filling process is required to be an electroplating filling process for blind holes on 0.4mmPITCH BGA, the thickness of the surface copper is 0.5oz, and the thickness of the osp plating layer is in the range of 0.2 to 0.5 μm (standard). The OZ is the length unit of the PCB industry, and 1OZ means that the average copper foil weight per unit area is 28.35g, and the average thickness of the copper foil is expressed as the weight per unit area.
The first power ply 1, the signal ply 2, the first grounding ply 3, the second power ply 4, the second grounding ply 5, the electromagnetic shielding ply 6, the impedance ply 7 and the third grounding ply 8 all adopt a mounting structure with single-sided placed components.
In the preferred embodiment, the mechanical aperture minimum of the circuit board is 10mil and the laser aperture minimum is 4mil. The minimum line width/line distance of the outer layer of the circuit board is 4/4mil, the line width/line distance of a finished product is +/-20% according to Gerber, mark points are circular with the diameter of 1mm, UL MARK adopts a character face mode S face, DATE CODE adopts a character face mode S face, and a board factory material number adopts a character face mode S face. The solder resist layer of the circuit board is 5-30 um higher than the copper on the surface (particularly, the solder resist layer is guaranteed to be free of copper leakage and yellowing), the hole plugging mode is full hole plugging, the tolerance of the solder resist layer is +/-0.03 mm according to GERBER, copper leakage of wires cannot occur, black oil bridges with the interval between two PADs being smaller than 7.5mil cannot be deleted, and PAD on green oil is allowed to be 1mil. The circuit board silk-screen layer type is double-sided, and the color is white (Standard), and partial characters on the PAD can be slightly shifted or deleted, but the element positioning outer frame silk-screen can not be shifted. The circuit board is formed by CNC, the tolerance of BGA bonding pads is + -10% (the diameter is more than or equal to 0.3 mm), + -15% (the diameter is less than 0.3 mm), the minimum diameter of BGA bonding pads is not less than 0.22mm, all BGA bonding pads are required to be plugged by OSP technology, all VIAs are plugged and covered with green oil (single-side windowed plug holes from un-windowed surfaces, double-side un-windowed double-side plug holes, double-side windowed VIA non-plug holes), tear drops are required to be added to lead wires on the surface of the BGA, the appearance tolerance is + -0.1 mm (Standard), and the board bending/board warping is 0.7% (Standard). The external dimension single plate (tolerance) ± 0.1mm and the connecting plate (tolerance) ± 0.1mm. The circuit board requires an impedance match of 50 ohms (six plates ± 10% error, four plates ± 15%). The circuit board is fabricated according to R0.5MM without internal corners and with internal corners smaller than R0.5MM, and other unlisted items refer to IPC-6012CLS2 specifications. The test method is based on the standard IPC (TM) 650, the reference electrical connection resistance 20Ω@5V and the insulation resistance 10MΩ@100deg.V.
According to the technical scheme, the number of the sensors of the electronic product of the intelligent wearable device is greatly increased by placing the components on one side of 8 layers, the sensor components of each layer of plate are reasonably distributed, and the signal lines and the ground lines are distributed adjacently through different layers, so that electromagnetic interference is greatly reduced, accuracy, reliability and stability of electronic signals are improved, and the electronic product can be flexibly applied to the electronic product of the intelligent wearable device.
The above examples are illustrative only and are not intended to be limiting. Any equivalent modifications or variations to the present application without departing from the spirit and scope of the present application are intended to be included in the scope of the following claims.