技术领域technical field
本发明涉及半导体集成电路设计，属于分类号H01L23/00下，具体为一种集成MIM电容器及其制造方法。The invention relates to the design of semiconductor integrated circuits, belongs to the classification number H01L23/00, and is specifically an integrated MIM capacitor and a manufacturing method thereof.
背景技术Background technique
电容器的应用在集成电路设计中始终是一个杠杆，设计者希望使用电容值尽量大的电容器，但大电容值往往带来的就是增大芯片面积，提高制造成本。如何提高单位芯片面积上的电容值（即电容密度），始终是集成电路领域的一个挑战。The application of capacitors is always a lever in integrated circuit design. Designers hope to use capacitors with as large a capacitance as possible, but large capacitances often lead to increased chip area and increased manufacturing costs. How to increase the capacitance value per unit chip area (that is, capacitance density) has always been a challenge in the field of integrated circuits.
现有的电容器，大致可以分为前道电容器和后道电容器，前道电容器例如MOS电容器、PN结电容器，后道电容器例如MIM（金属层-绝缘层-金属层）电容器、MOM（金属层-氧化层-金属层）电容器。其中，MIM电容器可以提供较好的频率以及温度相关特性，并且可形成于层间金属以及铜互连制程，降低与CMOS前端工艺整合的困难度及复杂度，因而被广泛用于各种集成电路例如模拟-逻辑、模拟-数字、混合信号以及射频电路中。Existing capacitors can be roughly divided into front-end capacitors and back-end capacitors, front-end capacitors such as MOS capacitors, PN junction capacitors, back-end capacitors such as MIM (metal layer-insulation layer-metal layer) capacitors, MOM (metal layer- oxide layer - metal layer) capacitor. Among them, MIM capacitors can provide better frequency and temperature-related characteristics, and can be formed in interlayer metal and copper interconnection processes, reducing the difficulty and complexity of integration with CMOS front-end processes, so they are widely used in various integrated circuits Examples include analog-logic, analog-digital, mixed-signal, and radio-frequency circuits.
现有的MIM电容器通常为平面结构，包括电容下极板、电容介质层以及电容上极板，形成两层金属电极之间夹着绝缘介质层的三明治结构。对于平面结构的MIM电容器，其电容密度最多可以达到4-6fF/μm2，而在实际应用中，仍然远远无法满足LCD驱动电路、RFCMOS电路等大电容集成电路的需求。因此，垂直型电容器是现在常用的增加电容方式的电容器，其多为增大极板正对面积的方式实现增加电容值。但是其多为单面引出电极，对于叠层封装体而言，该种单面电极引出是不利于互连的。Existing MIM capacitors usually have a planar structure, including a capacitor lower plate, a capacitor dielectric layer, and a capacitor upper plate, forming a sandwich structure with an insulating dielectric layer sandwiched between two layers of metal electrodes. For MIM capacitors with a planar structure, the capacitance density can reach up to 4-6fF/μm2, but in practical applications, it is still far from meeting the needs of large-capacitance integrated circuits such as LCD driver circuits and RFCMOS circuits. Therefore, the vertical type capacitor is a capacitor that is commonly used to increase capacitance, and most of them increase the capacitance value by increasing the area facing the plate. However, most of them lead out electrodes on one side, and for a stacked package, this kind of single-side electrode lead-out is not conducive to interconnection.
发明内容Contents of the invention
基于解决上述问题，本发明提供了一种集成MIM电容器的制造方法，包括如下步骤：Based on solving the above problems, the invention provides a method for manufacturing an integrated MIM capacitor, comprising the steps of:
（1）提供一半导体衬底，具有相对的正面和背面，所述衬底的正面上的第一区域具有可背金属化晶体管器件，且在所述正面上具有表面电极；(1) providing a semiconductor substrate having opposing front and back surfaces, a first region on the front surface of the substrate having back-metallizable transistor devices, and a surface electrode on the front surface;
（2）在所述衬底的正面上的第二区域形成沟槽，所述沟槽未贯穿所述背面，且所述沟槽的深度与所述晶体管器件延伸的深度相同；(2) forming a trench in a second region on the front side of the substrate, the trench not penetrating the back side, and having the same depth as the transistor device extends;
（3）在所述沟槽内填充第一介质层，所述第一介质层与所述正面齐平；(3) Filling the trench with a first dielectric layer, the first dielectric layer being flush with the front surface;
（4）在所述正面上形成多层第二介质层、在所述多层第二介质层内的连接所述表面电极的布线层以及在所述多层第二介质层内的正对所述第一介质层的垂直分布的多个第一金属柱；(4) Forming a multi-layer second dielectric layer on the front surface, a wiring layer connecting the surface electrodes in the multi-layer second dielectric layer, and a wiring layer in the multi-layer second dielectric layer facing all A plurality of vertically distributed first metal columns of the first dielectric layer;
（5）在所述多层第二介质层上形成上极板，所述上极板与所述多个第一金属柱附连；(5) forming an upper pole plate on the multi-layer second dielectric layer, and the upper pole plate is attached to the plurality of first metal pillars;
（6）在所述上极板上覆盖第三介质层；(6) Covering the upper plate with a third dielectric layer;
（7）研磨所述衬底的背面，露出所述第一介质层和晶体管器件；(7) Grinding the back side of the substrate to expose the first dielectric layer and transistor devices;
（8）通过刻蚀工艺除去所述第一介质层以及与所述第一介质层相对的所述多层第二介质层，形成开口，所述开口使得所述多个第一金属柱悬空；(8) removing the first dielectric layer and the multi-layer second dielectric layer opposite to the first dielectric layer through an etching process to form an opening, and the opening makes the plurality of first metal pillars suspended;
（9）在所述开口内填充高k材料以形成高k材料层，完全覆盖所述多个第一金属柱；(9) filling the opening with a high-k material to form a high-k material layer, completely covering the plurality of first metal pillars;
（10）在所述高k材料层中钻蚀多个通孔并填充金属材料，形成与所述第一金属柱间隔排列的多个第二金属柱，所述多个第一金属柱与所述多个第二金属柱呈叉指状排布；(10) Drilling a plurality of through holes in the high-k material layer and filling them with metal materials to form a plurality of second metal pillars spaced apart from the first metal pillars, and the plurality of first metal pillars and the first metal pillars are spaced apart from each other. The plurality of second metal pillars are arranged in an interdigitated shape;
（11）形成下极板，所述下极板与所述多个第二金属柱附连。(11) forming a lower pole plate, and the lower pole plate is attached to the plurality of second metal pillars.
根据本发明的实施例，还包括步骤（12）：在所述下极板和晶体管器件的背面处形成背面金属以引出背面电极。According to an embodiment of the present invention, the step (12) is further included: forming a backside metal on the backside of the lower plate and the transistor device to lead out a backside electrode.
根据本发明的实施例，所述步骤（8）中的蚀刻工艺采用各项异性蚀刻溶液实现。According to an embodiment of the present invention, the etching process in the step (8) is realized by using an anisotropic etching solution.
根据本发明的实施例，所述步骤（4）中的形成多个第一金属柱具体包括以下步骤：在所述正面形成第一层第二介质层，在所述第一层第二介质层上形成第二层第二介质层，利用光刻胶对所述第二层第二介质层进行开口，并填充金属，形成第一金属块，然后在第二层介质层上形成第三层第二介质层，同样利用光刻胶对所述第三层第二介质层进行开口，形成第二金属块，第一金属块和第二金属块上下对齐互连；重复上述形成第二介质层、形成开口以及形成金属块的步骤，上下互连的多个金属块共同组成单个的第一金属柱。According to an embodiment of the present invention, forming a plurality of first metal pillars in the step (4) specifically includes the following steps: forming a first layer of a second dielectric layer on the front surface, and forming a second dielectric layer on the first layer Form the second layer of the second dielectric layer on the second layer of the second dielectric layer, use photoresist to open the second layer of the second dielectric layer, and fill it with metal to form the first metal block, and then form the third layer of the second dielectric layer on the second layer of dielectric layer For the second dielectric layer, open the second dielectric layer of the third layer by using photoresist to form a second metal block, and the first metal block and the second metal block are aligned and interconnected up and down; repeat the above to form the second dielectric layer, In the step of forming an opening and forming a metal block, a plurality of metal blocks interconnected up and down together form a single first metal column.
根据本发明的实施例，所述第一介质层、多层第二介质层以及第三介质层均为低k材料，优选为氧化硅。According to an embodiment of the present invention, the first dielectric layer, the multiple second dielectric layers and the third dielectric layer are all low-k materials, preferably silicon oxide.
本发明提供了由上述方法制备而得到的一种集成MIM电容器，包括：The present invention provides an integrated MIM capacitor prepared by the above method, comprising:
一半导体衬底，其具有相对的正面和背面，所述衬底的正面上的第一区域具有可背金属化晶体管器件，且在所述正面上具有表面电极，所述晶体管器件从所述背面露出；A semiconductor substrate having opposing front and back sides, a first region on the front side of the substrate having back-metallizable transistor devices, and having surface electrodes on the front side, the transistor devices being removed from the back side exposed;
层间介电层，设置于所述正面上，在所述多层第二介质层内的连接所述表面电极的布线层；an interlayer dielectric layer disposed on the front surface, a wiring layer connected to the surface electrodes in the multi-layer second dielectric layer;
MIM电容器，嵌入在所述层间介电层内，且包括上极板、第一金属柱、下极板、第二金属柱和高k材料层；所述上极板与所述多个第一金属柱附连，所述下极板与所述多个第二金属柱附连；所述多个第一金属柱与所述第二金属柱交替间隔排列且呈叉指状排布，所述高k材料层位于所述上极板和下极板之间且填充于所述多个第一金属柱和多个第二金属柱之间；所述上极板嵌在所述层间介电层中，所述下极板嵌在所述衬底中，且所述下极板的一面从所述衬底的背面露出。The MIM capacitor is embedded in the interlayer dielectric layer, and includes an upper plate, a first metal post, a lower plate, a second metal post, and a high-k material layer; the upper plate is connected to the plurality of first metal posts A metal column is attached, and the lower plate is attached to the plurality of second metal columns; the plurality of first metal columns and the second metal columns are alternately arranged at intervals and interdigitated, so The high-k material layer is located between the upper pole plate and the lower pole plate and is filled between the plurality of first metal pillars and the plurality of second metal pillars; the upper pole plate is embedded in the interlayer interlayer In the electrical layer, the lower plate is embedded in the substrate, and one side of the lower plate is exposed from the back of the substrate.
根据本发明的实施例，还包括在所述下极板和晶体管器件的背面处的背面电极。According to an embodiment of the present invention, a back electrode at the back of the lower plate and the transistor device is further included.
根据本发明的实施例，所述下极板的厚度与所述衬底的厚度相同。According to an embodiment of the present invention, the thickness of the lower plate is the same as that of the substrate.
根据本发明的实施例，所述层间介电层为低k材料，优选为氧化硅。According to an embodiment of the present invention, the interlayer dielectric layer is a low-k material, preferably silicon oxide.
根据本发明的实施例，所述高k材料层包括氧化铝、氧化镧、氮化硅、氧化锶、五氧化二钽或二氧化锆。According to an embodiment of the present invention, the high-k material layer includes aluminum oxide, lanthanum oxide, silicon nitride, strontium oxide, tantalum pentoxide, or zirconium dioxide.
本发明的优点如下：（1）在衬底开槽填充的方式形成下极板，任何进行刻蚀填充高k材料，可以实现电容值的增大，且得到了Q值较高的垂直型MIM电容器结构；（2）本发明还同时实现了集成电路和MIM电容器的背金工艺，实现了双面电极的引出，便于后续封装。The advantages of the present invention are as follows: (1) The lower plate is formed by slotting and filling the substrate, and any high-k material is etched and filled, which can increase the capacitance value and obtain a vertical MIM with a higher Q value Capacitor structure; (2) The invention also realizes the back gold process of the integrated circuit and the MIM capacitor at the same time, realizes the lead-out of double-sided electrodes, and facilitates subsequent packaging.
附图说明Description of drawings
图1-12为本发明的集成MIM电容器的制造方法的示意图；Fig. 1-12 is the schematic diagram of the manufacturing method of integrated MIM capacitor of the present invention;
图13为本发明形成第一金属柱的示意图。FIG. 13 is a schematic diagram of forming a first metal pillar according to the present invention.
具体实施方式Detailed ways
本发明的目的在于提供一种具有MIM电容器的一体化背金方式。The purpose of the present invention is to provide an integrated gold backing method with MIM capacitors.
参加图1-12，本发明的集成MIM电容器的制造方法，包括如下步骤：Refer to Fig. 1-12, the manufacturing method of integrated MIM capacitor of the present invention, comprises the steps:
（1）提供一半导体衬底1，具有相对的正面和背面，所述衬底1的正面上的第一区域具有可背金属化晶体管器件2，且在所述正面上具有表面电极3；衬底1是通常是但是不限于硅衬底。在其它实施例中，衬底1可包括诸如锗的另外的元素半导体；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体或它们的组合。在实施例中，衬底103是绝缘体上半导体(SOI)。(1) Provide a semiconductor substrate 1 with opposite front and back sides, the first region on the front side of the substrate 1 has a back-metallizable transistor device 2, and has a surface electrode 3 on the front side; Substrate 1 is typically but not limited to a silicon substrate. In other embodiments, the substrate 1 may include another elemental semiconductor such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; including SiGe , GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP alloy semiconductors or combinations thereof. In an embodiment, the substrate 103 is a semiconductor on insulator (SOI).
（2）在所述衬底1的正面上的第二区域形成沟槽4，所述沟槽4未贯穿所述背面，且所述沟槽4的深度与所述晶体管器件2延伸的深度相同；(2) A trench 4 is formed in the second region on the front side of the substrate 1 , the trench 4 does not penetrate the back side, and the depth of the trench 4 is the same as the depth of the extension of the transistor device 2 ;
（3）在所述沟槽4内填充第一介质层5，所述第一介质层5与所述正面齐平；(3) filling the first dielectric layer 5 in the groove 4, the first dielectric layer 5 being flush with the front surface;
（4）在所述正面上形成多层第二介质层8、在所述多层第二介质层8内的连接所述表面电极3的布线层6以及在所述多层第二介质层8内的正对所述第一介质层5的垂直分布的多个第一金属柱7；(4) Form a multi-layer second dielectric layer 8 on the front surface, a wiring layer 6 connected to the surface electrode 3 in the multi-layer second dielectric layer 8 and a multi-layer second dielectric layer 8 in the multi-layer second dielectric layer 8 A plurality of vertically distributed first metal pillars 7 facing the first dielectric layer 5;
（5）在所述多层第二介质层8上形成上极板9，所述上极板9与所述多个第一金属柱7附连；(5) forming an upper pole plate 9 on the multi-layer second dielectric layer 8, and the upper pole plate 9 is attached to the plurality of first metal pillars 7;
（6）在所述上极板9上覆盖第三介质层10；(6) Covering the third dielectric layer 10 on the upper plate 9;
（7）研磨所述衬底的背面，露出所述第一介质层5和晶体管器件2；(7) Grinding the back side of the substrate to expose the first dielectric layer 5 and the transistor device 2;
（8）通过刻蚀工艺除去所述第一介质层5以及与所述第一介质层5相对的所述多层第二介质层8，形成开口11，所述开口11使得所述多个第一金属柱7悬空；(8) Removing the first dielectric layer 5 and the multiple second dielectric layers 8 opposite to the first dielectric layer 5 through an etching process to form openings 11 , and the openings 11 make the plurality of second dielectric layers A metal column 7 is suspended in the air;
（9）在所述开口11内填充高k材料以形成高k材料层12，完全覆盖所述多个第一金属柱7；(9) Filling the opening 11 with a high-k material to form a high-k material layer 12 to completely cover the plurality of first metal pillars 7 ;
（10）在所述高k材料层12中钻蚀多个通孔并填充金属材料，形成与所述第一金属柱7间隔排列的多个第二金属柱13，所述多个第一金属柱7与所述多个第二金属柱13呈叉指状排布；(10) Drilling a plurality of through holes in the high-k material layer 12 and filling them with metal materials to form a plurality of second metal pillars 13 spaced apart from the first metal pillars 7 , and the plurality of first metal pillars 7 The pillars 7 and the plurality of second metal pillars 13 are arranged in an interdigitated shape;
（11）形成下极板14，所述下极板14与所述多个第二金属柱13附连。(11) Forming the lower pole plate 14 , the lower pole plate 14 is attached to the plurality of second metal pillars 13 .
（12）在所述下极板14和晶体管器件2的背面处形成背面金属以引出背面电极15、16。(12) Forming back metal on the back of the lower plate 14 and the transistor device 2 to lead out the back electrodes 15 and 16 .
其中，所述步骤（8）中的蚀刻工艺采用各项异性蚀刻溶液实现。使用各种活性气体或湿蚀刻剂蚀刻掉每个介电层。例如，氢氟酸(HF)可以用于蚀刻掉氧化硅介电层。Wherein, the etching process in the step (8) is realized by using an anisotropic etching solution. Each dielectric layer is etched away using various reactive gases or wet etchants. For example, hydrofluoric acid (HF) may be used to etch away the silicon oxide dielectric layer.
多个第一金属柱7可以是任何合适的金属、金属合金或者金属堆叠件，包括但不限于W、Al和Cu的一种或多种。例如，参照图13，所述步骤（4）中的形成多个第一金属柱7具体包括以下步骤：在所述正面形成第一层第二介质层81，在所述第一层第二介质层81上形成第二层第二介质层82，利用光刻胶对所述第二层第二介质层82进行开口，并填充金属，形成第一金属块71，然后在第二层介质层82上形成第三层第二介质层83，同样利用光刻胶对所述第三层第二介质层进行开口，形成第二金属块72，第一金属块71和第二金属块72上下对齐互连；重复上述形成第二介质层、形成开口以及形成金属块的步骤，上下互连的多个金属块共同组成单个的第一金属柱7。The plurality of first metal pillars 7 may be any suitable metal, metal alloy or metal stack, including but not limited to one or more of W, Al and Cu. For example, referring to FIG. 13 , forming a plurality of first metal pillars 7 in the step (4) specifically includes the following steps: forming a first layer of second dielectric layer 81 on the front surface, and forming a first layer of second dielectric layer 81 on the first layer of second dielectric Form the second layer of the second dielectric layer 82 on the layer 81, use photoresist to open the second layer of the second dielectric layer 82, and fill it with metal to form the first metal block 71, and then in the second layer of dielectric layer 82 A third layer of second dielectric layer 83 is formed on it, and a photoresist is also used to open the third layer of second dielectric layer to form a second metal block 72. The first metal block 71 and the second metal block 72 are aligned up and down with each other. Connecting; repeating the above steps of forming the second dielectric layer, forming the opening and forming the metal block, a plurality of metal blocks interconnected up and down together form a single first metal column 7 .
根据本发明的实施例，所述第一介质层5、多层第二介质层8以及第三介质层10均为低k材料，优选为氧化硅。According to an embodiment of the present invention, the first dielectric layer 5 , the multi-layered second dielectric layer 8 and the third dielectric layer 10 are all low-k materials, preferably silicon oxide.
本发明提供了由上述方法制备而得到的一种集成MIM电容器，包括：The present invention provides an integrated MIM capacitor prepared by the above method, comprising:
一半导体衬底，其具有相对的正面和背面，所述衬底的正面上的第一区域具有可背金属化晶体管器件，且在所述正面上具有表面电极，所述晶体管器件从所述背面露出；A semiconductor substrate having opposing front and back sides, a first region on the front side of the substrate having back-metallizable transistor devices, and having surface electrodes on the front side, the transistor devices being removed from the back side exposed;
层间介电层，设置于所述正面上，在所述多层第二介质层内的连接所述表面电极的布线层；an interlayer dielectric layer disposed on the front surface, a wiring layer connected to the surface electrodes in the multi-layer second dielectric layer;
MIM电容器，嵌入在所述层间介电层内，且包括上极板、第一金属柱、下极板、第二金属柱和高k材料层；所述上极板与所述多个第一金属柱附连，所述下极板与所述多个第二金属柱附连；所述多个第一金属柱与所述第二金属柱交替间隔排列且呈叉指状排布，所述高k材料层位于所述上极板和下极板之间且填充于所述多个第一金属柱和多个第二金属柱之间；所述上极板嵌在所述层间介电层中，所述下极板嵌在所述衬底中，且所述下极板的一面从所述衬底的背面露出。The MIM capacitor is embedded in the interlayer dielectric layer, and includes an upper plate, a first metal post, a lower plate, a second metal post, and a high-k material layer; the upper plate is connected to the plurality of first metal posts A metal column is attached, and the lower plate is attached to the plurality of second metal columns; the plurality of first metal columns and the second metal columns are alternately arranged at intervals and interdigitated, so The high-k material layer is located between the upper pole plate and the lower pole plate and is filled between the plurality of first metal pillars and the plurality of second metal pillars; the upper pole plate is embedded in the interlayer interlayer In the electrical layer, the lower plate is embedded in the substrate, and one side of the lower plate is exposed from the back of the substrate.
此外，还包括在所述下极板和晶体管器件的背面处的背面电极。所述下极板的厚度与所述衬底的厚度相同。所述层间介电层为低k材料，优选为氧化硅。所述高k材料层包括氧化铝、氧化镧、氮化硅、氧化锶、五氧化二钽或二氧化锆。Additionally, a back electrode at the back of the lower plate and transistor device is included. The thickness of the lower plate is the same as that of the substrate. The interlayer dielectric layer is a low-k material, preferably silicon oxide. The high-k material layer includes aluminum oxide, lanthanum oxide, silicon nitride, strontium oxide, tantalum pentoxide or zirconium dioxide.
最后应说明的是：显然，上述实施例仅仅是为清楚地说明本发明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。Finally, it should be noted that: obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, rather than limiting the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. However, obvious changes or modifications derived therefrom are still within the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910622867.3ACN110416191A (en) | 2019-07-11 | 2019-07-11 | A kind of integrated MIM capacitor and its manufacturing method |
| Application Number | Priority Date | Filing Date | Title |
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| CN201910622867.3ACN110416191A (en) | 2019-07-11 | 2019-07-11 | A kind of integrated MIM capacitor and its manufacturing method |
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| CN110416191Atrue CN110416191A (en) | 2019-11-05 |
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| CN201910622867.3AWithdrawnCN110416191A (en) | 2019-07-11 | 2019-07-11 | A kind of integrated MIM capacitor and its manufacturing method |
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