技术领域technical field
本公开文件涉及一种显示装置与栅极驱动器，特别涉及一种可防止像素漏电的显示装置。The disclosure document relates to a display device and a gate driver, in particular to a display device capable of preventing pixel leakage.
背景技术Background technique
当目前主流的移动装置持续显示静止画面(例如，持续显示其中一个桌面分页)时，移动装置的显示装置会暂时停止更新显示画面以降低功率消耗。然而，当显示装置停止更新显示画面时，由于数据线具有低电压，像素电路与数据线之间会产生漏电流。此时，像素电路所显示的灰阶亮度会因为漏电流而逐渐改变，使得显示画面产生人眼可察觉的闪烁。When a current mainstream mobile device continues to display a static image (for example, continuously displays one of the desktop pages), the display device of the mobile device will temporarily stop updating the display image to reduce power consumption. However, when the display device stops updating the display image, due to the low voltage of the data line, a leakage current will be generated between the pixel circuit and the data line. At this time, the brightness of the gray scale displayed by the pixel circuit will gradually change due to the leakage current, so that the display screen will produce flicker that can be detected by human eyes.
发明内容Contents of the invention
本公开文件提供一种显示装置，显示装置包含多个纵向驱动线，且另包含多个切换电路与多个移位暂存器。多个切换电路对应耦接于多个纵向驱动线，用于接收至少一控制信号。多个移位暂存器包含末级移位暂存器，其中末级移位暂存器用于输出至少一控制信号。多个切换电路用于依据至少一控制信号，于第一时段中将多个纵向驱动线中的第一部分纵向驱动线设置为具有第一电压准位(电平)，将多个纵向驱动线中的第二部分纵向驱动线设置为具有第二电压准位，并且于第二时段中将第二部分纵向驱动线设置为具有第一电压准位，将第一部分纵向驱动线设置为具有第二电压准位。The disclosure document provides a display device. The display device includes a plurality of vertical driving lines, and further includes a plurality of switching circuits and a plurality of shift registers. The plurality of switching circuits are correspondingly coupled to the plurality of vertical driving lines for receiving at least one control signal. The plurality of shift registers includes a final stage shift register, wherein the final stage shift register is used to output at least one control signal. The plurality of switching circuits are used to set a first part of the plurality of vertical driving lines to have a first voltage level (level) in the first period according to at least one control signal, and set the plurality of vertical driving lines to have a first voltage level (level). The second part of the vertical driving lines is set to have the second voltage level, and in the second period, the second part of the vertical driving lines is set to have the first voltage level, and the first part of the vertical driving lines is set to have the second voltage quasi-position.
本公开文件另提供一种栅极驱动器，栅极驱动器适用于显示装置，其中显示装置包含多个纵向驱动线，栅极驱动器包含多个移位暂存器。多个移位暂存器包含末级移位暂存器，其中末级移位暂存器用于输出第一控制信号群组至多个切换电路，且多个切换电路对应耦接于多个纵向驱动线。多个切换电路用于依据第一控制信号群组，于第一时段中将多个纵向驱动线中的第一部分纵向驱动线设置为具有第一电压准位，将多个纵向驱动线中的第二部分纵向驱动线设置为具有第二电压准位，并且于第二时段中将第二部分纵向驱动线设置为具有第一电压准位，将第一部分纵向驱动线设置为具有第二电压准位。The disclosure further provides a gate driver, which is suitable for a display device, wherein the display device includes a plurality of vertical driving lines, and the gate driver includes a plurality of shift registers. The plurality of shift registers includes a final stage shift register, wherein the final stage shift register is used to output the first control signal group to a plurality of switching circuits, and the plurality of switching circuits are correspondingly coupled to a plurality of vertical drivers Wire. The plurality of switching circuits are used to set a first part of the plurality of vertical driving lines to have a first voltage level in a first period according to a first control signal group, and set a first part of the plurality of vertical driving lines to have a first voltage level. Two parts of the vertical driving lines are set to have the second voltage level, and in the second period, the second part of the vertical driving lines is set to have the first voltage level, and the first part of the vertical driving lines is set to have the second voltage level .
上述的显示装置与栅极驱动器能防止像素电路与垂直驱动线之间产生漏电流。The above display device and gate driver can prevent leakage current between the pixel circuit and the vertical driving line.
附图说明Description of drawings
为让公开文件的上述和其他目的、特征、优点与实施例能更明显易懂，说明书附图的说明如下：In order to make the above and other purposes, features, advantages and embodiments of the public document more obvious and understandable, the description of the attached drawings is as follows:
图1为根据本公开文件一实施例的显示装置简化后的功能方框图。FIG. 1 is a simplified functional block diagram of a display device according to an embodiment of the disclosure.
图2为依据本公开文件一实施例的栅极驱动器简化后的功能方框图。FIG. 2 is a simplified functional block diagram of a gate driver according to an embodiment of the disclosure.
图3为依据本公开文件一实施例的多个切换电路的电路示意图。FIG. 3 is a schematic circuit diagram of a plurality of switching circuits according to an embodiment of the disclosure.
图4为依据本公开文件一实施例的显示装置的运行方式示意图。FIG. 4 is a schematic diagram of an operation mode of a display device according to an embodiment of the disclosure.
图5为依据本公开文件一实施例的移位暂存器简化后的电路图。FIG. 5 is a simplified circuit diagram of a shift register according to an embodiment of the disclosure.
图6为依据本公开文件一实施例的第一级移位暂存器简化后的电路图。FIG. 6 is a simplified circuit diagram of a first-stage shift register according to an embodiment of the disclosure.
图7为依据本公开文件另一实施例的栅极驱动器简化后的功能方框图。FIG. 7 is a simplified functional block diagram of a gate driver according to another embodiment of the disclosure.
图8为依据本公开文件另一实施例的防漏电电路的电路示意图。FIG. 8 is a schematic circuit diagram of an anti-leakage circuit according to another embodiment of the disclosure.
图9为依据本公开文件另一实施例的显示装置的运行方式示意图。FIG. 9 is a schematic diagram of an operation mode of a display device according to another embodiment of the disclosure.
图10为依据本公开文件一实施例的末级移位暂存器简化后的电路图。FIG. 10 is a simplified circuit diagram of a final stage shift register according to an embodiment of the disclosure.
图11为依据本公开文件一实施例的第一级移位暂存器简化后的电路图。FIG. 11 is a simplified circuit diagram of a first-stage shift register according to an embodiment of the disclosure.
图12为依据本公开文件又一实施例的栅极驱动器简化后的功能方框图。FIG. 12 is a simplified functional block diagram of a gate driver according to yet another embodiment of the disclosure.
图13为依据本公开文件又一实施例的防漏电电路的电路示意图。FIG. 13 is a schematic circuit diagram of an anti-leakage circuit according to yet another embodiment of the disclosure.
图14为依据本公开文件又一实施例的显示装置的运行方式示意图。FIG. 14 is a schematic diagram of an operation mode of a display device according to another embodiment of the present disclosure.
图15为依据本公开文件一实施例的末级移位暂存器简化后的电路图。FIG. 15 is a simplified circuit diagram of a final stage shift register according to an embodiment of the disclosure.
图16为依据本公开文件一实施例的第一级移位暂存器简化后的电路图。FIG. 16 is a simplified circuit diagram of a first-stage shift register according to an embodiment of the disclosure.
图17为依据本公开文件再一实施例的栅极驱动器简化后的功能方框图。FIG. 17 is a simplified functional block diagram of a gate driver according to yet another embodiment of the disclosure.
图18为依据本公开文件再一实施例的防漏电电路的电路示意图。FIG. 18 is a schematic circuit diagram of an anti-leakage circuit according to yet another embodiment of the disclosure.
图19为依据本公开文件再一实施例的显示装置的运行方式示意图。FIG. 19 is a schematic diagram of an operation mode of a display device according to yet another embodiment of the disclosure.
图20为依据本公开文件一实施例的末级移位暂存器简化后的电路图。FIG. 20 is a simplified circuit diagram of a final stage shift register according to an embodiment of the disclosure.
图21为依据本公开文件一实施例的第一级移位暂存器简化后的电路图。FIG. 21 is a simplified circuit diagram of a first-stage shift register according to an embodiment of the disclosure.
图22为依据本公开文件一实施例的末级移位暂存器简化后的电路图。FIG. 22 is a simplified circuit diagram of a final shift register according to an embodiment of the disclosure.
附图标记说明：Explanation of reference signs:
100：显示装置 ODD：第一防护信号100: Display device ODD: First guard signal
110：控制电路 EVEN：第二防护信号110: Control circuit EVEN: Second protection signal
120：源极驱动器 CTL1：第一控制信号群组120: source driver CTL1: first control signal group
130：栅极驱动器 CTL2：第二控制信号群组130: Gate driver CTL2: Second control signal group
140：防漏电电路 CK：时脉信号140: Anti-leakage circuit CK: Clock signal
150：像素电路 XCK：反相时脉信号150: Pixel circuit XCK: Inverted clock signal
VL[1]～VL[x]：垂直信号线 ST：起始信号VL[1]～VL[x]: Vertical signal line ST: Start signal
HL[1]～HL[y]：水平信号线 SP：起始脉冲HL[1]～HL[y]: Horizontal signal line SP: Start pulse
210[1]～210[m]：移位暂存器 RS：重置信号210[1]～210[m]: shift register RS: reset signal
210[1]：移位暂存器 RP：重置脉冲210[1]: Shift register RP: Reset pulse
210[m]：移位暂存器 PW：电力输入210[m]: Shift register PW: Power input
210[m-1]：移位暂存器 Mu：多工信号群组210[m-1]: shift register Mu: multiplexing signal group
710[1]～710[m]：移位暂存器 Da：数据信号710[1]～710[m]: shift register Da: data signal
710[1]：移位暂存器 Gn[1]～Gn[y]：扫描信号710[1]: shift register Gn[1]～Gn[y]: scanning signal
710[m]：移位暂存器 CP：扫描脉冲710[m]: shift register CP: scan pulse
710[m-1]：移位暂存器 U1：第一上扫信号710[m-1]: shift register U1: first up-scan signal
1210[1]～1210[m]：移位暂存器 U2：第二上扫信号1210[1]～1210[m]: shift register U2: second up-scan signal
1210[1]：移位暂存器 U3：第三上扫信号1210[1]: shift register U3: third up-scan signal
1210[m]：移位暂存器 D1：第一下扫信号1210[m]: shift register D1: first downscan signal
1210[m-1]：移位暂存器 D2：第二下扫信号1210[m-1]: shift register D2: second downscan signal
1710[1]～1710[m]：移位暂存器 D3：第三下扫信号1710[1]～1710[m]: shift register D3: third downscan signal
1710[1]：移位暂存器 Vref1：第一参考电压1710[1]: shift register Vref1: first reference voltage
1710[m]：移位暂存器 Vref2：第二参考电压1710[m]: shift register Vref2: second reference voltage
1710[m-1]：移位暂存器 Vref3：第三参考电压1710[m-1]: shift register Vref3: third reference voltage
2200：移位暂存器 Vref4：第四参考电压2200: shift register Vref4: fourth reference voltage
310[1]～310[n]：切换电路 Vref5：第五参考电压310[1]～310[n]: switching circuit Vref5: fifth reference voltage
810[1]～810[n]：切换电路 Vref6：第六参考电压810[1]～810[n]: switching circuit Vref6: sixth reference voltage
1310[1]～1310[n]：切换电路 In1：第一电源端1310[1]～1310[n]: switching circuit In1: first power supply terminal
1810[1]～1810[n]：切换电路 In2：第二电源端1810[1]～1810[n]: switching circuit In2: second power supply terminal
510：驱动电路 O1：第一输出端510: Drive circuit O1: First output terminal
1010：驱动电路 O2：第二输出端1010: drive circuit O2: second output terminal
1510：驱动电路 O3：第三输出端1510: Drive circuit O3: Third output terminal
2010：驱动电路 GND：接地端2010: Drive circuit GND: Ground terminal
2210：驱动电路 N1：第一节点2210: drive circuit N1: first node
R1：电阻 N2：第二节点R1: resistor N2: second node
Tr1：第一驱动晶体管 P1：第一内部节点Tr1: first drive transistor P1: first internal node
Tr2：第二驱动晶体管 P2：第二内部节点Tr2: second drive transistor P2: second internal node
Tr3：第三驱动晶体管 P3：第三内部节点Tr3: third drive transistor P3: third internal node
Tr4：第四驱动晶体管 P4：第四内部节点Tr4: Fourth drive transistor P4: Fourth internal node
Tr5：第五驱动晶体管 P5：第五内部节点Tr5: fifth drive transistor P5: fifth internal node
Tr6：第六驱动晶体管 P6：第六内部节点Tr6: sixth drive transistor P6: sixth internal node
Tr7：第七驱动晶体管 M1：第一晶体管Tr7: seventh drive transistor M1: first transistor
Tr8：第八驱动晶体管 M2：第二晶体管Tr8: Eighth drive transistor M2: Second transistor
Tr9：第九驱动晶体管 M3：第三晶体管Tr9: ninth drive transistor M3: third transistor
Tr10：第十驱动晶体管 M4：第四晶体管Tr10: Tenth drive transistor M4: Fourth transistor
Tr11：第十一驱动晶体管 M5：第五晶体管Tr11: Eleventh drive transistor M5: Fifth transistor
M6：第六晶体管 M6: sixth transistor
M7：第七晶体管 M7: seventh transistor
M8：第八晶体管 M8: eighth transistor
具体实施方式Detailed ways
以下将配合相关附图来说明本公开文件的实施例。在附图中，相同的标号表示相同或类似的元件或方法流程。Embodiments of the disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.
图1为根据本公开文件一实施例的显示装置100简化后的功能方框图。显示装置100包含控制电路110、源极驱动器120、栅极驱动器130、防漏电电路140以及多个像素电路150。显示装置100还包含多个垂直信号线VL[1]～VL[x]与多个水平信号线HL[1]～HL[y]。多个像素电路150各自对应设置于垂直信号线VL[1]～VL[x]与水平信号线HL[1]～HL[y]的交叉处。源极驱动器120与栅极驱动器130用于通过垂直信号线VL[1]～VL[x]与水平信号线HL[1]～HL[y]驱动像素电路150。控制电路110用于提供源极驱动器120与栅极驱动器130运行所需要的各种电源输入与信号。显示装置100能暂时停止更新显示画面以节省电力消耗。并且，显示装置100于停止更新显示画面的过程中，能减轻多个像素电路150与垂直信号线VL[1]～VL[x]之间的漏电流。为使图面简洁而易于说明，显示装置100中的其他元件与连接关系并未示出于图1中。FIG. 1 is a simplified functional block diagram of a display device 100 according to an embodiment of the disclosure. The display device 100 includes a control circuit 110 , a source driver 120 , a gate driver 130 , an anti-leakage circuit 140 and a plurality of pixel circuits 150 . The display device 100 further includes a plurality of vertical signal lines VL[ 1 ]˜VL[x] and a plurality of horizontal signal lines HL[ 1 ]˜HL[y]. A plurality of pixel circuits 150 are respectively disposed at intersections of vertical signal lines VL[ 1 ]˜VL[x] and horizontal signal lines HL[ 1 ]˜HL[y]. The source driver 120 and the gate driver 130 are used to drive the pixel circuit 150 through the vertical signal lines VL[ 1 ]˜VL[x] and the horizontal signal lines HL[ 1 ]˜HL[y]. The control circuit 110 is used to provide various power inputs and signals required for the operation of the source driver 120 and the gate driver 130 . The display device 100 can temporarily stop updating the display screen to save power consumption. Moreover, the display device 100 can reduce the leakage current between the plurality of pixel circuits 150 and the vertical signal lines VL[ 1 ]˜VL[x] during the process of stopping updating the display image. In order to make the drawing concise and easy to explain, other components and connections in the display device 100 are not shown in FIG. 1 .
本公开说明书和附图中使用的元件编号和装置编号中的索引[1]～[n]、[1]～[x]与[1]～[y]等等，只是为了方便指称个别的元件和装置，并非有意将前述元件和装置的数量局限在特定数目。在本公开说明书和附图中，若使用某一元件编号或装置编号时没有指明该元件编号或装置编号的索引，则代表该元件编号或装置编号是指称所属元件群组或装置群组中不特定的任一元件或装置。例如，元件编号VL[1]指称的对象是垂直信号线VL[1]，而元件编号VL指称的对象则是垂直信号线VL[1]～VL[x]中不特定的任意垂直信号线。The index [1]～[n], [1]～[x], [1]～[y], etc. in the component numbers and device numbers used in this disclosure specification and drawings are only for convenience to refer to individual components and means, and there is no intention to limit the number of aforementioned elements and means to specific numbers. In this disclosure specification and drawings, if a component number or device number is used without specifying the index of the component number or device number, it means that the component number or device number refers to the component group or device group to which it belongs. any particular element or device. For example, the component number VL[1] refers to the vertical signal line VL[1], and the component number VL refers to any unspecified vertical signal line among the vertical signal lines VL[1]˜VL[x].
如图1所示，控制电路110用于提供数据信号Da与多工信号群组Mu至源极驱动器120，以使源极驱动器120依据多工信号群组Mu将数据信号Da写入像素电路150。控制电路110还用于提供时脉信号(时钟信号)CK、反相时脉信号XCK、起始信号ST、重置信号RS与电力输入PW至栅极驱动器130，以使栅极驱动器130依据时脉信号CK、反相时脉信号XCK、起始信号ST与重置信号RS导通或断开像素电路150与对应的垂直信号线VL。As shown in FIG. 1, the control circuit 110 is used to provide the data signal Da and the multiplexing signal group Mu to the source driver 120, so that the source driver 120 writes the data signal Da into the pixel circuit 150 according to the multiplexing signal group Mu. . The control circuit 110 is also used to provide a clock signal (clock signal) CK, an inverted clock signal XCK, a start signal ST, a reset signal RS and a power input PW to the gate driver 130, so that the gate driver 130 The pulse signal CK, the inverted clock signal XCK, the start signal ST and the reset signal RS turn on or off the pixel circuit 150 and the corresponding vertical signal line VL.
控制电路110还用于提供第一防护信号ODD与第二防护信号EVEN至防漏电电路140。栅极驱动器130用于提供第一控制信号群组CTL1与第二控制信号群组CTL2至防漏电电路140。防漏电电路140会依据第一控制信号群组CTL1与第二控制信号群组CTL2，于显示装置100暂时停止更新显示画面的期间，将第一防护信号ODD传递至部分的垂直信号线VL，并将第二防护信号EVEN传递至另一部分的垂直信号线VL。第一防护信号ODD与第二防护信号EVEN的电压准位被设置为接近于像素电路150存储的电压值，使得像素电路150与垂直信号线VL之间的漏电流得以减轻。The control circuit 110 is further configured to provide the first protection signal ODD and the second protection signal EVEN to the anti-leakage circuit 140 . The gate driver 130 is used for providing the first control signal group CTL1 and the second control signal group CTL2 to the anti-leakage circuit 140 . According to the first control signal group CTL1 and the second control signal group CTL2, the anti-leakage circuit 140 transmits the first protection signal ODD to some of the vertical signal lines VL during the period when the display device 100 temporarily stops updating the display image, and The second protection signal EVEN is transmitted to another part of the vertical signal line VL. The voltage levels of the first protection signal ODD and the second protection signal EVEN are set close to the voltage values stored in the pixel circuit 150 , so that the leakage current between the pixel circuit 150 and the vertical signal line VL is reduced.
实作上，像素电路150可以用各种合适的液晶像素电路来实现。在一实施例中，像素电路150产生128灰阶的亮度所需存储的电压值，于正半周期为第一电压值，于负半周期为第二电压值。第一防护信号ODD与第二防护信号EVEN被设置为分别等于第一电压值与第二电压值，以防止128灰阶左右亮度的像素电路150产生漏电流。由于人眼对于128灰阶附近的亮度变化较为敏感，本实施例可以有效提升使用者感受到的画面品质。In practice, the pixel circuit 150 can be realized by various suitable liquid crystal pixel circuits. In one embodiment, the pixel circuit 150 generates the 128-gray-scale brightness required to store the voltage value, which is the first voltage value in the positive half cycle and the second voltage value in the negative half cycle. The first protection signal ODD and the second protection signal EVEN are set to be equal to the first voltage value and the second voltage value respectively, so as to prevent the pixel circuit 150 with a brightness of about 128 gray scales from generating leakage current. Since the human eye is more sensitive to brightness changes near the 128 gray scale, this embodiment can effectively improve the picture quality perceived by the user.
图2为依据本公开文件一实施例的栅极驱动器130简化后的功能方框图。栅极驱动器130包含多级依序连接的移位暂存器210[1]～210[m]。移位暂存器210[1]～210[m]用于接收时脉信号CK与反向时脉信号XCK。移位暂存器210[1]与移位暂存器210[m]还用于接收电力输入PW，在本实施例中，电力输入PW包含第一参考电压Vref1、第二参考电压Vref2、第三参考电压Vref3与第四参考电压Vref4。FIG. 2 is a simplified functional block diagram of the gate driver 130 according to an embodiment of the disclosure. The gate driver 130 includes a plurality of sequentially connected shift registers 210 [ 1 ]˜ 210 [m]. The shift registers 210[1]˜210[m] are used to receive the clock signal CK and the reverse clock signal XCK. The shift register 210[1] and the shift register 210[m] are also used to receive the power input PW. In this embodiment, the power input PW includes the first reference voltage Vref1, the second reference voltage Vref2, the second The third reference voltage Vref3 and the fourth reference voltage Vref4.
另外，移位暂存器210[1]用于输出第一控制信号群组CTL1，移位暂存器210[m]用于输出第二控制信号群组CTL2。在本实施例中，第一控制信号群组CTL1包含第一上扫信号U1，第二控制信号群组CTL2包含第一下扫信号D1。移位暂存器210[1]与移位暂存器210[m]还分别用于接收起始信号ST与重置信号RS，并用于依据起始信号ST与重置信号RS控制移位暂存器210[2]～210[m-1]对应输出多个扫描信号Gn[1]～Gn[y]至水平驱动线HL[1]～HL[y]。In addition, the shift register 210[1] is used to output the first control signal group CTL1, and the shift register 210[m] is used to output the second control signal group CTL2. In this embodiment, the first control signal group CTL1 includes the first up-scan signal U1, and the second control signal group CTL2 includes the first down-scan signal D1. The shift register 210[1] and the shift register 210[m] are also used to receive the start signal ST and the reset signal RS respectively, and are used to control the shift register according to the start signal ST and the reset signal RS. The registers 210[2]-210[m-1] correspondingly output a plurality of scanning signals Gn[1]-Gn[y] to the horizontal driving lines HL[1]-HL[y].
图3为依据本公开文件一实施例的防漏电电路140的电路示意图。防漏电电路140包含多个切换电路310[1]～310[n]。每个切换电路310耦接于两条对应的垂直信号线VL，例如，切换电路310[1]耦接于垂直信号线VL[1]与垂直信号线VL[2]，切换电路310[2]耦接于垂直信号线VL[3]与垂直信号线VL[4]，依此类推。为方便理解，以下以切换电路310[1]为例进行说明。FIG. 3 is a schematic circuit diagram of an anti-leakage circuit 140 according to an embodiment of the disclosure. The anti-leakage circuit 140 includes a plurality of switching circuits 310 [ 1 ] to 310 [ n ]. Each switching circuit 310 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 310[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], and the switching circuit 310[2] It is coupled to the vertical signal line VL[3] and the vertical signal line VL[4], and so on. For the convenience of understanding, the switching circuit 310[1] is taken as an example for description below.
切换电路310[1]包含第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2。第一下扫开关Td1的第一端用于接收第一防护信号ODD。第一下扫开关Td1的第二端耦接于纵向驱动线VL[1]。第一下扫开关Td1的控制端用于接收第一下扫信号D1。第二下扫开关Td2的第一端用于接收第二防护信号EVEN。第二下扫开关Td2的第二端耦接于纵向驱动线VL[2]。第二下扫开关Td2的控制端用于接收第一下扫信号D1。The switching circuit 310[1] includes a first scan-down switch Td1, a second scan-down switch Td2, a first scan-up switch Tu1, and a second scan-up switch Tu2. The first end of the first down switch Td1 is used for receiving the first guard signal ODD. The second end of the first down switch Td1 is coupled to the vertical driving line VL[1]. The control terminal of the first down-scan switch Td1 is used for receiving the first down-scan signal D1. The first end of the second down switch Td2 is used for receiving the second protection signal EVEN. The second end of the second down scan switch Td2 is coupled to the vertical driving line VL[2]. The control terminal of the second down-scan switch Td2 is used for receiving the first down-scan signal D1.
第一上扫开关Tu1的第一端用于接收第一防护信号ODD。第一上扫开关Tu1的第二端耦接于纵向驱动线VL[1]。第一上扫开关Tu1的控制端用于接收第一上扫信号U1。第二上扫开关Tu2的第一端用于接收第二防护信号EVEN。第二上扫开关Tu2的第二端耦接于纵向驱动线VL[2]。第二上扫开关Tu2的控制端用于接收第一上扫信号U1。The first terminal of the first scan-up switch Tu1 is used for receiving the first guard signal ODD. The second terminal of the first scan-up switch Tu1 is coupled to the vertical driving line VL[1]. The control terminal of the first up-scan switch Tu1 is used for receiving the first up-scan signal U1. The first terminal of the second scan-up switch Tu2 is used for receiving the second protection signal EVEN. The second terminal of the second up-scan switch Tu2 is coupled to the vertical driving line VL[2]. The control terminal of the second up-scan switch Tu2 is used for receiving the first up-scan signal U1.
前述切换电路310[1]的连接方式、元件、实施方式以及优点，皆适用于切换电路310[2]～310[n]，为简洁起见，在此不重复赘述。The aforementioned connection methods, components, implementations and advantages of the switching circuit 310[1] are all applicable to the switching circuits 310[2]-310[n], and are not repeated here for the sake of brevity.
图4为依据本公开文件一实施例的显示装置100的运行方式示意图。以下将以图2、图3与图4来说明显示装置100的运行。于第一扫描阶段中，移位暂存器210[1]输出的第一上扫信号U1与移位暂存器210[m]输出的第一下扫信号D1具有禁能准位(例如，-8V)。多工信号群组Mu则具有致能准位(例如，8.5V)。当移位暂存器210[1]接收到起始信号ST提供的起始脉冲SP时，移位暂存器210[2]～210[m-1]会依序输出扫描脉冲CP。FIG. 4 is a schematic diagram of an operation mode of the display device 100 according to an embodiment of the disclosure. The operation of the display device 100 will be described below with reference to FIG. 2 , FIG. 3 and FIG. 4 . In the first scanning phase, the first up-scan signal U1 output from the shift register 210[1] and the first down-scan signal D1 output from the shift register 210[m] have a disable level (for example, -8V). The multiplexing signal group Mu has an enable level (for example, 8.5V). When the shift register 210[1] receives the start pulse SP provided by the start signal ST, the shift registers 210[2]˜210[m−1] will sequentially output the scan pulse CP.
换言之，当第一下扫信号D1与第一上扫信号U1都具有禁能准位，且移位暂存器210[1]接收到起始脉冲SP时，移位暂存器210[2]～210[m-1]会依序输出扫描脉冲CP。In other words, when both the first down-scan signal D1 and the first up-scan signal U1 have disable levels, and the shift register 210[1] receives the start pulse SP, the shift register 210[2] ~210[m-1] will sequentially output scan pulse CP.
因此，于第一扫描阶段中，第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2皆被关断。源极驱动器120会依据多工信号群组Mu将数据信号Da依序传递至垂直信号线VL[1]～VL[x]。此时，索引为奇数的垂直信号线VL(例如，垂直信号线VL[1]与垂直信号线VL[3]等等)会接收到正极性的电压，索引为偶数的垂直信号线VL(例如，垂直信号线VL[2]与垂直信号线VL[4]等等)则会接收到负极性的电压。Therefore, in the first scan phase, the first scan-down switch Td1 , the second scan-down switch Td2 , the first scan-up switch Tu1 and the second scan-up switch Tu2 are all turned off. The source driver 120 sequentially transmits the data signal Da to the vertical signal lines VL[ 1 ]˜VL[x] according to the multiplexing signal group Mu. At this time, the vertical signal lines VL with an odd index (for example, vertical signal line VL[1] and vertical signal line VL[3], etc.) will receive a positive polarity voltage, and the vertical signal lines VL with an even index (for example, , the vertical signal line VL[2] and the vertical signal line VL[4], etc.) will receive the voltage of negative polarity.
另外，与索引为奇数的垂直信号线VL耦接的像素电路150，会存储有正极性的电压，与索引为偶数的垂直信号线VL耦接的像素电路150，则会存储有负极性的电压。In addition, the pixel circuits 150 coupled to the odd-numbered vertical signal lines VL store positive polarity voltages, and the pixel circuits 150 coupled to the even-numbered vertical signal lines VL store negative polarity voltages. .
接着，于第一维持阶段中，第一上扫信号U1与多工信号群组Mu具有禁能准位。第一防护信号ODD会具有正极性的电压(例如，2.5V)，而第二防护信号EVEN会具有负极性的电压(例如，-2.5V)。当移位暂存器210[m]接收到移位暂存器210[m-1]输出的扫描脉冲CP时，移位暂存器210[m]会将第一下扫信号D1自禁能准位切换至致能准位。此时，移位暂存器210[2]～210[m-1]会停止输出扫描脉冲CP。Next, in the first sustaining phase, the first up-scan signal U1 and the multiplexing signal group Mu have a disable level. The first guard signal ODD has a positive polarity voltage (eg, 2.5V), and the second guard signal EVEN has a negative polarity voltage (eg, -2.5V). When the shift register 210[m] receives the scan pulse CP output by the shift register 210[m-1], the shift register 210[m] will automatically disable the first down-scan signal D1 The level switches to the enable level. At this time, the shift registers 210 [ 2 ]˜ 210 [ m−1 ] stop outputting the scan pulse CP.
因此，第一下扫开关Td1与第二下扫开关Td2会被导通，而第一上扫开关Tu1与第二上扫开关Tu2维持于关断状态。第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有正极性的电压。由于与索引为奇数的垂直信号线VL耦接的像素电路150亦存储有正极性的电压，所以索引为奇数的垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。Therefore, the first scan-down switch Td1 and the second scan-down switch Td2 are turned on, while the first scan-up switch Tu1 and the second scan-up switch Tu2 are kept in an off state. The first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first scan-down switch Td1 , so that the vertical signal line VL with an odd index has a positive voltage. Since the pixel circuits 150 coupled to the odd-numbered vertical signal lines VL also store positive voltages, the leakage current between the odd-numbered vertical signal lines VL and the corresponding pixel circuits 150 is reduced.
另一方面，第二防护信号EVEN会经由第二下扫开关Td2传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有负极性的电压。由于与索引为偶数的垂直信号线VL耦接的像素电路150亦存储有负极性的电压，所以索引为偶数的垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。On the other hand, the second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down switch Td2 , so that the even-numbered vertical signal line VL has a negative polarity voltage. Since the pixel circuits 150 coupled to the even-numbered vertical signal lines VL also store negative polarity voltages, the leakage current between the even-numbered vertical signal lines VL and the corresponding pixel circuits 150 is reduced.
于第二扫描阶段中，当移位暂存器210[m]接收到重置信号RS提供的重置脉冲RP时，移位暂存器210[m]将第一下扫信号D1自致能准位切换至禁能准位。接着，当移位暂存器210[1]再度接收到起始脉冲SP时，移位暂存器210[2]～210[m-1]会再度依序输出扫描脉冲CP。重置脉冲RP于时序上早于起始脉冲SP。亦即，于第一扫描阶段或第二扫描阶段中，移位暂存器210[m]会先接收到重置脉冲RP，然后移位暂存器210[1]才接收到起始脉冲SP。In the second scanning phase, when the shift register 210[m] receives the reset pulse RP provided by the reset signal RS, the shift register 210[m] self-enables the first down-scan signal D1 The level switches to the disabled level. Next, when the shift register 210 [ 1 ] receives the start pulse SP again, the shift registers 210 [ 2 ]˜ 210 [m−1] will sequentially output the scan pulse CP again. The reset pulse RP is earlier than the start pulse SP in timing. That is, in the first scanning phase or the second scanning phase, the shift register 210[m] will first receive the reset pulse RP, and then the shift register 210[1] will receive the start pulse SP .
此时，为了实现极性反转，索引为奇数的垂直信号线VL会改为接收到负极性的电压，而索引为偶数的垂直信号线VL则会改为接收到正极性的电压。显示装置100于第二扫描阶段的运行方式，相似于显示装置100于第一扫描阶段的运行方式，为简洁起见，在此不重复赘述。At this time, in order to achieve polarity inversion, the vertical signal lines VL with an odd index will receive a negative polarity voltage instead, and the vertical signal lines VL with an even index will receive a positive polarity voltage instead. The operation mode of the display device 100 in the second scanning phase is similar to the operation mode of the display device 100 in the first scanning phase, and for the sake of brevity, details are not repeated here.
于第二维持阶段中，第一防护信号ODD会切换至负极性的电压(例如，-2.5V)，而第二防护信号EVEN会切换至正极性的电压(例如，2.5V)。当移位暂存器210[m]接收到移位暂存器210[m-1]输出的扫描脉冲CP时，移位暂存器210[m]会将第一下扫信号D1自禁能准位切换至致能准位。In the second sustaining phase, the first protection signal ODD is switched to a negative polarity voltage (for example, −2.5V), and the second protection signal EVEN is switched to a positive polarity voltage (for example, 2.5V). When the shift register 210[m] receives the scan pulse CP output by the shift register 210[m-1], the shift register 210[m] will automatically disable the first down-scan signal D1 The level switches to the enable level.
因此，第一下扫开关Td1与第二下扫开关Td2会被导通，而第一上扫开关Tu1与第二上扫开关Tu2维持于关断状态。第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有负极性的电压。由于与索引为奇数的垂直信号线VL耦接的像素电路150亦存储有负极性的电压，所以索引为奇数的垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。Therefore, the first scan-down switch Td1 and the second scan-down switch Td2 are turned on, while the first scan-up switch Tu1 and the second scan-up switch Tu2 are kept in an off state. The first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first down switch Td1 , so that the vertical signal line VL with an odd index has a negative polarity voltage. Since the pixel circuits 150 coupled to the odd-numbered vertical signal lines VL also store negative polarity voltages, the leakage current between the odd-numbered vertical signal lines VL and the corresponding pixel circuits 150 is reduced.
另一方面，第二防护信号EVEN会经由第二下扫开关Td2传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有正极性的电压。由于与索引为偶数的垂直信号线VL耦接的像素电路150亦存储有正极性的电压，所以索引为偶数的垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。On the other hand, the second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down switch Td2 , so that the even-numbered vertical signal line VL has a positive voltage. Since the pixel circuits 150 coupled to the even-numbered vertical signal lines VL also store positive polarity voltages, the leakage current between the even-numbered vertical signal lines VL and the corresponding pixel circuits 150 is reduced.
另外，由上述可知，于第一维持阶段与第二维持阶段中，第一防护信号ODD与第二防护信号EVEN的波形彼此相反。In addition, it can be seen from the above that in the first sustaining phase and the second sustaining phase, the waveforms of the first protection signal ODD and the second protection signal EVEN are opposite to each other.
在某一实施例中，移位暂存器210[2]～210[m-1]是自图2的下方往上方依序输出扫描脉冲CP。亦即，移位暂存器210[m-1]会第一个输出扫描脉冲CP，而移位暂存器210[2]会最后一个输出扫描脉冲CP。此时，移位暂存器210[1]会由接收起始信号ST改为接收重置信号RS，并执行相似于图2至图4的实施例中移位暂存器210[m]的运行。移位暂存器210[m]会由接收重置信号RS改为接收起始信号ST，并执行相似于图2至图4的实施例中移位暂存器210[1]的运行。In a certain embodiment, the shift registers 210 [ 2 ]˜ 210 [ m−1 ] sequentially output the scan pulse CP from the bottom to the top of FIG. 2 . That is, the shift register 210[m−1] is the first to output the scan pulse CP, and the shift register 210[2] is the last to output the scan pulse CP. At this time, the shift register 210[1] will change from receiving the start signal ST to receive the reset signal RS, and perform a process similar to that of the shift register 210[m] in the embodiment of FIG. 2 to FIG. 4 run. The shift register 210[m] will change from receiving the reset signal RS to receive the start signal ST, and perform an operation similar to that of the shift register 210[1] in the embodiments of FIG. 2 to FIG. 4 .
在此情况下，第一下扫开关Td1与第二下扫开关Td2会维持于关断状态。第一上扫开关Tu1与第二上扫开关Tu2于第一扫描阶段与第二扫描阶段会被关断，并于第一维持阶段与第二维持阶段被导通。因此，于第一维持阶段与第二维持阶段中，第一防护信号ODD会经由第一上扫开关Tu1传递至索引为奇数的垂直驱动线VL，第二防护信号EVEN会经由第二上扫开关Tu2传递至索引为偶数的垂直驱动线VL。前述图2至图4的实施例的其他连接方式、元件、实施方式以及优点，皆适用于本实施例，为简洁起见，在此不重复赘述。In this case, the first down-scan switch Td1 and the second down-scan switch Td2 are kept in an off state. The first scan-up switch Tu1 and the second scan-up switch Tu2 are turned off during the first scan phase and the second scan phase, and are turned on during the first sustain phase and the second sustain phase. Therefore, in the first sustaining phase and the second sustaining phase, the first protection signal ODD will be transmitted to the odd-numbered vertical driving line VL through the first scan-up switch Tu1, and the second protection signal EVEN will be transmitted through the second scan-up switch. Tu2 is passed to the even-indexed vertical drive line VL. The other connection modes, components, implementation methods and advantages of the foregoing embodiments in FIGS. 2 to 4 are all applicable to this embodiment, and for the sake of brevity, details are not repeated here.
图5为依据本公开文件一实施例的移位暂存器210[m]简化后的电路图。移位暂存器210[m]包含第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4与驱动电路510。驱动电路510用于接收移位暂存器210[m]的前一级移位暂存器(亦即，移位暂存器210[m-1])输出的扫描脉冲CP，以及接收重置信号RS、第一参考电压Vref1、第二参考电压Vref2、第三参考电压Vref3与第四参考电压Vref4。FIG. 5 is a simplified circuit diagram of the shift register 210[m] according to an embodiment of the disclosure. The shift register 210[m] includes a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 and a driving circuit 510 . The driving circuit 510 is used to receive the scan pulse CP output by the previous stage shift register of the shift register 210[m] (that is, the shift register 210[m-1]), and receive the reset The signal RS, the first reference voltage Vref1 , the second reference voltage Vref2 , the third reference voltage Vref3 and the fourth reference voltage Vref4 .
第一晶体管M1耦接于第一电源端In1与第一节点N1之间，用于通过第一电源端In1接收第三参考电压Vref3。第二晶体管M2耦接于第一节点N1与接地端GND之间，其中第一晶体管M1与第二晶体管M2的控制端都耦接于驱动电路510。第三晶体管M3耦接于第一节点N1与第一输出端O1之间，且第三晶体管M3的控制端用于接收第一参考电压Vref1。第四晶体管M4耦接于第一输出端O1与接地端GND之间，且第四晶体管M4的控制端用于接收第二参考电压Vref2。The first transistor M1 is coupled between the first power terminal In1 and the first node N1 for receiving the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first node N1 and the ground terminal GND, wherein the control terminals of the first transistor M1 and the second transistor M2 are both coupled to the driving circuit 510 . The third transistor M3 is coupled between the first node N1 and the first output terminal O1, and the control terminal of the third transistor M3 is used for receiving the first reference voltage Vref1. The fourth transistor M4 is coupled between the first output terminal O1 and the ground terminal GND, and the control terminal of the fourth transistor M4 is used for receiving the second reference voltage Vref2.
当移位暂存器210[2]～210[m-1]具有第一扫描顺序(例如，由图2的上方至下方依序输出扫描脉冲CP)时，第一参考电压Vref1会具有高电压准位且第二参考电压Vref2会具有低电压准位。因此，第三晶体管M3会维持于导通状态，第四晶体管M4会维持于关断状态。When the shift registers 210[2]˜210[m-1] have a first scan sequence (for example, the scan pulse CP is sequentially output from top to bottom in FIG. 2), the first reference voltage Vref1 will have a high voltage level and the second reference voltage Vref2 has a low voltage level. Therefore, the third transistor M3 is maintained in an on state, and the fourth transistor M4 is maintained in an off state.
当移位暂存器210[m-1]输出扫描脉冲CP时，驱动电路510会导通第一晶体管M1并关断第二晶体管M2，以导通第一电源端In1与第一节点N1。此时，第三参考电压Vref3便会自第一电源端In1传递至第一输出端O1，并作为具有致能准位的第一下扫信号D1输出。When the shift register 210[m−1] outputs the scan pulse CP, the driving circuit 510 turns on the first transistor M1 and turns off the second transistor M2, so as to turn on the first power terminal In1 and the first node N1. At this time, the third reference voltage Vref3 is transmitted from the first power supply terminal In1 to the first output terminal O1, and is output as the first down-scan signal D1 with an enable level.
另一方面，当驱动电路510接收到重置信号RS的重置脉冲RP时，驱动电路510会关断第一晶体管M1并导通第二晶体管M2，以导通第一节点N1与接地端GND。此时，接地电压便会自接地端GND传递至第一输出端O1，并作为具有禁能准位的第一下扫信号D1输出。On the other hand, when the driving circuit 510 receives the reset pulse RP of the reset signal RS, the driving circuit 510 will turn off the first transistor M1 and turn on the second transistor M2, so as to connect the first node N1 and the ground terminal GND. . At this time, the ground voltage is transmitted from the ground terminal GND to the first output terminal O1, and is output as the first down-scan signal D1 with a disable level.
详细而言，驱动电路510包含第一驱动晶体管Tr1、第二驱动晶体管Tr2、第三驱动晶体管Tr3、第四驱动晶体管Tr4、第五驱动晶体管Tr5、第六驱动晶体管Tr6、第七驱动晶体管Tr7、第八驱动晶体管Tr8、第九驱动晶体管Tr9、第十驱动晶体管Tr10与第十一驱动晶体管Tr11。Specifically, the drive circuit 510 includes a first drive transistor Tr1, a second drive transistor Tr2, a third drive transistor Tr3, a fourth drive transistor Tr4, a fifth drive transistor Tr5, a sixth drive transistor Tr6, a seventh drive transistor Tr7, The eighth driving transistor Tr8 , the ninth driving transistor Tr9 , the tenth driving transistor Tr10 and the eleventh driving transistor Tr11 .
第一驱动晶体管Tr1的第一端用于接收时脉信号CK，第二端与控制端分别耦接于第一内部节点P1与第二内部节点P2。第二驱动晶体管Tr2的第一端、第二端与控制端分别耦接于第一内部节点P1、第三内部节点P3与第二内部节点P2，且第二驱动晶体管Tr2的第一端和第二端互相耦接。第三驱动晶体管Tr3的第一端、第二端与控制端分别耦接于第三内部节点P3、接地端GND与第四内部节点P4。第四驱动晶体管Tr4的第一端、第二端分别耦接于第二内部节点P2与第五内部节点P5，控制端用于接收第四参考电压Vref4。The first terminal of the first driving transistor Tr1 is used for receiving the clock signal CK, and the second terminal and the control terminal are coupled to the first internal node P1 and the second internal node P2 respectively. The first terminal, the second terminal and the control terminal of the second driving transistor Tr2 are respectively coupled to the first internal node P1, the third internal node P3 and the second internal node P2, and the first terminal of the second driving transistor Tr2 is connected to the first internal node P2. The two ends are coupled to each other. The first terminal, the second terminal and the control terminal of the third driving transistor Tr3 are respectively coupled to the third internal node P3, the ground terminal GND and the fourth internal node P4. The first terminal and the second terminal of the fourth driving transistor Tr4 are respectively coupled to the second internal node P2 and the fifth internal node P5, and the control terminal is used for receiving the fourth reference voltage Vref4.
第五驱动晶体管Tr5的第一端与控制端耦接于第三内部节点P3，第二端耦接于第五内部节点P5。第六驱动晶体管Tr6的第一端、第二端与控制端分别耦接于第五内部节点P5、接地端GND与第四内部节点P4。第七驱动晶体管Tr7的第一端与控制端用于接收重置信号RS，第二端耦接于第四内部节点P4。第八驱动晶体管Tr8的第一端用于接收第四参考电压Vref4，第二端耦接于电阻R1的第一端，控制端用于接收反相时脉信号XCK。The first terminal and the control terminal of the fifth driving transistor Tr5 are coupled to the third internal node P3, and the second terminal is coupled to the fifth internal node P5. The first terminal, the second terminal and the control terminal of the sixth driving transistor Tr6 are respectively coupled to the fifth internal node P5, the ground terminal GND and the fourth internal node P4. The first terminal and the control terminal of the seventh driving transistor Tr7 are used for receiving the reset signal RS, and the second terminal is coupled to the fourth internal node P4. The first end of the eighth driving transistor Tr8 is used to receive the fourth reference voltage Vref4 , the second end is coupled to the first end of the resistor R1 , and the control end is used to receive the inverted clock signal XCK.
第九驱动晶体管Tr9的第一端、第二端与控制端分别耦接于电阻R1的第二端、接地端GND与第五内部节点P5。第十驱动晶体管Tr10的第一端用于接收第一参考电压Vref1，第二端耦接于第五内部节点P5，控制端用于接收移位暂存器210[m-1]输出的扫描脉冲CP。第十一驱动晶体管Tr11的第一端耦接于第五内部节点P5，第二端用于接收第二参考电压Vref2，控制端用于接收重置信号RS。The first terminal, the second terminal and the control terminal of the ninth driving transistor Tr9 are respectively coupled to the second terminal of the resistor R1, the ground terminal GND and the fifth internal node P5. The first end of the tenth drive transistor Tr10 is used to receive the first reference voltage Vref1, the second end is coupled to the fifth internal node P5, and the control end is used to receive the scan pulse output by the shift register 210[m-1] CP. The first terminal of the eleventh driving transistor Tr11 is coupled to the fifth internal node P5, the second terminal is used for receiving the second reference voltage Vref2, and the control terminal is used for receiving the reset signal RS.
图6为依据本公开文件一实施例的第一级移位暂存器210[1]简化后的电路图。移位暂存器210[1]与移位暂存器210[m]相似。差异在于，移位暂存器210[1]的第三晶体管M3与第四晶体管M4的控制端分别用于接收第二参考电压Vref2与第一参考电压Vref1，且移位暂存器210[1]的第十驱动晶体管Tr10与第十一驱动晶体管Tr11的控制端分别用于接收起始信号ST与移位暂存器210[2]输出的扫描脉冲CP。因此，当移位暂存器210[2]～210[m-1]具有前述的第一扫描顺序时，移位暂存器210[1]的第三晶体管M3会关断而第四晶体管M4会导通，以将第一上扫信号U1维持于禁能准位。FIG. 6 is a simplified circuit diagram of the first-stage shift register 210 [1] according to an embodiment of the disclosure. The shift register 210[1] is similar to the shift register 210[m]. The difference is that the control terminals of the third transistor M3 and the fourth transistor M4 of the shift register 210[1] are respectively used to receive the second reference voltage Vref2 and the first reference voltage Vref1, and the shift register 210[1] ], the control terminals of the tenth drive transistor Tr10 and the eleventh drive transistor Tr11 are respectively used to receive the start signal ST and the scan pulse CP output by the shift register 210 [2]. Therefore, when the shift registers 210[2]˜210[m-1] have the aforementioned first scanning sequence, the third transistor M3 of the shift register 210[1] will be turned off and the fourth transistor M4 will be turned off. is turned on to maintain the first up-scan signal U1 at a disabled level.
在一实施例中，移位暂存器210[2]～210[m-1]具有第二扫描顺序(例如，由图2的下方至上方依序输出扫描脉冲CP)。此时，第一参考电压Vref1会具有低电压准位且第二参考电压Vref2会具有高电压准位。因此，移位暂存器210[1]的第三晶体管M3会导通而第四晶体管M4会关断，以使移位暂存器210[1]能够输出具有致能准位的第一上扫信号U1。另一方面，移位暂存器210[m]的第三晶体管M3会关断而第四晶体管M4会导通，以使移位暂存器210[m]输出的第一下扫信号D1维持于禁能准位。In one embodiment, the shift registers 210 [ 2 ]˜ 210 [ m−1 ] have a second scan sequence (for example, sequentially output scan pulses CP from bottom to top in FIG. 2 ). At this time, the first reference voltage Vref1 has a low voltage level and the second reference voltage Vref2 has a high voltage level. Therefore, the third transistor M3 of the shift register 210[1] is turned on and the fourth transistor M4 is turned off, so that the shift register 210[1] can output the first upper Sweep signal U1. On the other hand, the third transistor M3 of the shift register 210[m] is turned off and the fourth transistor M4 is turned on, so that the first down-scan signal D1 output by the shift register 210[m] maintains In the prohibition level.
在一无需双向扫描的实施例中，可以省略图2的移位暂存器210[1]，并将移位暂存器210[2]由接收移位暂存器210[1]的扫描脉冲CP改为接收起始信号ST。另外，还可以省略切换电路310中的第一上扫开关Tu1与第二上扫开关Tu2。In an embodiment that does not require bidirectional scanning, the shift register 210[1] of FIG. The CP instead receives a start signal ST. In addition, the first scan-up switch Tu1 and the second scan-up switch Tu2 in the switching circuit 310 can also be omitted.
此外，还可以省略图5的第一晶体管M1、第二晶体管M2、第三晶体管M3与第四晶体管M4，并将第一驱动晶体管Tr1的第一端改为接收第三参考电压Vref3。在此情况下，第一下扫信号D1会改由移位暂存器210[m]的第三内部节点P3输出。In addition, the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 in FIG. 5 can also be omitted, and the first end of the first driving transistor Tr1 is changed to receive the third reference voltage Vref3 . In this case, the first down-scan signal D1 is output from the third internal node P3 of the shift register 210[m] instead.
图7为依据本公开文件另一实施例的栅极驱动器130简化后的功能方框图。在本实施例中，栅极驱动器130包含依序连接的移位暂存器710[1]～710[m]。移位暂存器710[1]～710[m]相似于图2的移位暂存器210[1]～210[m]。差异在于，本实施例的电力输入PW包含第一参考电压Vref1、第二参考电压Vref2、第三参考电压Vref3、第四参考电压Vref4与第五参考电压Vref5，所以移位暂存器710[1]与710[m]除了用于接收第一参考电压Vref1至第四参考电压Vref4，还用于接收第五参考电压Vref5。FIG. 7 is a simplified functional block diagram of the gate driver 130 according to another embodiment of the present disclosure. In this embodiment, the gate driver 130 includes shift registers 710[1]˜710[m] connected in sequence. The shift registers 710[1]˜710[m] are similar to the shift registers 210[1]˜210[m] of FIG. 2 . The difference is that the power input PW of this embodiment includes the first reference voltage Vref1, the second reference voltage Vref2, the third reference voltage Vref3, the fourth reference voltage Vref4 and the fifth reference voltage Vref5, so the shift register 710[1 ] and 710[m] are not only used to receive the first reference voltage Vref1 to the fourth reference voltage Vref4, but also used to receive the fifth reference voltage Vref5.
另外，在本实施例中，第一控制信号群组CTL1包含第一上扫信号U1与第二上扫信号U2，第二控制信号群组CTL2包含第一下扫信号D1与第二下扫信号D2。In addition, in this embodiment, the first control signal group CTL1 includes the first up-scan signal U1 and the second up-scan signal U2, and the second control signal group CTL2 includes the first down-scan signal D1 and the second down-scan signal D2.
图8为依据本公开文件另一实施例的防漏电电路140的电路示意图。在本实施例中，防漏电电路140包含多个切换电路810[1]～810[n]。每个切换电路810耦接于两条对应的垂直信号线VL，例如，切换电路810[1]耦接于垂直信号线VL[1]与垂直信号线VL[2]，切换电路810[2]耦接于垂直信号线VL[3]与垂直信号线VL[4]，依此类推，为简洁起见，在此不重复赘述。为方便理解，以下以切换电路810[1]为例进行说明。FIG. 8 is a schematic circuit diagram of an anti-leakage circuit 140 according to another embodiment of the disclosure. In this embodiment, the anti-leakage circuit 140 includes a plurality of switching circuits 810[1]˜810[n]. Each switching circuit 810 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 810[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], and the switching circuit 810[2] It is coupled to the vertical signal line VL[ 3 ] and the vertical signal line VL[ 4 ], and so on. For the sake of brevity, details are not repeated here. For the convenience of understanding, the switching circuit 810[1] is taken as an example for description below.
切换电路810[1]包含第一下扫开关Td1、第二下扫开关Td2、第三下扫开关Td3与第四下扫开关Td4。切换电路810[1]还包含第一上扫开关Tu1、第二上扫开关Tu2、第三上扫开关Tu3与第四上扫开关Tu4。第一下扫开关Td1的第一端用于接收第一防护信号ODD。第一下扫开关Td1的第二端耦接于纵向信号线VL[1]。第一下扫开关Td1的控制端用于接收第一下扫信号D1。第二下扫开关Td2的第一端用于接收第二防护信号EVEN。第二下扫开关Td2的第二端耦接于纵向信号线VL[1]。第二下扫开关Td2的控制端用于接收第二下扫信号D2。The switching circuit 810 [ 1 ] includes a first scan-down switch Td1 , a second scan-down switch Td2 , a third scan-down switch Td3 and a fourth scan-down switch Td4 . The switching circuit 810[1] further includes a first scan-up switch Tu1, a second scan-up switch Tu2, a third scan-up switch Tu3, and a fourth scan-up switch Tu4. The first end of the first down switch Td1 is used for receiving the first guard signal ODD. The second end of the first down switch Td1 is coupled to the vertical signal line VL[1]. The control terminal of the first down-scan switch Td1 is used for receiving the first down-scan signal D1. The first end of the second down switch Td2 is used for receiving the second protection signal EVEN. The second end of the second down switch Td2 is coupled to the vertical signal line VL[1]. The control terminal of the second down-scan switch Td2 is used for receiving the second down-scan signal D2.
第三下扫开关Td3的第一端用于接收第二防护信号EVEN。第三下扫开关Td3的第二端耦接于第二纵向信号线VL[2]。第三下扫开关Td3的控制端用于接收第一下扫信号D1。第四下扫开关Td4的第一端用于接收第一防护信号ODD。第四下扫开关Td4的第二端耦接于纵向信号线VL[2]。第四下扫开关Td4的控制端用于接收第二下扫信号D2。The first end of the third sweep down switch Td3 is used for receiving the second protection signal EVEN. The second end of the third down switch Td3 is coupled to the second vertical signal line VL[2]. The control terminal of the third down-scan switch Td3 is used for receiving the first down-scan signal D1. The first end of the fourth down switch Td4 is used for receiving the first guard signal ODD. The second end of the fourth down switch Td4 is coupled to the vertical signal line VL[2]. The control terminal of the fourth down-scan switch Td4 is used for receiving the second down-scan signal D2.
第一上扫开关Tu1的第一端用于接收第一防护信号ODD。第一上扫开关Tu1的第二端耦接于纵向信号线VL[1]。第一上扫开关Tu1的控制端用于接收第一上扫信号U1。第二上扫开关Tu2的第一端用于接收第二防护信号EVEN。第二上扫开关Tu2的第二端耦接于纵向信号线VL[1]。第二上扫开关的控制端用于接收第二上扫信号U2。The first terminal of the first scan-up switch Tu1 is used for receiving the first guard signal ODD. The second terminal of the first scan-up switch Tu1 is coupled to the vertical signal line VL[1]. The control terminal of the first up-scan switch Tu1 is used for receiving the first up-scan signal U1. The first terminal of the second scan-up switch Tu2 is used for receiving the second protection signal EVEN. The second end of the second scan-up switch Tu2 is coupled to the vertical signal line VL[1]. The control terminal of the second up-scan switch is used for receiving the second up-scan signal U2.
第三上扫开关Tu3的第一端用于接收第二防护信号EVEN。第三上扫开关Tu3的第二端耦接于纵向信号线VL[2]。第三上扫开关Tu3的控制端用于接收第一上扫信号U1。第四上扫开关Tu4的第一端用于接收第一防护信号ODD。第四上扫开关Tu4的第二端耦接于纵向信号线VL[2]。第四上扫开关Tu4的控制端用于接收第二上扫信号U2。The first terminal of the third scan-up switch Tu3 is used for receiving the second protection signal EVEN. The second end of the third scan-up switch Tu3 is coupled to the vertical signal line VL[2]. The control terminal of the third up-scan switch Tu3 is used for receiving the first up-scan signal U1. The first end of the fourth scan-up switch Tu4 is used for receiving the first guard signal ODD. The second terminal of the fourth up-scan switch Tu4 is coupled to the vertical signal line VL[2]. The control terminal of the fourth up-scan switch Tu4 is used for receiving the second up-scan signal U2.
前述切换电路810[1]的连接方式、元件、实施方式以及优点，皆适用于切换电路810[2]～810[n]，为简洁起见，在此不重复赘述。The aforementioned connection methods, components, implementations and advantages of the switching circuit 810[1] are all applicable to the switching circuits 810[2]˜810[n], and are not repeated here for the sake of brevity.
图9为依据本公开文件另一实施例的显示装置100的运行方式示意图。以下将以图7、图8与图9来说明显示装置100的运行。在本实施例中，第一防护信号ODD维持于正极性的电压(例如，2.5V)，而第二防护信号EVEN维持于负极性的电压(例如，-2.5V)。FIG. 9 is a schematic diagram of the operation mode of the display device 100 according to another embodiment of the disclosure. The operation of the display device 100 will be described below with reference to FIG. 7 , FIG. 8 and FIG. 9 . In this embodiment, the first protection signal ODD is maintained at a positive voltage (for example, 2.5V), and the second protection signal EVEN is maintained at a negative voltage (for example, −2.5V).
在第一扫描阶段中，第一上扫信号U1、第二上扫信号U2、第一下扫信号D1与第二下扫信号D2具有禁能准位。因此，第一下扫开关Td1、第二下扫开关Td2、第三下扫开关Td3、第四下扫开关Td4、第一上扫开关Tu1、第二上扫开关Tu2、第三上扫开关Tu3与第四上扫开关Tu4被关断。In the first scan phase, the first up-scan signal U1 , the second up-scan signal U2 , the first down-scan signal D1 and the second down-scan signal D2 have a disable level. Therefore, the first scan-down switch Td1, the second scan-down switch Td2, the third scan-down switch Td3, the fourth scan-down switch Td4, the first scan-up switch Tu1, the second scan-up switch Tu2, and the third scan-up switch Tu3 And the fourth scan-up switch Tu4 is turned off.
此时，索引为奇数的垂直信号线VL会接收到正极性的电压，而索引为偶数的垂直信号线VL则会接收到负极性的电压。At this time, the vertical signal lines VL with an odd index receive a positive polarity voltage, and the vertical signal lines VL with an even index receive a negative polarity voltage.
在第一维持阶段中，第一下扫信号D1具有致能准位，而第一上扫信号U1、第二上扫信号U2与第二下扫信号D2维持于禁能准位。因此，第一下扫开关Td1与第三下扫开关Td3被导通，而第二下扫开关Td2、第四下扫开关Td4、第一上扫开关Tu1、第二上扫开关Tu2、第三上扫开关Tu3与第四下扫开关Tu4被关断。In the first sustaining phase, the first down-scan signal D1 has an enable level, and the first up-scan signal U1 , the second up-scan signal U2 and the second down-scan signal D2 maintain a disable level. Therefore, the first scan-down switch Td1 and the third scan-down switch Td3 are turned on, and the second scan-down switch Td2, the fourth scan-down switch Td4, the first scan-up switch Tu1, the second scan-up switch Tu2, the third scan-down switch The scan-up switch Tu3 and the fourth scan-down switch Tu4 are turned off.
此时，第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有正极性的电压。第二防护信号EVEN会经由第三下扫开关Td3传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有负极性的电压。因此，垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。At this time, the first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first scan-down switch Td1 , so that the vertical signal line VL with an odd index has a positive voltage. The second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the third down-sweep switch Td3 , so that the even-numbered vertical signal line VL has a negative polarity voltage. Therefore, leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is alleviated.
在第二扫描阶段中，第一上扫信号U1、第二上扫信号U2、第一下扫信号D1与第二下扫信号D2具有禁能准位。因此，第一下扫开关Td1、第二下扫开关Td2、第三下扫开关Td3、第四下扫开关Td4、第一上扫开关Tu1、第二上扫开关Tu2、第三上扫开关Tu3与第四上扫开关Tu4会再度被关断。In the second scan phase, the first up-scan signal U1 , the second up-scan signal U2 , the first down-scan signal D1 and the second down-scan signal D2 have a disable level. Therefore, the first scan-down switch Td1, the second scan-down switch Td2, the third scan-down switch Td3, the fourth scan-down switch Td4, the first scan-up switch Tu1, the second scan-up switch Tu2, and the third scan-up switch Tu3 And the fourth scan-up switch Tu4 is turned off again.
此时，索引为奇数的垂直信号线VL会接收到负极性的电压，而索引为偶数的垂直信号线VL则会接收到正极性的电压。At this time, the vertical signal lines VL with an odd index receive a voltage of negative polarity, while the vertical signal lines VL with an even index receive a voltage of positive polarity.
接着，在第二维持阶段中，第二下扫信号D2具有致能准位，而第一上扫信号U1、第二上扫信号U2与第一下扫信号D1维持于禁能准位。因此，第二下扫开关Td2与第四下扫开关Td4被导通，而第一下扫开关Td1、第三下扫开关Td3、第一上扫开关Tu1、第二上扫开关Tu2、第三上扫开关Tu3与第四下扫开关Tu4被关断。Next, in the second sustaining phase, the second down-scan signal D2 has an enable level, while the first up-scan signal U1 , the second up-scan signal U2 and the first down-scan signal D1 are maintained at a disable level. Therefore, the second scan-down switch Td2 and the fourth scan-down switch Td4 are turned on, and the first scan-down switch Td1, the third scan-down switch Td3, the first scan-up switch Tu1, the second scan-up switch Tu2, the third scan-down switch The scan-up switch Tu3 and the fourth scan-down switch Tu4 are turned off.
此时，第二防护信号EVEN会经由第二下扫开关Td2传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有负极性的电压。第一防护信号ODD会经由第四下扫开关Td4传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有正极性的电压。因此，垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。At this time, the second protection signal EVEN is transmitted to the vertical signal line VL with an odd index through the second scan-down switch Td2 , so that the vertical signal line VL with an odd index has a negative polarity voltage. The first protection signal ODD is transmitted to the even-numbered vertical signal line VL through the fourth down-sweep switch Td4 , so that the even-numbered vertical signal line VL has a positive voltage. Therefore, leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is alleviated.
由于在图7至图9的实施例中第一防护信号ODD与第二防护信号EVEN为直流信号，所以控制电路110的设计复杂度得以降低。Since the first protection signal ODD and the second protection signal EVEN are DC signals in the embodiments of FIGS. 7 to 9 , the design complexity of the control circuit 110 is reduced.
前述图2至图4的实施例的其余连接方式、元件、实施方式以及优点，皆适用于图7至图9的实施例，为简洁起见，在此不重复赘述。The rest of the connections, components, implementations and advantages of the aforementioned embodiments in FIGS. 2 to 4 are all applicable to the embodiments in FIGS. 7 to 9 , and are not repeated here for the sake of brevity.
在某一实施例中，移位暂存器710[2]～710[m-1]是自图7的下方往上方依序输出扫描脉冲CP。移位暂存器710[m-1]是第一个输出扫描脉冲CP，移位暂存器710[2]是最后一个输出扫描脉冲CP。此时，移位暂存器710[1]会由接收起始信号ST改为接收重置信号RS，并执行相似于图7至图9的实施例中移位暂存器710[m]的运行。移位暂存器710[m]会由接收重置信号RS改为接收起始信号ST，并执行相似于图7至图9的实施例中移位暂存器710[1]的运行。In one embodiment, the shift registers 710 [ 2 ]˜ 710 [ m−1 ] sequentially output the scan pulse CP from the bottom to the top of FIG. 7 . The shift register 710[m-1] is the first output scan pulse CP, and the shift register 710[2] is the last output scan pulse CP. At this time, the shift register 710[1] will change from receiving the start signal ST to receive the reset signal RS, and perform a process similar to that of the shift register 710[m] in the embodiment of FIG. 7 to FIG. 9 run. The shift register 710[m] is changed from receiving the reset signal RS to receiving the start signal ST, and performs an operation similar to that of the shift register 710[1] in the embodiments of FIG. 7 to FIG. 9 .
在此情况下，第一下扫开关Td1、第二下扫开关Td2、第三下扫开关Td3与第四下扫开关Td4会维持于关断状态。第一上扫开关Tu1与第三上扫开关Tu3会于第一扫描阶段与第二扫描阶段被关断，并于第一维持阶段被导通。第二上扫开关Tu2与第四上扫开关Tu4会于第一扫描阶段与第二扫描阶段被关断，并于第二维持阶段被导通。前述图7至图9的实施例的其他连接方式、元件、实施方式以及优点，皆适用于本实施例，为简洁起见，在此不重复赘述。In this case, the first scan-down switch Td1 , the second scan-down switch Td2 , the third scan-down switch Td3 and the fourth scan-down switch Td4 are kept in the off state. The first scan-up switch Tu1 and the third scan-up switch Tu3 are turned off during the first scan phase and the second scan phase, and are turned on during the first sustain phase. The second scan-up switch Tu2 and the fourth scan-up switch Tu4 are turned off during the first scan phase and the second scan phase, and are turned on during the second sustain phase. Other connection modes, components, implementation methods and advantages of the aforementioned embodiments in FIGS. 7 to 9 are all applicable to this embodiment, and for the sake of brevity, details are not repeated here.
图10为依据本公开文件一实施例的移位暂存器710[m]简化后的电路图。移位暂存器710[m]包含第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8与驱动电路1010。FIG. 10 is a simplified circuit diagram of a shift register 710[m] according to an embodiment of the disclosure. The shift register 710[m] includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and drive circuit 1010 .
第一晶体管M1耦接于第一电源端In1与第一节点N1之间，用于通过第一电源端In1接收第三参考电压Vref3。第二晶体管M2耦接于第一节点N1与接地端GND之间，其中第一晶体管M1与第二晶体管M2的控制端都耦接于驱动电路1010。第三晶体管M3耦接于第一节点N1与第一输出端O1之间，且第三晶体管M3的控制端用于接收第一参考电压Vref1。第四晶体管M4耦接于第一输出端O1与接地端GND之间，且第四晶体管M4的控制端用于接收第二参考电压Vref2。The first transistor M1 is coupled between the first power terminal In1 and the first node N1 for receiving the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first node N1 and the ground terminal GND, wherein the control terminals of the first transistor M1 and the second transistor M2 are both coupled to the driving circuit 1010 . The third transistor M3 is coupled between the first node N1 and the first output terminal O1, and the control terminal of the third transistor M3 is used for receiving the first reference voltage Vref1. The fourth transistor M4 is coupled between the first output terminal O1 and the ground terminal GND, and the control terminal of the fourth transistor M4 is used for receiving the second reference voltage Vref2.
第五晶体管M5耦接于第二电源端In2与第二节点N2之间，用于通过第二电源端In2接收第五参考电压Vref5。第六晶体管M6耦接于第二节点N2与接地端GND之间，其中第五晶体管M5与第六晶体管M6的控制端都耦接于驱动电路1010。第七晶体管M7耦接于第二节点N2与第二输出端O2之间，且第七晶体管M7的控制端用于接收第一参考电压Vref1。第八晶体管M8耦接于第二输出端O2与接地端GND之间，且第八晶体管M8的控制端用于接收第二参考电压Vref2。The fifth transistor M5 is coupled between the second power terminal In2 and the second node N2 for receiving the fifth reference voltage Vref5 through the second power terminal In2. The sixth transistor M6 is coupled between the second node N2 and the ground terminal GND, wherein the control terminals of the fifth transistor M5 and the sixth transistor M6 are both coupled to the driving circuit 1010 . The seventh transistor M7 is coupled between the second node N2 and the second output terminal O2, and the control terminal of the seventh transistor M7 is used for receiving the first reference voltage Vref1. The eighth transistor M8 is coupled between the second output terminal O2 and the ground terminal GND, and the control terminal of the eighth transistor M8 is used for receiving the second reference voltage Vref2.
驱动电路1010用于接收移位暂存器710[m]的前一级移位暂存器(亦即，移位暂存器710[m-1])输出的扫描脉冲CP，以及接收重置信号RS。图5的驱动电路510的其他连接方式、元件、实施方式以及优点，皆适用于驱动电路1010，为简洁起见，在此不重复赘述。The driving circuit 1010 is used to receive the scan pulse CP output by the previous stage shift register of the shift register 710[m] (that is, the shift register 710[m-1]), and receive the reset Signal RS. Other connection methods, components, implementations and advantages of the driving circuit 510 in FIG. 5 are all applicable to the driving circuit 1010 , and are not repeated here for the sake of brevity.
当移位暂存器710[2]～710[m-1]具有第一扫描顺序(例如，由图7的上方至下方依序输出扫描脉冲CP)时，第一参考电压Vref1会具有高电压准位且第二参考电压Vref2会具有低电压准位。因此，第三晶体管M3与第七晶体管M7会维持于导通状态，且第四晶体管M4与第八晶体管M8会维持于关断状态。When the shift registers 710[2]˜710[m-1] have a first scan sequence (for example, sequentially output scan pulses CP from top to bottom in FIG. 7), the first reference voltage Vref1 will have a high voltage level and the second reference voltage Vref2 has a low voltage level. Therefore, the third transistor M3 and the seventh transistor M7 are kept in the on state, and the fourth transistor M4 and the eighth transistor M8 are kept in the off state.
当移位暂存器710[m-1]输出扫描脉冲CP时，驱动电路1010会导通第一晶体管M1与第五晶体管M5，且关断第二晶体管M2与第六晶体管M6，以导通第一电源端In1与第一节点N1，以及导通第二电源端In2与第二节点N2。此时，第三参考电压Vref3会自第一电源端In1传递至第一输出端O1，并作为具有致能准位的第一下扫信号D1输出。第五参考电压Vref5会自第二电源端In2传递至第二输出端O2，并作为具有致能准位的第二下扫信号D2输出。When the shift register 710[m-1] outputs the scan pulse CP, the driving circuit 1010 will turn on the first transistor M1 and the fifth transistor M5, and turn off the second transistor M2 and the sixth transistor M6 to turn on The first power terminal In1 is connected to the first node N1, and the second power terminal In2 is connected to the second node N2. At this time, the third reference voltage Vref3 is transmitted from the first power supply terminal In1 to the first output terminal O1, and is output as the first down-scan signal D1 with an enable level. The fifth reference voltage Vref5 is transmitted from the second power supply terminal In2 to the second output terminal O2, and is output as a second down-scan signal D2 with an enable level.
另一方面，当驱动电路1010接收到重置信号RS的重置脉冲RP时，驱动电路1010会关断第一晶体管M1与第五晶体管M5，且导通第二晶体管M2与第六晶体管M6，以导通接地端GND与第一节点N1和第二节点N2。此时，接地电压便会自接地端GND传递至第一输出端O1和第二输出端O2，并作为具有禁能准位的第一下扫信号D1与第二下扫信号D2输出。On the other hand, when the driving circuit 1010 receives the reset pulse RP of the reset signal RS, the driving circuit 1010 will turn off the first transistor M1 and the fifth transistor M5, and turn on the second transistor M2 and the sixth transistor M6, To connect the ground terminal GND with the first node N1 and the second node N2. At this time, the ground voltage is transmitted from the ground terminal GND to the first output terminal O1 and the second output terminal O2, and is output as the first down-scan signal D1 and the second down-scan signal D2 with a disable level.
图11为依据本公开文件一实施例的移位暂存器710[1]简化后的电路图。移位暂存器710[1]与移位暂存器710[m]相似。差异在于，移位暂存器710[1]的第三晶体管M3与第七晶体管M7的控制端用于接收第二参考电压Vref2，第四晶体管M4与第八晶体管M8的控制端用于接收第一参考电压Vref1。另外，移位暂存器710[1]的第十驱动晶体管Tr10与第十一驱动晶体管Tr11的控制端分别用于接收起始信号ST与移位暂存器710[2]输出的扫描脉冲CP。因此，当移位暂存器710[2]～710[m-1]具有前述的第一扫描顺序时，移位暂存器710[1]的第三晶体管M3与第七晶体管M7会关断，而第四晶体管M4与第八晶体管M8会导通，以将第一上扫信号U1与第二上扫信号U2维持于禁能准位。FIG. 11 is a simplified circuit diagram of the shift register 710 [1] according to an embodiment of the disclosure. The shift register 710[1] is similar to the shift register 710[m]. The difference is that the control terminals of the third transistor M3 and the seventh transistor M7 of the shift register 710[1] are used to receive the second reference voltage Vref2, and the control terminals of the fourth transistor M4 and the eighth transistor M8 are used to receive the second reference voltage Vref2. A reference voltage Vref1. In addition, the control terminals of the tenth drive transistor Tr10 and the eleventh drive transistor Tr11 of the shift register 710[1] are respectively used to receive the start signal ST and the scan pulse CP output by the shift register 710[2] . Therefore, when the shift registers 710[2]˜710[m-1] have the aforementioned first scanning sequence, the third transistor M3 and the seventh transistor M7 of the shift register 710[1] are turned off. , and the fourth transistor M4 and the eighth transistor M8 are turned on to maintain the first up-scan signal U1 and the second up-scan signal U2 at a disable level.
在一实施例中，移位暂存器710[2]～710[m-1]具有第二扫描顺序(例如，由图7的下方至上方依序输出扫描脉冲CP)。此时，第一参考电压Vref1会具有低电压准位且第二参考电压Vref2会具有高电压准位。因此，移位暂存器210[1]的第三晶体管M3与第七晶体管M7会导通，而第四晶体管M4与第八晶体管M8会关断，以使移位暂存器210[1]能输出具有致能准位的第一上扫信号U1与第二上扫信号U2。另一方面，移位暂存器210[m]的第三晶体管M3与第七晶体管M7会关断，而第四晶体管M4与第八晶体管M8会导通，以使移位暂存器210[m]输出的第一下扫信号D1与第二下扫信号D2维持于禁能准位。In one embodiment, the shift registers 710 [ 2 ]˜ 710 [ m−1 ] have a second scan sequence (for example, sequentially output scan pulses CP from bottom to top in FIG. 7 ). At this time, the first reference voltage Vref1 has a low voltage level and the second reference voltage Vref2 has a high voltage level. Therefore, the third transistor M3 and the seventh transistor M7 of the shift register 210[1] are turned on, and the fourth transistor M4 and the eighth transistor M8 are turned off, so that the shift register 210[1] The first up-scan signal U1 and the second up-scan signal U2 with an enable level can be output. On the other hand, the third transistor M3 and the seventh transistor M7 of the shift register 210[m] are turned off, and the fourth transistor M4 and the eighth transistor M8 are turned on, so that the shift register 210[m] The first down-scan signal D1 and the second down-scan signal D2 output by m] are maintained at the disable level.
在一无需双向扫描的实施例中，可以省略图7的移位暂存器710[1]，并将移位暂存器710[2]由接收移位暂存器710[1]的扫描脉冲CP改为接收起始信号ST。另外，还可以省略切换电路810的第一上扫开关Tu1、第二上扫开关Tu2、第三上扫开关Tu3与第四上扫开关Tu4。In an embodiment that does not require bidirectional scanning, the shift register 710[1] of FIG. The CP instead receives a start signal ST. In addition, the first scan-up switch Tu1 , the second scan-up switch Tu2 , the third scan-up switch Tu3 , and the fourth scan-up switch Tu4 of the switching circuit 810 can also be omitted.
此外，还可以省略图10的第三晶体管M3、第四晶体管M4、第七晶体管M7与第八晶体管M8。在此情况下，第一下扫信号D1会改由移位暂存器710[m]的第一节点N1输出，而第二下扫信号D2会改由移位暂存器710[m]的第二节点N2输出。In addition, the third transistor M3 , the fourth transistor M4 , the seventh transistor M7 and the eighth transistor M8 in FIG. 10 can also be omitted. In this case, the first down-scan signal D1 will be output from the first node N1 of the shift register 710[m] instead, and the second down-scan signal D2 will be output from the first node N1 of the shift register 710[m] instead. The output of the second node N2.
图12为依据本公开文件又一实施例的栅极驱动器130简化后的功能方框图。在本实施例中，栅极驱动器130包含依序连接的移位暂存器1210[1]～1210[m]。移位暂存器1210[1]～1210[m]相似于图7的移位暂存器710[1]～710[m]。差异在于，本实施例的电力输入PW包含第一参考电压Vref1、第二参考电压Vref2与第四参考电压Vref4，移位暂存器1210[1]与移位暂存器1210[m]以接收第一防护信号ODD取代接收第三参考电压Vref3，且以接收第二防护信号EVEN取代接收第五参考电压Vref5。FIG. 12 is a simplified functional block diagram of a gate driver 130 according to yet another embodiment of the disclosure. In this embodiment, the gate driver 130 includes shift registers 1210[1]˜1210[m] connected in sequence. The shift registers 1210[1]˜1210[m] are similar to the shift registers 710[1]˜710[m] of FIG. 7 . The difference is that the power input PW of this embodiment includes the first reference voltage Vref1, the second reference voltage Vref2 and the fourth reference voltage Vref4, and the shift register 1210[1] and the shift register 1210[m] are used to receive The first protection signal ODD replaces receiving the third reference voltage Vref3 , and receives the second protection signal EVEN instead of receiving the fifth reference voltage Vref5 .
因此，在本实施例中，第一上扫信号U1、第二上扫信号U2、第一下扫信号D1与第二下扫信号D2的致能准位，会相同于第一防护信号ODD与第二防护信号EVEN的正极性电压或负极性电压。Therefore, in this embodiment, the enabling levels of the first up-scan signal U1, the second up-scan signal U2, the first down-scan signal D1, and the second down-scan signal D2 are the same as those of the first protection signal ODD and the second down-scan signal. Positive polarity voltage or negative polarity voltage of the second protection signal EVEN.
图13为依据本公开文件又一实施例的防漏电电路140的电路示意图。在本实施例中，防漏电电路140包含多个切换电路1310[1]～1310[n]。每个切换电路1310耦接于两条对应的垂直信号线VL，例如，切换电路1310[1]耦接于垂直信号线VL[1]与垂直信号线VL[2]，切换电路1310[2]耦接于垂直信号线VL[3]与垂直信号线VL[4]，依此类推，为简洁起见，在此不重复赘述。为方便理解，以下以切换电路1310[1]为例进行说明。FIG. 13 is a schematic circuit diagram of an anti-leakage circuit 140 according to yet another embodiment of the disclosure. In this embodiment, the anti-leakage circuit 140 includes a plurality of switching circuits 1310[1]˜1310[n]. Each switching circuit 1310 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 1310[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], and the switching circuit 1310[2] It is coupled to the vertical signal line VL[ 3 ] and the vertical signal line VL[ 4 ], and so on. For the sake of brevity, details are not repeated here. For the convenience of understanding, the switching circuit 1310[1] is taken as an example for description below.
切换电路1310[1]包含第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2。第一下扫开关Td1的第一端用于接收第一防护信号ODD。第一下扫开关Td1的第二端耦接于纵向驱动线VL[1]。第一下扫开关Td1的控制端用于接收第一下扫信号D1。第二下扫开关Td2的第一端用于接收第二防护信号EVEN。第二下扫开关Td2的第二端耦接于第二纵向驱动线VL[2]。第二下扫开关的控制端用于接收第二下扫信号D2。The switching circuit 1310[1] includes a first scan-down switch Td1, a second scan-down switch Td2, a first scan-up switch Tu1, and a second scan-up switch Tu2. The first end of the first down switch Td1 is used for receiving the first guard signal ODD. The second end of the first down switch Td1 is coupled to the vertical driving line VL[1]. The control terminal of the first down-scan switch Td1 is used for receiving the first down-scan signal D1. The first end of the second down switch Td2 is used for receiving the second protection signal EVEN. The second terminal of the second down scan switch Td2 is coupled to the second vertical driving line VL[2]. The control terminal of the second down-scan switch is used for receiving the second down-scan signal D2.
第一上扫开关Tu1的第一端用于接收第一防护信号ODD。第一上扫开关Tu1的第二端耦接于纵向驱动线VL[1]。第一上扫开关Tu1的控制端用于接收第一上扫信号U1。第二上扫开关Tu2的第一端用于接收第二防护信号EVEN。第二上扫开关Tu2的第二端耦接于纵向驱动线VL[2]。第二上扫开关Tu2的控制端用于接收第二上扫信号U2。The first terminal of the first scan-up switch Tu1 is used for receiving the first guard signal ODD. The second terminal of the first scan-up switch Tu1 is coupled to the vertical driving line VL[1]. The control terminal of the first up-scan switch Tu1 is used for receiving the first up-scan signal U1. The first terminal of the second scan-up switch Tu2 is used for receiving the second protection signal EVEN. The second terminal of the second up-scan switch Tu2 is coupled to the vertical driving line VL[2]. The control terminal of the second up-scan switch Tu2 is used for receiving the second up-scan signal U2.
前述切换电路1310[1]的连接方式、元件、实施方式以及优点，皆适用于切换电路1310[2]～1310[n]，为简洁起见，在此不重复赘述。The aforementioned connection methods, components, implementations and advantages of the switching circuit 1310[1] are all applicable to the switching circuits 1310[2]˜1310[n], and are not repeated here for the sake of brevity.
图14为依据本公开文件又一实施例的显示装置100的运行方式示意图。以下将以图12、图13与图14来说明显示装置100的运行。在第一扫描阶段中，第一上扫信号U1、第二上扫信号U2、第一下扫信号D1与第二下扫信号D2具有禁能准位。因此，第一上扫开关Tu1、第二上扫开关Tu2、第一下扫开关Td1与第二下扫开关Td2被关断。FIG. 14 is a schematic diagram of the operation mode of the display device 100 according to another embodiment of the present disclosure. The operation of the display device 100 will be described below with reference to FIG. 12 , FIG. 13 and FIG. 14 . In the first scan phase, the first up-scan signal U1 , the second up-scan signal U2 , the first down-scan signal D1 and the second down-scan signal D2 have a disable level. Therefore, the first scan-up switch Tu1 , the second scan-up switch Tu2 , the first scan-down switch Td1 and the second scan-down switch Td2 are turned off.
此时，索引为奇数的垂直信号线VL会接收到正极性的电压，而索引为偶数的垂直信号线VL则会接收到负极性的电压。At this time, the vertical signal lines VL with an odd index receive a positive polarity voltage, and the vertical signal lines VL with an even index receive a negative polarity voltage.
在第一维持阶段中，第一防护信号ODD具有正极性的电压(例如，2.5V)，第二防护信号EVEN具有负极性的电压(例如，-2.5V)。第一下扫信号D1会切换至第一致能准位，其中第一致能准位相同于第一防护信号ODD的正极性电压。第二下扫信号D2会切换至第二致能准位，其中第二致能准位相同于第二防护信号EVEN的负极性电压。因此，第一下扫开关Td1与第二下扫开关Td2会被导通，而第一上扫开关Tu1与第二上扫开关Tu2会被关断。In the first sustaining phase, the first protection signal ODD has a positive polarity voltage (for example, 2.5V), and the second protection signal EVEN has a negative polarity voltage (for example, −2.5V). The first down-scan signal D1 is switched to a first enabling level, wherein the first enabling level is equal to the positive polarity voltage of the first protection signal ODD. The second down-scan signal D2 is switched to a second enabling level, wherein the second enabling level is equal to the negative polarity voltage of the second protection signal EVEN. Therefore, the first scan-down switch Td1 and the second scan-down switch Td2 are turned on, and the first scan-up switch Tu1 and the second scan-up switch Tu2 are turned off.
此时，第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有正极性的电压。第二防护信号EVEN会经由第二下扫开关Td2传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有负极性的电压。因此，垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。At this time, the first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first scan-down switch Td1 , so that the vertical signal line VL with an odd index has a positive voltage. The second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down-sweep switch Td2 , so that the even-numbered vertical signal line VL has a negative polarity voltage. Therefore, leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is alleviated.
在第二扫描阶段中，第一上扫信号U1、第二上扫信号U2、第一下扫信号D1与第二下扫信号D2具有禁能准位。因此，第一上扫开关Tu1、第二上扫开关Tu2、第一下扫开关Td1与第二下扫开关Td2会再度被关断。In the second scan phase, the first up-scan signal U1 , the second up-scan signal U2 , the first down-scan signal D1 and the second down-scan signal D2 have a disable level. Therefore, the first scan-up switch Tu1 , the second scan-up switch Tu2 , the first scan-down switch Td1 and the second scan-down switch Td2 are turned off again.
此时，索引为奇数的垂直信号线VL会接收到负极性的电压，而索引为偶数的垂直信号线VL则会接收到正极性的电压。At this time, the vertical signal lines VL with an odd index receive a voltage of negative polarity, while the vertical signal lines VL with an even index receive a voltage of positive polarity.
在第二维持阶段中，第一防护信号ODD具有负极性的电压，第二防护信号EVEN具有正极性的电压。第一下扫信号D1会切换至第二致能准位，其中第致二能准位相同于第一防护信号ODD的负极性电压。第二下扫信号D2会切换至第一致能准位，其中第一致能准位相同于第二防护信号EVEN的正极性电压。因此，第一下扫开关Td1与第二下扫开关Td2会被导通，而第一上扫开关Tu1与第二上扫开关Tu2会被关断。In the second sustain phase, the first protection signal ODD has a voltage of negative polarity, and the second protection signal EVEN has a voltage of positive polarity. The first down-scan signal D1 is switched to a second enable level, wherein the second enable level is the same as the negative polarity voltage of the first protection signal ODD. The second down-scan signal D2 is switched to a first enable level, wherein the first enable level is equal to the positive polarity voltage of the second protection signal EVEN. Therefore, the first scan-down switch Td1 and the second scan-down switch Td2 are turned on, and the first scan-up switch Tu1 and the second scan-up switch Tu2 are turned off.
此时，第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有负极性的电压。第二防护信号EVEN会经由第二下扫开关Td2传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有正极性的电压。因此，垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。At this time, the first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first scan-down switch Td1 , so that the vertical signal line VL with an odd index has a negative polarity voltage. The second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down-sweep switch Td2 , so that the even-numbered vertical signal line VL has a positive voltage. Therefore, leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is alleviated.
图15为依据本公开文件一实施例的移位暂存器1210[m]简化后的电路图。移位暂存器1210[m]相似于图10的移位暂存器710[m]，差异在于，移位暂存器1210[m]的第一晶体管M1的第一端与第五晶体管M5的第一端分别用于接收第一防护信号ODD与第二防护信号EVEN。FIG. 15 is a simplified circuit diagram of a shift register 1210[m] according to an embodiment of the disclosure. The shift register 1210[m] is similar to the shift register 710[m] of FIG. The first ends of the first terminals are respectively used to receive the first protection signal ODD and the second protection signal EVEN.
当移位暂存器1210[1]～1210[m]具有第一扫描顺序(例如，由图12的上方往下方输出扫描脉冲CP)时，第一参考电压Vref1具有高电压准位，而第二参考电压Vref2具有低电压准位。因此，第一防护信号ODD会做为具有第一致能准位或第二致能准位的第一下扫信号D1输出，而第二防护信号EVEN会作为具有第一致能准位或第二致能准位的第二下扫信号D2输出。When the shift registers 1210[1]˜1210[m] have the first scan sequence (for example, the scan pulse CP is output from top to bottom in FIG. 12 ), the first reference voltage Vref1 has a high voltage level, and the second reference voltage Vref1 has a high voltage level. The second reference voltage Vref2 has a low voltage level. Therefore, the first protection signal ODD will be output as the first downscan signal D1 with the first or second enable level, and the second protection signal EVEN will be output as the first or second enable level The second down-scan signal D2 of the second enable level is output.
由上述可知，在第一维持阶段与第二维持阶段中，第一防护信号ODD与第二防护信号EVEN的波形彼此相反，第一下扫信号D1与第一防护信号ODD的电压准位相同，第二下扫信号D2与第二防护信号EVEN的电压准位相同。前述移位暂存器710[m]的其余连接方式、元件、实施方式以及优点，皆适用于移位暂存器1210[m]，为简洁起见，在此不重复赘述。It can be seen from the above that in the first sustaining phase and the second sustaining phase, the waveforms of the first protection signal ODD and the second protection signal EVEN are opposite to each other, and the voltage levels of the first downscan signal D1 and the first protection signal ODD are the same. The voltage level of the second down-scan signal D2 is the same as that of the second protection signal EVEN. The rest of the connections, components, implementations and advantages of the aforementioned shift register 710[m] are all applicable to the shift register 1210[m], and are not repeated here for the sake of brevity.
图16为依据本公开文件一实施例的移位暂存器1210[1]简化后的电路图。移位暂存器1210[1]相似于图11的移位暂存器710[1]，差异在于，移位暂存器1210[1]的第一晶体管M15的第一端与第五晶体管M5的第一端分别用于接收第一防护信号ODD与第二防护信号EVEN。前述移位暂存器710[1]的其余连接方式、元件、实施方式以及优点，皆适用于移位暂存器1210[1]，为简洁起见，在此不重复赘述。FIG. 16 is a simplified circuit diagram of the shift register 1210 [1] according to an embodiment of the disclosure. The shift register 1210[1] is similar to the shift register 710[1] in FIG. The first ends of the first terminals are respectively used to receive the first protection signal ODD and the second protection signal EVEN. The rest of the connections, components, implementations and advantages of the aforementioned shift register 710[1] are all applicable to the shift register 1210[1]. For the sake of brevity, the details are not repeated here.
在一实施例中，移位暂存器1210[1]～1210[m]具有第二扫描顺序(例如，由图12的下方往上方输出扫描脉冲CP)，且第一参考电压Vref1具有低电压准位，而第二参考电压Vref2具有高电压准位。因此，第一防护信号ODD会做为具有第一致能准位或第二致能准位的第一上拉信号U1被输出，第二防护信号EVEN会作为具有第一致能准位或第二致能准位的第二上拉信号U2被输出。此时，于第一维持阶段与第二维持阶段中，第一上拉开关Tu1与第二上拉开关Tu2会被导通，而第一下拉开关Td1与第二下拉开关Td2会被关断。In one embodiment, the shift registers 1210[1]˜1210[m] have a second scan sequence (for example, the scan pulse CP is output from bottom to top in FIG. 12 ), and the first reference voltage Vref1 has a low voltage level, and the second reference voltage Vref2 has a high voltage level. Therefore, the first protection signal ODD will be output as the first pull-up signal U1 with the first enable level or the second enable level, and the second protection signal EVEN will be output as the first pull-up signal U1 with the first enable level or the second enable level. The second pull-up signal U2 of the two enable levels is output. At this time, in the first sustaining phase and the second sustaining phase, the first pull-up switch Tu1 and the second pull-up switch Tu2 are turned on, and the first pull-down switch Td1 and the second pull-down switch Td2 are turned off. .
在此情况下，在第一维持阶段与第二维持阶段中，第一防护信号ODD与第二防护信号EVEN的波形彼此相反，第一上扫信号U1与第一防护信号ODD的电压准位相同，第二上扫信号U2与第二防护信号EVEN的电压准位相同。In this case, in the first sustaining phase and the second sustaining phase, the waveforms of the first protection signal ODD and the second protection signal EVEN are opposite to each other, and the voltage levels of the first up-scan signal U1 and the first protection signal ODD are the same. , the voltage level of the second up-scan signal U2 is the same as that of the second protection signal EVEN.
由上述可知，由于使用第一防护信号ODD与第二防护信号EVEN取代第三参考电压Vref3与第五参考电压Vref5，图12的栅极驱动器130具有走线简单的优点。From the above, it can be known that the gate driver 130 in FIG. 12 has the advantage of simple wiring because the first protection signal ODD and the second protection signal EVEN are used to replace the third reference voltage Vref3 and the fifth reference voltage Vref5 .
在一实施例中，为了抵销第一下拉开关Td1、第二下拉开关Td2、第一上拉开关Tu1与第二上拉开关Tu2的临界电压的影响，第一防护信号ODD与第二防护信号EVEN被设置为原本的电压准位再加上前述的临界电压。In one embodiment, in order to offset the influence of the threshold voltages of the first pull-down switch Td1, the second pull-down switch Td2, the first pull-up switch Tu1 and the second pull-up switch Tu2, the first guard signal ODD and the second guard The signal EVEN is set to the original voltage level plus the aforementioned threshold voltage.
例如，第一防护信号ODD与第二防护信号EVEN的正极性电压被设置为2.5V+Vth，负极性电压被设置为-2.5V+Vth，其中Vth表示第一下拉开关Td1、第二下拉开关Td2、第一上拉开关Tu1或第二上拉开关Tu2的临界电压。For example, the positive polarity voltage of the first protection signal ODD and the second protection signal EVEN is set to 2.5V+Vth, and the negative polarity voltage is set to -2.5V+Vth, wherein Vth represents the first pull-down switch Td1, the second pull-down The threshold voltage of the switch Td2, the first pull-up switch Tu1 or the second pull-up switch Tu2.
在一无需双向扫描的实施例中，可以省略图12的移位暂存器1210[1]，并将移位暂存器1210[2]由接收移位暂存器1210[1]的扫描脉冲CP改为接收起始信号ST。另外，还可以省略切换电路1310的第一上扫开关Tu1与第二上扫开关Tu2。In an embodiment that does not require bidirectional scanning, the shift register 1210[1] of FIG. The CP instead receives a start signal ST. In addition, the first scan-up switch Tu1 and the second scan-up switch Tu2 of the switching circuit 1310 can also be omitted.
此外，还可以省略图15的第三晶体管M3、第四晶体管M4、第七晶体管M7与第八晶体管M8。在此情况下，第一下扫信号D1会改由移位暂存器1210[m]的第一节点N1输出，而第二下扫信号D2会改由移位暂存器1210[m]的第二节点N2输出。In addition, the third transistor M3 , the fourth transistor M4 , the seventh transistor M7 and the eighth transistor M8 of FIG. 15 can also be omitted. In this case, the first down-scan signal D1 will be output from the first node N1 of the shift register 1210[m] instead, and the second down-scan signal D2 will be output from the first node N1 of the shift register 1210[m] instead. The output of the second node N2.
图17为依据本公开文件再一实施例的栅极驱动器130简化后的功能方框图。栅极驱动器130包含多级依序连接的移位暂存器1710[1]～1710[m]。移位暂存器1710[1]～1710[m]用于接收时脉信号CK、反向时脉信号XCK。移位暂存器1710[1]与移位暂存器1710[m]还用于接收电力输入PW，在本实施例中，电力输入PW包含第一参考电压Vref1、第二参考电压Vref2、第三参考电压Vref3与第四参考电压Vref4。FIG. 17 is a simplified functional block diagram of a gate driver 130 according to yet another embodiment of the disclosure. The gate driver 130 includes a plurality of sequentially connected shift registers 1710[1]˜1710[m]. The shift registers 1710[1]˜1710[m] are used to receive the clock signal CK and the reverse clock signal XCK. The shift register 1710[1] and the shift register 1710[m] are also used to receive the power input PW. In this embodiment, the power input PW includes the first reference voltage Vref1, the second reference voltage Vref2, the second The third reference voltage Vref3 and the fourth reference voltage Vref4.
另外，移位暂存器1710[1]用于接收起始信号ST，并用于输出第一控制信号群组CTL1。移位暂存器1710[m]用于接收重置信号RS，并用于输出第二控制信号群组CTL2。在本实施例中，第一控制信号群组CTL1包含第一上扫信号U1、第二上扫信号U2与第三上扫信号U3，第二控制信号群组CTL2包含第一下扫信号D1、第二下扫信号D2与第三下扫信号D3。移位暂存器1710[2]～1720[m-1]则用于对应输出多个扫描信号Gn[1]～Gn[y]至水平驱动线HL[1]～HL[y]。In addition, the shift register 1710[1] is used for receiving the start signal ST, and is used for outputting the first control signal group CTL1. The shift register 1710[m] is used for receiving the reset signal RS, and is used for outputting the second control signal group CTL2. In this embodiment, the first control signal group CTL1 includes the first up-scan signal U1, the second up-scan signal U2, and the third up-scan signal U3, and the second control signal group CTL2 includes the first down-scan signal D1, The second down-scan signal D2 and the third down-scan signal D3. The shift registers 1710[2]˜1720[m−1] are used to correspondingly output a plurality of scanning signals Gn[1]˜Gn[y] to the horizontal driving lines HL[1]˜HL[y].
图18为依据本公开文件再一实施例的防漏电电路140的电路示意图。防漏电电路140包含多个切换电路1810[1]～1810[n]。每个切换电路1810耦接于两条对应的垂直信号线VL，例如，切换电路1810[1]耦接于垂直信号线VL[1]与垂直信号线VL[2]，切换电路1810[2]耦接于垂直信号线VL[3]与垂直信号线VL[4]，依此类推，为简洁起见，在此不重复赘述。FIG. 18 is a schematic circuit diagram of an anti-leakage circuit 140 according to yet another embodiment of the disclosure. The anti-leakage circuit 140 includes a plurality of switching circuits 1810[1]˜1810[n]. Each switching circuit 1810 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 1810[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], and the switching circuit 1810[2] It is coupled to the vertical signal line VL[ 3 ] and the vertical signal line VL[ 4 ], and so on. For the sake of brevity, details are not repeated here.
在本实施例中，为了减轻信号线上的负载，相邻的切换电路1810是由不同的信号线控制，且信号线的分布是以三个切换电路1810为一循环。例如，切换电路1810[1]是由第一上扫信号U1与第一下扫信号D1控制，切换电路1810[2]是由第二上扫信号U2与第二下扫信号D2控制，切换电路1810[3]是由第三上扫信号U3与第三下扫信号D3控制，而切换电路1810[4]又再度由第一上扫信号U1与第一下扫信号D1控制，以此类推。为方便理解，以下以切换电路1810[1]、切换电路1810[2]与切换电路1810[3]为例进行说明。In this embodiment, in order to reduce the load on the signal lines, adjacent switching circuits 1810 are controlled by different signal lines, and the distribution of the signal lines is based on three switching circuits 1810 as a cycle. For example, the switching circuit 1810[1] is controlled by the first up-scan signal U1 and the first down-scan signal D1, the switching circuit 1810[2] is controlled by the second up-scan signal U2 and the second down-scan signal D2, and the switching circuit 1810[3] is controlled by the third up-scan signal U3 and the third down-scan signal D3, and the switching circuit 1810[4] is again controlled by the first up-scan signal U1 and the first down-scan signal D1, and so on. For the convenience of understanding, the switching circuit 1810[1], the switching circuit 1810[2] and the switching circuit 1810[3] are taken as examples for illustration below.
针对切换电路1810[1]而言，切换电路1810[1]包含第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2。第一下扫开关Td1的第一端用于接收第一防护信号ODD。第一下扫开关Td1的第二端耦接于第一纵向驱动线VL[1]。第一下扫开关Td1的控制端用于接收第一下扫信号D1。第二下扫开关Td2的第一端用于接收第二防护信号EVEN。第二下扫开关Td2的第二端耦接于第二纵向驱动线VL[2]。第二下扫开关Td2的控制端用于接收第一下扫信号D1。第一上扫开关Tu1的第一端用于接收第一防护信号ODD。第一上扫开关Tu1的第二端耦接于第一纵向驱动线VL[1]。第一上扫开关Tu1的控制端用于接收第一上扫信号U1。第二上扫开关Tu2的第一端用于接收第二防护信号EVEN。第二上扫开关Tu2的第二端耦接于第二纵向驱动线VL[2]。第二上扫开关Tu2的控制端用于接收第一上扫信号U1。For the switch circuit 1810[1], the switch circuit 1810[1] includes a first scan-down switch Td1, a second scan-down switch Td2, a first scan-up switch Tu1, and a second scan-up switch Tu2. The first end of the first down switch Td1 is used for receiving the first guard signal ODD. The second end of the first down switch Td1 is coupled to the first vertical driving line VL[1]. The control terminal of the first down-scan switch Td1 is used for receiving the first down-scan signal D1. The first end of the second down switch Td2 is used for receiving the second protection signal EVEN. The second terminal of the second down scan switch Td2 is coupled to the second vertical driving line VL[2]. The control terminal of the second down-scan switch Td2 is used for receiving the first down-scan signal D1. The first terminal of the first scan-up switch Tu1 is used for receiving the first guard signal ODD. The second end of the first scan switch Tu1 is coupled to the first vertical driving line VL[1]. The control terminal of the first up-scan switch Tu1 is used for receiving the first up-scan signal U1. The first terminal of the second scan-up switch Tu2 is used for receiving the second protection signal EVEN. The second terminal of the second up-scan switch Tu2 is coupled to the second vertical driving line VL[2]. The control terminal of the second up-scan switch Tu2 is used for receiving the first up-scan signal U1.
如图18所示，于切换电路1810[2]和切换电路1810[3]中，第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2的连接方式相似于切换电路1810[1]。差异在于，针对切换电路1810[2]而言，第一下扫开关Td1与第二下扫开关Td2是由第二下扫信号D2控制，且分别耦接于纵向驱动线VL[3]与纵向驱动线VL[4]，第一上扫开关Tu1与第二上扫开关Tu2是由第二上扫信号U2控制，且分别耦接于纵向驱动线VL[3]与纵向驱动线VL[4]。As shown in Figure 18, in the switching circuit 1810[2] and the switching circuit 1810[3], the first scan-down switch Td1, the second scan-down switch Td2, the first scan-up switch Tu1 and the second scan-up switch Tu2 The connection is similar to the switching circuit 1810 [1]. The difference is that, for the switch circuit 1810[2], the first scan-down switch Td1 and the second scan-down switch Td2 are controlled by the second scan-down signal D2, and are respectively coupled to the vertical drive line VL[3] and the vertical drive line VL[3]. The drive line VL[4], the first up-scan switch Tu1 and the second up-scan switch Tu2 are controlled by the second up-scan signal U2, and are respectively coupled to the vertical drive line VL[3] and the vertical drive line VL[4] .
另一项差异在于，针对切换电路1810[3]而言，第一下扫开关Td1与第二下扫开关Td2是由第三下扫信号D3控制，且分别耦接于纵向驱动线VL[5]与纵向驱动线VL[6]，第一上扫开关Tu1与第二上扫开关Tu2是由第三上扫信号U3控制，且分别耦接于纵向驱动线VL[5]与纵向驱动线VL[6]。Another difference is that, for the switch circuit 1810[3], the first scan-down switch Td1 and the second scan-down switch Td2 are controlled by the third scan-down signal D3, and are respectively coupled to the vertical driving line VL[5 ] and the vertical drive line VL[6], the first up-scan switch Tu1 and the second up-scan switch Tu2 are controlled by the third up-scan signal U3, and are respectively coupled to the vertical drive line VL[5] and the vertical drive line VL [6].
前述以切换电路1810[1]、切换电路1810[2]与切换电路1810[3]为一循环的连接方式，亦适用于切换电路1810[4]～1810[n]，为简洁起见，在此不重复赘述。The aforementioned connection mode of switching circuit 1810[1], switching circuit 1810[2] and switching circuit 1810[3] is also applicable to switching circuits 1810[4]-1810[n], for the sake of brevity, here Do not repeat the details.
图19为依据本公开文件再一实施例的显示装置100的运行方式示意图。以下将以图17、图18与图19来说明显示装置100的运行。于第一扫描阶段中，第一上扫信号U1、第二上扫信号2、第三上扫信号U3、第一下扫信号D1、第二下扫信号D2与第三下扫信号D3具有禁能准位。多工信号群组Mu具有致能准位。当移位暂存器1710[1]接收到触发信号ST提供的起始脉冲SP时，移位暂存器1710[2]～1710[m-1]会依序输出扫描脉冲CP。FIG. 19 is a schematic diagram of the operation mode of the display device 100 according to yet another embodiment of the present disclosure. The operation of the display device 100 will be described below with reference to FIG. 17 , FIG. 18 and FIG. 19 . In the first scanning stage, the first up-scan signal U1, the second up-scan signal 2, the third up-scan signal U3, the first down-scan signal D1, the second down-scan signal D2 and the third down-scan signal D3 have prohibited Can align. The multiplexing signal group Mu has an enable level. When the shift register 1710[1] receives the start pulse SP provided by the trigger signal ST, the shift registers 1710[2]˜1710[m-1] will sequentially output the scan pulse CP.
因此，第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2会被关断。此时，索引为奇数的垂直信号线VL会接收到正极性的电压，索引为偶数的垂直信号线VL则会接收到负极性的电压。Therefore, the first scan-down switch Td1 , the second scan-down switch Td2 , the first scan-up switch Tu1 and the second scan-up switch Tu2 are turned off. At this time, the vertical signal lines VL with an odd index receive a positive polarity voltage, and the vertical signal lines VL with an even index receive a negative polarity voltage.
于第一维持阶段中，第一上扫信号U1、第二上扫信号U2与第三上扫信号U3具有禁能准位，第一下扫信号D1、第二下扫信号D2与第三下扫信号D3则切换至致能准位。多工信号群组Mu具有禁能准位。第一防护信号ODD具有正极性的电压，而第二防护信号EVEN具有负极性的电压。In the first sustaining phase, the first up-scan signal U1, the second up-scan signal U2 and the third up-scan signal U3 have a disable level, the first down-scan signal D1, the second down-scan signal D2 and the third down-scan signal The scan signal D3 is switched to the enabling level. The multiplexing signal group Mu has a disable level. The first protection signal ODD has a positive voltage, and the second protection signal EVEN has a negative voltage.
因此，第一下扫开关Td1与第二下扫开关Td2会被导通，而第一上扫开关Tu1与第二上扫开关Tu2会维持于关断状态。此时，第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有正极性的电压。第二防护信号EVEN会经由第二下扫开关Td2传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有负极性的电压。因此，垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。Therefore, the first scan-down switch Td1 and the second scan-down switch Td2 are turned on, and the first scan-up switch Tu1 and the second scan-up switch Tu2 are kept in an off state. At this time, the first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first scan-down switch Td1 , so that the vertical signal line VL with an odd index has a positive voltage. The second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down-sweep switch Td2 , so that the even-numbered vertical signal line VL has a negative polarity voltage. Therefore, leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is alleviated.
于第二扫描阶段中，第一上扫信号U1、第二上扫信号2、第三上扫信号U3、第一下扫信号D1、第二下扫信号D2与第三下扫信号D3具有禁能准位。多工信号群组Mu具有致能准位。当移位暂存器1710[1]再度接收到触发信号ST提供的起始脉冲SP时，移位暂存器1710[2]～1710[m-1]会再度依序输出扫描脉冲CP。In the second scanning stage, the first up-scan signal U1, the second up-scan signal 2, the third up-scan signal U3, the first down-scan signal D1, the second down-scan signal D2, and the third down-scan signal D3 have prohibited Can align. The multiplexing signal group Mu has an enable level. When the shift register 1710[1] receives the start pulse SP provided by the trigger signal ST again, the shift registers 1710[2]˜1710[m-1] will sequentially output the scan pulse CP again.
因此，第一下扫开关Td1、第二下扫开关Td2、第一上扫开关Tu1与第二上扫开关Tu2会再度被关断。此时，索引为奇数的垂直信号线VL会接收到负极性的电压，索引为偶数的垂直信号线VL则会接收到正极性的电压。Therefore, the first scan-down switch Td1 , the second scan-down switch Td2 , the first scan-up switch Tu1 and the second scan-up switch Tu2 are turned off again. At this time, the vertical signal lines VL with an odd index receive a voltage of negative polarity, and the vertical signal lines VL with an even index receive a voltage of positive polarity.
于第二维持阶段中，第一上扫信号U1、第二上扫信号2与第三上扫信号U3具有禁能准位，第一下扫信号D1、第二下扫信号D2与第三下扫信号D3则切换至致能准位。多工信号群组Mu具有禁能准位。第一防护信号ODD具有负极性的电压，而第二防护信号EVEN具有正极性的电压。In the second sustaining phase, the first up-scan signal U1, the second up-scan signal 2 and the third up-scan signal U3 have a disable level, the first down-scan signal D1, the second down-scan signal D2 and the third down-scan signal The scan signal D3 is switched to the enabling level. The multiplexing signal group Mu has a disable level. The first guard signal ODD has a voltage of negative polarity, and the second guard signal EVEN has a voltage of positive polarity.
因此，第一下扫开关Td1与第二下扫开关Td2会被导通，而第一上扫开关Tu1与第二上扫开关Tu2会维持于关断状态。此时，第一防护信号ODD会经由第一下扫开关Td1传递至索引为奇数的垂直信号线VL，使得索引为奇数的垂直信号线VL具有负极性的电压。第二防护信号EVEN会经由第二下扫开关Td2传递至索引为偶数的垂直信号线VL，使得索引为偶数的垂直信号线VL具有正极性的电压。因此，垂直信号线VL与对应的像素电路150之间的漏电流得以减轻。Therefore, the first scan-down switch Td1 and the second scan-down switch Td2 are turned on, and the first scan-up switch Tu1 and the second scan-up switch Tu2 are kept in an off state. At this time, the first protection signal ODD is transmitted to the vertical signal line VL with an odd index through the first scan-down switch Td1 , so that the vertical signal line VL with an odd index has a negative polarity voltage. The second protection signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down-sweep switch Td2 , so that the even-numbered vertical signal line VL has a positive voltage. Therefore, leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is alleviated.
图20为依据本公开文件一实施例的移位暂存器1710[m]简化后的电路图。移位暂存器1710[m]包含第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8与驱动电路2010。驱动电路2010用于接收移位暂存器1710[m]的前一级移位暂存器(亦即，移位暂存器1710[m-1])输出的扫描脉冲CP，以及接收重置信号RS、第一参考电压Vref1、第二参考电压Vref2、第三参考电压Vref3与第四参考电压Vref4。FIG. 20 is a simplified circuit diagram of the shift register 1710[m] according to an embodiment of the disclosure. The shift register 1710[m] includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and Drive circuit 2010. The driving circuit 2010 is used to receive the scan pulse CP output by the shift register of the previous stage of the shift register 1710[m] (that is, the shift register 1710[m-1]), and receive the reset The signal RS, the first reference voltage Vref1 , the second reference voltage Vref2 , the third reference voltage Vref3 and the fourth reference voltage Vref4 .
前述驱动电路510的其余连接方式、元件、实施方式以及优点，皆适用于驱动电路2010，为简洁起见，在此不重复赘述。The rest of the connections, components, implementations and advantages of the aforementioned driving circuit 510 are all applicable to the driving circuit 2010 , and are not repeated here for the sake of brevity.
第一晶体管M1耦接于第一电源端In1与第一节点N1之间，其中第一晶体管M1通过第一电源端In1接收第三参考电压Vref3。第二晶体管M2耦接于该第一节点N1与接地端GND之间，其中第一晶体管M1与第二晶体管M2的控制端皆耦接于驱动电路2010。第三晶体管M3耦接于第一节点N1与第一输出端O1之间。第四晶体管M4耦接于第一节点N1与第二输出端O2之间。第五晶体管M5耦接于第一节点N1与第三输出端O3之间，其中第三晶体管M3、第四晶体管M4与第五晶体管M5的控制端皆用于接收第一参考电压Vref1。The first transistor M1 is coupled between the first power terminal In1 and the first node N1, wherein the first transistor M1 receives the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first node N1 and the ground terminal GND, wherein the control terminals of the first transistor M1 and the second transistor M2 are both coupled to the driving circuit 2010 . The third transistor M3 is coupled between the first node N1 and the first output terminal O1. The fourth transistor M4 is coupled between the first node N1 and the second output terminal O2. The fifth transistor M5 is coupled between the first node N1 and the third output terminal O3, wherein the control terminals of the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are all used to receive the first reference voltage Vref1.
第六晶体管M6耦接于第一输出端O1与接地端GND之间。第七晶体管M7耦接于第二输出端O2与接地端GND之间。第八晶体管M8耦接于第三输出端O3与接地端GND之间，其中第六晶体管M6、第七晶体管M7与第八晶体管M8的控制端皆用于接收第二参考电压Vref2。The sixth transistor M6 is coupled between the first output terminal O1 and the ground terminal GND. The seventh transistor M7 is coupled between the second output terminal O2 and the ground terminal GND. The eighth transistor M8 is coupled between the third output terminal O3 and the ground terminal GND, wherein the control terminals of the sixth transistor M6 , the seventh transistor M7 and the eighth transistor M8 are all used to receive the second reference voltage Vref2 .
当移位暂存器1710[2]～210[m-1]具有第一扫描顺序(例如，由图17的上方至下方依序输出扫描脉冲CP)时，第一参考电压Vref1会具有高电压准位且第二参考电压Vref2会具有低电压准位。因此，第三晶体管M3、第四晶体管M4与第五晶体管M5会维持于导通状态，第六晶体管M6、第七晶体管M7与第八晶体管M8会维持于关断状态。When the shift registers 1710[2]˜210[m-1] have a first scan sequence (for example, sequentially output scan pulses CP from top to bottom in FIG. 17), the first reference voltage Vref1 will have a high voltage level and the second reference voltage Vref2 has a low voltage level. Therefore, the third transistor M3 , the fourth transistor M4 and the fifth transistor M5 are kept in the on state, and the sixth transistor M6 , the seventh transistor M7 and the eighth transistor M8 are kept in the off state.
当移位暂存器1710[m-1]输出扫描脉冲CP时，驱动电路2010会导通第一晶体管M1并关断第二晶体管M2，以导通第一电源端In1与第一节点N1。此时，第三参考电压Vref3便会自第一电源端In1传递至第一输出端O1、第二输出端O2与第三输出端O3，并作为具有致能准位的第一下扫信号D1、第二下扫信号D2与第三下扫信号D3输出。When the shift register 1710[m−1] outputs the scan pulse CP, the driving circuit 2010 turns on the first transistor M1 and turns off the second transistor M2, so as to turn on the first power terminal In1 and the first node N1. At this time, the third reference voltage Vref3 is transmitted from the first power supply terminal In1 to the first output terminal O1, the second output terminal O2, and the third output terminal O3, and serves as the first down-scan signal D1 with an enable level. , The second down-scan signal D2 and the third down-scan signal D3 are output.
另一方面，当驱动电路2010接收到重置脉冲RP时，驱动电路2010会关断第一晶体管M1并导通第二晶体管M2，以导通第一节点N1与接地端GND。此时，接地电压便会自接地端GND传递至第一输出端O1、第二输出端O2与第三输出端O3，并作为具有禁能准位的第一下扫信号D1、第二下扫信号D2与第三下扫信号D3输出。On the other hand, when the driving circuit 2010 receives the reset pulse RP, the driving circuit 2010 turns off the first transistor M1 and turns on the second transistor M2 to connect the first node N1 and the ground terminal GND. At this time, the ground voltage will be transmitted from the ground terminal GND to the first output terminal O1, the second output terminal O2 and the third output terminal O3, and serve as the first down-scan signal D1 and the second down-scan signal with a disable level. The signal D2 and the third downscanning signal D3 are output.
图21为依据本公开文件一实施例的第一级移位暂存器1710[1]简化后的电路图。移位暂存器1710[1]与移位暂存器1710[m]相似。差异在于，移位暂存器1710[1]的第三晶体管M3、第四晶体管M4与第五晶体管M5的控制端用于接收第二参考电压Vref2，且第六晶体管M6、第七晶体管M7与第八晶体管M8的控制端用于接收第一参考电压Vref1。另外，移位暂存器1710[1]的第十四晶体管M14与第十五晶体管M15的控制端分别用于接收起始信号ST与移位暂存器1710[2]输出的扫描脉冲CP。FIG. 21 is a simplified circuit diagram of the first-stage shift register 1710[1] according to an embodiment of the disclosure. Shift register 1710[1] is similar to shift register 1710[m]. The difference is that the control terminals of the third transistor M3, the fourth transistor M4 and the fifth transistor M5 of the shift register 1710[1] are used to receive the second reference voltage Vref2, and the sixth transistor M6, the seventh transistor M7 and the The control terminal of the eighth transistor M8 is used for receiving the first reference voltage Vref1. In addition, the control terminals of the fourteenth transistor M14 and the fifteenth transistor M15 of the shift register 1710[1] are respectively used to receive the start signal ST and the scan pulse CP output by the shift register 1710[2].
因此，当移位暂存器1710[2]～1710[m-1]具有前述的第一扫描顺序时，移位暂存器1710[1]的第三晶体管M3、第四晶体管M4与第五晶体管M5会被关断，而第六晶体管M6、第七晶体管M7与第八晶体管M8会被导通，以将第一上扫信号U1、第二上扫信号U2与第三上扫信号U3维持于禁能准位。Therefore, when the shift registers 1710[2]˜1710[m-1] have the aforementioned first scanning order, the third transistor M3, the fourth transistor M4 and the fifth transistor M4 of the shift register 1710[1] The transistor M5 is turned off, and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned on to maintain the first up-scan signal U1, the second up-scan signal U2 and the third up-scan signal U3 In the prohibition level.
在一实施例中，移位暂存器1710[2]～1710[m-1]具有第二扫描顺序(例如，由图17的下方至上方依序输出扫描脉冲CP)。此时，第一参考电压Vref1会具有低电压准位，且第二参考电压Vref2会具有高电压准位。因此，移位暂存器1710[1]的第三晶体管M3、第四晶体管M4与第五晶体管M5会被导通，而第六晶体管M6、第七晶体管M7与第八晶体管M8会被关断，以使移位暂存器210[1]能够输出具有致能准位的第一上扫信号U1、第二上扫信号U2与第三上扫信号U3。另一方面，移位暂存器1710[m]的第三晶体管M3、第四晶体管M4与第五晶体管M5会被关断，而第六晶体管M6、第七晶体管M7与第八晶体管M8则会被导通，以使移位暂存器1710[m]输出的第一下扫信号D1、第二下扫信号D2与第三下扫信号D3维持于禁能准位。In one embodiment, the shift registers 1710[2]˜1710[m−1] have a second scanning order (for example, sequentially outputting the scanning pulse CP from bottom to top in FIG. 17 ). At this moment, the first reference voltage Vref1 has a low voltage level, and the second reference voltage Vref2 has a high voltage level. Therefore, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 of the shift register 1710[1] are turned on, and the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off. , so that the shift register 210 [ 1 ] can output the first up-scan signal U1 , the second up-scan signal U2 and the third up-scan signal U3 with enable levels. On the other hand, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 of the shift register 1710[m] are turned off, and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off. is turned on, so that the first down-scan signal D1 , the second down-scan signal D2 and the third down-scan signal D3 output from the shift register 1710[m] are maintained at the disabled level.
在一无需双向扫描的实施例中，可以省略图17的移位暂存器1710[1]，并将移位暂存器1710[2]由接收移位暂存器1710[1]的扫描脉冲CP改为接收起始信号ST。另外，还可以省略切换电路1810的第一上扫开关Tu1与第二上扫开关Tu2。In an embodiment that does not require bidirectional scanning, the shift register 1710[1] of FIG. The CP instead receives a start signal ST. In addition, the first scan-up switch Tu1 and the second scan-up switch Tu2 of the switching circuit 1810 can also be omitted.
此外，还可以将移位暂存器1710[m]替换为图22所示的移位暂存器2200。移位暂存器2200包含第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4与驱动电路2210。第一晶体管M1耦接于第一电源端In1与第一输出端O1之间，且第一晶体管M1通过第一电源端In1接收第三参考电压Vref3。第二晶体管M2耦接于第一输出端O1与接地端GND之间。第三晶体管M3耦接于第二电源端In2与第二输出端O2之间，且第三晶体管M3通过第二电源端In2接收第五参考电压Vref5。第四晶体管M4耦接于第二输出端O2与接地端GND之间。其中，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4的控制端皆耦接于驱动电路2210。In addition, the shift register 1710[m] can also be replaced with the shift register 2200 shown in FIG. 22 . The shift register 2200 includes a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 and a driving circuit 2210 . The first transistor M1 is coupled between the first power terminal In1 and the first output terminal O1, and the first transistor M1 receives the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first output terminal O1 and the ground terminal GND. The third transistor M3 is coupled between the second power terminal In2 and the second output terminal O2, and the third transistor M3 receives the fifth reference voltage Vref5 through the second power terminal In2. The fourth transistor M4 is coupled between the second output terminal O2 and the ground terminal GND. Wherein, the control terminals of the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 are all coupled to the driving circuit 2210 .
驱动电路2110相似于图20的的驱动电路2010，差异在于驱动电路2210的第一驱动晶体管Tr1的第一端用于接收第六参考电压Vref6。当移位暂存器1710[m-1]输出扫描脉冲CP时，驱动电路2110会导通第一驱动晶体管Tr1、第一晶体管M1、第三晶体管M3，并关断第三驱动晶体管Tr3、第二晶体管M2与第四晶体管M4。The driving circuit 2110 is similar to the driving circuit 2010 of FIG. 20 , the difference is that the first terminal of the first driving transistor Tr1 of the driving circuit 2210 is used to receive the sixth reference voltage Vref6 . When the shift register 1710[m-1] outputs the scanning pulse CP, the driving circuit 2110 will turn on the first driving transistor Tr1, the first transistor M1, and the third transistor M3, and turn off the third driving transistor Tr3, the third transistor The second transistor M2 and the fourth transistor M4.
此时，第三参考电压Vref3会传递至第三内部节点P3，并作为具有致能准位的第一下扫信号D1输出。第第六参考电压Vref6会传递至第一输出端O1，并作为具有致能准位的第二下扫信号D2输出。第五参考电压Vref5会传递至第二输出端O2，并作为具有致能准位的第三下扫信号D3输出。At this time, the third reference voltage Vref3 is transmitted to the third internal node P3 and output as the first down-scan signal D1 with an enable level. The sixth reference voltage Vref6 is transmitted to the first output terminal O1 and output as the second downscan signal D2 with an enable level. The fifth reference voltage Vref5 is delivered to the second output terminal O2 and output as the third down-scan signal D3 with enable level.
另一方面，当驱动电路2210接收到重置脉冲RP时，驱动电路2210会关断第一驱动晶体管Tr1、第一晶体管M1、第三晶体管M3，并导通第三驱动晶体管Tr3、第二晶体管M2与第四晶体管M4。此时，接地电压便会作为具有禁能准位的第一下扫信号D1、第二下扫信号D2与第三下扫信号D3输出。On the other hand, when the drive circuit 2210 receives the reset pulse RP, the drive circuit 2210 will turn off the first drive transistor Tr1, the first transistor M1, and the third transistor M3, and turn on the third drive transistor Tr3, the second transistor M2 and the fourth transistor M4. At this time, the ground voltage is output as the first down-scan signal D1 , the second down-scan signal D2 and the third down-scan signal D3 with the disable level.
由上述可知，当显示装置100暂停更新显示画面时，显示装置100可防止像素电路150与垂直驱动线VL之间产生漏电流。因此，显示装置100可提供高品质的显示画面。It can be seen from the above that when the display device 100 suspends updating the display frame, the display device 100 can prevent the leakage current between the pixel circuit 150 and the vertical driving line VL. Therefore, the display device 100 can provide high-quality display images.
在说明书及权利要求中使用了某些词汇来指称特定的元件。然而，所属技术领域中技术人员应可理解，同样的元件可能会用不同的名词来称呼。说明书及权利要求并不以名称的差异做为区分元件的方式，而是以元件在功能上的差异来做为区分的基准。在说明书及权利要求所提及的“包含”为开放式的用语，故应解释成“包含但不限定于”。另外，“耦接”在此包含任何直接及间接的连接手段。因此，若文中描述第一元件耦接于第二元件，则代表第一元件可通过电性连接或无线传输、光学传输等信号连接方式而直接地连接于第二元件，或者通过其他元件或连接手段间接地电性或信号连接至该第二元件。Certain terms are used in the description and claims to refer to particular elements. However, those skilled in the art should understand that the same element may be called by different terms. The specification and claims do not use the difference in name as the way to distinguish components, but the difference in function of the components as the basis for distinction. The "comprising" mentioned in the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.
在此所使用的“及/或”的描述方式，包含所列举的其中的一或多个项目的任意组合。另外，除非说明书中特别指明，否则任何单数格的用语都同时包含复数格的涵义。The description of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes plural meanings.
以上仅为本公开文件的优选实施例，凡依本公开文件权利要求所做的均等变化与修饰，皆应属本公开文件的涵盖范围。The above are only preferred embodiments of the disclosure, and all equivalent changes and modifications made in accordance with the claims of the disclosure shall fall within the scope of the disclosure.
| Application Number | Priority Date | Filing Date | Title |
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| US201862717260P | 2018-08-10 | 2018-08-10 | |
| US62/717,260 | 2018-08-10 | ||
| TW108101701 | 2019-01-16 | ||
| TW108101701ATWI680450B (en) | 2018-08-10 | 2019-01-16 | Display device and gate driving circuit |
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| CN110379393Atrue CN110379393A (en) | 2019-10-25 |
| CN110379393B CN110379393B (en) | 2022-01-11 |
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| CN201910696361.7AActiveCN110379393B (en) | 2018-08-10 | 2019-07-30 | Display device and gate driver |
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