In the embodiment of the invention, the target timing signal is determined according to the type and the sequence of the timing segments of the timing signal in the timing setting instruction, and the timing signal of the specified type can be generated, so that the timing of different types of I2C equipment is met. After a new I2C device with different time sequences is added, a new register does not need to be added, the time sequence of the existing register does not need to be modified, the generation of a time sequence signal which accords with the time sequence of the new I2C device is realized through a time sequence setting instruction, the use of the newly added I2C device can be facilitated, and the time cost is saved.

Optionally, the logic circuit board further includes:

and the control register is used for receiving a time sequence control instruction, and determining a port communicated with the I2C device to be interacted as a target port according to the time sequence control instruction, wherein the time sequence control instruction comprises the identification of the I2C device to be interacted.

Correspondingly, the executingmodule 302 is further configured to implement transmission of a target timing signal with the to-be-interacted I2C device through the target port.

When a plurality of I2C devices exist, the control register determines a port for communicating with the I2C device to be interacted as a target port through a timing control instruction. Theexecution module 302 implements transmission of the target timing signal with the above-mentioned I2C device to be interacted through the target port, and can implement interaction with a specific I2C device, thereby enabling simultaneous communication with a plurality of I2C devices.

Optionally, referring to fig. 4, the logic circuit board includes:

a plurality oftiming setting registers 301;

thecontrol register 303 is further configured to receive a timing setting instruction, allocate a correspondingtiming setting register 301 to the device to be interacted I2C, and send the timing setting instruction to thetiming setting register 301 corresponding to the device to be interacted I2C.

Thecontrol register 303 receives the timing control command and the timing setting command, selects an idletiming setting register 301 as thetiming setting register 301 corresponding to the I2C device to be interacted, and sends the timing setting command to thetiming setting register 301, so that thetiming setting register 301 configures the content of the target timing signal according to the timing setting command.

Thecontrol register 303 is responsible for transceiving control, and is set as shown in table 2; thetiming setting register 301 is responsible for setting a timing signal and transmitting and receiving data for each Byte, and the setting is shown in table 3.

TABLE 2

TABLE 3

In the embodiment of the invention, one time sequence setting register realizes the time sequence of one I2C device, can prevent the interference of time sequence signals of different I2C devices, does not need queue waiting among different I2C devices, and can improve the communication efficiency.

Optionally, theexecution module 302 may include multiple I2C controllers.

When the logic circuit board only comprises one I2C controller, the I2C bus of the I2C controller can mount a plurality of I2C devices, and if one I2C device has a problem, signals can be killed, so that timing signals of other I2C devices cannot be transmitted through the I2C bus. In the logic circuit of the embodiment of the present invention, theexecution module 302 includes a plurality of independent I2C controllers, each I2C controller controls one or several I2C devices, so that when an abnormality occurs in a certain I2C device, interaction of I2C devices responsible for other I2C controllers is not affected, thereby enhancing the disaster tolerance capability of the logic circuit board, wherein the other I2C controllers are I2C controllers other than the I2C controller responsible for the abnormal I2C device.

Optionally, taking a read/write operation of a temperature sensor as an example, the settings of the control register and the timing setting register are as follows:

writing 0x7826 to register 0x38 of the I2C device (I2C device address 0x20), issuing from port 7 of the logic board:

I2C_TSR0＝((0x20<<0)|0x1)|(0x1<<16)；

I2C_TSR1＝0x38|(0x2<<16)；

I2C_TSR2＝0x26|(0x3<<16)；

I2C_TSR3＝0x78|(0x3<<16)；

I2C_CSR＝0x7|(0x4<<8)|(0x1<<16)；

read 16bit data from I2C device (device address 0x20) register 0x38, issuing from port 7 of the logic board:

I2C_TSR0＝((0x20<<1)|0x0)|(0x1<<16)；

I2C_TSR1＝0x38|(0x2<<16)；

I2C_TSR2＝((0x20<<1)|0x0)|(0x1<<16)；

I2C _ TSR3 ═ 0x0| (0x4< < 16); // read data registerdata portion 0

I2C _ TSR4 ═ 0x0| (0x4< < 16); // read data registerdata portion 0

I2C_CSR＝0x7|(0x5<<8)|(0x1<<16)；

Wherein, I2C _ TSR is the setting of the timing setting register, and I2C _ CSR is the setting of the control register.

And configuring the time sequence setting register and the control register into the setting through the time sequence setting instruction and the time sequence control instruction, so as to realize the read/write operation aiming at the temperature sensor. Similarly, the specified configuration of the timing setting register and the control register can be realized by the timing setting instruction and the timing control instruction, so that the configuration of the I2C timing of any plurality of bytes can be realized.

Optionally, in the logic circuit board according to the embodiment of the present invention, the content of the target timing signal includes a timing segment representing a number of bytes read/written continuously;

the logic circuit board further includes:

For some types of I2C devices, for example: EEPROM (Electrically Erasable Programmable Read Only Memory) and the like require continuous reading and writing of a large amount of data. For this case, a timing segment for continuously reading and writing the number of bytes is configured in the timing setting register, and is used to control the number of bytes of the continuously read/written digits. Correspondingly, a continuous read-write buffer is arranged in the logic circuit board and used for caching continuous read/write data.

Optionally, taking the read/write operation of the EEPROM as an example, the settings of the control register and the timing setting register are as follows:

data of 0x80 length is written to a register of EEPROM (EEPROM address 0XA0), issued from port 7 of the logic circuit board:

writing data with the length of 0x80 into a continuous writing buffer area in a continuous reading and writing buffer area, wherein the data are sequentially sent out by an execution module of a logic circuit board after starting sending, and the sent length is configured through a time sequence setting register:

I2C _ TSR0 ═ ((0xA0< <0) |0x1) | (0x1< < 16); I2C Port and Address of write Slave

I2C _ TSR1 ═ 0x01| (0x2< < 16); // configuring the high 8 bits of the EEPROM offset Address to be written

I2C _ TSR2 ═ 0x80| (0x2< < 16); v/configuring the lower 8 bits of the EEPROM offset Address to be written

I2C _ TSR3 ═ 0x80| (0x6< < 16); // configuring the number of bytes of data written consecutively

I2C _ CSR ═ 0x7| (0x4< <8) | (0x1< < 16); // initiate transmission through port 7

Data of 0x80 length is read from a register of EEPROM (EEPROM address 0XA0), issued from port 7 of the logic circuit board:

I2C _ TSR1 ═ 0x01| (0x2< < 16); // configuring the high 8 bits of EEPROM offset addresses that need to be read

I2C _ TSR2 ═ 0x80| (0x2< < 16); // configuring the lower 8 bits of the EEPROM offset Address to be read

I2C _ TSR3 ═ 0x80| (0x5< < 16); // configuring the number of bytes of consecutive read data

I2C _ CSR ═ 0x7| (0x4< <8) | (0x1< < 16); // initiating a read through port 7

The data read from the EEPROM is buffered in a continuous read buffer of a continuous read-write buffer, and the master device can read data of 0x80 in length from the continuous read buffer.

In the embodiment of the invention, continuous reading and writing of data are realized by representing the time sequence segment of the continuous reading/writing byte number and the continuous reading and writing buffer area, and aiming at the data to be read and written with the byte number larger than 8 bits, the redundancy of time sequence signals can be reduced, the resource consumption of a time sequence setting register is reduced, and the communication efficiency between the master equipment and the slave equipment is improved.

The embodiment of the invention provides a method for generating a time sequence signal of I2C equipment, which is applied to a logic circuit board and comprises the following steps:

s501, receiving a time sequence setting instruction sent by the master device, wherein the time sequence setting instruction carries the type and the sequence of a time sequence fragment of a time sequence signal of the I2C device to be interacted.

The method for generating the I2C device timing signal in the embodiment of the present invention may be implemented by a timing system, and the timing system is any system capable of implementing the method for generating the I2C device timing signal in the embodiment of the present invention. For example: the timing system may be a device for executing the I2C device timing signal generating method according to the embodiment of the present invention, for example, the timing system is a logic circuit board; the timing system can also be an application program used for executing the I2C device timing signal generation method in the embodiment of the invention when running; the timing system may also be a storage medium for storing executable code for performing the I2C device timing signal generation method of embodiments of the present invention.

S502, generating a target time-series signal according to the type and sequence of the time-series segment of the time-series signal in the time-series setting command.

And generating a target time-series signal including the time-series segments of the types arranged according to the sequence according to the type and the sequence of the time-series segments of the time-series signals in the time-series setting command.

In the embodiment of the invention, the target time sequence signal is determined according to the type and the sequence of the time sequence segment of the time sequence signal in the time sequence setting instruction, and the time sequence signal of the specified type can be produced, so that the time sequence of different types of I2C equipment is met. After a new I2C device with different time sequences is added, a new register does not need to be added, the time sequence of the existing register does not need to be modified, the generation of a time sequence signal which accords with the time sequence of the new I2C device is realized through a time sequence setting instruction, the use of the newly added I2C device can be facilitated, and the time cost is saved.

Optionally, the method for generating a timing signal of I2C device according to the embodiment of the present invention further includes:

step one, receiving a time sequence control instruction sent by the master device, wherein the time sequence control instruction carries an identifier of the device to be interacted with I2C.

The identification of the device to be interacted with, I2C, may be the address of the device to be interacted with, I2C, the name of the device to be interacted with, I2C, and the like.

And step two, determining a port of the logic circuit board, which is communicated with the I2C equipment to be interacted, as a target port according to the identification of the I2C equipment to be interacted.

After the generating the target timing signal, the method further includes:

and completing the transmission of the target timing signal between the target port and the device to be interacted I2C.

And the target port is utilized to complete the transmission of the target timing signals between the logic circuit board and the I2C equipment to be interacted.

In the embodiment of the invention, the port of the logic circuit board, which is communicated with the I2C device to be interacted, is determined as the target port through the sequential control instruction. And through the target port, the transmission of target time sequence signals between the logic circuit and the I2C equipment to be interacted is realized, the interaction aiming at the specified I2C equipment can be realized, and the communication with a plurality of I2C equipment can be realized simultaneously.

For some I2C devices, for example: EEPROM, etc., which require continuous reading and writing of large amounts of data. For this case, a timing segment characterizing the number of consecutive read/write bytes is configured for controlling the number of consecutive read/write digits.

In the embodiment of the invention, the continuous reading and writing of data are realized by representing the time sequence segment of the number of bytes continuously read/written, and aiming at the data to be read and written with the number of bytes larger than 8 bits, the redundancy of time sequence signals can be effectively reduced, and the communication efficiency between the master equipment and the slave equipment is improved.

An embodiment of the present invention further provides a method for generating a timing signal of I2C device, which is applied to a master device, and with reference to fig. 6, the method includes:

s601, a read-write operation instruction is obtained, wherein the read-write operation instruction is an instruction for executing specified operation on the device to be interacted with I2C.

The method for generating the I2C device timing signal in the embodiment of the invention can be realized by a main device, wherein the main device is a terminal device, such as a smart phone, a computer or a single chip microcomputer. The read-write operation instruction can be input by a user or transmitted by other terminal equipment.

S602, generating a timing setting instruction for the read/write operation instruction, where the timing setting instruction carries a kind and a sequence of a timing segment of a timing signal.

Optionally, the generating a time sequence setting instruction for the read-write operation instruction includes:

step one, regarding the type of the device to be interacted with I2C, to which the read-write operation instruction is directed, as a target type, and regarding a specified operation executed by the read-write operation instruction as a target operation.

And step two, inquiring a preset type operation time sequence table, and determining the type and the sequence of the time sequence segments of the time sequence signals corresponding to the target operation in the target type, wherein the preset type operation time sequence table records the type and the sequence of the time sequence segments of the time sequence signals respectively corresponding to various specified operations in different I2C equipment types.

And step three, generating a time sequence setting instruction according to the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type.

The preset type operation timing table records timing signals of various specified operations of various types of I2C equipment, including the types and the sequence of various timing segments forming the timing signals. And inquiring a preset type operation time sequence table, determining the type and the sequence of a time sequence segment of a time sequence signal for executing specified operation in the type of the I2C equipment to be interacted, and generating a time sequence setting instruction.

S603, the time sequence setting instruction is sent to a logic circuit board, so that the logic circuit board generates a target time sequence signal according to the time sequence setting instruction.

And sending a time sequence setting instruction to the logic circuit board so that the logic circuit board receives the time sequence setting instruction and generates a target time sequence signal according to the type and the sequence of the time sequence segments of the time sequence signal in the time sequence setting instruction.

Optionally, the method for generating the I2C device timing signal applied to the master device further includes:

step one, generating a time sequence control instruction aiming at the read-write operation instruction, wherein the time sequence control instruction carries an identifier of the I2C device to be interacted.

And determining the identifier of the I2C device to be interacted, which is aimed at by the read-write operation instruction, and generating a time sequence control instruction carrying the identifier of the I2C device to be interacted.

And step two, sending the time sequence control instruction to the logic circuit board so that the logic circuit board determines a target port according to the time sequence control instruction, and completing transmission of the target time sequence signal between the logic circuit board and the to-be-interacted I2C equipment through the target port.

An embodiment of the present invention provides an I2C device timing signal generating apparatus, which is applied to a logic circuit board, and with reference to fig. 7, the apparatus includes:

a settinginstruction receiving module 701, configured to receive a timing setting instruction sent by a master device, where the timing setting instruction carries a type and an order of a timing segment of a timing signal for an I2C device to be interacted;

the timingsignal generating module 702 is configured to generate a target timing signal according to the type and the sequence of the timing segment of the timing signal in the timing setting instruction.

Optionally, the apparatus for generating a timing signal applied to the logic circuit board I2C further includes:

and a time sequence signal transmission module, configured to complete transmission of the target time sequence signal between the target port and the to-be-interacted I2C device.

An embodiment of the present invention provides an I2C device timing signal generating apparatus, which is applied to a master device, and with reference to fig. 8, the apparatus includes:

an operationinstruction obtaining module 801, configured to obtain a read-write operation instruction, where the read-write operation instruction is an instruction for executing a specified operation on an I2C device to be interacted;

a settinginstruction generating module 802, configured to generate a timing setting instruction for the read/write operation instruction, where the timing setting instruction carries a type and an order of a timing segment of a timing signal;

a settinginstruction sending module 803, configured to send the timing setting instruction to a logic circuit board, so that the logic circuit board generates a target timing signal according to the timing setting instruction.

Optionally, the apparatus for generating a device timing signal applied to the master device I2C further includes:

a control instruction generating module, configured to generate a timing control instruction for the read/write operation instruction, where the timing control instruction carries an identifier of the I2C device to be interacted;

and a control instruction sending module, configured to send the timing control instruction to the logic circuit board, so that the logic circuit board determines a target port according to the timing control instruction, and completes transmission of the target timing signal between the logic circuit board and the to-be-interacted I2C device through the target port.

Optionally, the settinginstruction generating module 802 includes:

a target query submodule, configured to query a preset type operation timing sequence table, and determine a type and a sequence of a timing segment of a timing signal corresponding to the target operation in the target type, where the preset type operation timing sequence table records the type and the sequence of the timing segment of the timing signal corresponding to each specified operation in different I2C device types;

An embodiment of the present invention provides an electronic device, see fig. 9, including aprocessor 901 and amemory 902, where thememory 902 is used to store a computer program; theprocessor 901 is configured to implement the following steps when executing the program stored in the memory 902:

Optionally, theprocessor 901 is configured to implement any one of the methods for generating the I2C device timing signal applied to the master device when executing the program stored in thememory 902.

Optionally, the electronic device further includes a communication interface and a communication bus, where theprocessor 901, the communication interface, and thememory 902 complete mutual communication through the communication bus.

The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the electronic equipment and other equipment.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements the following steps:

and generating the target time sequence signal according to the type and the sequence of the time sequence segments of the time sequence signal in the time sequence setting command.

Optionally, when being executed by a processor, the computer program can also implement any one of the methods for generating the I2C device timing signal applied to the logic circuit board.

Optionally, the computer program, when executed by the processor, is further capable of implementing any one of the methods for generating I2C device timing signals applied to the master device.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present specification are described in a related manner, each embodiment focuses on differences from other embodiments, and the same and similar parts in the embodiments are referred to each other.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for generating I2C equipment timing signals is applied to a logic circuit board, and the method comprises the following steps:

receiving a time sequence setting instruction sent by a master device, wherein the time sequence setting instruction carries the type and the sequence of a time sequence fragment of a time sequence signal of an I2C device to be interacted, and the time sequence setting instruction generating method comprises the following steps: taking the type of the I2C equipment to be interacted, which is aimed at by the read-write operation instruction, as a target type, and taking the specified operation executed by the read-write operation instruction as a target operation; inquiring a preset type operation time sequence table, and determining the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type, wherein the preset type operation time sequence table records the type and the sequence of the time sequence segment of the time sequence signal corresponding to each appointed operation in different I2C equipment types; generating a time sequence setting instruction according to the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type;

2. The method of claim 1, further comprising:

after the generating the target timing signal, the method further comprises:

3. The method of claim 1 or 2, wherein the target timing signal comprises a timing slice for characterizing a number of bytes read/written consecutively to enable consecutive reading/writing of data.

4. An I2C device timing signal generation method, applied to a master device, the method comprising:

generating a time sequence setting instruction according to the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type, wherein the time sequence setting instruction carries the type and the sequence of the time sequence segment of the time sequence signal;

5. The method of claim 4, further comprising:

6. An I2C equipment sequence signal generating device, which is applied to a logic circuit board, the device comprises:

the setting instruction receiving module is used for receiving a time sequence setting instruction sent by a master device, wherein the time sequence setting instruction carries the type and the sequence of a time sequence fragment of a time sequence signal of the I2C device to be interacted, and the time sequence setting instruction generating method comprises the following steps: taking the type of the I2C equipment to be interacted, which is aimed at by the read-write operation instruction, as a target type, and taking the specified operation executed by the read-write operation instruction as a target operation; inquiring a preset type operation time sequence table, and determining the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type, wherein the preset type operation time sequence table records the type and the sequence of the time sequence segment of the time sequence signal corresponding to each appointed operation in different I2C equipment types; generating a time sequence setting instruction according to the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type;

7. The apparatus of claim 6, further comprising:

8. The apparatus of claim 6 or 7, wherein the target timing signal comprises a timing slice for characterizing a number of bytes read/written consecutively to enable consecutive reading/writing of data.

9. An apparatus for generating I2C device timing signals, applied to a master device, the apparatus comprising:

a set instruction generating module, the set instruction generating module comprising:

the instruction generation submodule is used for generating a time sequence setting instruction according to the type and the sequence of the time sequence fragment of the time sequence signal corresponding to the target operation in the target type, wherein the time sequence setting instruction carries the type and the sequence of the time sequence fragment of the time sequence signal;

10. The apparatus of claim 9, further comprising:

11. A logic circuit board, comprising:

a time sequence setting register and an execution module;

the time sequence setting register is used for receiving a time sequence setting instruction, and configuring the content of a target time sequence signal for the I2C equipment to be interacted according to the type and the sequence of a time sequence fragment of the time sequence signal in the time sequence setting instruction, wherein the time sequence setting instruction generating method comprises the following steps: taking the type of the I2C equipment to be interacted, which is aimed at by the read-write operation instruction, as a target type, and taking the specified operation executed by the read-write operation instruction as a target operation; inquiring a preset type operation time sequence table, and determining the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type, wherein the preset type operation time sequence table records the type and the sequence of the time sequence segment of the time sequence signal corresponding to each appointed operation in different I2C equipment types; generating a time sequence setting instruction according to the type and the sequence of the time sequence segment of the time sequence signal corresponding to the target operation in the target type;

12. The logic circuit board of claim 11, further comprising:

13. The logic circuit board of claim 12, wherein the logic circuit board comprises:

a plurality of timing setting registers;

14. The logic circuit board of claim 12 or 13, wherein the content of the target timing signal includes a timing slice representing the number of bytes read/written consecutively;

the logic circuit board further includes:

15. An electronic device comprising a processor and a memory, wherein the memory is configured to store a computer program; the processor, when executing the program stored in the memory, implementing the method steps of any of claims 4-5.

16. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any one of the claims 1-3.

17. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any of the claims 4-5.