技术领域technical field
本发明涉及场效应晶体管器件领域，尤其涉及一种基于准零维接触的二维薄膜埋栅场效应晶体管。The invention relates to the field of field effect transistor devices, in particular to a two-dimensional film buried gate field effect transistor based on a quasi-zero-dimensional contact.
背景技术Background technique
随着摩尔定律的发展，集成电路中晶体管的特征尺寸越来越小，电路规模越来越大。然而随着尺寸的缩小，硅基集成电路的短沟道效应也就愈发明显，甚至会导致电路失效。而二维薄膜具有克服短沟道效应的特性，替换硅基材料成为集成电路主流材料具有巨大的潜力。与此同时，电路规模不断扩大对单个晶体管的驱动能力及电流开关比提出了更高的要求，然而现有对于如何减少晶体管，尤其是二维材料晶体管的接触电阻，增大晶体管的电流开关比以获得更高的驱动能力仍然是研究的重点。With the development of Moore's Law, the feature size of transistors in integrated circuits is getting smaller and smaller, and the circuit scale is getting bigger and bigger. However, as the size shrinks, the short-channel effect of silicon-based integrated circuits becomes more and more obvious, and may even lead to circuit failure. The two-dimensional thin film has the characteristics of overcoming the short channel effect, and it has great potential to replace silicon-based materials and become the mainstream material of integrated circuits. At the same time, the continuous expansion of circuit scale puts forward higher requirements for the driving capability and current switching ratio of a single transistor. However, how to reduce the contact resistance of transistors, especially two-dimensional material transistors, and increase the current switching ratio of transistors To obtain higher driving ability is still the focus of research.
传统的晶体管电极和二维材料之间的接触是采用溅射和电子束蒸发的方法制备，该方法虽然拥有工艺简单、易于大面积制备等优点，但是由于溅射和电子束蒸发所产生的靶金属原子能量高，非常容易造成二维材料的表面损伤，从而引入更多的表面能级，使得接触势垒变高，晶体管性能变差。The contact between the traditional transistor electrode and the two-dimensional material is prepared by sputtering and electron beam evaporation. Although this method has the advantages of simple process and easy large-area preparation, the target produced by sputtering and electron beam evaporation The high energy of metal atoms is very easy to cause surface damage of two-dimensional materials, thereby introducing more surface energy levels, making the contact barrier higher and transistor performance worse.
为了提高二维材料晶体管的驱动能力，降低接触电阻，目前采用的方法包括电极转移法和准一维接触法。In order to improve the driving ability of two-dimensional material transistors and reduce contact resistance, the methods currently used include electrode transfer method and quasi-one-dimensional contact method.
电极转移(完美的面接触)法，是利用胶带等方式反复粘黏二维晶体并利用有机物(如PDMS等)将二维材料附着在有机物上，利用显微镜对准，定点转移到已制备完毕的晶体管电极上，从而完成二维晶体管的制备。利用该方法可极大减少电极淀积过程中对于二维材料的损伤，降低电极-二维材料接触表面能级，从而降低接触势垒，提高晶体管开态电流。但该方法存在不易于制备复杂电路和难以与传统硅基工艺兼容等缺点。The electrode transfer (perfect surface contact) method is to use adhesive tape and other methods to repeatedly stick two-dimensional crystals and use organic matter (such as PDMS, etc.) to attach the two-dimensional material to the organic matter. On the transistor electrodes, thus completing the fabrication of two-dimensional transistors. Using this method can greatly reduce the damage to the two-dimensional material during the electrode deposition process, reduce the electrode-two-dimensional material contact surface energy level, thereby reducing the contact barrier and increasing the on-state current of the transistor. However, this method has the disadvantages that it is not easy to prepare complex circuits and is difficult to be compatible with traditional silicon-based processes.
准一维接触(线接触)法是利用边缘接触和碳纳米管等材料，使得接触形成准一维接触，实验验证该接触可以提升接触性能。然而缺点是制备工艺复杂，难以集成化和制备复杂电路。The quasi-one-dimensional contact (line contact) method uses materials such as edge contacts and carbon nanotubes to make the contact form a quasi-one-dimensional contact. Experiments have verified that the contact can improve the contact performance. However, the disadvantage is that the preparation process is complicated, and it is difficult to integrate and prepare complex circuits.
与此同时，由于硅基晶体管基于热载流子发射原理限制，存在亚阈值摆幅60mV/dec的理论极限，但新型超陡亚阈值摆幅器件能够大大减少泄露电流，降低静态功耗，因此受到了广泛关注，目前的超陡亚阈值摆幅器件主要分为三类：隧穿晶体管，负电容晶体管，纳电动继电器。At the same time, due to the limitation of silicon-based transistors based on the principle of hot carrier emission, there is a theoretical limit of subthreshold swing of 60mV/dec, but the new ultra-steep subthreshold swing device can greatly reduce leakage current and reduce static power consumption, so It has received extensive attention, and the current ultra-steep subthreshold swing devices are mainly divided into three categories: tunneling transistors, negative capacitance transistors, and nanoelectric relays.
隧穿晶体管主要利用在衬底上相反掺杂的半导体材料以完成更低的亚阈值摆幅。隧穿晶体管的工作原理主要是通过控制栅极电压，以完成本征区能带的变化，进而控制因量子隧道效应而产生的电流而获得低的亚阈值摆幅。Tunneling transistors mainly use oppositely doped semiconductor materials on the substrate to achieve lower subthreshold swing. The working principle of the tunneling transistor is mainly to complete the change of the energy band of the intrinsic region by controlling the gate voltage, and then control the current generated by the quantum tunneling effect to obtain a low sub-threshold swing.
负电容晶体管主要在栅极上利用铁电材料以完成更低的亚阈值摆幅。负电容晶体管的工作原理主要是利用铁电材料的负电容特性，以完成对于栅极电压的放大作用，以实现低的亚阈值摆幅。Negative capacitance transistors mainly use ferroelectric materials on the gate to achieve lower subthreshold swing. The working principle of the negative capacitance transistor is mainly to use the negative capacitance characteristics of the ferroelectric material to amplify the gate voltage to achieve a low sub-threshold swing.
纳电动继电器主要是利用横向致动的继电器以完成更低的亚阈值摆幅。纳电动继电器的工作原理主要是利用悬梁和漏极之间的静电力，以完成器件的抬起与合上，以实现低的亚阈值摆幅。Nanoelectric relays mainly utilize laterally actuated relays to achieve lower subthreshold swings. The working principle of the nanoelectric relay is mainly to use the electrostatic force between the suspension beam and the drain to complete the lifting and closing of the device to achieve a low sub-threshold swing.
从以上表述可以表明，降低接触的维度，有利于提升晶体管的性能。但目前，无论是主流工艺，抑或是科学研究中，晶体管中电极和沟道材料都无法达到准零维的接触(点接触)。如何实现准零维接触下的晶体管从而改进二维材料晶体管的性能，并同时提高二维材料晶体管的驱动电流表现，成为了亟待解决的问题。From the above expressions, it can be shown that reducing the dimension of the contact is beneficial to improving the performance of the transistor. But at present, whether it is the mainstream process or scientific research, the electrodes and channel materials in transistors cannot achieve quasi-zero-dimensional contact (point contact). How to realize the transistor under the quasi-zero-dimensional contact to improve the performance of the two-dimensional material transistor, and at the same time improve the driving current performance of the two-dimensional material transistor has become an urgent problem to be solved.
发明内容Contents of the invention
针对现有技术存在的上述问题，本发明提供了一种基于准零维接触的二维薄膜埋栅场效应晶体管；本发明利用接触电阻传输线理论分析并提出了一种全新的准零维接触方法，能够进一步降低晶体管接触电阻，提高晶体管驱动后端电路的能力，大大降低亚阈值摆幅，具有高的开关比。Aiming at the above-mentioned problems existing in the prior art, the present invention provides a two-dimensional thin film buried gate field-effect transistor based on quasi-zero-dimensional contact; the present invention analyzes and proposes a brand-new quasi-zero-dimensional contact method by using the contact resistance transmission line theory , can further reduce the contact resistance of the transistor, improve the ability of the transistor to drive the back-end circuit, greatly reduce the sub-threshold swing, and have a high switching ratio.
为了实现上述目的，本发明采用如下技术方案：In order to achieve the above object, the present invention adopts the following technical solutions:
本发明提出的一种基于准零维接触的二维薄膜埋栅场效应晶体管，其特征在于，包括：A two-dimensional film buried gate field-effect transistor based on a quasi-zero-dimensional contact proposed by the present invention is characterized in that it includes:
依次层叠的衬底、埋栅电极、埋栅介质层和二维薄膜，所述二维薄膜一侧依次层叠有准零维结构形成层和作为准零维金属源的第一电极，所述二维薄膜另一侧层叠有接地的第二电极；其中，A substrate, a buried gate electrode, a buried gate dielectric layer, and a two-dimensional thin film are sequentially stacked, and a quasi-zero-dimensional structure forming layer and a first electrode as a quasi-zero-dimensional metal source are sequentially stacked on one side of the two-dimensional thin film. A grounded second electrode is stacked on the other side of the dimensional film; wherein,
所述埋栅电极，采用金属、导电非金属或柔性电极材料制成，用于传导所述场效应晶体管的电压控制信号；The buried gate electrode is made of metal, conductive non-metal or flexible electrode material, and is used to conduct the voltage control signal of the field effect transistor;
所述埋栅介质层，由金属氧化物、二维绝缘体或柔性绝缘体制成，用于形成电场、并用于所述埋栅电极与在所述二维薄膜内形成的沟道间的隔离；The buried gate dielectric layer is made of metal oxide, a two-dimensional insulator or a flexible insulator, and is used to form an electric field and to isolate the buried gate electrode from the channel formed in the two-dimensional film;
所述二维薄膜，为具有半导体特性的二维薄膜，通过该二维薄膜对其内沟道的电阻进行调控，进而实现对所述场效应晶体管开关特性的调控；The two-dimensional thin film is a two-dimensional thin film with semiconductor characteristics, through which the resistance of the inner channel is regulated, thereby realizing the regulation and control of the switching characteristics of the field effect transistor;
所述准零维结构形成层，采用绝缘体材料通过光刻图像化和淀积方法制成，用于通过所述第一电极的金属电迁徙特性在所述准零维结构生成层内形成细丝状的导电通路，从而在所述第一电极和二维薄膜间形成准零维接触。The quasi-zero-dimensional structure-forming layer is made of an insulator material through photolithographic imaging and deposition methods, and is used to form filaments in the quasi-zero-dimensional structure-forming layer through the metal electromigration properties of the first electrode A conductive path in the form of a quasi-zero-dimensional contact is formed between the first electrode and the two-dimensional thin film.
进一步地，所述准零维结构形成层的厚度为0.7nm～300nm。Further, the thickness of the quasi-zero-dimensional structure-forming layer is 0.7nm-300nm.
进一步地，所述二维薄膜采用二维过渡金属硫族化合物薄膜、狄拉克二维薄膜、有机二维薄膜或柔性二维薄膜。Further, the two-dimensional thin film adopts a two-dimensional transition metal chalcogenide thin film, a Dirac two-dimensional thin film, an organic two-dimensional thin film or a flexible two-dimensional thin film.
本发明特点及有益效果：Features and beneficial effects of the present invention:
本发明对于场效应晶体管的接触问题提出了一个全新的解决方案。其原理是通过利用在强电场下电极金属电迁徙特性，使得在源漏极与二维薄膜内的沟道间形成一个导电细丝通路，该导电细丝通道是由金属原子组成。由于导电细丝拥有极小的横截面积，因此在水平方向认为与源漏极和沟道之间形成的金属导电细丝结构为准零维结构，从而使得准零维接触在源漏极和沟道间形成。通过利用接触电阻的传输线模型，发现随着接触维度的减少，其导电载流子在沟道层内散射减少，有利于载流子纵向传递，极大提高了接触性能和晶体管开态电流的大小。另外普通的电极材料在淀积过程中，由于采用溅射、电子束蒸发等工艺，电极材料能量较高，会对二维材料造成损伤，从而引入更多表面能级，接触性能变差。而利用准零维结构，电极材料和二维材料间有准零维结构形成层的隔离，对二维材料有保护作用，从而在另一方面减少表面能级的引入，以达到肖特基接触势垒的最低理论极限。从而进一步提高了晶体管的开态电流和后端驱动能力。对于准零维金属导电细丝结构，其保持时间长，实施例中能够超过1350小时，因此本发明的基于准零维接触的二维薄膜埋栅场效应晶体管具有很好的鲁棒性。另外，二维材料以其超薄的厚度，拥有突破现有硅基晶体管尺寸缩小的限制，维持摩尔定律进一步发展，能够应用于特征尺寸5nm以下的新芯片工艺。埋栅结构的应用，进一步控制栅极漏电，降低晶体管的工作电压，使得基于准零维接触的二维薄膜埋栅场效应晶体管能够在低电压、低功耗条件下运行。该器件的制备工艺与传统硅基工艺兼容，可以与硅基电路集成。基于准零维接触的二维薄膜埋栅场效应晶体管解决了硅基电路尺寸缩小及高集成度下单个晶体管的驱动问题，在大规模模拟电路及数字逻辑电路有广阔的应用前景和空间。The invention provides a brand new solution to the contact problem of field effect transistors. The principle is to use the electromigration characteristics of the electrode metal under a strong electric field to form a conductive filament path between the source and drain electrodes and the channel in the two-dimensional film. The conductive filament path is composed of metal atoms. Since the conductive filament has an extremely small cross-sectional area, the metal conductive filament structure formed between the source and drain and the channel is considered to be a quasi-zero-dimensional structure in the horizontal direction, so that the quasi-zero-dimensional contact between the source and drain and the channel is considered to be a quasi-zero-dimensional structure. formed between channels. By using the transmission line model of contact resistance, it is found that as the contact dimension decreases, the scattering of conductive carriers in the channel layer decreases, which is conducive to the longitudinal transfer of carriers, which greatly improves the contact performance and the on-state current of the transistor. . In addition, during the deposition process of ordinary electrode materials, due to the use of sputtering, electron beam evaporation and other processes, the energy of the electrode materials is high, which will cause damage to the two-dimensional materials, thereby introducing more surface energy levels and degrading the contact performance. However, using the quasi-zero-dimensional structure, there is a quasi-zero-dimensional structure-forming layer isolation between the electrode material and the two-dimensional material, which has a protective effect on the two-dimensional material, thereby reducing the introduction of surface energy levels on the other hand to achieve Schottky contact. The lowest theoretical limit of the potential barrier. Therefore, the on-state current and back-end driving capability of the transistor are further improved. For the quasi-zero-dimensional metal conductive filament structure, its retention time is long, and it can exceed 1350 hours in the embodiment, so the two-dimensional thin film buried gate field-effect transistor based on the quasi-zero-dimensional contact of the present invention has good robustness. In addition, with its ultra-thin thickness, two-dimensional materials can break through the limitation of the size reduction of existing silicon-based transistors, maintain the further development of Moore's law, and can be applied to new chip processes with feature sizes below 5nm. The application of the buried gate structure further controls the gate leakage and reduces the operating voltage of the transistor, so that the two-dimensional thin film buried gate field effect transistor based on the quasi-zero-dimensional contact can operate under low voltage and low power consumption conditions. The fabrication process of the device is compatible with traditional silicon-based processes and can be integrated with silicon-based circuits. The two-dimensional thin film buried gate field-effect transistor based on quasi-zero-dimensional contact solves the problem of reducing the size of silicon-based circuits and driving a single transistor under high integration, and has broad application prospects and space in large-scale analog circuits and digital logic circuits.
附图说明Description of drawings
图1是本发明实施例中基于准零维接触的二维薄膜埋栅场效应晶体管结构的主视图；Fig. 1 is a front view of the structure of a two-dimensional thin film buried gate field-effect transistor based on a quasi-zero-dimensional contact in an embodiment of the present invention;
图2是本发明实施例中基于准零维接触的二维薄膜埋栅场效应晶体管结构的右视图；2 is a right view of the structure of a two-dimensional thin film buried gate field effect transistor based on a quasi-zero-dimensional contact in an embodiment of the present invention;
图3是本发明实施例中基于准零维接触的二维薄膜埋栅场效应晶体管制备方法流程图；3 is a flow chart of a method for preparing a two-dimensional thin film buried gate field-effect transistor based on a quasi-zero-dimensional contact in an embodiment of the present invention;
图4是本发明实施例中基于准零维接触的二维薄膜埋栅场效应晶体管驱动电流特性与传统三维接触驱动电流特性比较示意图；其中，(a)是本发明实施例的性能示意图，(b)是传统三维接触的性能示意图。Fig. 4 is a schematic diagram comparing the driving current characteristics of the two-dimensional thin film buried gate field effect transistor based on the quasi-zero-dimensional contact and the traditional three-dimensional contact driving current characteristics in the embodiment of the present invention; wherein, (a) is a performance schematic diagram of the embodiment of the present invention, ( b) is a schematic diagram of the performance of traditional 3D contact.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
本发明实施例提供的一种基于准零维接触的二维薄膜埋栅场效应晶体管，其结构参见图1、图2，分别是该晶体管结构的主视图和右视图，包括依次层叠的衬底111、埋栅电极101、埋栅介质层102和二维薄膜103，二维薄膜103一侧依次层叠准零维结构形成层104和作为准零维金属源(所述准零维金属源是指形成准零维结构的金属来源，一般为金属电极)的第一电极105，另一侧层叠有接地的第二电极106；埋栅电极101和埋栅介质层102共同构成埋珊结构。其中，埋珊结构通过图形化和淀积方法制得，埋栅电极101用于传导本晶体管的电压控制信号，埋栅介质层102完全或部分(埋栅介质层覆盖埋栅电极的面积取决于埋栅介质层的制备方法，如常规的原子层淀积方法，采用的是完全覆盖；如采用先光刻再溅射的方法制备埋栅介质层，采用的是部分覆盖；无论采用上述哪种方法，对于沟道对应部分则必须完全覆盖)覆盖埋栅电极101，用于形成电场、并用于埋栅电极101和在二维薄膜103内形成的沟道间的隔离；准零维结构形成层104是由绝缘体材料通过光刻图形化和淀积方法(所述淀积方法包括常规的磁控溅射、电子束蒸发、化学气相淀积和物理气相淀积方法)制成，通过在第一电极105上施加外部电场(106V/m～109V/m)，使得第一电极105的金属原子在电迁徙的作用下，在准零维结构生成层104内形成细丝状的导电通路，从而在第一电极105和二维薄膜103间形成准零维接触，以此提高第一电极与二维薄膜内沟道之间的电流接触性能。A two-dimensional thin-film buried gate field-effect transistor based on a quasi-zero-dimensional contact provided by an embodiment of the present invention, its structure is shown in Figure 1 and Figure 2, which are the front view and right view of the transistor structure, including sequentially stacked substrates 111. A buried gate electrode 101, a buried gate dielectric layer 102 and a two-dimensional film 103, one side of the two-dimensional film 103 is sequentially stacked with a quasi-zero-dimensional structure forming layer 104 and used as a quasi-zero-dimensional metal source (the quasi-zero-dimensional metal source refers to Forming the metal source of the quasi-zero-dimensional structure, generally a metal electrode), the first electrode 105 is stacked on the other side with a grounded second electrode 106; the buried gate electrode 101 and the buried gate dielectric layer 102 together form a buried gate structure. Wherein, the buried gate structure is made by patterning and deposition methods, the buried gate electrode 101 is used to conduct the voltage control signal of the transistor, and the buried gate dielectric layer 102 is completely or partially (the area of the buried gate dielectric layer covering the buried gate electrode depends on The preparation method of the buried gate dielectric layer, such as the conventional atomic layer deposition method, adopts full coverage; if the buried gate dielectric layer is prepared by first photolithography and then sputtering, it adopts partial coverage; no matter which of the above method, the corresponding part of the channel must be completely covered) covering the buried gate electrode 101 for forming an electric field and for isolation between the buried gate electrode 101 and the channel formed in the two-dimensional thin film 103; the quasi-zero-dimensional structure forms a layer 104 is made of insulator material by photolithographic patterning and deposition methods (the deposition methods include conventional magnetron sputtering, electron beam evaporation, chemical vapor deposition and physical vapor deposition methods), through the first An external electric field (106 V/m-109 V/m) is applied to the electrode 105, so that the metal atoms of the first electrode 105 form a filament-like conductive layer in the quasi-zero-dimensional structure generation layer 104 under the action of electromigration. A path is formed to form a quasi-zero-dimensional contact between the first electrode 105 and the two-dimensional thin film 103, thereby improving the current contact performance between the first electrode and the channel in the two-dimensional thin film.
本发明实施例中各组成器件的具体实现方式及功能分别说明如下：The specific implementation and functions of each component device in the embodiment of the present invention are respectively described as follows:
所述衬底111，采用绝缘材料(本实施例选用硅衬底上热生长300nm SiO2后的晶圆)制成，用于为整个晶体管提供物理支撑和电学隔离，衬底111上表面与埋栅电极101相连接；The substrate 111 is made of an insulating material (in this embodiment, a wafer of 300nmSiO2 is thermally grown on a silicon substrate) and is used to provide physical support and electrical isolation for the entire transistor. The upper surface of the substrate 111 and the buried The gate electrodes 101 are connected;
所述埋栅电极101，上表面与埋栅介质层102(本实施例中，埋栅介质层102部分覆盖埋栅电极101；在另一实施例中，埋栅介质层102完全覆盖埋栅电极101)相连接，通过埋栅电极101传导本晶体管的电压控制信号；制成埋栅电极101的材料包括金属、导电非金属(例如可采用高掺杂p型和n型硅或锗半导体)和柔性电极材料等(本实施例采用Pt)；埋栅电极101的宽度为100nm～100um，厚度为10nm～50nm。The buried gate electrode 101, the upper surface and the buried gate dielectric layer 102 (in this embodiment, the buried gate dielectric layer 102 partially covers the buried gate electrode 101; in another embodiment, the buried gate dielectric layer 102 completely covers the buried gate electrode 101) are connected, and the voltage control signal of the transistor is conducted through the buried gate electrode 101; the material for making the buried gate electrode 101 includes metal, conductive non-metal (for example, highly doped p-type and n-type silicon or germanium semiconductors can be used) and Flexible electrode material, etc. (Pt is used in this embodiment); the width of the buried gate electrode 101 is 100nm-100um, and the thickness is 10nm-50nm.
所述埋栅介质层102，该埋栅介质层102的上下表面分别与二维薄膜103和埋栅电极101相连接，用于栅极和二维薄膜103内沟道间的隔离；制成埋栅介质层102的材料包括金属氧化物、二维绝缘体及柔性绝缘体中的任意一种，对于本实施例而言，为使用原子层淀积的15nm厚的氧化铪材料。利用埋栅电极101可降低栅控扫描电压，优化栅介质层漏电状况。The buried gate dielectric layer 102, the upper and lower surfaces of the buried gate dielectric layer 102 are respectively connected to the two-dimensional film 103 and the buried gate electrode 101, and is used for isolation between the gate and the channel in the two-dimensional film 103; The material of the gate dielectric layer 102 includes any one of metal oxides, two-dimensional insulators and flexible insulators. For this embodiment, it is hafnium oxide material with a thickness of 15 nm deposited by atomic layer deposition. Utilizing the buried gate electrode 101 can reduce the gate control scanning voltage and optimize the leakage condition of the gate dielectric layer.
所述二维薄膜103，下表面与埋栅介质层102连接，上表面分别与第二电极106和准零维结构形成层104连接，且第二电极106与准零维结构形成层104间不接触，在该二维薄膜内形成场效应晶体管沟道，通过二维薄膜对其内沟道电阻进行调控，进而实现对本场效应晶体管开关特性的调控，二维薄膜103材料可选用任意具有半导体特性的二维薄膜即可，如采用二维过渡金属硫族化合物薄膜、狄拉克二维薄膜、有机二维薄膜或柔性二维薄膜中的任意一种，厚度范围在0.33nm-50nm，对于本实施例而言，为具有较高载流子迁移率的2nm厚的二硫化钼。The two-dimensional thin film 103 has a lower surface connected to the buried gate dielectric layer 102, an upper surface connected to the second electrode 106 and the quasi-zero-dimensional structure forming layer 104 respectively, and there is no gap between the second electrode 106 and the quasi-zero-dimensional structure forming layer 104. Contact, form a field effect transistor channel in the two-dimensional film, and adjust the internal channel resistance through the two-dimensional film, and then realize the regulation and control of the switching characteristics of the field effect transistor. The material of the two-dimensional film 103 can be selected to have any semiconductor characteristics Two-dimensional thin films can be used, such as any one of two-dimensional transition metal chalcogenide thin films, Dirac two-dimensional thin films, organic two-dimensional thin films or flexible two-dimensional thin films, with a thickness ranging from 0.33nm to 50nm. For this implementation For example, 2nm thick molybdenum disulfide with higher carrier mobility.
准零维结构形成层104是本发明的核心，该准零维结构形成层104的上下表面分别与第一电极105和二维薄膜103相连接，构成准零维结构形成层104的材料一般为绝缘体材料，包括金属氧化物及其他在其内部的金属原子能够形成导电细丝的材料，准零维结构形成层104为0.7nm～300nm。对于本实施例而言，为使用原子层淀积的8nm厚的氧化铪材料。通过利用在强电场(106V/m～109V/m)下第一电极105的金属电迁徙特性，使得在源漏极与二维薄膜103内的沟道间形成一个导电细丝通路，该导电细丝通道是由金属原子组成。由于导电细丝拥有nm级甚至于级的横截面积，因此在水平方向认为与源漏极和二维薄膜内沟道之间形成的金属导电细丝结构为准零维结构，从而使得准零维接触在源漏极和二维薄膜内沟道间形成。通过利用接触电阻的传输线模型，发现随着接触维度的减少，其导电载流子在沟道层内散射减少，有利于载流子纵向传递，极大提高了接触性能和晶体管开态电流的大小。另一方面，利用准零维结构，第一电极105和二维薄膜103间有准零维结构形成层104的隔离，对二维薄膜103具有保护作用，从而在另一方面减少表面能级的引入，以达到肖特基接触势垒的最低理论极限，从而进一步提高了本晶体管的开态电流和后端驱动能力。The quasi-zero-dimensional structure-forming layer 104 is the core of the present invention. The upper and lower surfaces of the quasi-zero-dimensional structure-forming layer 104 are respectively connected to the first electrode 105 and the two-dimensional film 103. The material forming the quasi-zero-dimensional structure-forming layer 104 is generally Insulator materials include metal oxides and other materials in which metal atoms can form conductive filaments, and the quasi-zero-dimensional structure forming layer 104 is 0.7nm-300nm. For this embodiment, an 8 nm thick hafnium oxide material is used by atomic layer deposition. By using the metal electromigration properties of the first electrode 105 under a strong electric field (106 V/m-109 V/m), a conductive filament path is formed between the source and drain electrodes and the channel in the two-dimensional film 103 , the conductive filament channel is composed of metal atoms. Due to the conductive filaments have nanoscale even The cross-sectional area of the level, so the metal conductive filament structure formed between the source and drain and the channel in the two-dimensional film is considered to be a quasi-zero-dimensional structure in the horizontal direction, so that the quasi-zero-dimensional contact between the source and drain and the two-dimensional film Formation of channels in the film. By using the transmission line model of contact resistance, it is found that as the contact dimension decreases, the scattering of conductive carriers in the channel layer decreases, which is conducive to the longitudinal transfer of carriers, which greatly improves the contact performance and the on-state current of the transistor. . On the other hand, using the quasi-zero-dimensional structure, the first electrode 105 and the two-dimensional film 103 are separated by the quasi-zero-dimensional structure forming layer 104, which has a protective effect on the two-dimensional film 103, thereby reducing the surface energy level on the other hand. Introduced to achieve the lowest theoretical limit of the Schottky contact barrier, thereby further improving the on-state current and back-end driving capability of the transistor.
所述第一电极105，构成该第一电极105的材料包括铝、银、铜等能够产生电迁徙的材料，对于本实施例而言，为溅射的Ag。For the first electrode 105, the material constituting the first electrode 105 includes materials capable of electromigration such as aluminum, silver, copper, etc., and for this embodiment, it is sputtered Ag.
所述第二电极106，构成该第二电极106的材料包括金属及其他导电非金属，、掺杂半导体、柔性电极材料，对于本实施例而言，为溅射的Pt/Ti组合。For the second electrode 106, the material constituting the second electrode 106 includes metals and other conductive non-metals, doped semiconductors, and flexible electrode materials. For this embodiment, it is a combination of sputtered Pt/Ti.
参见图3，是本发明上述各实施例中基于准零维接触的二维薄膜埋栅场效应晶体管的制备方法流程图，该方法包括以下步骤：Referring to FIG. 3 , it is a flowchart of a method for preparing a two-dimensional thin film buried gate field-effect transistor based on a quasi-zero-dimensional contact in each of the above embodiments of the present invention. The method includes the following steps:
S201：在衬底111上采用图形化和淀积方法制备埋栅电极101及埋栅介质层102，对于本实施例而言，使用掩模版曝光或电子束曝光工艺等相应的制作工艺完成埋栅电极101的制备，使用原子层淀积的方式完成埋栅介质层102的制备。S201: Prepare the buried gate electrode 101 and the buried gate dielectric layer 102 on the substrate 111 by patterning and deposition methods. For this embodiment, the buried gate is completed using a corresponding manufacturing process such as mask exposure or electron beam exposure. For the preparation of the electrode 101, the preparation of the buried gate dielectric layer 102 is completed by means of atomic layer deposition.
S202：采用干法(机械剥离法)或湿法转移方法将二维材料转移到埋栅介质层102上，并通过图形化、刻蚀方法制备具有导电沟道的二维薄膜103，所述图形化的方式为：掩模版曝光或电子束曝光工艺等相应的制作工艺，所述刻蚀方法为等离子体干法刻蚀或化学反应腐蚀法。S202: Transfer the two-dimensional material to the buried gate dielectric layer 102 by a dry method (mechanical lift-off method) or a wet transfer method, and prepare a two-dimensional thin film 103 with a conductive channel by patterning and etching, the pattern The way of etching is: corresponding manufacturing process such as mask plate exposure or electron beam exposure process, and the etching method is plasma dry etching or chemical reaction etching.
S203：采用掩模版曝光或电子束曝光工艺等相应的制作工艺，在二维薄膜103上制备第二电极106。S203: Prepare the second electrode 106 on the two-dimensional thin film 103 by using a corresponding manufacturing process such as mask exposure or electron beam exposure.
S204：利用化学气相沉积或物理气相沉积的方式在二维薄膜103上制备准零维结构形成层104。并通过图形化，刻蚀方法确定准零维结构形成层104在二维薄膜103上的具体位置，所述图形化的方式为：掩模版曝光或电子束曝光工艺等相应的制作工艺，所述刻蚀方法为等离子体干法刻蚀或化学反应腐蚀法。S204: Prepare a quasi-zero-dimensional structure-forming layer 104 on the two-dimensional thin film 103 by means of chemical vapor deposition or physical vapor deposition. And determine the specific position of the quasi-zero-dimensional structure forming layer 104 on the two-dimensional film 103 by patterning and etching methods. The patterning method is: mask plate exposure or electron beam exposure process and other corresponding manufacturing processes. The etching method is plasma dry etching or chemical reaction etching.
S205：采用同S201方法，在准零维结构形成层104上制备第一电极105。S205: Prepare the first electrode 105 on the quasi-zero-dimensional structure forming layer 104 by using the same method as S201.
S206：采用同S201方法在埋栅电极101上制备栅极电极引出端110。S206: Prepare the gate electrode lead-out terminal 110 on the buried gate electrode 101 by the same method as S201.
本发明实施例有效性验证：Validity verification of the embodiment of the present invention:
为了验证本发明实施例的效果，将图1所示晶体管中的第一电极105通过导线与一个源漏信号输入装置的正极端连接，该源漏信号输入装置的负极端通过导线与第二电极106连接，在埋栅电极101上设置栅极电极引出端110(制成埋栅电极引出端110的材料包括金属、导电非金属(例如可采用高掺杂p型和n型硅或锗半导体)、柔性电极材料等，制成埋栅电极引出端110的材料可以与埋栅电极101相同，也可以与埋栅电极101不同，本实施例采用金属Pt)，该栅极电极引出端110通过栅控信号输入装置接入第二电极106和源漏信号输入装置负极端的公共端。In order to verify the effect of the embodiment of the present invention, the first electrode 105 in the transistor shown in Figure 1 is connected to the positive end of a source-drain signal input device through a wire, and the negative end of the source-drain signal input device is connected to the second electrode through a wire. 106 connection, on the buried gate electrode 101, the gate electrode terminal 110 is set (the material for making the buried gate electrode terminal 110 includes metal, conductive non-metal (for example, highly doped p-type and n-type silicon or germanium semiconductors can be used) , flexible electrode materials, etc., the material for making the lead-out end 110 of the buried gate electrode may be the same as that of the buried-gate electrode 101, or may be different from the buried-gate electrode 101. This embodiment uses metal Pt), and the lead-out end 110 of the gate electrode passes through the gate The control signal input device is connected to the common terminal of the second electrode 106 and the negative terminal of the source-drain signal input device.
参见图4，是本发明实施例中基于准零维接触的二维薄膜埋栅场效应晶体管电流开关特性和开态电流较三维接触比较的示意图，其中，(a)为本发明实施例结果图，(b)为现有的三维接触结果图；漏极电流坐标轴301，栅极电压扫描302，栅极漏电坐标轴303。Referring to Fig. 4, it is a schematic diagram of the current switching characteristics and on-state current of the two-dimensional thin film buried gate field effect transistor based on the quasi-zero-dimensional contact compared with the three-dimensional contact in the embodiment of the present invention, wherein (a) is the result diagram of the embodiment of the present invention , (b) is the existing three-dimensional contact result diagram; drain current coordinate axis 301, gate voltage scan 302, gate leakage coordinate axis 303.
当漏极电压为6V，栅极扫描从-2V到11V时，其沟道电流传输曲线304和栅极漏电流305随栅极电压的变化可以得到：基于准零维接触的埋栅二维薄膜晶体管的沟道电流开关比在2.6e9；并且埋栅结构的使用使得栅极扫描电压范围变小，栅极漏电低，器件性能好。相比较于普通三维接触的二维晶体管的栅极漏电流307，本发明中准零维接触可以使得开态电流提高近50倍，极大降低器件的接触电阻，提高晶体管电流驱动能力。When the drain voltage is 6V and the gate scans from -2V to 11V, the channel current transfer curve 304 and gate leakage current 305 can be obtained as a function of the gate voltage: a buried gate two-dimensional film based on a quasi-zero-dimensional contact The channel current switch ratio of the transistor is 2.6e9; and the use of the buried gate structure makes the gate scanning voltage range smaller, the gate leakage is low, and the device performance is good. Compared with the gate leakage current 307 of a two-dimensional transistor with ordinary three-dimensional contact, the quasi-zero-dimensional contact in the present invention can increase the on-state current by nearly 50 times, greatly reduce the contact resistance of the device, and improve the current driving capability of the transistor.
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.
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| CN201910278746.1ACN110323282A (en) | 2019-04-09 | 2019-04-09 | It is a kind of based on quasi-zero dimension contact two-dimensional film bury grid field effect transistor |
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| CN201910278746.1ACN110323282A (en) | 2019-04-09 | 2019-04-09 | It is a kind of based on quasi-zero dimension contact two-dimensional film bury grid field effect transistor |
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