技术领域technical field
本发明涉及显示器领域，特别涉及一种薄膜晶体管器件及其制备方法。The invention relates to the field of displays, in particular to a thin film transistor device and a preparation method thereof.
背景技术Background technique
由于顶栅结构的TFT(Thin Film Transistor，薄膜晶体管)具有较低的寄生电容，较优良的电学特性，因此被广泛应用于显示装置中。Since a TFT (Thin Film Transistor, thin film transistor) with a top-gate structure has lower parasitic capacitance and better electrical characteristics, it is widely used in display devices.
现有技术中在制作顶栅结构的薄膜晶体管器件TFT时，由于要采用到栅极Gate与栅极绝缘图案GI的自对准工艺，而栅极Gate通常采用湿法刻蚀工艺制作，栅极绝缘图案GI通过干法刻蚀工艺制作，在利用湿法刻蚀工艺刻蚀栅极Gate时，由于刻蚀液会在光刻胶下面多刻蚀一小段距离，这样导致栅极Gate相比栅极绝缘图案GI短出一小段距离，即栅极Gate与栅极绝缘图案GI在衬底基板上的正投影不能完全重合。由于栅极绝缘图案GI上方两侧均有一小段距离无栅极Gate，导致缺少栅极Gate覆盖的栅极绝缘图案GI下方的有源层图案IGZO没有被栅极Gate调控，进而导致顶栅结构的TFT的开启电流不足，从而影响顶栅TFT的电学特性，使得显示装置的显示效果也受到影响。In the prior art, when fabricating a thin film transistor device TFT with a top-gate structure, since a self-alignment process between the gate Gate and the gate insulation pattern GI is used, the gate Gate is usually produced by a wet etching process, and the gate gate The insulating pattern GI is produced by a dry etching process. When the gate Gate is etched by a wet etching process, the etchant will etch a small distance under the photoresist, which causes the gate Gate The pole insulation pattern GI is short by a small distance, that is, the orthographic projections of the gate Gate and the gate insulation pattern GI on the base substrate cannot completely coincide. Since there is a small distance on both sides above the gate insulation pattern GI without a gate Gate, the active layer pattern IGZO below the gate insulation pattern GI that lacks the coverage of the gate Gate is not regulated by the gate Gate, which leads to the failure of the top gate structure. The turn-on current of the TFT is insufficient, thereby affecting the electrical characteristics of the top-gate TFT, so that the display effect of the display device is also affected.
发明内容Contents of the invention
本发明的目的在于，解决现有的薄膜晶体管器件中栅极绝缘层上表面边缘处无栅极层，导致栅极绝缘层下方的有源层的边缘处未被调控，薄膜晶体管器件的电学特性差、显示装置显示效果不佳等技术问题。The purpose of the present invention is to solve the problem that there is no gate layer at the edge of the upper surface of the gate insulating layer in the existing thin film transistor device, resulting in the unregulated edge of the active layer below the gate insulating layer, and the electrical characteristics of the thin film transistor device Poor, poor display effect of the display device and other technical problems.
为实现上述目的，本发明提供一种薄膜晶体管器件，包括：基板；有源层，设于所述基板一侧的表面；栅极绝缘层，设于所述有源层远离所述基板一侧的表面；导电层，设于所述栅极绝缘层远离所述有源层一侧的表面；以及栅极层，设于所述导电层远离所述栅极绝缘层一侧的表面。To achieve the above object, the present invention provides a thin film transistor device, comprising: a substrate; an active layer disposed on the surface of one side of the substrate; a gate insulating layer disposed on the side of the active layer away from the substrate the surface of the conductive layer; the conductive layer is arranged on the surface of the gate insulating layer away from the active layer; and the gate layer is arranged on the surface of the conductive layer away from the gate insulating layer.
进一步地，所述导电层的材质包括氧化物半导体，所述氧化物半导体包括铟镓锌氧化物；所述导体层的厚度为100A～400A。Further, the material of the conductive layer includes an oxide semiconductor, and the oxide semiconductor includes indium gallium zinc oxide; the thickness of the conductive layer is 100A˜400A.
进一步地，所述导电层的尺寸与所述栅极绝缘层的尺寸一致，且所述导电层与所述栅极绝缘层相对设置；所述栅极层的尺寸小于所述导电层的尺寸，且所述栅极层与所述导电层相对设置。Further, the size of the conductive layer is consistent with the size of the gate insulating layer, and the conductive layer is arranged opposite to the gate insulating layer; the size of the gate layer is smaller than the size of the conductive layer, And the gate layer is disposed opposite to the conductive layer.
进一步地，所述薄膜晶体管器件还包括：遮光层，设于所述基板一侧的表面；以及缓冲层，设于所述遮光层远离所述基板一侧的表面；其中，所述有源层设于所述缓冲层远离所述基板一侧的表面，且与所述遮光层相对设置。Further, the thin film transistor device further includes: a light-shielding layer disposed on the surface of the substrate; and a buffer layer disposed on the surface of the light-shielding layer away from the substrate; wherein the active layer It is arranged on the surface of the buffer layer away from the substrate and opposite to the light shielding layer.
进一步地，所述薄膜晶体管器件还包括：介电层，设于所述栅极层远离所述导电层一侧的表面；介电层过孔，穿过所述介电层，且与所述有源层相对设置；源漏极层，设于所述介电层远离所述缓冲层一侧的表面，且穿过所述介电层过孔连接至所述有源层；保护层，设于所述源漏极层及所述介电层远离所述缓冲层一侧的表面；保护层过孔，穿过所述保护层，且与所述源漏极层相对设置；以及像素电极层，设于所述保护层过孔内侧壁，且延伸至所述保护层远离所述源漏极层一侧的表面，所述像素电极层连接至所述源漏极层。Further, the thin film transistor device further includes: a dielectric layer disposed on the surface of the gate layer away from the conductive layer; a dielectric layer via hole passing through the dielectric layer and connecting with the The active layer is arranged oppositely; the source and drain layer is arranged on the surface of the dielectric layer away from the buffer layer, and is connected to the active layer through the dielectric layer through a hole; the protective layer is arranged On the surface of the source-drain layer and the dielectric layer away from the buffer layer; via holes in the protective layer pass through the protective layer and are arranged opposite to the source-drain layer; and a pixel electrode layer , arranged on the inner sidewall of the via hole in the protection layer, and extending to the surface of the protection layer on a side away from the source and drain layers, and the pixel electrode layer is connected to the source and drain layers.
为实现上述目的，本发明还提供一种薄膜晶体管器件的制备方法包括如下步骤：遮光层制备步骤，在一基板上制备出一遮光层；缓冲层制备步骤，在所述遮光层及所述基板的上表面制备出一缓冲层；有源层制备步骤，在所述缓冲层的上表面制备出一有源层；以及栅极层制备步骤，在所述有源层的上表面依次制备出栅极绝缘层、导电层及栅极层。In order to achieve the above object, the present invention also provides a preparation method of a thin film transistor device comprising the following steps: a light shielding layer preparation step, a light shielding layer is prepared on a substrate; a buffer layer preparation step, the light shielding layer and the substrate are prepared A buffer layer is prepared on the upper surface of the buffer layer; the active layer preparation step is to prepare an active layer on the upper surface of the buffer layer; and the gate layer preparation step is to sequentially prepare a grid on the upper surface of the active layer Pole insulating layer, conductive layer and gate layer.
进一步地，所述栅极层制备步骤包括以下步骤：无机层形成步骤，在所述有源层及所述缓冲层的上表面沉积无机材料，形成一无机层；半导体层形成步骤，在所述无机层的上表面沉积氧化物半导体材料，形成一半导体层；金属层形成步骤，在所述半导体层的上表面沉积金属材料，形成一金属层；以及刻蚀步骤，刻蚀出栅极层、导电层及栅极绝缘层。Further, the gate layer preparation step includes the following steps: an inorganic layer forming step, depositing inorganic materials on the upper surfaces of the active layer and the buffer layer to form an inorganic layer; a semiconductor layer forming step, in the Depositing an oxide semiconductor material on the upper surface of the inorganic layer to form a semiconductor layer; a metal layer forming step, depositing a metal material on the upper surface of the semiconductor layer to form a metal layer; and an etching step to etch the gate layer, conductive layer and gate insulating layer.
进一步地，所述刻蚀步骤包括以下步骤：光刻胶涂布步骤，在所述第一金属层的上表面涂布一光刻胶；第一刻蚀步骤，利用湿法刻蚀工艺将所述金属层刻蚀成栅极层；第二刻蚀步骤，利用干法刻蚀工艺将所述半导体层刻蚀成导电层，将所述无机层刻蚀成栅极绝缘层，使得所述导电层的尺寸与所述栅极绝缘层的尺寸一致；光刻胶剥离步骤，剥离光刻胶；以及导体化步骤，导体化处理未被所述栅极绝缘层覆盖的有源层。Further, the etching step includes the following steps: a photoresist coating step, coating a photoresist on the upper surface of the first metal layer; a first etching step, using a wet etching process to coat the The metal layer is etched into a gate layer; in the second etching step, the semiconductor layer is etched into a conductive layer using a dry etching process, and the inorganic layer is etched into a gate insulating layer, so that the conductive The size of the layer is consistent with the size of the gate insulating layer; the step of stripping the photoresist, stripping off the photoresist; and the step of conductorizing, conducting the active layer not covered by the gate insulating layer.
进一步地，在所述第二刻蚀步骤中，刻蚀气体包括三氯化硼。Further, in the second etching step, the etching gas includes boron trichloride.
进一步地，在所述导体化步骤中，离子轰击处理或离子注入处理所述基板；其中，所述离子轰击处理的离子包括氩气离子或氦气离子；所述离子注入处理的离子包括铝离子或钙离子。Further, in the conducting step, the substrate is treated by ion bombardment treatment or ion implantation; wherein, the ions of the ion bombardment treatment include argon ions or helium ions; the ions of the ion implantation treatment include aluminum ions or calcium ions.
本发明的技术效果在于，在栅极层及栅极绝缘层之间增加一导电层，且所述导电层与所述栅极绝缘层使用同一刻蚀工艺刻蚀所得，使得导电图案与栅极绝缘层在基板上的正投影重合，即栅极绝缘层上表面上各处位置均存在导电层，所述导电层弥补了现有技术中栅极绝缘层边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘层下面对应的有源层都可以被栅极层调控，加大薄膜晶体管器件的开启电流，增强薄膜晶体管器件的电学特性，提高显示装置的显示效果。The technical effect of the present invention is that a conductive layer is added between the gate layer and the gate insulating layer, and the conductive layer and the gate insulating layer are etched by the same etching process, so that the conductive pattern and the gate The orthographic projections of the insulating layer on the substrate overlap, that is, there are conductive layers everywhere on the upper surface of the gate insulating layer, and the conductive layer makes up for a short distance above the edge of the gate insulating layer in the prior art. defects, so that the corresponding active layer under the entire gate insulating layer can be regulated by the gate layer, increase the turn-on current of the thin film transistor device, enhance the electrical characteristics of the thin film transistor device, and improve the display effect of the display device.
附图说明Description of drawings
图1为本发明实施例所述的薄膜晶体管器件的制备方法的流程图；Fig. 1 is the flowchart of the preparation method of the thin film transistor device described in the embodiment of the present invention;
图2为本发明实施例所述的缓冲层制备步骤之后的薄膜晶体管器件的结构示意图；2 is a schematic structural view of a thin film transistor device after the buffer layer preparation step described in the embodiment of the present invention;
图3为本发明实施例所述的有源层制备步骤之后的薄膜晶体管器件的结构示意图；3 is a schematic structural view of a thin film transistor device after the active layer preparation step described in the embodiment of the present invention;
图4为本发明实施例所述的栅极层制备步骤的流程图；4 is a flow chart of the gate layer preparation steps described in the embodiment of the present invention;
图5为本发明实施例所述的刻蚀步骤的流程图；5 is a flow chart of the etching steps described in the embodiment of the present invention;
图6为本发明实施例所述的栅极层制备步骤之后的薄膜晶体管器件的结构示意图；6 is a schematic structural diagram of a thin film transistor device after the step of preparing a gate layer according to an embodiment of the present invention;
图7为本发明实施例所述的介电层开孔步骤之后的薄膜晶体管器件的结构示意图；7 is a schematic structural diagram of a thin film transistor device after the step of opening a hole in a dielectric layer according to an embodiment of the present invention;
图8为本发明实施例所述的源漏极层制备步骤之后的薄膜晶体管器件的结构示意图；8 is a schematic structural view of a thin film transistor device after the step of preparing the source and drain layers according to the embodiment of the present invention;
图9为本发明实施例所述的保护层开孔步骤之后的薄膜晶体管器件的结构示意图；9 is a schematic structural diagram of a thin film transistor device after the step of opening holes in the protective layer according to an embodiment of the present invention;
图10为本发明实施例所述的薄膜晶体管器件的结构示意图。FIG. 10 is a schematic structural diagram of a thin film transistor device according to an embodiment of the present invention.
部分组件标识如下：Some components are identified as follows:
1、基板；2、遮光层；3、缓冲层；4、有源层；41、半导体部；42、导体部；5、栅极绝缘层；6、导电层；7、栅极层；1. Substrate; 2. Shading layer; 3. Buffer layer; 4. Active layer; 41. Semiconductor part; 42. Conductor part; 5. Gate insulating layer; 6. Conductive layer; 7. Gate layer;
8、介电层；81、介电层过孔；9、源漏极层；10、保护层；101、保护层过孔；11、像素电极层。8. A dielectric layer; 81. A via hole in a dielectric layer; 9. A source-drain layer; 10. A protective layer; 101. A via hole in a protective layer; 11. A pixel electrode layer.
具体实施方式Detailed ways
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, to fully introduce the technical content of the present invention to those skilled in the art, to prove that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make the technical content of the present invention clearer. It is easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be realized through many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein, and the descriptions of the following embodiments are not intended to limit the scope of the present invention.
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only appended The directions in the drawings and the direction terms used herein are used to explain and illustrate the present invention, rather than to limit the protection scope of the present invention.
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。In the drawings, components with the same structure are denoted by the same numerals, and components with similar structures or functions are denoted by similar numerals. In addition, for ease of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。When certain components are described as "on" another component, the component may be placed directly on the other component; there may also be an intermediate component on which the component is placed , and the intermediate component is placed on another component. When a component is described as being "mounted to" or "connected to" another component, both can be understood as being "mounted" or "connected" directly, or a component is "mounted to" or "connected to" through an intermediate component Another component.
如图1～10所示，本实施例提供一种薄膜晶体管器件的制备方法，包括以下步骤S1～S8。As shown in FIGS. 1-10 , this embodiment provides a method for manufacturing a thin film transistor device, including the following steps S1-S8.
S1遮光层制备步骤，在基板1的上表面沉积遮光材料，经黄光工艺及刻蚀工艺后形成遮光层图案，即遮光层2。Step S1 for preparing a light-shielding layer, depositing a light-shielding material on the upper surface of the substrate 1 , and forming a light-shielding layer pattern, that is, a light-shielding layer 2 , after a yellow light process and an etching process.
S2缓冲层制备步骤，在遮光层2及基板1的上表面沉积缓冲材料，经黄光工艺及刻蚀工艺后形成缓冲层图案，即缓冲层3(参见图2)，缓冲层3为二氧化硅SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，其中二氧化硅SiO2膜层设于顶层。S2 buffer layer preparation step, deposit buffer material on the upper surface of light-shielding layer 2 and substrate 1, form buffer layer pattern after yellow light process and etching process, that is, buffer layer 3 (see Figure 2), buffer layer 3 is carbon dioxide Silicon SiO2 film layer or multi-layer stack of silicon dioxide SiO2 and silicon nitrideSiNx , wherein the silicon dioxide SiO2 film layer is arranged on the top layer.
S3有源层制备步骤，在缓冲层3的上表面沉积半导体材料，优选为铟镓锌氧化物IGZO，经黄光工艺及刻蚀工艺后形成半导体图案，即有源层4(参见图3)，有源层4的膜层厚度为300A～500A，优选为400A。S3 Active layer preparation step, depositing a semiconductor material on the upper surface of the buffer layer 3, preferably indium gallium zinc oxide IGZO, forming a semiconductor pattern after the yellow light process and etching process, that is, the active layer 4 (see Figure 3) , the film thickness of the active layer 4 is 300A˜500A, preferably 400A.
S4栅极层制备步骤，在有源层4及缓冲层3的上表面制备出栅极绝缘层5、导电层6及栅极层7。S4 gate layer preparation step, preparing a gate insulating layer 5 , a conductive layer 6 and a gate layer 7 on the upper surfaces of the active layer 4 and the buffer layer 3 .
如图4～6所示，所述栅极层制备步骤具体包括以下步骤S41～S44。As shown in FIGS. 4-6 , the gate layer preparation step specifically includes the following steps S41-S44.
S41无机层制备步骤，在有源层4及缓冲层3的上表面沉积无机材料，形成一无机层。S42半导体层制备步骤，在所述无机层的在所述无机层的上表面沉积氧化物半导体材料，所述氧化物半导体材料为铟镓锌氧化物IGZO，形成一半导体层。S43第一金属层形成步骤，在所述半导体层的上表面沉积金属材料，所述金属材料包括铜Cu或钼Mo，形成一第一金属层。S41 Inorganic layer preparation step, depositing inorganic materials on the upper surfaces of the active layer 4 and the buffer layer 3 to form an inorganic layer. S42 The step of preparing a semiconductor layer, depositing an oxide semiconductor material on the upper surface of the inorganic layer, the oxide semiconductor material being indium gallium zinc oxide IGZO, to form a semiconductor layer. S43 The step of forming a first metal layer, depositing a metal material on the upper surface of the semiconductor layer, and the metal material includes copper Cu or molybdenum Mo to form a first metal layer.
S44刻蚀步骤，刻蚀出栅极层、导电层及栅极绝缘层，将所述第一金属层刻蚀成栅极层7，将半导体层刻蚀成导电层6，将无机层刻蚀成栅极绝缘层5，所述刻蚀步骤包括以下步骤S441～S445。S44 etching step, etching the gate layer, conductive layer and gate insulating layer, etching the first metal layer into the gate layer 7, etching the semiconductor layer into the conductive layer 6, etching the inorganic layer To form the gate insulating layer 5, the etching step includes the following steps S441-S445.
S441光刻胶涂布步骤，在所述第一金属层的上表面涂布一层光刻胶PR。S442第一刻蚀步骤，利用湿法刻蚀工艺将所述第一金属层刻蚀成栅极层7。所述湿法刻蚀的原理为把基板浸泡在化学试剂或试剂溶液中，使没有被抗蚀剂掩蔽的那一部分薄膜表面与试剂发生化学反应而被除去。S443第二刻蚀步骤，利用干法刻蚀工艺将所述半导体层刻蚀成导电层6，将所述无机层刻蚀成栅极绝缘层5，使得导电层6的尺寸与栅极绝缘层5的尺寸相同或相似，导电层6的尺寸与栅极绝缘层5在基板1上的正投影重合。所述干法刻蚀的刻蚀气体优选三氯化硼BCL3。S444光刻胶剥离步骤，剥离光刻胶。S445导体化步骤，自对准导体化处理未被栅极层绝缘层5覆盖的有源层。所述导体化处理包括离子轰击处理或离子注入处理，其中，所述离子轰击处理的离子包括氩气离子或氦气离子；所述离子注入处理是离子包括铝离子或钙离子。此时，有源层4被分为半导体部41及导体部42，半导体部41为被栅极绝缘层5覆盖的部分，导体部42为半导体部41两侧未被栅极绝缘层5覆盖的有源层(参见图6)。S441 photoresist coating step, coating a layer of photoresist PR on the upper surface of the first metal layer. S442 a first etching step, etching the first metal layer into the gate layer 7 by using a wet etching process. The principle of wet etching is to immerse the substrate in a chemical reagent or a reagent solution, so that the part of the film surface not masked by the resist reacts chemically with the reagent and is removed. S443 The second etching step is to etch the semiconductor layer into a conductive layer 6 by using a dry etching process, and etch the inorganic layer into a gate insulating layer 5, so that the size of the conductive layer 6 is the same as that of the gate insulating layer. 5 are the same or similar in size, and the size of the conductive layer 6 coincides with the orthographic projection of the gate insulating layer 5 on the substrate 1 . The etching gas for dry etching is preferably boron trichloride BCL3 . S444 Photoresist stripping step, stripping the photoresist. S445 conductorization step, conducting self-alignment conductorization on the active layer not covered by the gate insulating layer 5 . The conducting treatment includes ion bombardment treatment or ion implantation treatment, wherein the ions in the ion bombardment treatment include argon ions or helium ions; the ion implantation treatment includes aluminum ions or calcium ions. At this time, the active layer 4 is divided into a semiconductor portion 41 and a conductor portion 42. The semiconductor portion 41 is a portion covered by the gate insulating layer 5, and the conductor portion 42 is a portion not covered by the gate insulating layer 5 on both sides of the semiconductor portion 41. active layer (see Figure 6).
在栅极绝缘层5及栅极层7之间增加导电层6，使得栅极绝缘层5的上表面各处都存在导电图案，弥补了现有技术中栅极绝缘层上表面的边缘处无栅极的缺陷，可以使得栅极绝缘层5下方对应的有源层半导体部41都能被栅极层7调控，加大薄膜晶体管器件的开启电流，增强薄膜晶体管器件的电学特性。采用湿法刻蚀和干法刻蚀并用的刻蚀方法，可根据不同材质的膜层刻蚀出不同的图案。A conductive layer 6 is added between the gate insulating layer 5 and the gate layer 7, so that there are conductive patterns everywhere on the upper surface of the gate insulating layer 5, which makes up for the gaps in the edge of the upper surface of the gate insulating layer in the prior art. The defect of the gate can make the corresponding active layer semiconductor part 41 under the gate insulating layer 5 be regulated by the gate layer 7, increase the turn-on current of the thin film transistor device, and enhance the electrical characteristics of the thin film transistor device. Using wet etching and dry etching combined etching method, different patterns can be etched out according to the film layers of different materials.
S5介电层制备步骤，在缓冲层3及栅极层7的上表面沉积介电层材料，经黄光工艺及刻蚀工艺后形成介电层8及介电层过孔81，两个以上介电层过孔81穿过介电层8，介电层过孔81与有源层的导体部42相对设置，便于后续的电路导通(参见图7)。S5 dielectric layer preparation step, depositing a dielectric layer material on the upper surface of the buffer layer 3 and the gate layer 7, forming a dielectric layer 8 and a dielectric layer via hole 81 after a yellow light process and an etching process, more than two The dielectric layer via hole 81 passes through the dielectric layer 8 , and the dielectric layer via hole 81 is arranged opposite to the conductor portion 42 of the active layer to facilitate subsequent circuit conduction (see FIG. 7 ).
S6源漏极层制备步骤，在介电层过孔81内沉积一金属材料，形成一第二金属层，所述第二金属层延伸至介电层8，经黄光工艺及刻蚀工艺后，所述第二金属层形成源漏极层9，源漏极层9穿过介电层过孔81连接至有源层的导体部42，保证源漏极层9与有源层4的电性连接，保证整个薄膜晶体管器件的电路连接畅通(参见图8)。S6 source and drain layer preparation step, depositing a metal material in the dielectric layer via hole 81 to form a second metal layer, the second metal layer extends to the dielectric layer 8, after the yellow light process and the etching process , the second metal layer forms the source-drain layer 9, and the source-drain layer 9 is connected to the conductor part 42 of the active layer through the dielectric layer via hole 81, so as to ensure the electrical connection between the source-drain layer 9 and the active layer 4. Sexual connection to ensure smooth circuit connection of the entire thin film transistor device (see FIG. 8 ).
S7保护层制备步骤，在源漏极层9及介电层8的上表面沉积钝化材料，经黄光工艺及刻蚀工艺后，形成保护层10及保护层过孔101，保护层过孔101穿过保护层10，与源漏极层9相对设置，为后续的像素电极层提供电连接通道(参见图9)。S7 protective layer preparation step, deposit passivation material on the upper surface of the source drain layer 9 and the dielectric layer 8, after the yellow light process and the etching process, form the protective layer 10 and the protective layer via hole 101, the protective layer via hole 101 passes through the protective layer 10 and is arranged opposite to the source and drain layers 9 to provide electrical connection channels for subsequent pixel electrode layers (see FIG. 9 ).
S8像素电极层制备步骤，在保护层过孔101内沉积像素电极材料氧化铟锡ITO，且延伸至保护层10的上表面，经黄光工艺及刻蚀工艺后，形成像素电极层11，像素电极层11通过保护层过孔101连接至源漏极层9，完成薄膜晶体管器件的电路连接。S8 pixel electrode layer preparation step, deposit the pixel electrode material indium tin oxide ITO in the protective layer via hole 101, and extend to the upper surface of the protective layer 10, after the yellow light process and the etching process, the pixel electrode layer 11 is formed, and the pixel The electrode layer 11 is connected to the source-drain layer 9 through the protective layer via hole 101 to complete the circuit connection of the thin film transistor device.
本实施例所述的薄膜晶体管器件的制备方法的技术效果在于，在栅极层及栅极绝缘层之间增加一导电层，且所述导电层与所述栅极绝缘层使用同一刻蚀工艺刻蚀所得，使得导电图案与栅极绝缘层在基板上的正投影重合，即栅极绝缘层上表面上各处位置均存在导电层，所述导电层弥补了现有技术中栅极绝缘层边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘层下面对应的有源层都可以被栅极层调控，加大薄膜晶体管器件的开启电流，增强薄膜晶体管器件的电学特性，提高显示装置的显示效果。The technical effect of the preparation method of the thin film transistor device described in this embodiment is that a conductive layer is added between the gate layer and the gate insulating layer, and the conductive layer and the gate insulating layer use the same etching process The result of etching, so that the conductive pattern coincides with the orthographic projection of the gate insulating layer on the substrate, that is, there are conductive layers everywhere on the upper surface of the gate insulating layer, and the conductive layer makes up for the gap of the gate insulating layer in the prior art. There is no gate defect in a short distance above the edge, so that the corresponding active layer under the entire gate insulating layer can be regulated by the gate layer, increasing the turn-on current of the thin film transistor device, and enhancing the electrical characteristics of the thin film transistor device. The display effect of the display device is improved.
如图10所示，本实施例还提供一种薄膜晶体管器件，包括基板1、遮光层2、缓冲层3、有源层4、栅极绝缘层5、导电层6、栅极层7、介电层8、源漏极层9、保护层10及像素电极层11。As shown in FIG. 10, this embodiment also provides a thin film transistor device, including a substrate 1, a light shielding layer 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a conductive layer 6, a gate layer 7, a dielectric Electrical layer 8 , source and drain layer 9 , protection layer 10 and pixel electrode layer 11 .
遮光层2设于基板1的上表面，且遮光层2未覆盖整个基板1，遮光层2起到遮光作用。The light-shielding layer 2 is disposed on the upper surface of the substrate 1, and the light-shielding layer 2 does not cover the entire substrate 1, and the light-shielding layer 2 plays a role of light-shielding.
缓冲层3设于遮光层2及基板1的上表面，缓冲层3起到缓冲作用，缓冲层3的材质为二氧化硅SiO2或者硅的氮化物SiNx，可为单层SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，且二氧化硅SiO2膜层设于顶层。The buffer layer 3 is arranged on the upper surface of the light-shielding layer 2 and the substrate 1. The buffer layer 3 plays a buffer role. The material of the buffer layer 3 is silicon dioxide SiO2 or silicon nitride SiNx , which can be a single-layer SiO2 film layer. Or a multi-layer stack of silicon dioxide SiO2 and silicon nitrideSiNx , and the silicon dioxide SiO2 film layer is set on the top layer.
有源层4设于缓冲层3的上表面，且与遮光层2相对设置。有源层4包括半导体部41及导体部42，导体部42设于半导体部41的外侧，半导体部41保持半导体特性。有源层4的材质为氧化物半导体，例如铟镓锌氧化物IGZO，厚度为300A～500A，在本实施例中，有源层4的厚度优选为400A。The active layer 4 is disposed on the upper surface of the buffer layer 3 and opposite to the light shielding layer 2 . The active layer 4 includes a semiconductor portion 41 and a conductor portion 42 , the conductor portion 42 is disposed outside the semiconductor portion 41 , and the semiconductor portion 41 maintains semiconductor properties. The active layer 4 is made of an oxide semiconductor, such as indium gallium zinc oxide IGZO, and has a thickness of 300A˜500A. In this embodiment, the thickness of the active layer 4 is preferably 400A.
栅极绝缘层5设于有源层4及缓冲层3的上表面，栅极绝缘层5可为单层SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，且二氧化硅SiO2膜层设于底层。The gate insulating layer 5 is disposed on the upper surfaces of the active layer 4 and the buffer layer 3, and the gate insulating layer 5 can be a single-layer SiO2 film layer or a multi-layer stack of silicon dioxide SiO2 and silicon nitrideSiNx , And the silicon dioxide SiO2 film layer is set on the bottom layer.
导电层6设于栅极绝缘层5的上表面，且与栅极绝缘层的尺寸相同或非常相似，导电层6与栅极绝缘层5在基板1上的正投影重合，导电层6的材质为氧化物半导体，例如铟镓锌氧化物IGZO，厚度为100A～400A。The conductive layer 6 is arranged on the upper surface of the gate insulating layer 5, and has the same or very similar size as the gate insulating layer. The conductive layer 6 overlaps with the orthographic projection of the gate insulating layer 5 on the substrate 1. The material of the conductive layer 6 It is an oxide semiconductor, such as indium gallium zinc oxide IGZO, with a thickness of 100A-400A.
导电层6与栅极绝缘层5的尺寸相同或相似，使得栅极绝缘层5的上表面都存在导电图案，弥补了现有技术中栅极绝缘层上表面边缘处无栅极的缺陷，使得栅极绝缘层5下面对应的有源层的半导体部41都能被栅极层7调控，加大薄膜晶体管器件的开启电流，增强薄膜晶体管器件的电学特性，提高显示装置的显示效果。The size of the conductive layer 6 is the same as or similar to that of the gate insulating layer 5, so that there are conductive patterns on the upper surface of the gate insulating layer 5, which makes up for the defect that there is no gate at the edge of the upper surface of the gate insulating layer in the prior art, so that The semiconductor portion 41 of the corresponding active layer under the gate insulating layer 5 can be regulated by the gate layer 7 to increase the turn-on current of the thin film transistor device, enhance the electrical characteristics of the thin film transistor device, and improve the display effect of the display device.
栅极层7设于导电层6的上表面，且尺寸小于导电层6的尺寸，即栅极层7在基板1上的正投影的面积小于导电层6在基板1上的正投影的面积。栅极层7的材质为金属，如铜Cu或钼Mo。The gate layer 7 is disposed on the upper surface of the conductive layer 6 and has a size smaller than that of the conductive layer 6 , that is, the area of the orthographic projection of the gate layer 7 on the substrate 1 is smaller than the area of the orthographic projection of the conductive layer 6 on the substrate 1 . The gate layer 7 is made of metal, such as copper Cu or molybdenum Mo.
介电层8设于栅极层7及缓冲层3的上表面，介电层8上设有两个以上介电层过孔81，介电层过孔81穿过介电层8，且与有源层4的导体部42相对设置，为后续源漏极层提供通道。The dielectric layer 8 is arranged on the upper surface of the gate layer 7 and the buffer layer 3, the dielectric layer 8 is provided with more than two dielectric layer via holes 81, the dielectric layer via holes 81 pass through the dielectric layer 8, and are connected with the The conductor portion 42 of the active layer 4 is disposed opposite to provide a channel for the subsequent source and drain layers.
源漏极层9设于介电层过孔81内，且延伸至介电层8的上表面，源漏极层9连接至有源层4的导体部42，形成源漏极层9与有源层4的电性连接。源漏极层9的材质为金属。The source-drain layer 9 is arranged in the dielectric layer via hole 81 and extends to the upper surface of the dielectric layer 8. The source-drain layer 9 is connected to the conductor portion 42 of the active layer 4 to form the source-drain layer 9 and the active layer. The electrical connection of the source layer 4. The source-drain layer 9 is made of metal.
保护层10设于源漏极层9及介电层8的上表面，保护层10也为钝化层，起到保护下面各膜层的作用。保护层10上设有保护层过孔101，保护层过孔101穿过保护层10，且与源漏极层9相对设置，为后续像素电极层提供电连接的通道。The protective layer 10 is disposed on the upper surfaces of the source-drain layer 9 and the dielectric layer 8 , and the protective layer 10 is also a passivation layer to protect the lower film layers. A protective layer via hole 101 is provided on the protective layer 10 , and the protective layer via hole 101 passes through the protective layer 10 and is opposite to the source and drain layer 9 , providing an electrical connection channel for the subsequent pixel electrode layer.
像素电极层11设于保护层过孔101底部及内侧壁，连接至源漏极层9，且延伸至保护层10的上表面，像素电极层11的材质为氧化铟锡ITO。The pixel electrode layer 11 is disposed on the bottom and inner sidewall of the protective layer via hole 101 , connected to the source and drain layers 9 , and extends to the upper surface of the protective layer 10 . The material of the pixel electrode layer 11 is ITO.
本实施例所述的薄膜晶体管器件的技术效果在于，在栅极层及栅极绝缘层之间增加一导电层，且所述导电层与所述栅极绝缘层使用同一刻蚀工艺刻蚀所得，使得导电图案与栅极绝缘层在基板上的正投影重合，即栅极绝缘层上表面上各处位置均存在导电层，所述导电层弥补了现有技术中栅极绝缘层边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘层下面对应的有源层都可以被上方的栅极层调控，加大薄膜晶体管器件的开启电流，增强薄膜晶体管器件的电学特性，提高显示装置的显示效果。The technical effect of the thin film transistor device described in this embodiment is that a conductive layer is added between the gate layer and the gate insulating layer, and the conductive layer and the gate insulating layer are etched by the same etching process. , so that the conductive pattern coincides with the orthographic projection of the gate insulating layer on the substrate, that is, there are conductive layers everywhere on the upper surface of the gate insulating layer, and the conductive layer makes up for the gap at the edge of the gate insulating layer in the prior art. There is no gate defect in a short distance above, so that the corresponding active layer under the entire gate insulating layer can be regulated by the upper gate layer, increasing the turn-on current of the thin film transistor device, enhancing the electrical characteristics of the thin film transistor device, and improving The display effect of the display device.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered Be the protection scope of the present invention.
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