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CN110163354B - Computing device and method - Google Patents

Computing device and method
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CN110163354B
CN110163354BCN201910195598.7ACN201910195598ACN110163354BCN 110163354 BCN110163354 BCN 110163354BCN 201910195598 ACN201910195598 ACN 201910195598ACN 110163354 BCN110163354 BCN 110163354B
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Abstract

Translated fromChinese

一种计算装置,包括:用于获取输入数据以及计算指令的存储单元(10);用于从存储单元(10)提取计算指令,对该计算指令进行译码以得到一个或多个运算指令和将一个或多个运算指令以及输入数据发送给运算单元(12)的控制器单元(11);和用于根据一个或多个运算指令对输入数据执行计算得到计算指令的结果的运算单元(12)。所述计算装置对参与机器学习计算的数据采用定点数据进行表示,可提升训练运算的处理速度和处理效率。

Figure 201910195598

A computing device, comprising: a storage unit (10) for acquiring input data and calculation instructions; for extracting calculation instructions from the storage unit (10), and decoding the calculation instructions to obtain one or more operation instructions and A controller unit (11) for sending one or more operation instructions and input data to an operation unit (12); and an operation unit (12) for performing a calculation on the input data according to the one or more operation instructions to obtain a result of the calculation instruction ). The computing device uses fixed-point data to represent the data participating in the machine learning calculation, which can improve the processing speed and processing efficiency of the training operation.

Figure 201910195598

Description

Translated fromChinese
一种计算装置及方法A computing device and method

技术领域technical field

本申请涉及信息处理技术领域,具体涉及一种计算装置及方法。The present application relates to the technical field of information processing, and in particular, to a computing device and method.

背景技术Background technique

随着信息技术的不断发展和人们日益增长的需求,人们对信息及时性的要求越来越高了。目前,终端对信息的获取以及处理均是基于通用处理器获得的。With the continuous development of information technology and people's increasing demands, people's requirements for information timeliness are getting higher and higher. At present, the terminal acquires and processes information based on a general-purpose processor.

在实践中发现,这种基于通用处理器运行软件程序来处理信息的方式,受限于通用处理器的运行速率,特别是在通用处理器负荷较大的情况下,信息处理效率较低、时延较大,对于信息处理的计算模型例如训练模型来说,训练运算的计算量更大,通用的处理器完成训练运算的时间长,效率低。In practice, it is found that this method of processing information based on general-purpose processors running software programs is limited by the operating speed of the general-purpose processors, especially when the general-purpose processors are heavily loaded, the information processing efficiency is low, and the time is limited. If the delay is large, for a computing model of information processing, such as a training model, the computing amount of the training operation is larger, and the general-purpose processor takes a long time to complete the training operation, and the efficiency is low.

发明内容SUMMARY OF THE INVENTION

本申请实施例提供了一种计算装置及方法,可提升运算的处理速度,提高效率。The embodiments of the present application provide a computing device and method, which can improve the processing speed of the operation and improve the efficiency.

第一方面,本申请实施例提供一种计算装置包括:存储单元、转换单元、运算单元以及控制器单元;所述存储单元包括缓存和寄存器,In a first aspect, an embodiment of the present application provides a computing device including: a storage unit, a conversion unit, an arithmetic unit, and a controller unit; the storage unit includes a cache and a register,

所述控制器单元,用于确定第一输入数据的小数点位置和定点数据的位宽;所述定点数据的位宽为所述第一输入数据转换为定点数据的位宽;The controller unit is configured to determine the decimal point position of the first input data and the bit width of the fixed-point data; the bit width of the fixed-point data is the bit width of the first input data converted into the fixed-point data;

所述运算单元,用于初始化所述第一输入数据的小数点位置和调整所述第一输入数据的小数点位置;并将所述调整后的第一输入数据的小数点位置存储至所述存储单元的缓存中,The arithmetic unit is used to initialize the decimal point position of the first input data and adjust the decimal point position of the first input data; and store the adjusted decimal point position of the first input data in the storage unit. in cache,

所述控制器单元,用于从所述寄存器中获取第一输入数据和多个运算指令,并从所述缓存中获取所述调整后的第一输入数据的小数点位置;将所述调整后的第一输入数据的小数点位置及所述第一输入数据传输至所述转换单元;The controller unit is configured to obtain the first input data and a plurality of operation instructions from the register, and obtain the decimal point position of the adjusted first input data from the cache; The decimal point position of the first input data and the first input data are transmitted to the conversion unit;

所述转换单元,用于根据所述调整后的第一输入数据的小数点位置将所述第一输入数据转换为第二输入数据;the conversion unit, configured to convert the first input data into the second input data according to the position of the decimal point of the adjusted first input data;

其中,所述运算单元初始化所述第一输入数据的小数点位置,包括:Wherein, the operation unit initializes the decimal point position of the first input data, including:

根据经验值常量初始化所述第一输入数据的小数点位置。The decimal point position of the first input data is initialized according to an empirical value constant.

在一种可能的实施例中,所述运算单元调整所述第一输入数据的小数点位置,包括:In a possible embodiment, the operation unit adjusts the decimal point position of the first input data, including:

根据所述第一输入数据中数据绝对值的最大值单步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据中数据绝对值的最大值逐步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据分布单步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据分布逐步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据绝对值最大值向下调整所述第一输入数据的小数点位置。Adjust the decimal point position of the first input data upward in a single step according to the maximum value of the absolute value of the data in the first input data, or; gradually adjust the first input data upward according to the maximum value of the absolute value of the data in the first input data. The decimal point position of the input data, or; adjust the decimal point position of the first input data upward in a single step according to the distribution of the first input data, or; adjust the first input data gradually upward according to the distribution of the first input data The decimal point position of the first input data, or: adjust the decimal point position of the first input data downward according to the maximum absolute value of the first input data.

在一种可能的实施例中,所述计算装置用于执行机器学习计算,In a possible embodiment, the computing device is configured to perform machine learning computations,

所述控制器单元,还用于将所述多个运算指令传输至所述运算单元;the controller unit, further configured to transmit the plurality of operation instructions to the operation unit;

所述转换单元,还用于将所述第二输入数据传输至所述运算单元;the conversion unit, further configured to transmit the second input data to the operation unit;

所述运算单元,还用于根据所述多个运算指令对所述第二输入数据进行运算,以得到运算结果。The operation unit is further configured to perform an operation on the second input data according to the plurality of operation instructions to obtain an operation result.

在一种可能的实施例中,所述机器学习计算包括:人工神经网络运算,所述第一输入数据包括:输入神经元数据和权值数据;所述计算结果为输出神经元数据。In a possible embodiment, the machine learning calculation includes: artificial neural network operation, the first input data includes: input neuron data and weight data; and the calculation result is output neuron data.

在一种可能的实施例中,所述运算单元包括一个主处理电路和多个从处理电路;In a possible embodiment, the operation unit includes a master processing circuit and a plurality of slave processing circuits;

所述主处理电路,用于对所述第二输入数据进行执行前序处理以及与所述多个从处理电路之间传输数据和所述多个运算指令;the master processing circuit, configured to perform pre-processing on the second input data and transmit data and the multiple operation instructions with the multiple slave processing circuits;

所述多个从处理电路,用于依据从所述主处理电路传输第二输入数据以及所述多个运算指令并执行中间运算得到多个中间结果,并将多个中间结果传输给所述主处理电路;The plurality of slave processing circuits are configured to obtain a plurality of intermediate results according to transmitting the second input data and the plurality of operation instructions from the main processing circuit and performing intermediate operations, and transmit the plurality of intermediate results to the master processing circuit;

所述主处理电路,用于对所述多个中间结果执行后续处理得到所述运算结果。The main processing circuit is configured to perform subsequent processing on the plurality of intermediate results to obtain the operation result.

在一种可能的实施例中,所述计算装置还包括:直接内存访问DMA单元;In a possible embodiment, the computing device further includes: a direct memory access DMA unit;

所述缓存,还用于存储所述第一输入数据;其中,所述缓存包括高速暂存缓存;The cache is also used to store the first input data; wherein, the cache includes a high-speed temporary cache;

所述寄存器,还用于存储所述第一输入数据中标量数据;The register is also used to store scalar data in the first input data;

所述DMA单元,用于从所述存储单元中读取数据或者向所述存储单元存储数据。The DMA unit is configured to read data from the storage unit or store data to the storage unit.

在一种可能的实施例中,当所述第一输入数据为定点数据时,所述运算单元还包括:In a possible embodiment, when the first input data is fixed-point data, the operation unit further includes:

推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.

在一种可能的实施例中,所述运算单元还包括:数据缓存单元,用于缓存所述一个或多个中间结果。In a possible embodiment, the operation unit further includes: a data cache unit, configured to cache the one or more intermediate results.

在一种可能的实施例中,所述运算单元包括:树型模块,所述树型模块包括:一个根端口和多个支端口,所述树型模块的根端口连接所述主处理电路,所述树型模块的多个支端口分别连接多个从处理电路中的一个从处理电路;In a possible embodiment, the operation unit includes: a tree module, the tree module includes: a root port and a plurality of branch ports, the root port of the tree module is connected to the main processing circuit, The multiple branch ports of the tree module are respectively connected to one slave processing circuit in the multiple slave processing circuits;

所述树型模块,用于转发所述主处理电路与所述多个从处理电路之间的数据以及运算指令;其中,所述树型模型为n叉树结构,所述n为大于或等于2的整数。The tree-type module is used to forward data and operation instructions between the master processing circuit and the plurality of slave processing circuits; wherein, the tree-type model is an n-ary tree structure, and n is greater than or equal to An integer of 2.

在一种可能的实施例中,所述运算单元还包括分支处理电路,In a possible embodiment, the operation unit further includes a branch processing circuit,

所述主处理电路,具体用于确定所述输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块、广播数据以及多个运算指令中的至少一个运算指令发送给所述分支处理电路;The main processing circuit is specifically configured to determine that the input neuron is broadcast data, the weight is distribution data, allocate one distribution data into multiple data blocks, and divide at least one data block, sending broadcast data and at least one operation instruction among the plurality of operation instructions to the branch processing circuit;

所述分支处理电路,用于转发所述主处理电路与所述多个从处理电路之间的数据块、广播数据以及运算指令;The branch processing circuit is configured to forward data blocks, broadcast data and operation instructions between the master processing circuit and the plurality of slave processing circuits;

所述多个从处理电路,用于依据该运算指令对接收到的数据块以及广播数据执行运算得到中间结果,并将中间结果传输给所述分支处理电路;The plurality of slave processing circuits are configured to perform operations on the received data blocks and broadcast data according to the operation instructions to obtain intermediate results, and transmit the intermediate results to the branch processing circuits;

所述主处理电路,还用于将所述分支处理电路发送的中间结果进行后续处理得到所述运算指令的结果,将所述计算指令的结果发送至所述控制器单元。The main processing circuit is further configured to perform subsequent processing on the intermediate result sent by the branch processing circuit to obtain the result of the operation instruction, and send the result of the calculation instruction to the controller unit.

在一种可能的实施例中,所述多个从处理电路呈阵列分布;每个从处理电路与相邻的其他从处理电路连接,所述主处理电路连接所述多个从处理电路中的K个从处理电路,所述K个从处理电路为:第1行的n个从处理电路、第m行的n个从处理电路以及第1列的m个从处理电路;In a possible embodiment, the plurality of slave processing circuits are distributed in an array; each slave processing circuit is connected to other adjacent slave processing circuits, and the master processing circuit is connected to one of the plurality of slave processing circuits. K slave processing circuits, the K slave processing circuits are: n slave processing circuits in the first row, n slave processing circuits in the mth row, and m slave processing circuits in the first column;

所述K个从处理电路,用于在所述主处理电路以及多个从处理电路之间的数据以及指令的转发;The K slave processing circuits are used for data and instruction forwarding between the master processing circuit and a plurality of slave processing circuits;

所述主处理电路,还用于确定所述输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块以及多个运算指令中的至少一个运算指令发送给所述K个从处理电路;The main processing circuit is further configured to determine that the input neuron is broadcast data, the weight is distribution data, distribute one distribution data into a plurality of data blocks, and assign at least one data block of the plurality of data blocks and at least one operation instruction in the plurality of operation instructions is sent to the K slave processing circuits;

所述K个从处理电路,用于转换所述主处理电路与所述多个从处理电路之间的数据;the K slave processing circuits for converting data between the master processing circuit and the plurality of slave processing circuits;

所述多个从处理电路,用于依据所述运算指令对接收到的数据块执行运算得到中间结果,并将运算结果传输给所述K个从处理电路;The multiple slave processing circuits are configured to perform operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the K slave processing circuits;

所述主处理电路,用于将所述K个从处理电路发送的中间结果进行处理得到该计算指令的结果,将该计算指令的结果发送给所述控制器单元。The main processing circuit is configured to process the K intermediate results sent from the processing circuit to obtain the result of the calculation instruction, and send the result of the calculation instruction to the controller unit.

在一种可能的实施例中,所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该计算指令的结果;In a possible embodiment, the main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the calculation instruction;

或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该计算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the calculation instruction.

在一种可能的实施例中,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;In a possible embodiment, the main processing circuit includes: one or any combination of an activation processing circuit and an addition processing circuit;

所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;

所述加法处理电路,用于执行加法运算或累加运算。The addition processing circuit is used for performing addition operation or accumulation operation.

所述从处理电路包括:The slave processing circuit includes:

乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;

累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.

第二方面,本申请实施例提供一种计算方法,包括:In a second aspect, an embodiment of the present application provides a computing method, including:

控制器单元确定第一输入数据的小数点位置和定点数据的位宽,所述定点数据的位宽为所述第一输入数据的为定点数据的位宽;运算单元初始化所述第一输入数据的小数点位置和调整所述第一输入数据的小数点位置;转换单元获取调整后的第一输入数据的小数点位置,并根据所述调整后的小数点位置将所述第一输入数据转换为第二输入数据;其中,所述运算单元初始化所述第一输入数据的小数点位置,包括:根据经验值常量初始化所述第一输入数据的小数点位置。The controller unit determines the decimal point position of the first input data and the bit width of the fixed-point data, and the bit width of the fixed-point data is the bit width of the fixed-point data of the first input data; the operation unit initializes the first input data. Decimal point position and adjusting the decimal point position of the first input data; the conversion unit obtains the adjusted decimal point position of the first input data, and converts the first input data into the second input data according to the adjusted decimal point position ; wherein, the operation unit initializing the decimal point position of the first input data includes: initializing the decimal point position of the first input data according to an empirical value constant.

在一种可能的实施例中,所述运算单元调整所述第一输入数据的小数点位置,包括:In a possible embodiment, the operation unit adjusts the decimal point position of the first input data, including:

根据所述第一输入数据中数据绝对值的最大值单步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据中数据绝对值的最大值逐步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据分布单步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据分布逐步向上调整所述第一输入数据的小数点位置,或者;根据所述第一输入数据绝对值最大值向下调整所述第一输入数据的小数点位置。Adjust the decimal point position of the first input data upward in a single step according to the maximum value of the absolute value of the data in the first input data, or; gradually adjust the first input data upward according to the maximum value of the absolute value of the data in the first input data. The decimal point position of the input data, or; adjust the decimal point position of the first input data upward in a single step according to the distribution of the first input data, or; adjust the first input data gradually upward according to the distribution of the first input data The decimal point position of the first input data, or: adjust the decimal point position of the first input data downward according to the maximum absolute value of the first input data.

在一种可能的实施例中,所述计算方法为用于执行机器学习计算的方法,所述方法还包括:所述运算单元根据所述多个运算指令对所述第二输入数据进行运算,以得到运算结果。In a possible embodiment, the calculation method is a method for performing machine learning calculation, and the method further includes: the operation unit performs an operation on the second input data according to the plurality of operation instructions, to get the result of the operation.

在一种可能的实施例中,所述机器学习计算包括:人工神经网络运算,所述第一输入数据包括:输入神经元和权值;所述计算结果为输出神经元。In a possible embodiment, the machine learning calculation includes: an artificial neural network operation, the first input data includes: an input neuron and a weight; the calculation result is an output neuron.

在一种可能的实施例中,当所述第一输入数据为定点数据时,所述方法还包括:In a possible embodiment, when the first input data is fixed-point data, the method further includes:

所述运算单元根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。The operation unit derives the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.

第三方面,本发明实施例提供了一种机器学习运算装置,该机器学习运算装置包括一个或者多个第一方面所述的计算装置。该机器学习运算装置用于从其他处理装置中获取待运算数据和控制信息,并执行指定的机器学习运算,将执行结果通过I/O接口传递给其他处理装置;In a third aspect, an embodiment of the present invention provides a machine learning computing device, where the machine learning computing device includes one or more computing devices described in the first aspect. The machine learning computing device is used to obtain the data to be computed and control information from other processing devices, execute the specified machine learning operation, and transmit the execution result to other processing devices through the I/O interface;

当所述机器学习运算装置包含多个所述计算装置时,所述多个所述计算装置间可以通过特定的结构进行链接并传输数据;When the machine learning computing device includes a plurality of the computing devices, the plurality of the computing devices can be linked through a specific structure and data can be transmitted;

其中,多个所述计算装置通过PCIE总线进行互联并传输数据,以支持更大规模的机器学习的运算;多个所述计算装置共享同一控制系统或拥有各自的控制系统;多个所述计算装置共享内存或者拥有各自的内存;多个所述计算装置的互联方式是任意互联拓扑。Wherein, a plurality of the computing devices are interconnected and transmit data through the PCIE bus to support larger-scale machine learning operations; a plurality of the computing devices share the same control system or have their own control systems; a plurality of the computing devices The devices share memory or have their own memory; the interconnection of a plurality of the computing devices is any interconnection topology.

第四方面,本发明实施例提供了一种组合处理装置,该组合处理装置包括如第三方面所述的机器学习处理装置、通用互联接口,和其他处理装置。该机器学习运算装置与上述其他处理装置进行交互,共同完成用户指定的操作。该组合处理装置还可以包括存储装置,该存储装置分别与所述机器学习运算装置和所述其他处理装置连接,用于保存所述机器学习运算装置和所述其他处理装置的数据。In a fourth aspect, an embodiment of the present invention provides a combined processing device, where the combined processing device includes the machine learning processing device described in the third aspect, a universal interconnection interface, and other processing devices. The machine learning computing device interacts with the above-mentioned other processing devices to jointly complete the operation specified by the user. The combined processing device may further include a storage device, which is respectively connected to the machine learning computing device and the other processing device, and is used for saving the data of the machine learning computing device and the other processing device.

第五方面,本发明实施例提供了一种神经网络芯片,该神经网络芯片包括上述第一方面所述的计算装置、上述第三方面所述的机器学习运算装置或者上述第四方面所述的组合处理装置。In a fifth aspect, an embodiment of the present invention provides a neural network chip, where the neural network chip includes the computing device described in the first aspect, the machine learning computing device described in the third aspect, or the fourth aspect described above. Combined processing unit.

第六方面,本发明实施例提供了一种神经网络芯片封装结构,该神经网络芯片封装结构包括上述第五方面所述的神经网络芯片;In a sixth aspect, an embodiment of the present invention provides a neural network chip packaging structure, and the neural network chip packaging structure includes the neural network chip described in the fifth aspect;

第七方面,本发明实施例提供了一种板卡,该板卡包括存储器件、接口装置和控制器件以及上述第五方面所述的神经网络芯片;In a seventh aspect, an embodiment of the present invention provides a board card, the board card includes a storage device, an interface device, a control device, and the neural network chip described in the fifth aspect;

其中,所述神经网络芯片与所述存储器件、所述控制器件以及所述接口装置分别连接;Wherein, the neural network chip is respectively connected with the storage device, the control device and the interface device;

所述存储器件,用于存储数据;the storage device for storing data;

所述接口装置,用于实现所述芯片与外部设备之间的数据传输;the interface device for realizing data transmission between the chip and an external device;

所述控制器件,用于对所述芯片的状态进行监控。The control device is used for monitoring the state of the chip.

进一步地,所述存储器件包括:多组存储单元,每一组所述存储单元与所述芯片通过总线连接,所述存储单元为:DDR SDRAM;Further, the storage device includes: multiple groups of storage units, each group of the storage units is connected to the chip through a bus, and the storage units are: DDR SDRAM;

所述芯片包括:DDR控制器,用于对每个所述存储单元的数据传输与数据存储的控制;The chip includes: a DDR controller for controlling data transmission and data storage of each of the storage units;

所述接口装置为:标准PCIE接口。The interface device is: a standard PCIE interface.

第八方面,本发明实施例提供了一种电子装置,该电子装置包括上述第五方面所述的神经网络芯片、第六方面所述的神经网络芯片封装结构或者上述第七方面所述的板卡。In an eighth aspect, an embodiment of the present invention provides an electronic device, the electronic device includes the neural network chip described in the fifth aspect, the neural network chip packaging structure described in the sixth aspect, or the board described in the seventh aspect. Card.

在一些实施例中,所述电子设备包括数据处理装置、机器人、电脑、打印机、扫描仪、平板电脑、智能终端、手机、行车记录仪、导航仪、传感器、摄像头、服务器、云端服务器、相机、摄像机、投影仪、手表、耳机、移动存储、可穿戴设备、交通工具、家用电器、和/或医疗设备。In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, Cameras, projectors, watches, headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

在一些实施例中,所述交通工具包括飞机、轮船和/或车辆;所述家用电器包括电视、空调、微波炉、冰箱、电饭煲、加湿器、洗衣机、电灯、燃气灶、油烟机;所述医疗设备包括核磁共振仪、B超仪和/或心电图仪。In some embodiments, the vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical Equipment includes MRI machines, ultrasound machines and/or electrocardiographs.

本发明的这些方面或其他方面在以下实施例的描述中会更加简明易懂。These and other aspects of the invention will be more clearly understood from the description of the following embodiments.

附图说明Description of drawings

为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

图1为本申请实施例提供一种定点数据的数据结构示意图;1 provides a schematic diagram of a data structure of fixed-point data according to an embodiment of the present application;

图2为本申请实施例提供另一种定点数据的数据结构示意图;FIG. 2 provides a schematic diagram of a data structure of another fixed-point data according to an embodiment of the present application;

图2A为本申请实施例提供另一种定点数据的数据结构示意图;FIG. 2A provides a schematic diagram of a data structure of another fixed-point data according to an embodiment of the present application;

图2B为本申请实施例提供另一种定点数据的数据结构示意图;FIG. 2B provides a schematic diagram of a data structure of another fixed-point data according to an embodiment of the present application;

图3本申请实施例提供一种计算装置的结构示意图;3 is a schematic structural diagram of a computing device provided by an embodiment of the present application;

图3A是本申请一个实施例提供的计算装置的结构示意图;3A is a schematic structural diagram of a computing device provided by an embodiment of the present application;

图3B是本申请另一个实施例提供的计算装置的结构示意图;3B is a schematic structural diagram of a computing device provided by another embodiment of the present application;

图3C是本申请另一个实施例提供的计算装置的结构示意图;3C is a schematic structural diagram of a computing device provided by another embodiment of the present application;

图3D是本申请实施例提供的主处理电路的结构示意图;3D is a schematic structural diagram of a main processing circuit provided by an embodiment of the present application;

图3E是本申请另一个实施例提供的计算装置的结构示意图;3E is a schematic structural diagram of a computing device provided by another embodiment of the present application;

图3F是本申请实施例提供的树型模块的结构示意图;3F is a schematic structural diagram of a tree module provided by an embodiment of the present application;

图3G是本申请另一个实施例提供的计算装置的结构示意图;3G is a schematic structural diagram of a computing device provided by another embodiment of the present application;

图3H是本申请另一个实施例提供的计算装置的结构示意图;3H is a schematic structural diagram of a computing device provided by another embodiment of the present application;

图4为本申请实施例提供的一种单层人工神经网络正向运算流程图;4 is a flow chart of forward operation of a single-layer artificial neural network provided by an embodiment of the present application;

图5为本申请实施例提供的一种神经网络正向运算和反向训练流程图;Fig. 5 is a kind of neural network forward operation and reverse training flow chart provided by the embodiment of the application;

图6是本申请实施例提供的一种组合处理装置的结构图;6 is a structural diagram of a combined processing device provided by an embodiment of the present application;

图6A是本申请另一个实施例提供的计算装置的结构示意图;6A is a schematic structural diagram of a computing device provided by another embodiment of the present application;

图7是本申请实施例提供的另一种组合处理装置的结构图;7 is a structural diagram of another combined processing device provided by an embodiment of the present application;

图8为本申请实施例提供的一种板卡的结构示意图;FIG. 8 is a schematic structural diagram of a board provided by an embodiment of the present application;

图9为本申请实施例提供的一种计算方法的流程示意图;9 is a schematic flowchart of a calculation method provided by an embodiment of the present application;

图10为本申请实施例提供的一种数据的小数点位置确定和调整流程示意图;10 is a schematic flowchart of the determination and adjustment of the decimal point position of a kind of data provided by the embodiment of the present application;

图11为本申请实施例提供的一种分布式系统的结构示意图;FIG. 11 is a schematic structural diagram of a distributed system provided by an embodiment of the application;

图12为本申请实施例提供的另一种分布式系统的结构示意图。FIG. 12 is a schematic structural diagram of another distributed system provided by an embodiment of the present application.

具体实施方式Detailed ways

下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象,而不是用于描述特定顺序。此外,术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", "third" and "fourth" in the description and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

在本文中提及“实施例”意味着,结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例,也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是,本文所描述的实施例可以与其它实施例相结合Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments

本申请实施例提供一种数据类型,该数据类型包括调整因子,该调整因子用于指示该数据类型的取值范围及精度。An embodiment of the present application provides a data type, where the data type includes an adjustment factor, and the adjustment factor is used to indicate a value range and precision of the data type.

其中,上述调整因子包括第一缩放因子和第二缩放因子(可选地),该第一缩放因子用于指示上述数据类型的精度;上述第二缩放因子用于调整上述数据类型的取值范围。Wherein, the above-mentioned adjustment factor includes a first scale factor and a second scale factor (optional), the first scale factor is used to indicate the precision of the above-mentioned data type; the above-mentioned second scale factor is used to adjust the value range of the above-mentioned data type .

可选地,上述第一缩放因子可为2-m、8-m、10-m、2、3、6、9、10、2m、8m、10m或者其他值。Optionally, the above-mentioned first scaling factor may be 2-m , 8-m , 10-m , 2, 3, 6, 9, 10, 2m , 8m , 10m or other values.

具体地,上述第一缩放因子可为小数点位置。比如以二进制表示的输入数据INA1的小数点位置向右移动m位后得到的输入数据INB1=INA1*2m,即输入数据INB1相对于输入数据INA1放大了2m倍;再比如,以十进制表示的输入数据INA2的小数点位置左移动n位后得到的输入数据INB2=INA2/10n,即输入数据INA2相对于输入数据INB2缩小了10n倍,m和n均为整数。Specifically, the above-mentioned first scaling factor may be a decimal point position. For example, the input data INB1=INA1*2m obtained after the decimal point position of the input data INA1 expressed in binary is shifted to the right by m bits, that is, the input data INB1 is enlarged by 2m times relative to the input data INA1; for another example, the decimal expressed The input data INB2=INA2/10n obtained after the decimal point position of the input data INA2 is shifted to the left by n bits, that is, the input data INA2 is reduced by 10n times relative to the input data INB2, and both m and n are integers.

可选地,上述第二缩放因子可为2、8、10、16或其他值。Optionally, the above-mentioned second scaling factor may be 2, 8, 10, 16 or other values.

举例说明,上述输入数据对应的数据类型的取值范围为8-15-816,在进行运算过程中,得到的运算结果大于输入数据对应的数据类型的取值范围对应的最大值时,将该数据类型的取值范围乘以该数据类型的第二缩放因子(即8),得到新的取值范围8-14-817;当上述运算结果小于上述输入数据对应的数据类型的取值范围对应的最小值时,将该数据类型的取值范围除以该数据类型的第二缩放因子(8),得到新的取值范围8-16-815For example, the value range of the data type corresponding to the above input data is 8-15 -816 . During the operation process, when the obtained operation result is greater than the maximum value corresponding to the value range of the data type corresponding to the input data, the The value range of the data type is multiplied by the second scaling factor (ie 8) of the data type to obtain a new value range 8-14 -817 ; when the above operation result is less than the value of the data type corresponding to the above input data When the minimum value corresponding to the range is reached, the value range of the data type is divided by the second scaling factor (8) of the data type to obtain a new value range of 8-16 -815 .

对于任何格式的数据(比如浮点数、离散数据)都可以加上缩放因子,以调整该数据的大小和精度。For data in any format (such as floating point numbers, discrete data), scaling factors can be added to adjust the size and precision of the data.

需要说明的是,本申请说明书下文提到的小数点位置都可以是上述第一缩放因子,在此不再叙述。It should be noted that, the position of the decimal point mentioned below in the specification of this application may all be the above-mentioned first scaling factor, which will not be described here.

下面介绍定点数据的结构,参加图1,图1为本申请实施例提供一种定点数据的数据结构示意图。如图1所示有符号的定点数据,该定点数据占X比特位,该定点数据又可称为X位定点数据。其中,该X位定点数据包括占1比特的符号位、M比特的整数位和N比特的小数位,X-1=M+N。对于无符号的定点数据,只包括M比特的整数位和N比特的小数位,即X=M+N。The structure of fixed-point data is described below, referring to FIG. 1 , which provides a schematic diagram of a data structure of fixed-point data according to an embodiment of the present application. As shown in FIG. 1, the signed fixed-point data occupies X bits, and the fixed-point data may also be called X-bit fixed-point data. Wherein, the X-bit fixed-point data includes a sign bit occupying 1 bit, an integer bit of M bits, and a decimal bit of N bits, X−1=M+N. For unsigned fixed-point data, only M bits of integer bits and N bits of fractional bits are included, that is, X=M+N.

相比于32位浮点数据表示形式,本发明采用的短位定点数据表示形式除了占用比特位数更少外,对于网路模型中同一层、同一类型的数据,如第一个卷积层的所有卷积核、输入神经元或者偏置数据,还另外设置了一个标志位记录定点数据的小数点位置,该标志位即为Point Location。这样可以根据输入数据的分布来调整上述标志位的大小,从而达到调整定点数据的精度与定点数据可表示范围。Compared with the 32-bit floating point data representation, the short-bit fixed-point data representation adopted by the present invention not only occupies fewer bits, but also for the same layer and the same type of data in the network model, such as the first convolutional layer. All the convolution kernels, input neurons or bias data of , also set a flag bit to record the decimal point position of the fixed-point data, the flag bit is Point Location. In this way, the size of the flag bit can be adjusted according to the distribution of the input data, so as to adjust the precision of the fixed-point data and the representable range of the fixed-point data.

举例说明,将浮点数68.6875转换为小数点位置为5的有符号16位定点数据。其中,对于小数点位置为5的有符号16位定点数据,其整数部分占10比特,小数部分占5比特,符号位占1比特。上述转换单元将上述浮点数68.6875转换成有符号16位定点数据为0000010010010110,如图2所示。As an example, converts the floating-point number 68.6875 to signed 16-bit fixed-point data with a decimal point of 5. Among them, for the signed 16-bit fixed-point data whose decimal point position is 5, the integer part occupies 10 bits, the fractional part occupies 5 bits, and the sign bit occupies 1 bit. The above conversion unit converts the above floating point number 68.6875 into signed 16-bit fixed point data as 0000010010010110, as shown in FIG. 2 .

在一种可能的实施例中,上述定点数据还可用图2A所示方式进行表示。如图2A所示,该定点数据所占的比特位数为bitnum,小数点位置为s,该定点数据的精度为2s。第一位为符号位,用于指示该定数据是正数还是负数。比如当符号位为0时,表示该定点数据为正数;当符号位为1时,表示该定点数据为负数。该定点数据表示的范围为[neg,pos],其中,pos=(2bitnum-1-1)*2s,neg=-(2bitnum-1-1)*2sIn a possible embodiment, the above-mentioned fixed-point data can also be represented in the manner shown in FIG. 2A . As shown in FIG. 2A , the number of bits occupied by the fixed-point data is bitnum, the position of the decimal point is s, and the precision of the fixed-point data is 2s . The first bit is the sign bit, which is used to indicate whether the fixed data is positive or negative. For example, when the sign bit is 0, it means that the fixed-point data is a positive number; when the sign bit is 1, it means that the fixed-point data is a negative number. The range represented by the fixed-point data is [neg, pos], where pos=(2bitnum-1 -1)*2s and neg=-(2bitnum-1 -1)*2s .

其中,上述bitnum可以去任意正整数。上述s可为任意不小于s_min的整数Among them, the above bitnum can be any positive integer. The above s can be any integer not less than s_min

可选地,上述bitnum可为8、16、24、32、64或者其他值。进一步地,上述s_min为-64。Optionally, the above bitnum may be 8, 16, 24, 32, 64 or other values. Further, the above-mentioned s_min is -64.

可选地,上述bitnum为8,16,24,32或者其他值。s可以取任意不小于s_min的整数,进一步地,s_min取-64。Optionally, the above bitnum is 8, 16, 24, 32 or other values. s can take any integer not less than s_min, and further, s_min takes -64.

在一种实施例中,对于数值较大的数据可采用多种定点表示方法,具体参见图2B:如图2B所示,对上述数值较大的数据采用3种定点数据组合表示,即该数据由定点数据1、定点数据2和定点数据3组成。其中,定点数据1的位宽为bitnum1,小数点位置为s1,定点数据2的位宽为bitnum2,小数点位置为s2;定点数据3的位宽为bitnum3,小数点位置为s3,且bitnum2-2=s1-1,bitnum3-2=s2-1。采用3种定点数据表示的范围为[neg,pos],其中,pos=(2bitnum-1-1)*2s,neg=-(2bitnum-1-1)*2sIn one embodiment, a variety of fixed-point representation methods can be used for data with larger numerical values, as shown in FIG. 2B : as shown in FIG. 2B , three fixed-point data combinations are used to represent the above-mentioned data with larger numerical values, that is, the data It consists of fixed-point data 1, fixed-point data 2 and fixed-point data 3. Among them, the bit width of fixed-point data 1 is bitnum1, the position of the decimal point is s1, the bit width of fixed-point data 2 is bitnum2, and the position of the decimal point is s2; the bit width of fixed-point data 3 is bitnum3, the position of the decimal point is s3, and bitnum2-2=s1 -1, bitnum3-2=s2-1. The range represented by the three kinds of fixed-point data is [neg, pos], where pos=(2bitnum-1 -1)*2s and neg=-(2bitnum-1 -1)*2s .

首先介绍本申请使用的计算装置。参阅图3,提供了一种计算装置,该计算装置包括:控制器单元11、运算单元12和转换单元13,其中,控制器单元11与运算单元12连接,转换单元13与上述控制器单元11和运算单元12均相连接;First, the computing device used in this application is introduced. Referring to FIG. 3, a computing device is provided, the computing device includes: acontroller unit 11, anarithmetic unit 12 and aconversion unit 13, wherein thecontroller unit 11 is connected to thearithmetic unit 12, and theconversion unit 13 is connected to the above-mentionedcontroller unit 11. and theoperation unit 12 are all connected;

在一个可能的实施例中,控制器单元11,用于获取第一输入数据以及计算指令。In a possible embodiment, thecontroller unit 11 is configured to acquire first input data and calculation instructions.

在一个实施例里,第一输入数据是机器学习数据。进一步地,机器学习数据包括输入神经元数据,权值数据。输出神经元数据是最终输出结果或者中间数据。In one embodiment, the first input data is machine learning data. Further, the machine learning data includes input neuron data and weight data. The output neuron data is the final output result or intermediate data.

在一种可选方案中,获取第一输入数据以及计算指令方式具体可以通过数据输入输出单元得到,该数据输入输出单元具体可以为一个或多个数据I/O接口或I/O引脚。In an optional solution, the method of acquiring the first input data and the calculation instruction may be obtained through a data input and output unit, and the data input and output unit may be one or more data I/O interfaces or I/O pins.

上述计算指令包括但不限于:正向运算指令或反向训练指令,或其他神经网络运算指令等等,例如卷积运算指令,本申请具体实施方式并不限制上述计算指令的具体表现形式。The above calculation instructions include but are not limited to: forward operation instructions or reverse training instructions, or other neural network operation instructions, etc., such as convolution operation instructions. The specific embodiment of the present application does not limit the specific expression form of the above calculation instructions.

上述控制器单元11,还用于解析所述计算指令得到数据转换指令和/或一个或多个运算指令,其中,所述数据转换指令包括操作域和操作码,该操作码用于指示所述数据类型转换指令的功能,所述数据类型转换指令的操作域包括小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式标识。The above-mentionedcontroller unit 11 is further configured to parse the calculation instruction to obtain a data conversion instruction and/or one or more operation instructions, wherein the data conversion instruction includes an operation domain and an operation code, and the operation code is used to indicate the The function of the data type conversion instruction, the operation field of the data type conversion instruction includes the decimal point position, the flag bit used to indicate the data type of the first input data, and the conversion mode identifier of the data type.

当上述数据转换指令的操作域为存储空间的地址时,上述控制器单元11根据该地址对应的存储空间中获取上述小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式标识。When the operation domain of the above-mentioned data conversion instruction is the address of the storage space, the above-mentionedcontroller unit 11 obtains the above-mentioned decimal point position, the flag bit for indicating the data type of the first input data, and the data type according to the storage space corresponding to the address. Conversion method ID.

上述控制器单元11将所述数据转换指令的操作码和操作域及所述第一输入数据传输至所述转换单元13;将所述多个运算指令传输至所述运算单元12;The above-mentionedcontroller unit 11 transmits the operation code and operation domain of the data conversion instruction and the first input data to theconversion unit 13; transmits the plurality of operation instructions to theoperation unit 12;

上述转换单元13,用于根据所述数据转换指令的操作码和操作域将所述第一输入数据转换为第二输入数据,该第二输入数据为定点数据;并将所述第二输入数据传输至运算单元12;Theabove conversion unit 13 is configured to convert the first input data into second input data according to the operation code and operation domain of the data conversion instruction, and the second input data is fixed-point data; and convert the second input data transmitted to theoperation unit 12;

上述运算单元12,用于根据所述多个运算指令对所述第二输入数据进行运算,以得到所述计算指令的计算结果。The above-mentionedoperation unit 12 is configured to perform operation on the second input data according to the plurality of operation instructions, so as to obtain the calculation result of the calculation instructions.

在一中可能的实施例中,本申请提供的技术方案将运算单元12设置成一主多从结构,对于正向运算的计算指令,其可以将依据正向运算的计算指令将数据进行拆分,这样通过多个从处理电路102即能够对计算量较大的部分进行并行运算,从而提高运算速度,节省运算时间,进而降低功耗。如图3A所示,上述运算单元12包括一个主处理电路101和多个从处理电路102;In one possible embodiment, the technical solution provided by the present application sets thearithmetic unit 12 into a master-multi-slave structure, and for the calculation instruction of the forward operation, it can split the data according to the calculation instruction of the forward operation, In this way, a plurality ofslave processing circuits 102 can perform parallel operations on parts with a large amount of calculation, thereby increasing the operation speed, saving the operation time, and further reducing the power consumption. As shown in FIG. 3A, the above-mentionedarithmetic unit 12 includes amaster processing circuit 101 and a plurality ofslave processing circuits 102;

上述主处理电路101,用于对上述第二输入数据进行执行前序处理以及与上述多个从处理电路102之间传输数据和上述多个运算指令;The above-mentionedmaster processing circuit 101 is used to perform pre-processing on the above-mentioned second input data and transmit data and the above-mentioned plurality of operation instructions with the above-mentioned plurality ofslave processing circuits 102;

上述多个从处理电路102,用于依据从上述主处理电路101传输第二输入数据以及上述多个运算指令并执行中间运算得到多个中间结果,并将多个中间结果传输给上述主处理电路101;The plurality ofslave processing circuits 102 are configured to obtain a plurality of intermediate results according to the transmission of the second input data and the plurality of operation instructions from the above-mentionedmain processing circuit 101 and perform intermediate operations, and transmit the plurality of intermediate results to the above-mentioned main processing circuit. 101;

上述主处理电路101,用于对上述多个中间结果执行后续处理得到上述计算指令的计算结果。The above-mentionedmain processing circuit 101 is configured to perform subsequent processing on the above-mentioned multiple intermediate results to obtain the calculation result of the above-mentioned calculation instruction.

在一个实施例里,机器学习运算包括深度学习运算(即人工神经网络运算),机器学习数据(即第一输入数据)包括输入神经元和权值(即神经网络模型数据)。输出神经元为上述计算指令的计算结果或中间结果。下面以深度学习运算为例,但应理解的是,不局限在深度学习运算。In one embodiment, the machine learning operations include deep learning operations (ie, artificial neural network operations), and the machine learning data (ie, first input data) include input neurons and weights (ie, neural network model data). The output neuron is the calculation result or the intermediate result of the above calculation instruction. The following uses deep learning operations as an example, but it should be understood that it is not limited to deep learning operations.

可选的,上述计算装置还可以包括:该存储单元10和直接内存访问(directmemory access,DMA)单元50,存储单元10可以包括:寄存器、缓存中的一个或任意组合,具体的,所述缓存,用于存储所述计算指令;所述寄存器201,用于存储所述第一输入数据和标量。其中第一输入数据包括输入神经元、权值和输出神经元。Optionally, the above-mentioned computing device may further include: thestorage unit 10 and a direct memory access (direct memory access, DMA)unit 50, and thestorage unit 10 may include: one or any combination of a register and a cache. Specifically, the cache , which is used to store the calculation instruction; theregister 201 is used to store the first input data and the scalar. The first input data includes input neurons, weights and output neurons.

所述缓存202为高速暂存缓存。Thecache 202 is a temporary cache.

DMA单元50用于从存储单元10读取或存储数据。TheDMA unit 50 is used to read or store data from thestorage unit 10 .

在一种可能的实施例中,上述寄存器201中存储有上述运算指令、第一输入数据、小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式标识;上述控制器单元11直接从上述寄存器201中获取上述运算指令、第一输入数据、小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式标识;将第一输入数据、小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式标识出传输至上述转换单元13;将上述运算指令传输至上述运算单元12;In a possible embodiment, the above-mentionedregister 201 stores the above-mentioned operation instruction, the first input data, the decimal point position, the flag bit used to indicate the data type of the first input data, and the conversion mode identifier of the data type; the above-mentioned control Thecontroller unit 11 directly obtains the above-mentioned operation instruction, the first input data, the decimal point position, the flag bit for indicating the data type of the first input data, and the conversion mode identification of the data type from the above-mentionedregister 201; the first input data, the decimal point The position, the flag bit for indicating the data type of the first input data, and the conversion mode of the data type are identified and transmitted to the above-mentionedconversion unit 13; the above-mentioned operation instruction is transmitted to the above-mentionedoperation unit 12;

上述转换单元13根据上述小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式标识将上述第一输入数据转换为第二输入数据;然后将该第二输入数据传输至上述运算单元12;The above-mentionedconversion unit 13 converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, the flag bit for indicating the data type of the first input data and the conversion mode identification of the data type; then this second input data is transmitted. to the above-mentionedarithmetic unit 12;

上述运算单元12根据上述运算指令对上述第二输入数据进行运算,以得到运算结果。The above-mentionedoperation unit 12 performs operation on the above-mentioned second input data according to the above-mentioned operation instruction to obtain an operation result.

可选的,该控制器单元11包括:指令缓存单元110、指令处理单元111和存储队列单元113;Optionally, thecontroller unit 11 includes: aninstruction cache unit 110, aninstruction processing unit 111 and astorage queue unit 113;

所述指令缓存单元110,用于存储所述人工神经网络运算关联的计算指令;Theinstruction cache unit 110 is used to store the calculation instructions associated with the artificial neural network operation;

所述指令处理单元111,用于对所述计算指令解析得到所述数据转换指令和所述多个运算指令,并解析所述数据转换指令以得到所述数据转换指令的操作码和操作域;Theinstruction processing unit 111 is configured to parse the calculation instruction to obtain the data conversion instruction and the plurality of operation instructions, and parse the data conversion instruction to obtain the operation code and operation domain of the data conversion instruction;

所述存储队列单元113,用于存储指令队列,该指令队列包括:按该队列的前后顺序待执行的多个运算指令或计算指令。Thestorage queue unit 113 is used to store an instruction queue, and the instruction queue includes: a plurality of operation instructions or calculation instructions to be executed in the order of the queue.

举例说明,在一个可选的技术方案中,主处理电路101也可以包括一个控制单元,该控制单元可以包括主指令处理单元,具体用于将指令译码成微指令。当然在另一种可选方案中,从处理电路102也可以包括另一个控制单元,该另一个控制单元包括从指令处理单元,具体用于接收并处理微指令。上述微指令可以为指令的下一级指令,该微指令可以通过对指令的拆分或解码后获得,能被进一步解码为各部件、各单元或各处理电路的控制信号。For example, in an optional technical solution, themain processing circuit 101 may also include a control unit, and the control unit may include a main instruction processing unit, which is specifically configured to decode instructions into micro-instructions. Of course, in another optional solution, theslave processing circuit 102 may also include another control unit, and the other control unit includes a slave instruction processing unit, which is specifically configured to receive and process micro-instructions. The above-mentioned micro-instruction may be the next-level instruction of the instruction, and the micro-instruction can be obtained by dividing or decoding the instruction, and can be further decoded into the control signal of each component, each unit or each processing circuit.

在一种可选方案中,该计算指令的结构可以如下表1所示。In an optional solution, the structure of the calculation instruction may be as shown in Table 1 below.

操作码opcode寄存器或立即数register or immediate寄存器/立即数register/immediate……...

表1Table 1

上表中的省略号表示可以包括多个寄存器或立即数。The ellipsis in the above table indicates that multiple registers or immediate values can be included.

在另一种可选方案中,该计算指令可以包括:一个或多个操作域以及一个操作码。该计算指令可以包括神经网络运算指令。以神经网络运算指令为例,如表1所示,其中,寄存器号0、寄存器号1、寄存器号2、寄存器号3、寄存器号4可以为操作域。其中,每个寄存器号0、寄存器号1、寄存器号2、寄存器号3、寄存器号4可以是一个或者多个寄存器的号码。In another optional solution, the computing instruction may include: one or more operation domains and an operation code. The calculation instructions may include neural network operation instructions. Taking the neural network operation instruction as an example, as shown in Table 1, register number 0,register number 1,register number 2,register number 3, and register number 4 may be operation domains. Wherein, each register number 0,register number 1,register number 2,register number 3, and register number 4 may be the numbers of one or more registers.

Figure BDA0001995399720000091
Figure BDA0001995399720000091

表2Table 2

上述寄存器可以为片外存储器,当然在实际应用中,也可以为片内存储器,用于存储数据,该数据具体可以为n维数据,n为大于等于1的整数,例如,n=1时,为1维数据,即向量,如n=2时,为2维数据,即矩阵,如n=3或3以上时,为多维张量。The above register can be an off-chip memory. Of course, in practical applications, it can also be an on-chip memory for storing data. Specifically, the data can be n-dimensional data, where n is an integer greater than or equal to 1. For example, when n=1, It is 1-dimensional data, that is, a vector. For example, when n=2, it is 2-dimensional data, that is, a matrix. For example, when n=3 or more, it is a multi-dimensional tensor.

可选的,该控制器单元11还可以包括:Optionally, thecontroller unit 11 may further include:

依赖关系处理单元112,用于在具有多个运算指令时,确定第一运算指令与所述第一运算指令之前的第零运算指令是否存在关联关系,如所述第一运算指令与所述第零运算指令存在关联关系,则将所述第一运算指令缓存在所述指令缓存单元110内,在所述第零运算指令执行完毕后,从所述指令缓存单元110提取所述第一运算指令传输至所述运算单元;The dependencyrelationship processing unit 112 is configured to determine whether there is an associated relationship between the first operation instruction and the zeroth operation instruction before the first operation instruction when there are multiple operation instructions, such as the first operation instruction and the first operation instruction. If there is an association relationship between zero operation instructions, the first operation instruction is cached in theinstruction cache unit 110, and after the zeroth operation instruction is executed, the first operation instruction is extracted from theinstruction cache unit 110. transmitted to the computing unit;

所述确定该第一运算指令与第一运算指令之前的第零运算指令是否存在关联关系包括:依据所述第一运算指令提取所述第一运算指令中所需数据(例如矩阵)的第一存储地址区间,依据所述第零运算指令提取所述第零运算指令中所需矩阵的第零存储地址区间,如所述第一存储地址区间与所述第零存储地址区间具有重叠的区域,则确定所述第一运算指令与所述第零运算指令具有关联关系,如所述第一存储地址区间与所述第零存储地址区间不具有重叠的区域,则确定所述第一运算指令与所述第零运算指令不具有关联关系。The determining whether there is an association relationship between the first operation instruction and the zeroth operation instruction before the first operation instruction includes: extracting the first data (for example, a matrix) required in the first operation instruction according to the first operation instruction. storage address interval, extracting the zeroth storage address interval of the matrix required in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have an overlapping area, Then it is determined that the first operation instruction and the zeroth operation instruction have an associated relationship. If the first storage address interval and the zeroth storage address interval do not have overlapping areas, then it is determined that the first operation instruction and the zeroth storage address interval do not overlap. The zeroth operation instruction has no association relationship.

在另一种可选实施例中,如图3B所示,上述运算单元12包括一个主处理电路101、多个从处理电路102和多个分支处理电路103。In another optional embodiment, as shown in FIG. 3B , the above-mentionedoperation unit 12 includes onemaster processing circuit 101 , multipleslave processing circuits 102 and multiplebranch processing circuits 103 .

上述主处理电路101,具体用于确定所述输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块、广播数据以及多个运算指令中的至少一个运算指令发送给所述分支处理电路103;The above-mentionedmain processing circuit 101 is specifically configured to determine that the input neuron is broadcast data, and the weight is distribution data, distribute one distribution data into multiple data blocks, and divide at least one data block, sending broadcast data and at least one operation instruction among the plurality of operation instructions to thebranch processing circuit 103;

所述分支处理电路103,用于转发所述主处理电路101与所述多个从处理电路102之间的数据块、广播数据以及运算指令;Thebranch processing circuit 103 is configured to forward data blocks, broadcast data and operation instructions between themaster processing circuit 101 and the plurality ofslave processing circuits 102;

所述多个从处理电路102,用于依据该运算指令对接收到的数据块以及广播数据执行运算得到中间结果,并将中间结果传输给所述分支处理电路103;The plurality ofslave processing circuits 102 are used to perform operations on the received data blocks and broadcast data according to the operation instruction to obtain intermediate results, and transmit the intermediate results to thebranch processing circuits 103;

上述主处理电路101,还用于将上述分支处理电路103发送的中间结果进行后续处理得到上述运算指令的结果,将上述计算指令的结果发送至上述控制器单元11。Themain processing circuit 101 is further configured to perform subsequent processing on the intermediate result sent by thebranch processing circuit 103 to obtain the result of the operation instruction, and send the result of the calculation instruction to thecontroller unit 11 .

在另一种可选实施例中,运算单元12如图3C所示,可以包括一个主处理电路101和多个从处理电路102。如图3C所示,多个从处理电路102呈阵列分布;每个从处理电路102与相邻的其他从处理电路102连接,主处理电路101连接所述多个从处理电路102中的K个从处理电路102,所述K个从处理电路102为:第1行的n个从处理电路102、第m行的n个从处理电路102以及第1列的m个从处理电路102,需要说明的是,如图3C所示的K个从处理电路102仅包括第1行的n个从处理电路102、第m行的n个从处理电路102以及第1列的m个从处理电路102,即该K个从处理电路102为多个从处理电路102中直接与主处理电路101连接的从处理电路102。In another optional embodiment, as shown in FIG. 3C , theoperation unit 12 may include onemaster processing circuit 101 and multipleslave processing circuits 102 . As shown in FIG. 3C , multipleslave processing circuits 102 are distributed in an array; eachslave processing circuit 102 is connected to other adjacentslave processing circuits 102 , and themaster processing circuit 101 is connected to K of the multipleslave processing circuits 102Slave processing circuits 102, the Kslave processing circuits 102 are: nslave processing circuits 102 in the first row, nslave processing circuits 102 in the mth row, and mslave processing circuits 102 in the first column, which need to be explained. 3C, the Kslave processing circuits 102 only include nslave processing circuits 102 in the first row, nslave processing circuits 102 in the mth row, and mslave processing circuits 102 in the first column. That is, the Kslave processing circuits 102 are theslave processing circuits 102 directly connected to themaster processing circuit 101 among the plurality ofslave processing circuits 102 .

K个从处理电路102,用于在上述主处理电路101以及多个从处理电路102之间的数据以及指令的转发;Kslave processing circuits 102 for forwarding data and instructions between the above-mentionedmaster processing circuit 101 and a plurality ofslave processing circuits 102;

所述主处理电路101,还用于确定上述输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块以及多个运算指令中的至少一个运算指令发送给所述K个从处理电路102;Themain processing circuit 101 is further configured to determine that the input neuron is broadcast data, the weight is distribution data, distribute one distribution data into multiple data blocks, and assign at least one data block and sending at least one operation instruction among the plurality of operation instructions to the Kslave processing circuits 102;

所述K个从处理电路102,用于转换所述主处理电路101与所述多个从处理电路102之间的数据;The Kslave processing circuits 102 are used to convert data between themaster processing circuit 101 and the plurality ofslave processing circuits 102;

所述多个从处理电路102,用于依据所述运算指令对接收到的数据块执行运算得到中间结果,并将运算结果传输给所述K个从处理电路102;The multipleslave processing circuits 102 are configured to perform operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the Kslave processing circuits 102;

所述主处理电路101,用于将所述K个从处理电路102发送的中间结果进行处理得到该计算指令的结果,将该计算指令的结果发送给所述控制器单元11。Themain processing circuit 101 is configured to process the K intermediate results sent from theprocessing circuit 102 to obtain a result of the calculation instruction, and send the result of the calculation instruction to thecontroller unit 11 .

可选的,如图3D所示,上述图3A-图3C中的主处理电路101还可以包括:激活处理电路1011、加法处理电路1012中的一种或任意组合;Optionally, as shown in FIG. 3D, themain processing circuit 101 in the above-mentioned FIGS. 3A-3C may further include: one or any combination of an activation processing circuit 1011 and an addition processing circuit 1012;

激活处理电路1011,用于执行主处理电路101内数据的激活运算;The activation processing circuit 1011 is used to execute the activation operation of the data in themain processing circuit 101;

加法处理电路1012,用于执行加法运算或累加运算。The addition processing circuit 1012 is used for performing addition operation or accumulation operation.

上述从处理电路102包括:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;转发处理电路(可选的),用于将接收到的数据块或乘积结果转发。累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The above-mentionedslave processing circuit 102 includes: a multiplication processing circuit for performing a product operation on the received data block to obtain a product result; a forwarding processing circuit (optional) for forwarding the received data block or the product result. The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.

在一种可行的实施例中,上述第一输入数据为数据类型与参与运算的运算指令所指示的运算类型不一致的数据,第二输入数据为数据类型与参与运算的运算指令所指示的运算类型一致的数据,上述转换单元13获取上述数据转换指令的操作码和操作域,该操作码用于指示该数据转换指令的功能,操作域包括小数点位置和数据类型的转换方式标识。上述转换单元13根据上述小数点位置和数据类型的转换方式标识将上述第一输入数据转换为第二输入数据。In a feasible embodiment, the above-mentioned first input data is data whose data type is inconsistent with the operation type indicated by the operation instruction participating in the operation, and the second input data is the data type and the operation type indicated by the operation instruction participating in the operation. Theconversion unit 13 obtains the operation code and operation field of the data conversion instruction, the operation code is used to indicate the function of the data conversion instruction, and the operation field includes the decimal point position and the conversion mode identifier of the data type. Theconversion unit 13 converts the first input data into the second input data according to the decimal point position and the conversion method identification of the data type.

具体地,上述数据类型的转换方式标识与上述数据类型的转换方式一一对应。参见下表3,表3为一种可行的数据类型的转换方式标识与数据类型的转换方式的对应关系表。Specifically, the conversion mode identifiers of the above data types are in one-to-one correspondence with the conversion modes of the above data types. See Table 3 below. Table 3 is a corresponding relationship table between a feasible data type conversion mode identifier and a data type conversion mode.

数据类型的转换方式标识Data type conversion method identifier数据类型的转换方式How to convert data types0000定点数据转换为定点数据Convert fixed-point data to fixed-point data0101浮点数据转换为浮点数据Convert floating point data to floatingpoint data1010定点数据转换为浮点数据Convert fixed-point data to floating-point data1111浮点数据转换为定点数据Convert floating point data to fixed point data

表3table 3

如表3所示,当上述数据类型的转换方式标识为00时,上述数据类型的转换方式为定点数据转换为定点数据;当上述数据类型的转换方式标识为01时,上述数据类型的转换方式为浮点数据转换为浮点数据;当上述数据类型的转换方式标识为10时,上述数据类型的转换方式为定点数据转换为浮点数据;当上述数据类型的转换方式标识为11时,上述数据类型的转换方式为浮点数据转换为定点数据。As shown in Table 3, when the conversion method of the above-mentioned data type is marked as 00, the conversion method of the above-mentioned data type is that fixed-point data is converted into fixed-point data; when the conversion method of the above-mentioned data type is marked as 01, the conversion method of the above-mentioned data type is Convert floating point data to floating point data; when the conversion method of the above data type is marked as 10, the conversion method of the above data type is to convert fixed-point data to floating point data; when the conversion method of the above data type is marked as 11, the above The conversion method of the data type is to convert floating-point data to fixed-point data.

可选地,上述数据类型的转换方式标识与数据类型的转换方式的对应关系还可如下表4所示。Optionally, the corresponding relationship between the data type conversion mode identifier and the data type conversion mode may also be as shown in Table 4 below.

数据类型的转换方式标识Data type conversion method identifier数据类型的转换方式How to convert data types0000000064位定点数据转换为64位浮点数据Convert 64-bit fixed-point data to 64-bit floating-point data0001000132位定点数据转换为64位浮点数据Convert 32-bit fixed-point data to 64-bit floating-point data0010001016位定点数据转换为64位浮点数据Convert 16-bit fixed-point data to 64-bit floating-point data0011001132位定点数据转换为32位浮点数据Convert 32-bit fixed-point data to 32-bit floating-point data0100010016位定点数据转换为32位浮点数据Convert 16-bit fixed-point data to 32-bit floating-point data0101010116位定点数据转换为16位浮点数据Convert 16-bit fixed-point data to 16-bit floating-point data0110011064位浮点数据转换为64位定点数据Convert 64-bit floating point data to 64-bit fixed-point data0111011132位浮点数据转换为64位定点数据Convert 32-bit floating point data to 64-bit fixed-point data1000100016位浮点数据转换为64位定点数据Convert 16-bit floating point data to 64-bit fixed-point data1001100132位浮点数据转换为32位定点数据Convert 32-bit floating-point data to 32-bit fixed-point data1010101016位浮点数据转换为32位定点数据Convert 16-bit floating-point data to 32-bit fixed-point data1011101116位浮点数据转换为16位定点数据Convert 16-bit floating point data to 16-bit fixed-point data

表4Table 4

如表4所示,当上述数据类型的转换方式标识为0000时,上述数据类型的转换方式为64位定点数据转换为64位浮点数据;当上述数据类型的转换方式标识为0001时,上述数据类型的转换方式为32位定点数据转换为64位浮点数据;当上述数据类型的转换方式标识为0010时,上述数据类型的转换方式为16位定点数据转换为64位浮点数据;当上述数据类型的转换方式标识为0011时,上述数据类型的转换方式为32位定点数据转换为32位浮点数据;当上述数据类型的转换方式标识为0100时,上述数据类型的转换方式为16位定点数据转换为32位浮点数据;当上述数据类型的转换方式标识为0101时,上述数据类型的转换方式为16位定点数据转换为16位浮点数据;当上述数据类型的转换方式标识为0110时,上述数据类型的转换方式为64位浮点数据转换为64位定点数据;当上述数据类型的转换方式标识为0111时,上述数据类型的转换方式为32位浮点数据转换为64位定点数据;当上述数据类型的转换方式标识为1000时,上述数据类型的转换方式为16位浮点数据转换为64位定点数据;当上述数据类型的转换方式标识为1001时,上述数据类型的转换方式为32位浮点数据转换为32位定点数据;当上述数据类型的转换方式标识为1010时,上述数据类型的转换方式为16位浮点数据转换为32位定点数据;当上述数据类型的转换方式标识为1011时,上述数据类型的转换方式为16位浮点数据转换为16位定点数据。As shown in Table 4, when the conversion method of the above data type is marked as 0000, the conversion method of the above data type is that 64-bit fixed-point data is converted into 64-bit floating-point data; when the conversion method of the above data type is marked as 0001, the above The conversion method of the data type is to convert 32-bit fixed-point data to 64-bit floating-point data; when the conversion method of the above data type is identified as 0010, the conversion method of the above data type is to convert 16-bit fixed-point data to 64-bit floating-point data; when When the conversion method of the above data type is marked as 0011, the conversion method of the above data type is that 32-bit fixed-point data is converted into 32-bit floating-point data; when the conversion method of the above data type is marked as 0100, the conversion method of the above data type is 16 The fixed-point data is converted into 32-bit floating-point data; when the conversion method of the above data type is marked as 0101, the conversion method of the above data type is 16-bit fixed-point data is converted into 16-bit floating-point data; when the conversion method of the above data type is marked When it is 0110, the conversion method of the above data type is to convert 64-bit floating point data to 64-bit fixed-point data; when the conversion method of the above data type is marked as 0111, the conversion method of the above data type is 32-bit floating point data to 64 When the conversion method of the above data type is marked as 1000, the conversion method of the above data type is that 16-bit floating point data is converted into 64-bit fixed-point data; when the conversion method of the above data type is marked as 1001, the above data type The conversion method of 32-bit floating point data is converted to 32-bit fixed-point data; when the conversion method of the above data type is marked as 1010, the conversion method of the above data type is 16-bit floating-point data to 32-bit fixed-point data; when the above data type is converted to 32-bit fixed-point data; When the type conversion mode identifier is 1011, the conversion mode of the above data type is 16-bit floating point data to 16-bit fixed-point data.

在一种可行的实施例中,上述控制器单元11从上述存储单元10中获取计算指令,解析该计算指令以得到一个或者多个运算指令,其中该运算指令可为可变格式运算指令或者定点格式运算指令。In a feasible embodiment, thecontroller unit 11 obtains a calculation instruction from thestorage unit 10, and parses the calculation instruction to obtain one or more operation instructions, where the operation instruction may be a variable-format operation instruction or a fixed-point operation instruction Format operation instructions.

其中,上述可变格式运算指令包括操作码和操作域,该操作码用于指示该可变格式运算指令的功能,上述操作域包括第一输入数据的首地址、第一输入数据的长度(可选地)、输出数据的首地址、小数点位置、第一输入数据的数据类型标志位(可选地)和操作类型标识。Wherein, the above-mentioned variable format operation instruction includes an operation code and an operation field, the operation code is used to indicate the function of the variable format operation instruction, and the above-mentioned operation field includes the first address of the first input data, the length of the first input data (optional Optionally), the first address of the output data, the decimal point position, the data type flag bit (optionally) of the first input data, and the operation type identifier.

当上述运算指令为可变格式运算指令时,上述控制器单元11解析上述可变格式运算指令,以得到上述第一输入数据的首地址、第一输入数据的长度、输出数据的首地址、小数点位置、第一输入数据的数据类型标志位和操作类型标识,然后根据第一输入数据的首地址和上述第一输入数据的长度从上述存储单元10中获取第一输入数据,然后将第一输入数据、小数点位置、第一输入数据的数据类型标志位和操作类型标识传输至上述转换单元13,然后将上述输出数据的首地址上述运算单元12;When the operation instruction is a variable format operation instruction, thecontroller unit 11 parses the variable format operation instruction to obtain the first address of the first input data, the length of the first input data, the first address of the output data, and the decimal point. Position, the data type flag bit of the first input data and the operation type identification, then obtain the first input data from the above-mentionedstorage unit 10 according to the first address of the first input data and the length of the first input data, and then the first input data The data, the decimal point position, the data type flag bit and the operation type identification of the first input data are transmitted to the above-mentionedconversion unit 13, and then the above-mentionedoperation unit 12 of the first address of the above-mentioned output data;

上述转换单元13根据上述数据类型标志位、上述小数点位置和上述操作类型标识指示的操作类型将上述第一输入数据转换为第二输入数据;然后将该第二输入数据传输至上述运算单元12。Theconversion unit 13 converts the first input data into second input data according to the data type flag bit, the decimal point position, and the operation type indicated by the operation type identifier; and then transmits the second input data to theoperation unit 12 .

上述运算单元12的主处理电路101和从处理电路102对上述第二输入数据进行运算,以得到上述计算指令的结果;将该计算指令的结果存储至上述存储单元10中上述输出数据的首地址对应的位置。Themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform operations on the above-mentioned second input data to obtain the result of the above-mentioned calculation instruction; store the result of the calculation instruction in the first address of the above-mentioned output data in the above-mentionedstorage unit 10 corresponding location.

其中,上述操作类型标识用于指示上述运算单元12进行运算时参与运算的数据的类型。该类型包括定点数据,浮点数据、整型数据和离散数据等。The above-mentioned operation type identifier is used to indicate the type of data involved in the operation when theoperation unit 12 performs the operation. This type includes fixed-point data, floating-point data, integer data, and discrete data.

在一种可能的实施例中,上述存储单元10中存储有上述第一输入数据的首地址、第一输入数据的长度、输出数据的首地址、小数点位置、第一输入数据的数据类型标志位和操作类型标识,上述控制器单元11直接从上述存储单元10中获取上述上述第一输入数据的首地址、第一输入数据的长度、输出数据的首地址、小数点位置、第一输入数据的数据类型标志位和操作类型标识,然后按照上述过程进行后续操作。In a possible embodiment, thestorage unit 10 stores the first address of the first input data, the length of the first input data, the first address of the output data, the decimal point position, and the data type flag bit of the first input data. and operation type identification, the above-mentionedcontroller unit 11 directly obtains the first address of the above-mentioned first input data, the length of the first input data, the first address of the output data, the decimal point position, the data of the first input data from the above-mentionedstorage unit 10 Type flag bit and operation type identification, and then follow the above process to perform subsequent operations.

举例说明,上述操作类型标识为0或1。当该标志位为1时,上述运算单元12的主处理电路101和从处理电路102进行浮点运算,即参与运算的数据类型为浮点数据;当操作类型标识为0时,上述运算单元12的主处理电路101和从处理电路102进行定点运算,即参与运算的数据类型为定点数据。For example, the above operation type identifier is 0 or 1. When the flag bit is 1, themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform floating-point operations, that is, the data type involved in the operation is floating-point data; when the operation type identifier is 0, the above-mentionedoperation unit 12 Themaster processing circuit 101 and theslave processing circuit 102 perform fixed-point operations, that is, the data type involved in the operations is fixed-point data.

上述运算单元12可根据上述数据标志位和操作类型标识确定输入数据的类型和进行运算的类型。The above-mentionedoperation unit 12 may determine the type of input data and the type of operation to be performed according to the above-mentioned data flag bit and the operation type identifier.

具体地,参见表5,表5为数据类型标志位与操作类型标识的映射关系表。Specifically, see Table 5, which is a mapping relationship table between data type flag bits and operation type identifiers.

Figure BDA0001995399720000121
Figure BDA0001995399720000121

表5table 5

如表5所示,当上述操作类型标识为0且上述数据类型标志位为0时,上述第一输入数据为定点数据,上述运算单元12的主处理电路101和从处理电路102进行定点运算,不进行数据转换;当上述操作类型标识为0且上述数据类型标志位为1时,上述第一输入数据为浮点数据,上述运算单元12的主处理电路101和从处理电路102进行浮点运算,不进行数据转换;当上述操作类型标识为1且上述数据类型标志位为0时,上述第一输入数据为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为浮点数据,上述运算单元12的主处理电路101和从处理电路102对第二输入数据进行运算;当上述操作类型标识为1且上述数据类型标志位为1时,上述第一输入数据为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为定点数据,上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行运算。As shown in Table 5, when the above-mentioned operation type flag is 0 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is fixed-point data, and themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform fixed-point operations, No data conversion is performed; when the above-mentioned operation type identifier is 0 and the above-mentioned data type flag bit is 1, the above-mentioned first input data is floating-point data, and themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedarithmetic unit 12 perform floating-point operations. , do not perform data conversion; when the above-mentioned operation type flag is 1 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the first according to the above-mentioned decimal point position. Two input data, the second input data is floating point data, themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 operate on the second input data; when the above-mentioned operation type flag is 1 and the above-mentioned data type flag bit is 1 When the first input data is floating-point data, theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is fixed-point data. The main processing circuit of thearithmetic unit 12 101 and theslave processing circuit 102 operate on the second input data.

其中,上述定点数据包括64位定点数据、32位定点数据、16位定点数据。上述浮点数据64位浮点数据、32位浮点数据和16位浮点数据。上述标志位与操作类型标识的映射关系具体还可参见下表6。The above-mentioned fixed-point data includes 64-bit fixed-point data, 32-bit fixed-point data, and 16-bit fixed-point data. The above floating point data are 64-bit floating-point data, 32-bit floating-point data, and 16-bit floating-point data. For details on the mapping relationship between the flag bits and the operation type identifier, please refer to Table 6 below.

Figure BDA0001995399720000131
Figure BDA0001995399720000131

Figure BDA0001995399720000141
Figure BDA0001995399720000141

表6Table 6

如表6所示,当上述操作类型标识为0000且上述数据类型标志位为0时,上述第一输入数据为64为定点数据,上述运算单元12的主处理电路101和从处理电路102进行64位定点运算,不进行数据类型转换;当上述操作类型标识为0000且上述数据类型标志位为1时,上述第一输入数据为64为浮点数据,上述运算单元12的主处理电路101和从处理电路102进行64位浮点运算,不进行数据类型转换;当上述操作类型标识为0001且上述数据类型标志位为0时,上述第一输入数据为32为定点数据,上述运算单元12的主处理电路101和从处理电路102进行32位定点运算,不进行数据类型转换;当上述操作类型标识为0001且上述数据类型标志位为1时,上述第一输入数据为32为浮点数据,上述运算单元12的主处理电路101和从处理电路102进行32位浮点运算,不进行数据类型转换;当上述操作类型标识为0010且上述数据类型标志位为0时,上述第一输入数据为16为定点数据,上述运算单元12的主处理电路101和从处理电路102进行16位定点运算,不进行数据类型转换;当上述操作类型标识为0010且上述数据类型标志位为1时,上述第一输入数据为16为浮点数据,上述运算单元12的主处理电路101和从处理电路102进行16位浮点运算,不进行数据类型转换。As shown in Table 6, when the above-mentioned operation type identifier is 0000 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 64 fixed-point data, and themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64 Bit-fixed-point operation, no data type conversion is performed; when the above-mentioned operation type identifier is 0000 and the above-mentioned data type flag bit is 1, the above-mentioned first input data is 64 floating-point data, and themain processing circuit 101 of the above-mentionedoperation unit 12 and the slave Theprocessing circuit 102 performs 64-bit floating-point operations, and does not perform data type conversion; when the above-mentioned operation type identifier is 0001 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 32 is fixed-point data, and the main unit of the above-mentionedoperation unit 12. Theprocessing circuit 101 and theslave processing circuit 102 perform 32-bit fixed-point operations, and do not perform data type conversion; when the above-mentioned operation type identifier is 0001 and the above-mentioned data type flag bit is 1, the above-mentioned first input data is 32 is floating-point data, and the above-mentioned first input data is 32 floating-point data. Themain processing circuit 101 and theslave processing circuit 102 of thearithmetic unit 12 perform 32-bit floating-point operations without data type conversion; when the above-mentioned operation type identifier is 0010 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 16 For fixed-point data, themain processing circuit 101 of the above-mentionedarithmetic unit 12 and theslave processing circuit 102 perform 16-bit fixed-point operations without data type conversion; when the above-mentioned operation type is marked as 0010 and the above-mentioned data type flag bit is 1, the above-mentioned first The input data is 16 floating-point data, and themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 16-bit floating-point operations without data type conversion.

当上述操作类型标识为0011且上述数据类型标志位为0时,上述第一输入数据为64为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为64为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行64位浮点运算;当上述操作类型标识为0011且上述数据类型标志位为1时,上述第一输入数据为64为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为64为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行64位定点运算。When the above-mentioned operation type identifier is 0011 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 64 fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 64 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 0011 and the above-mentioned data type When the flag bit is 1, the first input data is 64 floating point data, theconversion unit 13 first converts the first input data into second input data according to the decimal point position, and the second input data is 64 fixed point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64-bit fixed-point operation on the second input data.

当上述操作类型标识为0100且上述数据类型标志位为0时,上述第一输入数据为32为定点数据,上述转换单元13根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为64为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行64位浮点运算;当上述操作类型标识为0100且上述数据类型标志位为1时,上述第一输入数据为32为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为64为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行64位定点运算。When the above-mentioned operation type identifier is 0100 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 32 is fixed-point data, and the above-mentionedconversion unit 13 converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, and the first input data is The second input data is 64 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 0100 and the above-mentioned data type identifier When the bit is 1, the first input data is 32 floating point data, theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, the second input data is 64 fixed point data, and then Themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64-bit fixed-point operation on the second input data.

当上述操作类型标识为0101且上述数据类型标志位为0时,上述第一输入数据为16为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为64为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行64位浮点运算;当上述操作类型标识为0101且上述数据类型标志位为1时,上述第一输入数据为16为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为64为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行64位定点运算。When the above-mentioned operation type identifier is 0101 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 16 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 64-bit floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 0101 and the above-mentioned data type When the flag bit is 1, the first input data is 16 which is floating point data, theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 64 which is fixed point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 64-bit fixed-point operation on the second input data.

当上述操作类型标识为0110且上述数据类型标志位为0时,上述第一输入数据为32为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为32为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行32位浮点运算;当上述操作类型标识为0110且上述数据类型标志位为1时,上述第一输入数据为32为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为32为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行32位定点运算。When the above-mentioned operation type identifier is 0110 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 32 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 32 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 32-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 0110 and the above-mentioned data type When the flag bit is 1, the first input data is 32, which is floating-point data, and theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 32, which is fixed-point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 32-bit fixed-point operation on the second input data.

当上述操作类型标识为0111且上述数据类型标志位为0时,上述第一输入数据为16为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为32为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行32位浮点运算;当上述操作类型标识为0111且上述数据类型标志位为1时,上述第一输入数据为16为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为32为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行32位定点运算。When the above-mentioned operation type identifier is 0111 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 16 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 32 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 32-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 0111 and the above-mentioned data type When the flag bit is 1, the first input data is 16, which is floating point data, and theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 32, which is fixed-point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 32-bit fixed-point operation on the second input data.

当上述操作类型标识为1000且上述数据类型标志位为0时,上述第一输入数据为16为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为16为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行16位浮点运算;当上述操作类型标识为1000且上述数据类型标志位为1时,上述第一输入数据为16为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为16为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行16位定点运算。When the above-mentioned operation type identifier is 1000 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 16 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 16 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 16-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 1000 and the above-mentioned data type When the flag bit is 1, the first input data is 16, which is floating-point data, and theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 16, which is fixed-point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of theoperation unit 12 perform 16-bit fixed-point operation on the second input data.

当上述操作类型标识为1001且上述数据类型标志位为0时,上述第一输入数据为64为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为32为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行32位浮点运算;当上述操作类型标识为1001且上述数据类型标志位为1时,上述第一输入数据为64为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为32为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行32位定点运算。When the above-mentioned operation type identifier is 1001 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 64 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 32 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 32-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 1001 and the above-mentioned data type When the flag bit is 1, the first input data is 64 floating point data, theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 32 fixed point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 32-bit fixed-point operation on the second input data.

当上述操作类型标识为1010且上述数据类型标志位为0时,上述第一输入数据为64为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为16为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行16位浮点运算;当上述操作类型标识为1010且上述数据类型标志位为1时,上述第一输入数据为64为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为16为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行16位定点运算。When the above-mentioned operation type identifier is 1010 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 64 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 16 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 16-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 1010 and the above-mentioned data type When the flag bit is 1, the first input data is 64 floating point data, theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 16 fixed point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of theoperation unit 12 perform 16-bit fixed-point operation on the second input data.

当上述操作类型标识为1011且上述数据类型标志位为0时,上述第一输入数据为32为定点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为16为浮点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行16位浮点运算;当上述操作类型标识为1011且上述数据类型标志位为1时,上述第一输入数据为32为浮点数据,上述转换单元13先根据上述小数点位置将上述第一输入数据转换为第二输入数据,第二输入数据为16为定点数据,然后上述运算单元12的主处理电路101和从处理电路102对该第二输入数据进行16位定点运算。When the above-mentioned operation type identifier is 1011 and the above-mentioned data type flag bit is 0, the above-mentioned first input data is 32 is fixed-point data, and the above-mentionedconversion unit 13 first converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, The second input data is 16 floating-point data, and then themain processing circuit 101 and theslave processing circuit 102 of the above-mentionedoperation unit 12 perform 16-bit floating-point operations on the second input data; when the above-mentioned operation type identifier is 1011 and the above-mentioned data type When the flag bit is 1, the first input data is 32 floating point data, theconversion unit 13 first converts the first input data into second input data according to the position of the decimal point, and the second input data is 16 fixed point data, Then, themaster processing circuit 101 and theslave processing circuit 102 of theoperation unit 12 perform 16-bit fixed-point operation on the second input data.

在一种可行的实施例中,上述运算指令为定点格式运算指令,该定点格式运算指令包括操作域和操作码,该操作码用于指示该定点格式运算指令的功能,定点格式运算指令的操作码包括第一输入数据的首地址,第一输入数据的长度(可选地)、输出数据的首地址和小数点位置。In a feasible embodiment, the above-mentioned operation instruction is a fixed-point format operation instruction, and the fixed-point format operation instruction includes an operation field and an operation code. The operation code is used to indicate the function of the fixed-point format operation instruction, and the operation of the fixed-point format operation instruction. The code includes the first address of the first input data, the length of the first input data (optionally), the first address of the output data and the decimal point position.

上述控制器单元11获取上述定点格式运算指令后,解析该定点格式运算指令,以得到上述第一输入数据的首地址、第一输入数据的长度、输出数据的首地址和小数点位置;然后上述控制器单元11根据上述第一输入数据的首地址和第一输入数据的长度从上述存储单元10中获取第一输入数据,接着将该第一输入数据和小数点位置传输至上述转换单元13;将上述输出数据的首地址传输至上述运算单元12。上述转换单元根据上述小数点位置将上述第一输入数据转换为第二输入数据,然后将该第二输入数据传输至上述运算单元13,该运算单元12的主处理电路101和从处理电路102按照对上述第二输入数据进行运算,以得到计算指令的结果,并将该计算指令的结果存储至上述存储单元10中上述输出数据的首地址对应的位置。After the above-mentionedcontroller unit 11 obtains the above-mentioned fixed-point format operation instruction, it parses the fixed-point format operation instruction to obtain the first address of the above-mentioned first input data, the length of the first input data, the first address of the output data and the decimal point position; then the above control Theprocessor unit 11 obtains the first input data from the above-mentionedstorage unit 10 according to the first address of the above-mentioned first input data and the length of the first input data, and then transmits the first input data and the decimal point position to the above-mentionedconversion unit 13; The first address of the output data is transmitted to the above-mentionedoperation unit 12 . The above-mentioned conversion unit converts the above-mentioned first input data into the second input data according to the above-mentioned decimal point position, and then transmits the second input data to the above-mentionedoperation unit 13. The above-mentioned second input data is operated to obtain the result of the calculation instruction, and the result of the calculation instruction is stored in the position corresponding to the first address of the above-mentioned output data in the above-mentionedstorage unit 10 .

在一种可行的实施例中,上述计算装置的运算单元13在进行上述多层神经网络模型的第i层的运算之前,该计算装置的控制器单元11获取配置指令,该配置指令包括小数点位置和参与运算的数据类型。该控制器单元11解析该配置指令,以得到小数点位置和参与运算的数据类型,或者从上述存储单元10中直接获取上述小数点位置和参与运算的数据类型,然后上述控制器单元11获取输入数据后,判断输入数据的数据类型与参与运算的数据类型是否一致;当确定输入数据的数据类型与参与运算的数据类型不一致时,上述控制器单元11将上述输入数据、小数点位置和参与运算的数据类型传输至上述转换单元13;该转换单元根据上述小数点位置和参与运算的数据类型对上述输入数据进行数据类型转换,使得输入数据的数据类型与参与运算的数据类型一致;然后将转换后的数据传输至上述运算单元12,该运算单元12的主处理电路101和从处理电路102对转换后的输入数据进行运算;当确定输入数据的数据类型与参与运算的数据类型一致时,上述控制器单元11将上述输入数据传输至上述运算单元12,该运算单元12的主处理电路101和从处理电路102直接对输入数据进行运算,不用进行数据类型转换。In a feasible embodiment, before theoperation unit 13 of the above-mentioned computing device performs the operation of the i-th layer of the above-mentioned multi-layer neural network model, thecontroller unit 11 of the computing device obtains a configuration instruction, and the configuration instruction includes the position of the decimal point and the data types involved in the operation. Thecontroller unit 11 parses the configuration instruction to obtain the position of the decimal point and the data type involved in the operation, or directly obtains the position of the decimal point and the data type involved in the operation from thestorage unit 10, and then thecontroller unit 11 obtains the input data after , judging whether the data type of the input data is consistent with the data type participating in the operation; When determining that the data type of the input data is inconsistent with the data type participating in the operation, the above-mentionedcontroller unit 11 will be the above-mentioned input data, the decimal point position and the data type participating in the operation. Transfer to above-mentionedconversion unit 13; This conversion unit carries out data type conversion to above-mentioned input data according to above-mentioned decimal point position and the data type participating in the operation, so that the data type of the input data is consistent with the data type participating in the operation; Then the converted data is transmitted To the above-mentionedarithmetic unit 12, themain processing circuit 101 of thearithmetic unit 12 and the input data after the conversion are operated from theprocessing circuit 102; when it is determined that the data type of the input data is consistent with the data type participating in the operation, the above-mentionedcontroller unit 11 The above-mentioned input data is transmitted to the above-mentionedoperation unit 12, and themain processing circuit 101 and theslave processing circuit 102 of theoperation unit 12 directly perform operation on the input data without data type conversion.

进一步地,当上述输入数据为定点数据且参与运算的数据类型为定点数据时,上述控制器单元11判断输入数据的小数点位置与参与运算的小数点位置是否一致,若不一致,上述控制器单元11将上述输入数据、输入数据的小数点位置和参与运算的小数点位置传输至上述转换单元13,该转换单元13将输入数据转换为与小数点位置与参与运算的数据的小数点位置一致的定点数据,然后将转换后的数据传输至上述运算单元,该运算单元12的主处理电路101和从处理电路102对转换后的数据进行运算。Further, when the above-mentioned input data is fixed-point data and the data type participating in the operation is fixed-point data, the above-mentionedcontroller unit 11 judges whether the decimal point position of the input data is consistent with the decimal point position participating in the operation, if inconsistent, the above-mentionedcontroller unit 11 will The decimal point position of above-mentioned input data, input data and the decimal point position of participating in operation are transmitted to above-mentionedconversion unit 13, and thisconversion unit 13 converts the input data into fixed-point data consistent with the decimal point position of decimal point position and the data participating in operation, and then converts The converted data is transmitted to the above-mentioned operation unit, and themaster processing circuit 101 and theslave processing circuit 102 of theoperation unit 12 perform operations on the converted data.

换句话说,上述运算指令可以替换为上述配置指令。In other words, the above-mentioned operation instructions can be replaced with the above-mentioned configuration instructions.

另一个实施例里,该运算指令为矩阵乘以矩阵的指令、累加指令、激活指令等等计算指令。In another embodiment, the operation instruction is a matrix-by-matrix instruction, an accumulation instruction, an activation instruction, and other calculation instructions.

在一种可选的实施方案中,如图3E所示,所述运算单元包括:树型模块40,所述树型模块包括:一个根端口401和多个支端口404,所述树型模块的根端口连接所述主处理电路101,所述树型模块的多个支端口分别连接多个从处理电路102中的一个从处理电路102;In an optional implementation, as shown in FIG. 3E, the operation unit includes: atree module 40, the tree module includes: a root port 401 and a plurality of branch ports 404, the tree module The root port of the tree module is connected to themaster processing circuit 101, and the multiple branch ports of the tree module are respectively connected to oneslave processing circuit 102 of the multipleslave processing circuits 102;

上述树型模块具有收发功能,如图3E所示,该树型模块即为发送功能,如图6A所示,该树型模块即为接收功能。The above-mentioned tree-type module has a transceiver function. As shown in FIG. 3E , the tree-type module is a sending function. As shown in FIG. 6A , the tree-type module is a receiving function.

所述树型模块,用于转发所述主处理电路101与所述多个从处理电路102之间的数据块、权值以及运算指令。The tree module is configured to forward data blocks, weights and operation instructions between themaster processing circuit 101 and the plurality ofslave processing circuits 102 .

可选的,该树型模块为计算装置的可选择结果,其可以包括至少1层节点,该节点为具有转发功能的线结构,该节点本身可以不具有计算功能。如树型模块具有零层节点,即无需该树型模块。Optionally, the tree-type module is a selectable result of the computing device, which may include at least one layer of nodes, the node is a line structure with a forwarding function, and the node itself may not have a computing function. If a tree-type module has zero-level nodes, the tree-type module is not required.

可选的,该树型模块可以为n叉树结构,例如,如图3F所示的二叉树结构,当然也可以为三叉树结构,该n可以为大于等于2的整数。本申请具体实施方式并不限制上述n的具体取值,上述层数也可以为2,从处理电路102可以连接除倒数第二层节点以外的其他层的节点,例如可以连接如图3F所示的倒数第一层的节点。Optionally, the tree module may be an n-ary tree structure, for example, a binary tree structure as shown in FIG. 3F , or a ternary tree structure, of course, and n may be an integer greater than or equal to 2. The specific implementation manner of the present application does not limit the specific value of the above n, and the above-mentioned number of layers can also be 2, and theslave processing circuit 102 can be connected to nodes of other layers except the nodes of the penultimate layer, for example, it can be connected as shown in FIG. 3F The node of the penultimate level of .

可选的,上述运算单元可以携带单独的缓存,如图3G所示,可以包括:神经元缓存单元,该神经元缓存单元63缓存该从处理电路102的输入神经元向量数据和输出神经元值数据。Optionally, the above-mentioned operation unit may carry a separate buffer, as shown in FIG. 3G , may include: a neuron buffer unit, theneuron buffer unit 63 buffers the input neuron vector data and the output neuron value of theslave processing circuit 102 data.

如图3H所示,该运算单元还可以包括:权值缓存单元64,用于缓存该从处理电路102在计算过程中需要的权值数据。As shown in FIG. 3H , the operation unit may further include: a weightvalue buffer unit 64 for buffering weight value data required by theslave processing circuit 102 in the calculation process.

在一种可选实施例中,以神经网络运算中的全连接运算为例,过程可以为:y=f(wx+b),其中,x为输入神经元矩阵,w为权值矩阵,b为偏置标量,f为激活函数,具体可以为:sigmoid函数,tanh、relu、softmax函数中的任意一个。这里假设为二叉树结构,具有8个从处理电路102,其实现的方法可以为:In an optional embodiment, taking the fully connected operation in the neural network operation as an example, the process may be: y=f(wx+b), where x is the input neuron matrix, w is the weight matrix, b is a bias scalar, and f is an activation function, which can be: sigmoid function, any one of tanh, relu, and softmax functions. Here, it is assumed to be a binary tree structure with 8slave processing circuits 102, and the implementation method can be as follows:

控制器单元11从存储单元10内获取输入神经元矩阵x,权值矩阵w以及全连接运算指令,将输入神经元矩阵x,权值矩阵w以及全连接运算指令传输给主处理电路101;Thecontroller unit 11 obtains the input neuron matrix x, the weight matrix w and the fully connected operation instruction from thestorage unit 10, and transmits the input neuron matrix x, the weight matrix w and the fully connected operation instruction to themain processing circuit 101;

主处理电路101将输入神经元矩阵x拆分成8个子矩阵,然后将8个子矩阵通过树型模块分发给8个从处理电路102,将权值矩阵w广播给8个从处理电路102,Themain processing circuit 101 splits the input neuron matrix x into 8 sub-matrices, then distributes the 8 sub-matrices to the 8slave processing circuits 102 through the tree module, and broadcasts the weight matrix w to the 8slave processing circuits 102,

从处理电路102并行执行8个子矩阵与权值矩阵w的乘法运算和累加运算得到8个中间结果,将8个中间结果发送给主处理电路101;Theprocessing circuit 102 executes the multiplication and accumulation operations of 8 sub-matrices and the weight matrix w in parallel to obtain 8 intermediate results, and sends the 8 intermediate results to themain processing circuit 101;

上述主处理电路101,用于将8个中间结果排序得到wx的运算结果,将该运算结果执行偏置b的运算后执行激活操作得到最终结果y,将最终结果y发送至控制器单元11,控制器单元11将该最终结果y输出或存储至存储单元10内。The above-mentionedmain processing circuit 101 is used to sort the 8 intermediate results to obtain the operation result of wx, perform the operation of the offset b on the operation result and then execute the activation operation to obtain the final result y, and send the final result y to thecontroller unit 11, Thecontroller unit 11 outputs or stores the final result y into thestorage unit 10 .

在一个实施例里,运算单元12包括但不仅限于:第一部分的第一个或多个乘法器;第二部分的一个或者多个加法器(更具体的,第二个部分的加法器也可以组成加法树);第三部分的激活函数单元;和/或第四部分的向量处理单元。更具体的,向量处理单元可以处理向量运算和/或池化运算。第一部分将输入数据1(in1)和输入数据2(in2)相乘得到相乘之后的输出(out),过程为:out=in1*in2;第二部分将输入数据in1通过加法器相加得到输出数据(out)。更具体的,第二部分为加法树时,将输入数据in1通过加法树逐级相加得到输出数据(out),其中in1是一个长度为N的向量,N大于1,过程为:out=in1[1]+in1[2]+...+in1[N],和/或将输入数据(in1)通过加法数累加之后和输入数据(in2)相加得到输出数据(out),过程为:out=in1[1]+in1[2]+...+in1[N]+in2,或者将输入数据(in1)和输入数据(in2)相加得到输出数据(out),过程为:out=in1+in2;第三部分将输入数据(in)通过激活函数(active)运算得到激活输出数据(out),过程为:out=active(in),激活函数active可以是sigmoid、tanh、relu、softmax等,除了做激活操作,第三部分可以实现其他的非线性函数,可将输入数据(in)通过运算(f)得到输出数据(out),过程为:out=f(in)。向量处理单元将输入数据(in)通过池化运算得到池化操作之后的输出数据(out),过程为out=pool(in),其中pool为池化操作,池化操作包括但不限于:平均值池化,最大值池化,中值池化,输入数据in是和输出out相关的一个池化核中的数据。In one embodiment, theoperation unit 12 includes, but is not limited to: one or more multipliers in the first part; one or more adders in the second part (more specifically, the adders in the second part can also be The activation function unit of the third part; and/or the vector processing unit of the fourth part. More specifically, the vector processing unit may process vector operations and/or pooling operations. The first part multiplies the input data 1 (in1) and the input data 2 (in2) to obtain the multiplied output (out), the process is: out=in1*in2; the second part adds the input data in1 through the adder to get Output data (out). More specifically, when the second part is an addition tree, the input data in1 is added step by step through the addition tree to obtain the output data (out), where in1 is a vector of length N, N is greater than 1, and the process is: out=in1 [1]+in1[2]+...+in1[N], and/or add the input data (in1) to the input data (in2) after accumulating the addition number to obtain the output data (out), the process is: out=in1[1]+in1[2]+...+in1[N]+in2, or add the input data (in1) and the input data (in2) to get the output data (out), the process is: out= in1+in2; in the third part, the input data (in) is operated by the activation function (active) to obtain the activation output data (out), the process is: out=active (in), the activation function active can be sigmoid, tanh, relu, softmax Etc., in addition to the activation operation, the third part can implement other nonlinear functions, and the input data (in) can be obtained through the operation (f) to obtain the output data (out), and the process is: out=f(in). The vector processing unit performs the pooling operation on the input data (in) to obtain the output data (out) after the pooling operation. The process is out=pool(in), where pool is the pooling operation. The pooling operation includes but is not limited to: average Value pooling, max pooling, median pooling, the input data in is the data in a pooling kernel related to the output out.

所述运算单元执行运算包括第一部分是将所述输入数据1和输入数据2相乘,得到相乘之后的数据;和/或第二部分执行加法运算(更具体的,为加法树运算,用于将输入数据1通过加法树逐级相加),或者将所述输入数据1通过和输入数据2相加得到输出数据;和/或第三部分执行激活函数运算,对输入数据通过激活函数(active)运算得到输出数据;和/或第四部分执行池化运算,out=pool(in),其中pool为池化操作,池化操作包括但不限于:平均值池化,最大值池化,中值池化,输入数据in是和输出out相关的一个池化核中的数据。以上几个部分的运算可以自由选择一个多个部分进行不同顺序的组合,从而实现各种不同功能的运算。计算单元相应的即组成了二级,三级,或者四级流水级架构。The operation performed by the operation unit includes that the first part is to multiply theinput data 1 and theinput data 2 to obtain the multiplied data; and/or the second part performs an addition operation (more specifically, an addition tree operation, using In addition, theinput data 1 is added step by step through the addition tree), or theinput data 1 is obtained by adding theinput data 2 to the output data; and/or the third part performs the activation function operation, and the input data is passed through the activation function ( active) operation to obtain output data; and/or the fourth part performs a pooling operation, out=pool(in), where pool is a pooling operation, and the pooling operation includes but is not limited to: average pooling, maximum value pooling, For median pooling, the input data in is the data in a pooling kernel related to the output out. For the operations of the above parts, one or more parts can be freely selected to be combined in different orders, so as to realize the operations of various functions. Correspondingly, the computing unit constitutes a two-level, three-level, or four-level pipeline architecture.

需要说明的是,上述第一输入数据为长位数非定点数据,例如32位浮点数据,也可以是针对标准的64位或者16位浮点数等,这里只是以32位为具体实施例进行说明;上述第二输入数据为短位数定点数据,又称为较少位数定点数据,表示相对于长位数非定点数据的第一输入数据来说,采用更少的位数来表示的定点数据。It should be noted that the above-mentioned first input data is long-digit non-fixed-point data, such as 32-bit floating-point data, or can also be for standard 64-bit or 16-bit floating-point numbers, etc. Here, only 32-bit is used as a specific example. Explanation; the above-mentioned second input data is short-digit fixed-point data, also known as less-digit fixed-point data, which means that compared with the first input data of long-digit non-fixed-point data, it is represented by fewer digits. Fixed-point data.

在一种可行的实施例中,上述第一输入数据为非定点数据,上述第二输入数据为定点数据,该第一输入数据占的比特位数大于或者等于上述第二输入数据占的比特位数。比如上述第一输入输入数据为32位浮点数,上述第二输入数据为32位定点数据;再比如上述第一输入输入数据为32位浮点数,上述第二输入数据为16位定点数据。In a feasible embodiment, the first input data is non-fixed-point data, the second input data is fixed-point data, and the number of bits occupied by the first input data is greater than or equal to the number of bits occupied by the second input data number. For example, the first input data is a 32-bit floating point number, and the second input data is 32-bit fixed-point data; for example, the first input data is a 32-bit floating point number, and the second input data is 16-bit fixed-point data.

具体地,对于不同的网络模型的不同的层,上述第一输入数据包括不同类型的数据。该不同类型的数据的小数点位置不相同,即对应的定点数据的精度不同。对于全连接层,上述第一输入数据包括输入神经元、权值和偏置数据等数据;对于卷积层时,上述第一输入数据包括卷积核、输入神经元和偏置数据等数据。Specifically, for different layers of different network models, the above-mentioned first input data includes different types of data. The decimal point positions of the different types of data are different, that is, the precision of the corresponding fixed-point data is different. For a fully connected layer, the first input data includes data such as input neurons, weights, and bias data; for a convolutional layer, the first input data includes data such as convolution kernels, input neurons, and bias data.

比如对于全连接层,上述小数点位置包括输入神经元的小数点位置、权值的小数点位置和偏置数据的小数点位置。其中,上述输入神经元的小数点位置、权值的小数点位置和偏置数据的小数点位置可以全部相同或者部分相同或者互不相同。For example, for a fully connected layer, the above-mentioned decimal point position includes the decimal point position of the input neuron, the decimal point position of the weight, and the decimal point position of the bias data. Wherein, the position of the decimal point of the input neuron, the position of the decimal point of the weight, and the position of the decimal point of the bias data may be all the same or partially the same or different from each other.

在一种可行的实施例中,所述控制器单元11还用于:在获取第一输入数据以及计算指令之前,确定所述第一输入数据的小数点位置和定点数据的位宽;所述定点数据的位宽为所述第一输入数据转换为定点数据的位宽;In a feasible embodiment, thecontroller unit 11 is further configured to: before acquiring the first input data and the calculation instruction, determine the position of the decimal point of the first input data and the bit width of the fixed point data; the fixed point The bit width of the data is the bit width at which the first input data is converted into fixed-point data;

运算单元12,还用于初始化所述第一输入数据的小数点位置和调整所述第一输入数据的小数点位置。Thearithmetic unit 12 is further configured to initialize the decimal point position of the first input data and adjust the decimal point position of the first input data.

其中,上述第一输入数据的定点数据的位宽为以定点数据表示的第一输入数据所占的比特位,上述小数点位置为以定点数据表示的第一数据数据的小数部分所占的比特位。该小数点位置用于表征定点数据的精度。具体参见图2A的相关描述。Wherein, the bit width of the fixed-point data of the first input data is the bits occupied by the first input data represented by the fixed-point data, and the position of the decimal point is the bits occupied by the fractional part of the first data data represented by the fixed-point data . The decimal point position is used to characterize the precision of fixed-point data. Please refer to the related description of FIG. 2A for details.

具体地,第一输入数据可以为任意类型的数据,该第一输入数据a根据上述小数点位置和定点数据的位宽转换为第二输入数据

Figure BDA0001995399720000181
具体如下:Specifically, the first input data may be any type of data, and the first input data a is converted into the second input data according to the position of the decimal point and the bit width of the fixed-point data
Figure BDA0001995399720000181
details as follows:

Figure BDA0001995399720000191
Figure BDA0001995399720000191

其中,当上述第一输入数据a满足条件neg≤a≤pos时,上述第二输入数据

Figure BDA0001995399720000192
为|a/2s|*2s;当上述第一输入数据a大于pos时,上述第二输入数据
Figure BDA0001995399720000193
为pos;当上述第一输入数据a小于neg时,上述第二输入数据
Figure BDA0001995399720000194
为neg。Wherein, when the first input data a satisfies the condition neg≤a≤pos, the second input data
Figure BDA0001995399720000192
is |a/2s |*2s ; when the above-mentioned first input data a is greater than pos, the above-mentioned second input data
Figure BDA0001995399720000193
is pos; when the above-mentioned first input data a is less than neg, the above-mentioned second input data
Figure BDA0001995399720000194
for neg.

在一种实施例中,对于卷积层和全连接层的输入神经元、权值、输出神经元、输入神经元导数、输出神经元导数和权值导数均采用定点数据进行表示。In one embodiment, the input neurons, weights, output neurons, input neuron derivatives, output neuron derivatives, and weight derivatives of the convolutional layer and the fully connected layer are all represented by fixed-point data.

可选地,上述输入神经元采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述输入神经元采用的定点数据的位宽为8。Optionally, the bit width of the fixed-point data used by the above-mentioned input neurons may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used by the above input neuron is 8.

可选地,上述权值采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述权值采用的定点数据的位宽为8。Optionally, the bit width of the fixed-point data used by the above weights may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used for the above weights is 8.

可选地,上述输入神经元导数采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述输入神经元导数采用的定点数据的位宽为16。Optionally, the bit width of the fixed-point data used for the input neuron derivative may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used for the above input neuron derivative is 16.

可选地,上述输出神经元导数采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述输出神经元导数采用的定点数据的位宽为24。Optionally, the bit width of the fixed-point data used for the above-mentioned output neuron derivative may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used for the above-mentioned output neuron derivative is 24.

可选地,上述权值导数采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述权值导数采用的定点数据的位宽为24。Optionally, the bit width of the fixed-point data used for the weight derivative may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used in the weight derivative is 24.

在一种实施例中,对于参与上述多层网络模型运算的数据中数值较大的数据a可采用多种定点表示方法,具体参见图2B的相关描述。In an embodiment, multiple fixed-point representation methods may be used for the data a with a larger value in the data participating in the above-mentioned multi-layer network model operation. For details, please refer to the relevant description of FIG. 2B .

具体地,第一输入数据可以为任意类型的数据,该第一输入数据a根据上述小数点位置和定点数据的位宽转换为第二输入数据

Figure BDA0001995399720000195
具体如下:Specifically, the first input data may be any type of data, and the first input data a is converted into the second input data according to the position of the decimal point and the bit width of the fixed-point data
Figure BDA0001995399720000195
details as follows:

Figure BDA0001995399720000196
Figure BDA0001995399720000196

其中,当上述第一输入数据a满足条件neg≤a≤pos时,上述第二输入数据

Figure BDA0001995399720000197
Figure BDA0001995399720000198
Figure BDA0001995399720000199
当上述第一输入数据a大于pos时,上述第二输入数据
Figure BDA00019953997200001910
为pos;当上述第一输入数据a小于neg时,上述第二输入数据
Figure BDA00019953997200001911
为neg。Wherein, when the first input data a satisfies the condition neg≤a≤pos, the second input data
Figure BDA0001995399720000197
for
Figure BDA0001995399720000198
and
Figure BDA0001995399720000199
When the first input data a is greater than pos, the second input data
Figure BDA00019953997200001910
is pos; when the above-mentioned first input data a is less than neg, the above-mentioned second input data
Figure BDA00019953997200001911
for neg.

进一步地,所述运算单元12初始化所述第一输入数据的小数点位置,包括:Further, theoperation unit 12 initializes the decimal point position of the first input data, including:

根据所述第一输入数据绝对值的最大值初始化所述第一输入数据的小数点位置,或者;Initialize the decimal point position of the first input data according to the maximum value of the absolute value of the first input data, or;

根据所述第一输入数据的绝对值最小值初始化所述第一输入数据的小数点位置,或者;Initialize the decimal point position of the first input data according to the minimum absolute value of the first input data, or;

根据所述第一输入数据中不同数据类型间关系初始化所述第一输入数据的小数点位置,或者;Initialize the decimal point position of the first input data according to the relationship between different data types in the first input data, or;

根据经验值常量初始化所述第一输入数据的小数点位置。The decimal point position of the first input data is initialized according to an empirical value constant.

具体地,其中,上述小数点位置s需要根据不同类别的数据、不同神经网络层的数据,处于不同迭代轮次的数据进行初始化和动态调整。Specifically, the above-mentioned decimal point position s needs to be initialized and dynamically adjusted according to data of different categories, data of different neural network layers, and data in different iteration rounds.

下面具体介绍第一输入数据的小数点位置s的初始化过程,即确定进行第一次将第一输入数据转换时定点数据所采用的小数点位置s。The following specifically describes the initialization process of the decimal point position s of the first input data, that is, determining the decimal point position s used by the fixed-point data when converting the first input data for the first time.

其中,上述运算单元1211对上述第一输入数据的小数点位置s进行初始化包括:根据第一输入数据绝对值最大值初始化第一输入数据的小数点位置s;根据第一输入数据绝对值的最小值初始化第一输入数据的小数点位置s;根据第一输入数据中不同数据类型间关系初始化第一输入数据的小数点位置s;根据经验值常量初始化第一输入数据的小数点位置s。The operation unit 1211 initializing the decimal point position s of the first input data includes: initializing the decimal point position s of the first input data according to the maximum absolute value of the first input data; initializing according to the minimum value of the absolute value of the first input data. The decimal point position s of the first input data; the decimal point position s of the first input data is initialized according to the relationship between different data types in the first input data; the decimal point position s of the first input data is initialized according to the empirical value constant.

具体地,下面分别具体介绍上述初始化过程。Specifically, the above initialization processes are described in detail below.

a)、上述计算单元12根据第一输入数据绝对值的最大值初始化第一输入数据的小数点位置s:a), the above-mentionedcalculation unit 12 initializes the decimal point position s of the first input data according to the maximum value of the absolute value of the first input data:

上述运算单元12具体通过进行以下公式所示的运算,以初始化上述第一输入数据的小数点位置s:。The above-mentionedoperation unit 12 specifically performs the operation shown in the following formula to initialize the decimal point position s of the above-mentioned first input data: .

Figure BDA0001995399720000201
Figure BDA0001995399720000201

其中,上述amax为上述第一输入数据绝对值的最大值,上述bitnum为上述第一输入数据转换为定点数据的位宽,上述sa为上述第一输入数据的小数点位置。The amax is the maximum absolute value of the first input data, the bitnum is the bit width of the first input data converted to fixed-point data, and the sa is the decimal point position of the first input data.

其中,参与运算的数据按类别与网络层次可分为:第l层的输入神经元X(l)、输出神经元Y(l)、权值W(l)、输入神经元导数

Figure BDA0001995399720000202
输出神经元导数
Figure BDA0001995399720000203
和权值导数
Figure BDA0001995399720000204
寻找绝对值最大值时,可以按数据类别寻找;可以分层、分类别寻找;可以分层、分类别、分组寻找。第一输入数据绝对值的最大值的确定方法包括:Among them, the data involved in the operation can be divided into: the input neuron X(l) of the lth layer, the output neuron Y(l) , the weight W(l) , the input neuron derivative
Figure BDA0001995399720000202
output neuron derivative
Figure BDA0001995399720000203
and weight derivatives
Figure BDA0001995399720000204
When looking for the maximum absolute value, you can search by data category; you can search by layers and categories; you can search by layers, categories, and groups. The method for determining the maximum value of the absolute value of the first input data includes:

a.1)、上述计算单元12按数据类别寻找绝对值最大值a.1), theabove calculation unit 12 finds the absolute maximum value according to the data category

具体地,第一输入数据包括向量/矩阵中的每个元素为ai(l),其中,该a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA0001995399720000205
或输出神经元导数
Figure BDA0001995399720000206
或权值导数
Figure BDA0001995399720000207
换言之,上述第一输入数据包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数,上述第一输入数据的小数点位置包括输入神经元的小数点位置、权值的小数点位置、输出神经元的小数点位置、输入神经元导数的小数点位置、权值导数的小数点位置和输出神经元导数的小数点位置。该输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数均以矩阵或者向量形式表示的。上述运算单元12通过遍历上述多层网络模型的每一层的向量/矩阵中所有元素,获取每种类别数据的绝对值最大值,即
Figure BDA0001995399720000208
通过公式
Figure BDA0001995399720000209
确定每种类别数据a转换为定点数据的小数点位置sa。Specifically, the first input data includes that each element in the vector/matrix is ai(l) , where a(l) can be an input neuron X(l) or an output neuron Y(l) or a weight value W(l) or input neuron derivative
Figure BDA0001995399720000205
or output neuron derivative
Figure BDA0001995399720000206
or weight derivative
Figure BDA0001995399720000207
In other words, the first input data includes input neurons, weights, output neurons, input neuron derivatives, weight derivatives, and output neuron derivatives, and the decimal point position of the first input data includes the decimal point position of the input neuron, the weight value The decimal point position of the value, the decimal point position of the output neuron, the decimal point position of the input neuron derivative, the decimal point position of the weight derivative, and the decimal point position of the output neuron derivative. The input neuron, the weight, the output neuron, the input neuron derivative, the weight derivative and the output neuron derivative are all represented in the form of a matrix or a vector. The above-mentionedoperation unit 12 obtains the absolute maximum value of each type of data by traversing all elements in the vector/matrix of each layer of the above-mentioned multi-layer network model, that is,
Figure BDA0001995399720000208
by formula
Figure BDA0001995399720000209
Determine the decimal point position sa for converting each category of data a to fixed-point data.

a.2)、上述计算单元12按照分层和分数据类别寻找绝对值最大值a.2), theabove calculation unit 12 finds the absolute maximum value according to the hierarchical and sub-data categories

具体地,第一输入数据向量/矩阵中的每个元素为ai(l),其中,该a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA00019953997200002010
或输出神经元导数
Figure BDA00019953997200002011
或权值导数
Figure BDA00019953997200002012
换言之,上述多层网络模型的每层均包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数。上述第一输入数据的小数点位置包括输入神经元的小数点位置、权值的小数点位置、输出神经元的小数点位置、输入神经元导数的小数点位置、权值导数的小数点位置和输出神经元导数的小数点位置。该输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数均以矩阵/向量表示。上述运算单元12通过遍历多层网络模型的每层的每种数据的向量/矩阵中的所有元素,获取每种类别数据的绝对值的最大值,即
Figure BDA00019953997200002013
通过公式:
Figure BDA00019953997200002014
确定在第l层每种类别数据a的小数点位置
Figure BDA00019953997200002015
Specifically, each element in the first input data vector/matrix is ai(l) , where a(l) can be an input neuron X(l) or an output neuron Y(l) or a weight W(l) or input neuron derivative
Figure BDA00019953997200002010
or output neuron derivative
Figure BDA00019953997200002011
or weight derivative
Figure BDA00019953997200002012
In other words, each layer of the above-mentioned multi-layer network model includes input neurons, weights, output neurons, derivatives of input neurons, derivatives of weights, and derivatives of output neurons. The position of the decimal point of the first input data includes the position of the decimal point of the input neuron, the position of the decimal point of the weight, the position of the decimal point of the output neuron, the position of the decimal point of the derivative of the input neuron, the position of the decimal point of the derivative of the weight value, and the decimal point of the derivative of the output neuron. Location. The input neuron, weight, output neuron, input neuron derivative, weight derivative, and output neuron derivative are all represented by a matrix/vector. The above-mentionedoperation unit 12 obtains the maximum value of the absolute value of each type of data by traversing all elements in the vector/matrix of each type of data in each layer of the multi-layer network model, that is,
Figure BDA00019953997200002013
Via the formula:
Figure BDA00019953997200002014
Determine the decimal point position of each category of data a in the lth layer
Figure BDA00019953997200002015

a.3)、上述计算单元12按照分层、分数据类别和分组进寻找绝对值最大值a.3), the above-mentionedcalculation unit 12 searches for the absolute value maximum value according to stratification, sub-data category and grouping

具体地,第一输入数据向量/矩阵中的每个元素为ai(l),其中a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA0001995399720000211
或输出神经元导数
Figure BDA0001995399720000212
或权值导数
Figure BDA0001995399720000213
换言之,上述多层网络模型的每层的数据类别包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数。上述运算单元12将上述多层网络模型的每层的每种类型数据分为g组,或者通过其他任意分组规则进行分组。上述运算单元12然后遍历上述多层网络模型中每层每种类型数据对应的g组数据中每组数据的每个元素,获取该组数据中绝对值最大的元素,即
Figure BDA0001995399720000214
通过公式
Figure BDA0001995399720000215
确定每层中每种数据类别对应的g组数据每组的小数点位置
Figure BDA0001995399720000216
Specifically, each element in the first input data vector/matrix is ai(l) , where a(l) can be an input neuron X(l) or an output neuron Y(l) or a weight W(l ) or the input neuron derivative
Figure BDA0001995399720000211
or output neuron derivative
Figure BDA0001995399720000212
or weight derivative
Figure BDA0001995399720000213
In other words, the data categories of each layer of the above-mentioned multi-layer network model include input neurons, weights, output neurons, derivatives of input neurons, derivatives of weights, and derivatives of output neurons. The above-mentionedoperation unit 12 divides each type of data of each layer of the above-mentioned multi-layer network model into g groups, or groups according to other arbitrary grouping rules. The above-mentionedarithmetic unit 12 then traverses each element of each group of data in the g group data corresponding to each type of data in each layer in the above-mentioned multi-layer network model, and obtains the element with the largest absolute value in the group of data, that is,
Figure BDA0001995399720000214
by formula
Figure BDA0001995399720000215
Determine the decimal point position of each group of g data corresponding to each data category in each layer
Figure BDA0001995399720000216

其中,上述任意分组规则包括但不限定于根据数据范围进行分组、根据数据训练批次进行分组等规则。Wherein, the above arbitrary grouping rules include but are not limited to rules such as grouping according to data range, grouping according to data training batches, and the like.

b)上述运算单元12根据第一输入数据的绝对值最小值初始化该第一输入数据的小数点位置s:b) The above-mentionedarithmetic unit 12 initializes the decimal point position s of the first input data according to the absolute value minimum value of the first input data:

具体地,上述运算单元12找到待量化数据的绝对值最小值amin,通过以下公式确定定点化精度s。Specifically, the above-mentionedoperation unit 12 finds the absolute value minimum value amin of the data to be quantized, and determines the fixed point precision s by the following formula.

Figure BDA0001995399720000217
Figure BDA0001995399720000217

其中,上述amin为上述第一输入数据的绝对值最小值。获取amin的过程具体可参见上述步骤a.1)、a.2)、a.3)。Wherein, the above amin is the minimum absolute value of the above first input data. For details of the process of obtaining amin , please refer to the above steps a.1), a.2), and a.3).

c)上述运算单元12根据第一输入数据中不同数据类型间关系初始化所述第一输入数据的小数点位置s:c) The abovearithmetic unit 12 initializes the decimal point position s of the first input data according to the relationship between different data types in the first input data:

具体地,多层网络模型中的任一层(比如第l层)的数据类型a(l)的小数点位置

Figure BDA0001995399720000218
由上述运算单元12根据第l层的数据类型b(l)的小数点位置
Figure BDA0001995399720000219
和公式
Figure BDA00019953997200002110
确定。Specifically, the decimal point position of the data type a(l) of any layer (such as the lth layer) in the multi-layer network model
Figure BDA0001995399720000218
The position of the decimal point according to the data type b(l) of the lth layer by the above-mentionedarithmetic unit 12
Figure BDA0001995399720000219
and formula
Figure BDA00019953997200002110
Sure.

其中,a(l)和b(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA00019953997200002111
或输出神经元导数
Figure BDA00019953997200002112
或权值导数
Figure BDA00019953997200002113
其中,a(l)和b(l)为整数常数。where a(l) and b(l) can be input neuron X(l) or output neuron Y(l) or weight W(l) or input neuron derivative
Figure BDA00019953997200002111
or output neuron derivative
Figure BDA00019953997200002112
or weight derivative
Figure BDA00019953997200002113
where a(l) and b(l) are integer constants.

d)上述计算单元12根据经验值常量初始化第一输入数据的小数点位置s:d) The above-mentionedcalculation unit 12 initializes the decimal point position s of the first input data according to the empirical value constant:

具体地,上述多层网络模型的任一层(比如第l层)的数据类型a(l)的小数点位置sa(l)可人为设定sa(l)=c,其中c为整数常数,上述a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA00019953997200002114
或输出神经元导数
Figure BDA00019953997200002115
或权值导数
Figure BDA00019953997200002116
Specifically, the decimal point position sa(l) of the data type a(l) of any layer (such as the lth layer) of the above-mentioned multi-layer network model can be manually set as sa(l) = c, where c is an integer constant , the above a(l) can be input neuron X(l) or output neuron Y(l) or weight W(l) or input neuron derivative
Figure BDA00019953997200002114
or output neuron derivative
Figure BDA00019953997200002115
or weight derivative
Figure BDA00019953997200002116

进一步地,上述输入神经元的小数点位置初始化值和输出神经元的小数点位置初始化值均可在[-8,8]范围内选取;权值的小数点位置初始化值可在[-17,8]范围内选取,输入神经元导数的小数点位置初始化值和输出神经元导数的小数点位置初始化值均可在[-40,-20]范围内选取。权值导数的小数点位置初始化值可在[-48,-12]范围内选取。Further, the initialization value of the decimal point position of the input neuron and the initialization value of the decimal point position of the output neuron can be selected in the range of [-8, 8]; the initialization value of the decimal point position of the weight can be in the range of [-17, 8]. The initial value of the decimal point position of the input neuron derivative and the initial value of the decimal point position of the output neuron derivative can be selected within the range of [-40,-20]. The initial value of the decimal point position of the weight derivative can be selected in the range of [-48,-12].

下面具体介绍上述运算单元12动态调整数据上述小数点位置s的方法。The method for dynamically adjusting the above-mentioned decimal point position s of the data by the above-mentionedarithmetic unit 12 will be specifically described below.

上述运算单元12动态调整小数点位置s的方法包括向上调整s(s变大),和向下调整s(s变小)。具体包括根据第一输入数据绝对值最大值单步向上调整;根据第一输入数据绝对值最大值逐步向上调整;根据第一输入数据分布单步向上调整;根据第一输入数据分布逐步向上调整;根据第一输入数据绝对值最大值向下调整。The above-mentioned method for dynamically adjusting the decimal point position s by thearithmetic unit 12 includes adjusting s upward (s increasing), and adjusting s downward (s decreasing). Specifically, it includes a single-step upward adjustment according to the absolute maximum value of the first input data; a step-by-step upward adjustment according to the absolute maximum value of the first input data; a single-step upward adjustment according to the first input data distribution; and a step-by-step upward adjustment according to the first input data distribution; Adjust downward according to the maximum value of the absolute value of the first input data.

a)、上述运算单元12根据第一输入数据中数据绝对值的最大值单步向上调整:a), the above-mentionedarithmetic unit 12 is adjusted upward in a single step according to the maximum value of the absolute value of the data in the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos]。其中,pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。当上述第一输入数据中数据绝对值的最大值amax≥pos时,则调整之后的小数点位置为

Figure BDA0001995399720000221
否则不调整上述小数点位置,即s_new=s_old。Assuming that the position of the decimal point is s_old before adjustment, the fixed-point data corresponding to the position of the decimal point s_old can indicate that the data range is [neg, pos]. Wherein, pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum-1 -1)*2s_old . When the maximum value of the absolute value of the data in the first input data is amax ≥ pos, the adjusted decimal point position is
Figure BDA0001995399720000221
Otherwise, the position of the decimal point is not adjusted, that is, s_new=s_old.

b)、上述运算单元12根据第一输入数据中数据绝对值的最大值逐步向上调整:b), the above-mentionedarithmetic unit 12 is adjusted upward step by step according to the maximum value of the absolute value of the data in the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。当上述第一输入数据中数据绝对值的最大值amax≥pos时,则调整之后的小数点位置为s_new=s_old+1;否则不调整上述小数点位置,即s_new=s_old。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . When the maximum value amax ≥ pos of the absolute value of the data in the first input data, the adjusted decimal point position is s_new=s_old+1; otherwise, the decimal point position is not adjusted, that is, s_new=s_old.

c)、上述运算单元12根据第一输入数据分布单步向上调整:c), the above-mentionedarithmetic unit 12 is adjusted upward in a single step according to the first input data distribution:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。计算第一输入数据的绝对值的统计量,如绝对值的均值amean和绝对值的标准差astd。设置数据的最大范围amax=amean+nastd。当amax≥pos时,

Figure BDA0001995399720000222
否则不调整上述小数点位置,即s_new=s_old。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . Statistics of absolute values of the first input data are calculated, such as the mean amean of the absolute values and the standard deviation astd of the absolute values. Set the maximum range of data amax =amean +nastd . When amax ≥ pos,
Figure BDA0001995399720000222
Otherwise, the position of the decimal point is not adjusted, that is, s_new=s_old.

进一步地,上述n可取2或者3Further, the above n can take 2 or 3

d)、上述运算单元12根据第一输入数据分布逐步向上调整:d), the above-mentionedarithmetic unit 12 is gradually adjusted upward according to the first input data distribution:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。计算第一输入数据的绝对值的统计量,如绝对值的均值amean和绝对值的标准差astd。设置数据的最大范围amax=amean+nastd,n可取3。当amax≥pos时,s_new=s_old+1,否则不调整上述小数点位置,即s_new=s_old。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . Statistics of absolute values of the first input data are calculated, such as the mean amean of the absolute values and the standard deviation astd of the absolute values. Set the maximum range of data amax =amean +nastd , and n can take 3. When amax ≥ pos, s_new=s_old+1, otherwise, the position of the decimal point is not adjusted, that is, s_new=s_old.

e)、上述运算单元12根据第一输入数据绝对值最大值向下调整:e), the above-mentionedarithmetic unit 12 is adjusted downward according to the absolute maximum value of the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。当第一输入数据的绝对值最大值amax<2s_old+(bitnum-n)且s_old≥smin时,s_new=s_old-1,其中n为整数常数,smin可以是整数,也可以是负无穷。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . When the absolute maximum value of the first input data amax <2s_old+(bitnum-n) and s_old≥smin , s_new=s_old-1, where n is an integer constant, and smin can be an integer or negative infinity .

进一步地,上述n为3,上述smin为-64。Further, the above n is 3, and the above smin is -64.

可选地,对于调整上述小数点位置的频率,可以是永远不调整第一输入数据的小数点位置;或者是每隔n个第一训练周期(即iteration)调整一次,n为常量;或者每隔n个第二训练周期(即epoch)调整一次,n为常量;或者是每隔n个第一训练周期或n个第二训练周期调整一次第一输入数据的小数点位置,每隔n个第一训练周期或第二训练周期调整一次第一输入数据的小数点位置,然后调整n=αn,其中α大于1;或者是每隔n个第一训练周期或第二训练周期调整一次第一输入数据的小数点位置,随着训练轮数递增,逐渐减小n。Optionally, for the frequency of adjusting the position of the decimal point, the position of the decimal point of the first input data can be never adjusted; or it is adjusted once every n first training periods (ie iteration), where n is a constant; or every n The second training cycle (ie epoch) is adjusted once, and n is a constant; or the decimal point position of the first input data is adjusted every n first training cycles or n second training cycles, and every n first training cycles are adjusted. Adjust the decimal point position of the first input data once in a period or the second training period, and then adjust n=αn, where α is greater than 1; or adjust the decimal point of the first input data every n first training periods or second training periods position, and gradually decrease n as the number of training epochs increases.

进一步地,每隔100个第一训练周期调整一次输入神经元的小数点位置、权值的小数点位置和输出神经元的小数点位置。每隔20个第一训练周期调整一次输入神经元导数的小数点位置和输出神经元导数的小数点位置。Further, the decimal point position of the input neuron, the decimal point position of the weight and the decimal point position of the output neuron are adjusted every 100 first training cycles. Adjust the decimal point position of the input neuron derivative and the decimal point position of the output neuron derivative every 20 first training epochs.

需要说明的是,上述第一训练周期为训练一批次样本所需的时间,第二训练周期为对所有训练样本进行一次训练所需的时间。It should be noted that the above-mentioned first training period is the time required to train a batch of samples, and the second training period is the time required to perform one training on all the training samples.

在一种可能的实施例中,上述控制器单元11或上述运算单元12按照上述过程获取上述第一输入数据的小数点位置后,将第一输入数据的小数点位置存储至存储单元10的缓存202中。In a possible embodiment, after thecontroller unit 11 or thearithmetic unit 12 acquires the decimal point position of the first input data according to the above process, the decimal point position of the first input data is stored in thebuffer 202 of thestorage unit 10 .

当上述计算指令为立即数寻址的指令时,上述主处理单元101直接根据该计算指令的操作域所指示的小数点位置将第一输入数据进行转换为第二输入数据;当上述计算指令为直接寻址或者间接寻址的指令时,上述主处理单元101根据该计算指令的操作域所指示的存储空间获取第一输入数据的小数点位置,然后根据该小数点位置将第一输入数据进行转换为第二输入数据。When the calculation instruction is an instruction of immediate addressing, themain processing unit 101 directly converts the first input data into the second input data according to the decimal point position indicated by the operation field of the calculation instruction; when the calculation instruction is a direct When addressing or indirectly addressing the instruction, the above-mentionedmain processing unit 101 obtains the decimal point position of the first input data according to the storage space indicated by the operation field of the calculation instruction, and then converts the first input data into the first input data according to the decimal point position. 2. Input data.

上述计算装置还包括舍入单元,在进行运算过程中,由于对第二输入数据进行加法运算、乘法运算和/或其他运算得到的运算结果(该运算结果包括中间运算结果和计算指令的结果)的精度会超出当前定点数据的精度范围,因此上述运算缓存单元缓存上述中间运算结果。在运算结束后,上述舍入单元对超出定点数据精度范围的运算结果进行舍入操作,得到舍入后的运算结果,然后上述数据转换单元将该舍入后的运算结果转换为当前定数数据类型的数据。The above-mentioned computing device also includes a rounding unit. During the operation, the operation result obtained by performing addition operation, multiplication operation and/or other operation on the second input data (the operation result includes the intermediate operation result and the result of the calculation instruction) The precision of the above will exceed the precision range of the current fixed-point data, so the above-mentioned operation buffer unit caches the above-mentioned intermediate operation result. After the operation is completed, the rounding unit performs a rounding operation on the operation result that exceeds the precision range of the fixed-point data to obtain the rounded operation result, and then the data conversion unit converts the rounded operation result into the current constant data type The data.

具体地,上述舍入单元对上述中间运算结果进行舍入操作,该舍入操作为随机舍入操作、四舍五入操作、向上舍入操作、向下舍入操作和截断舍入操作中的任一种。Specifically, the above-mentioned rounding unit performs a rounding operation on the above-mentioned intermediate operation result, and the rounding operation is any one of a random rounding operation, a rounding operation, an upward rounding operation, a downward rounding operation and a truncation rounding operation. .

当上述舍入单元执行随机舍入操作时,该舍入单元具体执行如下操作:When the above-mentioned rounding unit performs a random rounding operation, the rounding unit specifically performs the following operations:

Figure BDA0001995399720000231
Figure BDA0001995399720000231

其中,y表示对舍入前的运算结果x进行随机舍入得到的数据,即上述舍入后的运算结果,ε为当前定点数据表示格式所能表示的最小正数,即2-Point Location

Figure BDA0001995399720000232
表示对上述舍入前的运算结果x直接截得定点数据所得的数(类似于对小数做向下取整操作),w.p.表示概率,上述公式表示对上述舍入前的运算结果x进行随机舍入获得的数据为
Figure BDA0001995399720000233
的概率为
Figure BDA0001995399720000234
对上述中间运算结果x进行随机舍入获得的数据为
Figure BDA0001995399720000235
的概率为
Figure BDA0001995399720000236
Among them, y represents the data obtained by randomly rounding the operation result x before rounding, that is, the operation result after the above rounding, ε is the smallest positive number that can be represented by the current fixed-point data representation format, that is, 2-Point Location ,
Figure BDA0001995399720000232
Represents the number obtained by directly intercepting the fixed-point data from the operation result x before the rounding (similar to the rounding down operation for decimals), wp represents the probability, and the above formula represents the random rounding of the operation result x before the rounding. The data obtained is
Figure BDA0001995399720000233
The probability is
Figure BDA0001995399720000234
The data obtained by randomly rounding the above intermediate operation result x is:
Figure BDA0001995399720000235
The probability is
Figure BDA0001995399720000236

当上述舍入单元进行四舍五入操作时,该舍入单元具体执行如下操作:When the above-mentioned rounding unit performs a rounding operation, the rounding unit specifically performs the following operations:

Figure BDA0001995399720000237
Figure BDA0001995399720000237

其中,y表示对上述舍入前的运算结果x进行四舍五入后得到的数据,即上述舍入后的运算结果,ε为当前定点数据表示格式所能表示的最小正整数,即2-Point Location

Figure BDA0001995399720000238
为ε的整数倍,其值为小于或等于x的最大数。上述公式表示当上述舍入前的运算结果x满足条件
Figure BDA0001995399720000239
时,上述舍入后的运算结果为
Figure BDA00019953997200002310
当上述舍入前的运算结果满足条件
Figure BDA00019953997200002311
时,上述舍入后的运算结果为
Figure BDA00019953997200002312
Among them, y represents the data obtained by rounding the above operation result x before rounding, that is, the above rounded operation result, ε is the smallest positive integer that can be represented by the current fixed-point data representation format, that is, 2-Point Location ,
Figure BDA0001995399720000238
is an integer multiple of ε, and its value is the largest number less than or equal to x. The above formula indicates that when the result x of the operation before the rounding above satisfies the condition
Figure BDA0001995399720000239
, the result of the above rounded operation is
Figure BDA00019953997200002310
When the result of the above operation before rounding satisfies the condition
Figure BDA00019953997200002311
, the result of the above rounded operation is
Figure BDA00019953997200002312

当上述舍入单元进行向上舍入操作时,该舍入单元具体执行如下操作:When the above-mentioned rounding unit performs a round-up operation, the rounding unit specifically performs the following operations:

Figure BDA00019953997200002313
Figure BDA00019953997200002313

其中,y表示对上述舍入前运算结果x进行向上舍入后得到的数据,即上述舍入后的运算结果,

Figure BDA00019953997200002314
为ε的整数倍,其值为大于或等于x的最小数,ε为当前定点数据表示格式所能表示的最小正整数,即2-Point Location。Among them, y represents the data obtained by rounding up the above-mentioned operation result x before rounding, that is, the above-mentioned rounded operation result,
Figure BDA00019953997200002314
It is an integer multiple of ε, and its value is the smallest number greater than or equal to x. ε is the smallest positive integer that can be represented by the current fixed-point data representation format, that is, 2-Point Location .

当上述舍入单元进行向下舍入操作时,该舍入单元具体执行如下操作:When the above rounding unit performs the rounding down operation, the rounding unit specifically performs the following operations:

Figure BDA00019953997200002315
Figure BDA00019953997200002315

其中,y表示对上述舍入前的运算结果x进行向下舍入后得到的数据,即上述舍入后的运算结果,

Figure BDA0001995399720000241
为ε的整数倍,其值为小于或等于x的最大数,ε为当前定点数据表示格式所能表示的最小正整数,即2-Point Location。Among them, y represents the data obtained by rounding down the above-mentioned operation result x before rounding, that is, the above-mentioned rounded operation result,
Figure BDA0001995399720000241
It is an integer multiple of ε, and its value is the largest number less than or equal to x, and ε is the smallest positive integer that can be represented by the current fixed-point data representation format, that is, 2-Point Location .

当上述舍入单元进行截断舍入操作时,该舍入单元具体执行如下操作:When the above-mentioned rounding unit performs a truncation and rounding operation, the rounding unit specifically performs the following operations:

y=[x]y=[x]

其中,y表示对上述舍入前的运算结果x进行截断舍入后得到的数据,即上述舍入后的运算结果,[x]表示对上述运算结果x直接截得定点数据所得的数据。Among them, y represents the data obtained by truncating and rounding the operation result x before rounding, that is, the operation result after the rounding, and [x] represents the data obtained by directly truncating the fixed-point data of the operation result x.

上述舍入单元得到上述舍入后的中间运算结果后,上述运算单元12根据上述第一输入数据的小数点位置将该舍入后的中间运算结果转换为当前定点数据类型的数据。After the rounding unit obtains the rounded intermediate operation result, theoperation unit 12 converts the rounded intermediate operation result into data of the current fixed-point data type according to the decimal point position of the first input data.

在一种可行的实施例中,上述运算单元12对上述一个或者多个中间结果中的数据类型为浮点数据的中间结果不做截断处理。In a feasible embodiment, the above-mentionedoperation unit 12 does not perform truncation processing on the intermediate results whose data type is floating-point data in the above-mentioned one or more intermediate results.

上述运算单元12的从处理电路102根据上述方法进行运算得到的中间结果,由于在该运算过程中存在乘法、除法等会使得到的中间结果超出存储器存储范围的运算,对于超出存储器存储范围的中间结果,一般会对其进行截断处理;但是由于在本申请运算过程中产生的中间结果不用存储在存储器中,因此不用对超出存储器存储范围的中间结果进行截断,极大减少了中间结果的精度损失,提高了计算结果的精度。The intermediate result obtained from the operation performed by theprocessing circuit 102 of the above-mentionedoperation unit 12 according to the above-mentioned method, since there are operations such as multiplication, division, etc. that will cause the obtained intermediate result to exceed the storage range of the memory, for the intermediate result beyond the storage range of the memory. As a result, it is generally truncated; however, since the intermediate results generated in the operation process of this application do not need to be stored in the memory, there is no need to truncate the intermediate results beyond the storage range of the memory, which greatly reduces the precision loss of the intermediate results. , which improves the accuracy of the calculation results.

在一种可行的实施例中,上述运算单元12还包括推导单元,当该运算单元12接收到参与定点运算的输入数据的小数点位置,该推导单元根据该参与定点运算的输入数据的小数点位置推导得到进行定点运算过程中得到一个或者多个中间结果的小数点位置。上述运算子单元进行运算得到的中间结果超过其对应的小数点位置所指示的范围时,上述推导单元将该中间结果的小数点位置左移M位,以使该中间结果的精度位于该中间结果的小数点位置所指示的精度范围之内,该M为大于0的整数。In a feasible embodiment, the above-mentionedoperation unit 12 further includes a derivation unit. When theoperation unit 12 receives the decimal point position of the input data participating in the fixed-point operation, the derivation unit derives the decimal point position of the input data participating in the fixed-point operation. Gets the decimal point position at which one or more intermediate results are obtained during fixed-point arithmetic. When the intermediate result obtained by the operation performed by the above-mentioned operator unit exceeds the range indicated by its corresponding decimal point position, the above-mentioned derivation unit shifts the decimal point position of the intermediate result to the left by M places, so that the precision of the intermediate result is located at the decimal point of the intermediate result. Within the precision range indicated by the position, the M is an integer greater than 0.

举例说明,上述第一输入数据包括输入数据I1和输入数据I2,分别对应的小数点位置分别为P1和P2,且P1>P2,当上述运算指令所指示的运算类型为加法运算或者减法运算,即上述运算子单元进行I1+I2或者I1-I2操作时,上述推导单元推导得到进行上述运算指令所指示的运算过程的中间结果的小数点位置为P1;当上述运算指令所指示的运算类型为乘法运算,即上述运算子单元进行I1*I2操作时,上述推导单元推导得到进行上述运算指令所指示的运算过程的中间结果的小数点位置为P1*P2。For example, the above-mentioned first input data includes input data I1 and input data I2, and the corresponding decimal point positions are P1 and P2 respectively, and P1>P2, when the operation type indicated by the above operation instruction is an addition operation or a subtraction operation, that is, When above-mentioned operation subunit carries out I1+I2 or I1-I2 operation, the decimal point position that above-mentioned deriving unit derives and obtains the intermediate result of the operation process indicated by above-mentioned operation instruction is P1; When the operation type indicated by above-mentioned operation instruction is multiplication operation That is, when the above operation subunit performs the I1*I2 operation, the decimal point position at which the above-mentioned deriving unit derives the intermediate result of the operation process indicated by the above operation instruction is P1*P2.

在一种可行的实施例中,上述运算单元12还包括:In a feasible embodiment, the above-mentionedoperation unit 12 further includes:

数据缓存单元,用于缓存上述一个或多个中间结果。The data cache unit is used to cache the above one or more intermediate results.

在一种可选的实施例中,上述计算装置还包括数据统计单元,该数据统计单元用于对所述多层网络模型的每一层中同一类型的输入数据进行统计,以得到所述每一层中每种类型的输入数据的小数点位置。In an optional embodiment, the above computing device further includes a data statistics unit, which is configured to perform statistics on input data of the same type in each layer of the multi-layer network model, so as to obtain the The decimal point position for each type of input data in a layer.

该数据统计单元也可以是外部装置的一部分,上述计算装置在进行数据转换之前,从外部装置获取参与运算数据的小数点位置。The data statistics unit may also be a part of an external device, and the computing device obtains the position of the decimal point of the data involved in the calculation from the external device before performing the data conversion.

具体地,上述数据统计单元包括:Specifically, the above-mentioned data statistics unit includes:

获取子单元,用于提取所述多层网络模型的每一层中同一类型的输入数据;acquiring subunits for extracting the same type of input data in each layer of the multi-layer network model;

统计子单元,用于统计并获取所述多层网络模型的每一层中同一类型的输入数据在预设区间上的分布比例;a statistical subunit, used to count and obtain the distribution ratio of the same type of input data in each layer of the multi-layer network model in the preset interval;

分析子单元,用于根据所述分布比例获取所述多层网络模型的每一层中同一类型的输入数据的小数点位置。An analysis subunit, configured to obtain the decimal point position of input data of the same type in each layer of the multi-layer network model according to the distribution ratio.

其中,上述预设区间可为

Figure BDA0001995399720000242
i=0,1,2,…,n,n为预设设定的一正整数,X为定点数据所占的比特位数。上述预设区间
Figure BDA0001995399720000251
包括n+1个子区间。上述统计子单元统计上述多层网络模型的每一层中同一类型的输入数据在上述n+1个子区间上分布信息,并根据该分布信息获取上述第一分布比例。该第一分布比例为p0,p1,p2,…,pn,该n+1个数值为上述多层网络模型的每一层中同一类型的输入数据在上述n+1个子区间上的分布比例。上述分析子单元预先设定一个溢出率EPL,从0,1,2,…,n中获取去最大的i,使得pi≥1-EPL,该最大的i为上述多层网络模型的每一层中同一类型的输入数据的小数点位置。换句话说,上述分析子单元取上述多层网络模型的每一层中同一类型的输入数据的小数点位置为:max{i/pi≥1-EPL,i∈{0,1,2,…,n}},即在满足大于或者等于1-EPL的pi中,选取最大的下标值i为上述多层网络模型的每一层中同一类型的输入数据的小数点位置。Wherein, the above-mentioned preset interval may be
Figure BDA0001995399720000242
i=0,1,2,...,n, where n is a preset positive integer, and X is the number of bits occupied by the fixed-point data. The above preset interval
Figure BDA0001995399720000251
Including n+1 subintervals. The above-mentioned statistical subunit counts the distribution information of the input data of the same type in the above-mentioned n+1 sub-intervals in each layer of the above-mentioned multi-layer network model, and obtains the above-mentioned first distribution ratio according to the above-mentioned distribution information. The first distribution ratio is p0 , p1 , p2 ,..., pn , and the n+1 values are the same type of input data in each layer of the above-mentioned multi-layer network model in the above-mentioned n+1 sub-intervals distribution ratio. The above analysis subunit presets an overflow rate EPL, and obtains the largest i from 0, 1, 2, ..., n, so that pi ≥ 1-EPL, the largest i is each of the above multi-layer network models. The decimal point position for input data of the same type in the layer. In other words, the above analysis subunit takes the decimal point position of the same type of input data in each layer of the above multi-layer network model as: max{i /pi ≥1-EPL,i∈{0,1,2,… ,n}}, that is, in the pi that is greater than or equal to 1-EPL, select the largest subscript value i as the decimal point position of the same type of input data in each layer of the above-mentioned multi-layer network model.

需要说明的是,上述pi为上述多层网络模型的每一层中同一类型的输入数据中取值在区间

Figure BDA0001995399720000252
中的输入数据的个数与上述多层网络模型的每一层中同一类型的输入数据总个数的比值。比如m1个多层网络模型的每一层中同一类型的输入数据中有m2个输入数据取值在区间
Figure BDA0001995399720000253
中,则上述
Figure BDA0001995399720000254
It should be noted that the above pi is the value in the interval of the same type of input data in each layer of the above-mentioned multi-layer network model.
Figure BDA0001995399720000252
The ratio of the number of input data in the above-mentioned multi-layer network model to the total number of input data of the same type in each layer of the above-mentioned multi-layer network model. For example, in each layer of m1 multi-layer network models, there are m2 input data values of the same type in the range of the same type of input data.
Figure BDA0001995399720000253
, then the above
Figure BDA0001995399720000254

在一种可行的实施例中,为了提高运算效率,上述获取子单元随机或者抽样提取所述多层网络模型的每一层中同一类型的输入数据中的部分数据,然后按照上述方法获取该部分数据的小数点位置,然后根据该部分数据的小数点位置对该类型输入数据进行数据转换(包括浮点数据转换为定点数据、定点数据转换为定点数据、定点数据转换为定点数据等等),可以实现在即保持精度的前提下,又可以提高计算速度和效率。In a feasible embodiment, in order to improve the operation efficiency, the obtaining subunit randomly or randomly extracts part of the input data of the same type in each layer of the multi-layer network model, and then obtains the part according to the above method The decimal point position of the data, and then perform data conversion (including floating point data to fixed point data, fixed point data to fixed point data, fixed point data to fixed point data, etc.) according to the decimal point position of this part of the data. On the premise of maintaining the accuracy, the calculation speed and efficiency can be improved.

可选地,上述数据统计单元可根据上述同一类型的数据或者同一层数据的中位值确定该同一类型的数据或者同一层数据的位宽和小数点位置,或者根据上述同一类型的数据或者同一层数据的平均值确定该同一类型的数据或者同一层数据的位宽和小数点位置。Optionally, the above-mentioned data statistics unit can determine the bit width and decimal point position of the above-mentioned same type of data or the same layer of data according to the median value of the above-mentioned same type of data or the same layer of data, or according to the above-mentioned same type of data or the same layer of data. The average value of the data determines the bit width and decimal point position of the same type of data or the same layer of data.

可选地,上述运算单元根据对上述同一类型的数据或者同一层数据进行运算得到的中间结果超过该同一层类型的数据或者同一层数据的小数点位置和位宽所对应的取值范围时,该运算单元不对该中间结果进行截断处理,并将该中间结果缓存到该运算单元的数据缓存单元中,以供后续的运算使用。Optionally, when the intermediate result obtained by the operation unit according to the operation on the data of the same type or the data of the same layer exceeds the value range corresponding to the decimal point position and the bit width of the data of the same layer type or the data of the same layer, the The operation unit does not truncate the intermediate result, and caches the intermediate result in the data buffer unit of the operation unit for use in subsequent operations.

具体地,上述操作域包括输入数据的小数点位置和数据类型的转换方式标识。上述指令处理单元对该数据转换指令解析以得到上述输入数据的小数点位置和数据类型的转换方式标识。上述处理单元还包括数据转换单元,该数据转换单元根据上述输入数据的小数点位置和数据类型的转换方式标识将上述第一输入数据转换为第二输入数据。Specifically, the above-mentioned operation field includes the decimal point position of the input data and the identification of the conversion mode of the data type. The above-mentioned instruction processing unit parses the data conversion instruction to obtain the position of the decimal point of the above-mentioned input data and the identification of the conversion mode of the data type. The processing unit further includes a data conversion unit, which converts the first input data into the second input data according to the position of the decimal point of the input data and the conversion mode identification of the data type.

需要说明的是,上述网络模型包括多层,比如全连接层、卷积层、池化层和输入层。上述至少一个输入数据中,属于同一层的输入数据具有同样的小数点位置,即同一层的输入数据共用或者共享同一个小数点位置。It should be noted that the above network model includes multiple layers, such as a fully connected layer, a convolutional layer, a pooling layer and an input layer. In the above at least one input data, the input data belonging to the same layer have the same decimal point position, that is, the input data of the same layer share or share the same decimal point position.

上述输入数据包括不同类型的数据,比如包括输入神经元、权值和偏置数据。上述输入数据中属于同一类型的输入数据具有同样的小数点位置,即上述同一类型的输入数据共用或共享同一个小数点位置。The above-mentioned input data includes different types of data, such as including input neurons, weights, and bias data. The input data belonging to the same type in the above input data have the same decimal point position, that is, the above input data of the same type share or share the same decimal point position.

比如运算指令所指示的运算类型为定点运算,而参与该运算指令所指示的运算的输入数据为浮点数据,故而在进行定点运算之前,上述数转换单元将该输入数据从浮点数据转换为定点数据;再比如运算指令所指示的运算类型为浮点运算,而参与该运算指令所指示的运算的输入数据为定点数据,则在进行浮点运算之前,上述数据转换单元将上述运算指令对应的输入数据从定点数据转换为浮点数据。For example, the operation type indicated by the operation instruction is fixed-point operation, and the input data participating in the operation indicated by the operation instruction is floating-point data. Therefore, before the fixed-point operation is performed, the above-mentioned number conversion unit converts the input data from floating-point data to Fixed-point data; for example, the operation type indicated by the operation instruction is floating-point operation, and the input data participating in the operation indicated by the operation instruction is fixed-point data. The input data is converted from fixed-point data to floating-point data.

对于本申请所涉及的宏指令(比如计算指令和数据转换指令),上述控制器单元11可对宏指令进行解析,以得到该宏指令的操作域和操作码;根据该操作域和操作码生成该宏指令对应的微指令;或者,上述控制器单元11对宏指令进行译码,得到该宏指令对应的微指令。For the macro instructions (such as calculation instructions and data conversion instructions) involved in the present application, the above-mentionedcontroller unit 11 can parse the macro instructions to obtain the operation domain and operation code of the macro instruction; The microinstruction corresponding to the macroinstruction; or, the above-mentionedcontroller unit 11 decodes the macroinstruction to obtain the microinstruction corresponding to the macroinstruction.

在一种可行的实施例中,在片上系统(System On Chip,SOC)中包括主处理器和协处理器,该主处理器包括上述计算装置。该协处理器根据上述方法获取上述多层网络模型的每一层中同一类型的输入数据的小数点位置,并将该多层网络模型的每一层中同一类型的输入数据的小数点位置传输至上述计算装置,或者该计算装置在需要使用上述多层网络模型的每一层中同一类型的输入数据的小数点位置时,从上述协处理器中获取上述多层网络模型的每一层中同一类型的输入数据的小数点位置。In a feasible embodiment, a system on chip (System On Chip, SOC) includes a main processor and a coprocessor, and the main processor includes the above computing device. The coprocessor obtains the decimal point position of the same type of input data in each layer of the multi-layer network model according to the above method, and transmits the decimal point position of the same type of input data in each layer of the multi-layer network model to the above-mentioned The computing device, or when the computing device needs to use the decimal point position of the same type of input data in each layer of the above-mentioned multi-layer network model, obtains the same type of data in each layer of the above-mentioned multi-layer network model from the above-mentioned coprocessor. Enter the decimal point position of the data.

在一种可行的实施例中,上述第一输入数据为均为非定点数据,该非定点数据包括包括长位数浮点数据、短位数浮点数据、整型数据和离散数据等。In a feasible embodiment, the above-mentioned first input data are all non-fixed-point data, and the non-fixed-point data includes long-bit floating-point data, short-bit floating-point data, integer data, and discrete data.

上述第一输入数据的数据类型互不相同。比如上述输入神经元、权值和偏置数据均为浮点数据;上述输入神经元、权值和偏置数据中的部分数据为浮点数据,部分数据为整型数据;上述输入神经元、权值和偏置数据均为整型数据。上述计算装置可实现非定点数据到定点数据的转换,即可实现长位数浮点数据、短位数浮点数据、整型数据和离散数据等类型等数据向定点数据的转换。该定点数据可为有符号定点数据或者无符号定点数据。The data types of the above-mentioned first input data are different from each other. For example, the above input neurons, weights and bias data are all floating point data; some of the above input neurons, weights and bias data are floating point data, and some data are integer data; the above input neurons, The weight and bias data are both integer data. The above computing device can realize the conversion of non-fixed-point data to fixed-point data, that is, the conversion of long-digit floating-point data, short-digit floating-point data, integer data, discrete data and other types of data to fixed-point data. The fixed-point data may be signed fixed-point data or unsigned fixed-point data.

在一种可行的实施例中,上述第一输入数据和第二输入数据均为定点数据,且第一输入数据和第二输入数据可均为有符号的定点数据,或者均为无符号的定点数据,或者其中一个为无符号的定点数据,另一个为有符号的定点数据。且第一输入数据的小数点位置和第二输入数据的小数点位置不同。In a feasible embodiment, the first input data and the second input data are both fixed-point data, and the first input data and the second input data may both be signed fixed-point data, or both are unsigned fixed-point data data, or one of them is unsigned fixed-point data and the other is signed fixed-point data. And the decimal point position of the first input data and the decimal point position of the second input data are different.

在一种可行的实施例中,第一输入数据为定点数据,上述第二输入数据为非定点数据。换言之,上述计算装置可实现定点数据到非定点数据的转换。In a feasible embodiment, the first input data is fixed-point data, and the second input data is non-fixed-point data. In other words, the above computing device can realize the conversion of fixed-point data to non-fixed-point data.

图4为本发明实施例提供的一种单层神经网络正向运算流程图。该流程图描述利用本发明实施的计算装置和指令集实现的一种单层神经网络正向运算的过程。对于每一层来说,首先对输入神经元向量进行加权求和计算出本层的中间结果向量。该中间结果向量加偏置并激活得到输出神经元向量。将输出神经元向量作为下一层的输入神经元向量。FIG. 4 is a flowchart of forward operation of a single-layer neural network according to an embodiment of the present invention. The flow chart describes the forward operation process of a single-layer neural network implemented by the computing device and the instruction set implemented in the present invention. For each layer, the input neuron vector is first weighted and summed to calculate the intermediate result vector of this layer. The intermediate result vector is biased and activated to obtain the output neuron vector. Use the output neuron vector as the input neuron vector for the next layer.

在一个具体的应用场景中,上述计算装置可以是一个训练装置。在进行神经网络模型训练之前,该训练装置获取参与神经网络模型训练的训练数据,该训练数据为非定点数据,并按照上述方法获取上述训练数据的小数点位置。上述训练装置根据上述训练数据的小数点位置将该训练数据转换为以定点数据表示的训练数据。上述训练装置根据该以定点数据表示的训练数据进行正向神经网络运算,得到神经网络运算结果。上述训练装置对超出训练数据的小数点位置所能表示数据精度范围的神经网络运算结果进行随机舍入操作,以得到舍入后的神经网络运算结果,该神经网络运算结果位于上述训练数据的小数点位置所能表示数据精度范围内。按照上述方法,上述训练装置获取多层神经网络每层的神经网络运算结果,即输出神经元。上述训练装置根据每层输出神经元得到输出神经元的梯度,并根据该输出神经元的梯度进行反向运算,得到权值梯度,从而根据该权值梯度更新神经网络模型的权值。In a specific application scenario, the above computing device may be a training device. Before training the neural network model, the training device obtains training data participating in the training of the neural network model, the training data is non-fixed-point data, and obtains the decimal point position of the training data according to the above method. The training device converts the training data into training data represented by fixed-point data according to the decimal point position of the training data. The above training device performs forward neural network operation according to the training data represented by the fixed-point data, and obtains a neural network operation result. The above-mentioned training device performs random rounding operation on the neural network operation result that exceeds the range of data precision that the decimal point position of the training data can represent, so as to obtain the rounded neural network operation result, and the neural network operation result is located at the decimal point position of the above-mentioned training data. The data can be represented within the precision range. According to the above method, the above training device obtains the neural network operation result of each layer of the multi-layer neural network, that is, the output neuron. The above training device obtains the gradient of the output neuron according to the output neuron of each layer, and performs a reverse operation according to the gradient of the output neuron to obtain the weight gradient, so as to update the weight of the neural network model according to the weight gradient.

上述训练装置重复执行上述过程,以达到训练神经网络模型的目的。The above-mentioned training apparatus repeatedly performs the above-mentioned process to achieve the purpose of training the neural network model.

需要指出的是,在进行正向运算和反向训练之前,上述计算装置对参与正向运算的数据进行数据转换;对参与反向训练的数据不进行数据转换;或者,上述计算装置对参与正向运算的数据不进行数据转换;对参与反向训练的数据进行数据转换;上述计算装置对参与正向运算的数据参与反向训练的数据均进行数据转换;具体数据转换过程可参见上述相关实施例的描述,在此不再叙述。It should be pointed out that, before performing forward operation and reverse training, the above-mentioned computing device performs data conversion on the data participating in the forward operation; it does not perform data conversion on the data participating in the reverse training; No data conversion is performed on the data of the forward operation; data conversion is performed on the data participating in the reverse training; the above-mentioned computing device performs data conversion on the data participating in the forward operation and the data involved in the reverse training; the specific data conversion process can refer to the above-mentioned relevant implementation. The description of the example will not be described here.

其中,上述正向运算包括上述多层神经网络运算,该多层神经网络运算包括卷积等运算,该卷积运算是由卷积运算指令实现的。Wherein, the above-mentioned forward operation includes the above-mentioned multi-layer neural network operation, the multi-layer neural network operation includes operations such as convolution, and the convolution operation is realized by a convolution operation instruction.

上述卷积运算指令为Cambricon指令集中的一种指令,该Cambricon指令集的特征在于,指令由操作码和操作数组成,指令集包含四种类型的指令,分别是控制指令(controlinstructions),数据传输指令(data transfer instructions),运算指令(computationalinstructions),逻辑指令(logical instructions)。The above-mentioned convolution operation instruction is an instruction in the Cambricon instruction set. The Cambricon instruction set is characterized in that the instruction consists of an opcode and an operand. The instruction set includes four types of instructions, namely control instructions (control instructions), data transmission Instructions (data transfer instructions), operation instructions (computationalinstructions), logical instructions (logical instructions).

优选的,指令集中每一条指令长度为定长。例如,指令集中每一条指令长度可以为64bit。Preferably, the length of each instruction in the instruction set is a fixed length. For example, the length of each instruction in the instruction set may be 64 bits.

进一步的,控制指令用于控制执行过程。控制指令包括跳转(jump)指令和条件分支(conditional branch)指令。Further, the control instructions are used to control the execution process. Control instructions include jump instructions and conditional branch instructions.

进一步的,数据传输指令用于完成不同存储介质之间的数据传输。数据传输指令包括加载(load)指令,存储(store)指令,搬运(move)指令。load指令用于将数据从主存加载到缓存,store指令用于将数据从缓存存储到主存,move指令用于在缓存与缓存或者缓存与寄存器或者寄存器与寄存器之间搬运数据。数据传输指令支持三种不同的数据组织方式,包括矩阵,向量和标量。Further, the data transfer instruction is used to complete data transfer between different storage media. Data transfer instructions include load (load) instructions, store (store) instructions, and move (move) instructions. The load instruction is used to load data from main memory to the cache, the store instruction is used to store data from the cache to the main memory, and the move instruction is used to move data between cache and cache or between cache and registers or between registers and registers. Data transfer instructions support three different ways of organizing data, including matrices, vectors, and scalars.

进一步的,运算指令用于完成神经网络算术运算。运算指令包括矩阵运算指令,向量运算指令和标量运算指令。Further, the operation instruction is used to complete the neural network arithmetic operation. The operation instructions include matrix operation instructions, vector operation instructions and scalar operation instructions.

更进一步的,矩阵运算指令完成神经网络中的矩阵运算,包括矩阵乘向量(matrixmultiply vector),向量乘矩阵(vector multiply matrix),矩阵乘标量(matrixmultiply scalar),外积(outer product),矩阵加矩阵(matrix add matrix),矩阵减矩阵(matrix subtract matrix)。Further, the matrix operation instruction completes the matrix operation in the neural network, including matrix multiply vector (matrixmultiply vector), vector multiplies matrix (vector multiply matrix), matrix multiplication scalar (matrixmultiply scalar), outer product (outer product), matrix addition Matrix (matrix add matrix), matrix subtraction matrix (matrix subtract matrix).

更进一步的,向量运算指令完成神经网络中的向量运算,包括向量基本运算(vector elementary arithmetics),向量超越函数运算(vector transcendentalfunctions),内积(dot product),向量随机生成(random vector generator),向量中最大/最小值(maximum/minimum of a vector)。其中向量基本运算包括向量加,减,乘,除(add,subtract,multiply,divide),向量超越函数是指那些不满足任何以多项式作系数的多项式方程的函数,包括但不仅限于指数函数,对数函数,三角函数,反三角函数。Further, the vector operation instruction completes the vector operation in the neural network, including vector elementary arithmetics, vector transcendentalfunctions, inner product (dot product), vector random generation (random vector generator), maximum/minimum of a vector. The vector basic operations include vector addition, subtraction, multiplication, and division (add, subtract, multiply, divide), and vector transcendental functions refer to those functions that do not satisfy any polynomial equation with polynomials as coefficients, including but not limited to exponential functions. Number functions, trigonometric functions, inverse trigonometric functions.

更进一步的,标量运算指令完成神经网络中的标量运算,包括标量基本运算(scalar elementary arithmetics)和标量超越函数运算(scalar transcendentalfunctions)。其中标量基本运算包括标量加,减,乘,除(add,subtract,multiply,divide),标量超越函数是指那些不满足任何以多项式作系数的多项式方程的函数,包括但不仅限于指数函数,对数函数,三角函数,反三角函数。Further, the scalar operation instructions perform scalar operations in the neural network, including scalar elementary arithmetics and scalar transcendental functions. The scalar basic operations include scalar addition, subtraction, multiplication, and division (add, subtract, multiply, divide), and scalar transcendental functions refer to those functions that do not satisfy any polynomial equation with polynomials as coefficients, including but not limited to exponential functions. Number functions, trigonometric functions, inverse trigonometric functions.

进一步的,逻辑指令用于神经网络的逻辑运算。逻辑运算包括向量逻辑运算指令和标量逻辑运算指令。Further, the logic instruction is used for the logic operation of the neural network. Logic operations include vector logic operation instructions and scalar logic operation instructions.

更进一步的,向量逻辑运算指令包括向量比较(vector compare),向量逻辑运算(vector logical operations)和向量大于合并(vector greater than merge)。其中向量比较包括但不限于大于,小于,等于,大于或等于,小于或等于和不等于。向量逻辑运算包括与,或,非。Further, the vector logical operation instructions include vector compare, vector logical operations and vector greater than merge. Where vector comparisons include, but are not limited to, greater than, less than, equal to, greater than or equal to, less than or equal to, and not equal to. Vector logic operations include AND, OR, NOT.

更进一步的,标量逻辑运算包括标量比较(scalar compare),标量逻辑运算(scalar logical operations)。其中标量比较包括但不限于大于,小于,等于,大于或等于,小于或等于和不等于。标量逻辑运算包括与,或,非。Further, scalar logical operations include scalar compare and scalar logical operations. Where scalar comparisons include, but are not limited to, greater than, less than, equal to, greater than or equal to, less than or equal to, and not equal to. Scalar logical operations include AND, OR, NOT.

对于多层神经网络,其实现过程是,在正向运算中,当上一层人工神经网络执行完成之后,下一层的运算指令会将运算单元中计算出的输出神经元作为下一层的输入神经元进行运算(或者是对该输出神经元进行某些操作再作为下一层的输入神经元),同时,将权值也替换为下一层的权值;在反向运算中,当上一层人工神经网络的反向运算执行完成后,下一层运算指令会将运算单元中计算出的输入神经元梯度作为下一层的输出神经元梯度进行运算(或者是对该输入神经元梯度进行某些操作再作为下一层的输出神经元梯度),同时将权值替换为下一层的权值。如图5所示,图5中虚线的箭头表示反向运算,实现的箭头表示正向运算。For the multi-layer neural network, the implementation process is that in the forward operation, when the upper layer of artificial neural network is executed, the operation instruction of the next layer will use the output neurons calculated in the operation unit as the output neurons of the next layer. The input neurons are operated (or some operations are performed on the output neurons and then used as the input neurons of the next layer), and at the same time, the weights are also replaced with the weights of the next layer; in the reverse operation, when After the reverse operation of the artificial neural network of the previous layer is executed, the operation instruction of the next layer will calculate the gradient of the input neuron calculated in the operation unit as the gradient of the output neuron of the next layer (or the input neuron). The gradient performs some operations and then serves as the output neuron gradient of the next layer), and at the same time replaces the weights with the weights of the next layer. As shown in FIG. 5 , the dotted arrows in FIG. 5 represent reverse operations, and the implemented arrows represent forward operations.

另一个实施例里,该运算指令为矩阵乘以矩阵的指令、累加指令、激活指令等等计算指令,包括正向运算指令和方向训练指令。In another embodiment, the operation instruction is a matrix-by-matrix instruction, an accumulation instruction, an activation instruction, and other calculation instructions, including a forward operation instruction and a direction training instruction.

下面通过神经网络运算指令来说明如图3A所示的计算装置的具体计算方法。对于神经网络运算指令来说,其实际需要执行的公式可以为:s=s(∑wxi+b),其中,即将权值w乘以输入数据xi,进行求和,然后加上偏置b后做激活运算s(h),得到最终的输出结果s。The specific computing method of the computing device shown in FIG. 3A will be described below by using the neural network operation instructions. For the neural network operation instruction, the actual formula that needs to be executed can be: s=s(∑wxi +b), where the weight w is multiplied by the input data xi , summed, and then the bias is added After b, do the activation operation s(h) to get the final output result s.

如图3A所示的计算装置执行神经网络正向运算指令的方法具体可以为:The method for executing the neural network forward operation instruction by the computing device as shown in FIG. 3A may specifically be:

上述转换单元13对上述第一输入数据进行数据类型转换后,控制器单元11从指令缓存单元110内提取神经网络正向运算指令、神经网络运算指令对应的操作域以及至少一个操作码,控制器单元11将该操作域传输至数据访问单元,将该至少一个操作码发送至运算单元12。After theconversion unit 13 performs data type conversion on the first input data, thecontroller unit 11 extracts the neural network forward operation instruction, the operation domain corresponding to the neural network operation instruction, and at least one operation code from theinstruction buffer unit 110, and the controller Theunit 11 transmits the operation field to the data access unit, and sends the at least one operation code to theoperation unit 12 .

控制器单元11从存储单元10内提取该操作域对应的权值w和偏置b(当b为0时,不需要提取偏置b),将权值w和偏置b传输至运算单元的主处理电路101,控制器单元11从存储单元10内提取输入数据Xi,将该输入数据Xi发送至主处理电路101。Thecontroller unit 11 extracts the weight w and the offset b corresponding to the operation domain from the storage unit 10 (when b is 0, the offset b does not need to be extracted), and transmits the weight w and the offset b to the operation unit. In themain processing circuit 101 , thecontroller unit 11 extracts the input data Xi from thestorage unit 10 , and sends the input data Xi to themain processing circuit 101 .

主处理电路101将输入数据Xi拆分成n个数据块;Themain processing circuit 101 splits the input data Xi into n data blocks;

控制器单元11的指令处理单元111依据该至少一个操作码确定乘法指令、偏置指令和累加指令,将乘法指令、偏置指令和累加指令发送至主处理电路101,主处理电路101将该乘法指令、权值w以广播的方式发送给多个从处理电路102,将该n个数据块分发给该多个从处理电路102(例如具有n个从处理电路102,那么每个从处理电路102发送一个数据块);多个从处理电路102,用于依据该乘法指令将该权值w与接收到的数据块执行乘法运算得到中间结果,将该中间结果发送至主处理电路101,该主处理电路101依据该累加指令将多个从处理电路102发送的中间结果执行累加运算得到累加结果,依据该偏执指令将该累加结果执行加偏执b得到最终结果,将该最终结果发送至该控制器单元11。Theinstruction processing unit 111 of thecontroller unit 11 determines the multiplication instruction, the bias instruction and the accumulation instruction according to the at least one operation code, and sends the multiplication instruction, the bias instruction and the accumulation instruction to themain processing circuit 101, and themain processing circuit 101 executes the multiplication instruction. The instruction and weight w are sent to multipleslave processing circuits 102 in a broadcast manner, and the n data blocks are distributed to the multiple slave processing circuits 102 (for example, there are nslave processing circuits 102, then eachslave processing circuit 102 send a data block); a plurality ofslave processing circuits 102 are used to perform a multiplication operation on the weight w and the received data block according to the multiplication instruction to obtain an intermediate result, and send the intermediate result to themaster processing circuit 101, the master Theprocessing circuit 101 performs an accumulation operation on a plurality of intermediate results sent from theprocessing circuit 102 according to the accumulation instruction to obtain an accumulation result, and executes the accumulation result according to the paranoid instruction and adds a bias b to obtain a final result, and sends the final result to thecontroller unit 11.

另外,加法运算和乘法运算的顺序可以调换。In addition, the order of addition and multiplication can be reversed.

需要说明的是,上述计算装置执行神经网络反向训练指令的方法类似于上述计算装置执行神经网络执行正向运算指令的过程,具体可参见上述反向训练的相关描述,在此不再叙述。It should be noted that the method for the above-mentioned computing device to execute the reverse training instruction of the neural network is similar to the process for the above-mentioned computing device to execute the forward operation instruction of the neural network.

本申请提供的技术方案通过一个指令即神经网络运算指令即实现了神经网络的乘法运算以及偏置运算,在神经网络计算的中间结果均无需存储或提取,减少了中间数据的存储以及提取操作,所以其具有减少对应的操作步骤,提高神经网络的计算效果的优点。The technical solution provided by the present application realizes the multiplication operation and bias operation of the neural network through one instruction, that is, the neural network operation instruction. The intermediate results of the neural network calculation do not need to be stored or extracted, thereby reducing the storage and extraction operations of intermediate data. Therefore, it has the advantages of reducing the corresponding operation steps and improving the calculation effect of the neural network.

本申请还揭露了一个机器学习运算装置,其包括一个或多个在本申请中提到的计算装置,用于从其他处理装置中获取待运算数据和控制信息,执行指定的机器学习运算,执行结果通过I/O接口传递给外围设备。外围设备譬如摄像头,显示器,鼠标,键盘,网卡,wifi接口,服务器。当包含一个以上计算装置时,计算装置间可以通过特定的结构进行链接并传输数据,譬如,通过PCIE总线进行互联并传输数据,以支持更大规模的机器学习的运算。此时,可以共享同一控制系统,也可以有各自独立的控制系统;可以共享内存,也可以每个加速器有各自的内存。此外,其互联方式可以是任意互联拓扑。The present application also discloses a machine learning computing device, which includes one or more computing devices mentioned in the present application, and is used to obtain data to be operated and control information from other processing devices, execute specified machine learning operations, execute The result is passed to the peripheral device through the I/O interface. Peripherals such as camera, monitor, mouse, keyboard, network card, wifi interface, server. When more than one computing device is included, the computing devices can be linked and transmitted through a specific structure, for example, interconnected and transmitted through a PCIE bus, so as to support larger-scale machine learning operations. At this time, the same control system can be shared, or there can be independent control systems; memory can be shared, or each accelerator can have its own memory. In addition, the interconnection method can be any interconnection topology.

该机器学习运算装置具有较高的兼容性,可通过PCIE接口与各种类型的服务器相连接。The machine learning computing device has high compatibility and can be connected with various types of servers through the PCIE interface.

本申请还揭露了一个组合处理装置,其包括上述的机器学习运算装置,通用互联接口,和其他处理装置。机器学习运算装置与其他处理装置进行交互,共同完成用户指定的操作。图6为组合处理装置的示意图。The present application also discloses a combined processing device, which includes the above-mentioned machine learning computing device, a universal interconnection interface, and other processing devices. The machine learning computing device interacts with other processing devices to jointly complete the operation specified by the user. FIG. 6 is a schematic diagram of a combined processing device.

其他处理装置,包括中央处理器CPU、图形处理器GPU、机器学习处理器等通用/专用处理器中的一种或以上的处理器类型。其他处理装置所包括的处理器数量不做限制。其他处理装置作为机器学习运算装置与外部数据和控制的接口,包括数据搬运,完成对本机器学习运算装置的开启、停止等基本控制;其他处理装置也可以和机器学习运算装置协作共同完成运算任务。Other processing devices include one or more processor types among general-purpose/special-purpose processors such as central processing units (CPUs), graphics processing units (GPUs), and machine learning processors. The number of processors included in other processing devices is not limited. Other processing devices serve as the interface between the machine learning computing device and external data and control, including data transfer, to complete the basic control of starting and stopping the machine learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

通用互联接口,用于在所述机器学习运算装置与其他处理装置间传输数据和控制指令。该机器学习运算装置从其他处理装置中获取所需的输入数据,写入机器学习运算装置片上的存储装置;可以从其他处理装置中获取控制指令,写入机器学习运算装置片上的控制缓存;也可以读取机器学习运算装置的存储模块中的数据并传输给其他处理装置。The universal interconnection interface is used to transmit data and control instructions between the machine learning computing device and other processing devices. The machine learning computing device obtains required input data from other processing devices, and writes it into a storage device on-chip of the machine learning computing device; it can obtain control instructions from other processing devices and write it into the control cache on the machine learning computing device chip; The data in the storage module of the machine learning computing device can be read and transmitted to other processing devices.

可选的,该结构如图7所示,还可以包括存储装置,存储装置分别与所述机器学习运算装置和所述其他处理装置连接。存储装置用于保存在所述机器学习运算装置和所述其他处理装置的数据,尤其适用于所需要运算的数据在本机器学习运算装置或其他处理装置的内部存储中无法全部保存的数据。Optionally, as shown in FIG. 7 , the structure may further include a storage device, and the storage device is respectively connected to the machine learning computing device and the other processing device. The storage device is used to save the data in the machine learning computing device and the other processing devices, and is especially suitable for data that cannot be fully stored in the internal storage of the machine learning computing device or other processing devices.

该组合处理装置可以作为手机、机器人、无人机、视频监控设备等设备的SOC片上系统,有效降低控制部分的核心面积,提高处理速度,降低整体功耗。此情况时,该组合处理装置的通用互联接口与设备的某些部件相连接。某些部件譬如摄像头,显示器,鼠标,键盘,网卡,wifi接口。The combined processing device can be used as an SOC system for mobile phones, robots, drones, video surveillance equipment and other equipment, effectively reducing the core area of the control part, improving the processing speed and reducing the overall power consumption. In this case, the general interconnection interface of the combined processing device is connected to certain components of the apparatus. Some components such as camera, monitor, mouse, keyboard, network card, wifi interface.

在一个可行的实施例中,还申请了一种分布式系统,该系统包括n1个主处理器和n2个协处理器,n1是大于或等于0的整数,n2是大于或等于1的整数。该系统可以是各种类型的拓扑结构,包括但不限于如图3B所示的拓扑结果、图3C所示的拓扑结构、图11所示的拓扑结构和图12所示的拓扑结构。In a feasible embodiment, a distributed system is also applied. The system includes n1 main processors and n2 coprocessors, where n1 is an integer greater than or equal to 0, and n2 is an integer greater than or equal to 1. The system can be of various types of topologies, including but not limited to the topology results shown in FIG. 3B , the topology shown in FIG. 3C , the topology shown in FIG. 11 , and the topology shown in FIG. 12 .

该主处理器将输入数据及其小数点位置和计算指令分别发送至上述多个协处理器;或者上述主处理器将上述输入数据及其小数点位置和计算指令发送至上述多个从处理器中的部分从处理器,该部分从处理器再将上述输入数据及其小数点位置和计算指令发送至其他从处理器。上述该协处理器包括上述计算装置,该计算装置根据上述方法和计算指令对上述输入数据进行运算,得到运算结果;The master processor sends the input data and its decimal point position and calculation instructions to the multiple coprocessors respectively; or the master processor sends the input data and its decimal point position and calculation instructions to the multiple slave processors. Part of the slave processor, this part of the slave processor then sends the above input data and its decimal point position and calculation instructions to other slave processors. The above-mentioned coprocessor includes the above-mentioned computing device, and the computing device performs an operation on the above-mentioned input data according to the above-mentioned method and the computing instruction to obtain an operation result;

其中,上述输入数据包括但不限定于输入神经元、权值和偏置数据等等。Wherein, the above-mentioned input data includes, but is not limited to, input neurons, weights, bias data, and so on.

上述协处理器将运算结果直接发送至上述主处理器,或者与主处理器没有连接关系的协处理器将运算结果先发送至与主处理器有连接关系的协处理器,然后该协处理器将接收到的运算结果发送至上述主处理器。The coprocessor directly sends the operation result to the main processor, or the coprocessor that is not connected to the main processor sends the operation result to the coprocessor that is connected to the main processor, and then the coprocessor has a connection relationship with the main processor. The received operation result is sent to the above-mentioned main processor.

在一些实施例里,还申请了一种芯片,其包括了上述机器学习运算装置或组合处理装置。In some embodiments, a chip is also applied, which includes the above-mentioned machine learning computing device or combined processing device.

在一些实施例里,申请了一种芯片封装结构,其包括了上述芯片。In some embodiments, a chip package structure is applied, which includes the above-mentioned chip.

在一些实施例里,申请了一种板卡,其包括了上述芯片封装结构。In some embodiments, a board card is applied, which includes the above-mentioned chip packaging structure.

在一些实施例里,申请了一种电子设备,其包括了上述板卡。参阅图8,图8提供了一种板卡,上述板卡除了包括上述芯片389以外,还可以包括其他的配套部件,该配套部件包括但不限于:存储器件390、接收装置391和控制器件392;In some embodiments, an electronic device is applied, which includes the above board. Referring to FIG. 8 , FIG. 8 provides a board card. In addition to the above-mentioned chip 389 , the board card may also include other supporting components, including but not limited to: a storage device 390 , a receivingdevice 391 and a control device 392 ;

所述存储器件390与所述芯片封装结构内的芯片通过总线连接,用于存储数据。所述存储器件可以包括多组存储单元393。每一组所述存储单元与所述芯片通过总线连接。可以理解,每一组所述存储单元可以是DDR SDRAM(英文:Double Data Rate SDRAM,双倍速率同步动态随机存储器)。The storage device 390 is connected to the chip in the chip package structure through a bus, and is used for storing data. The memory device may include groups of memory cells 393 . Each group of the memory cells is connected to the chip through a bus. It can be understood that each group of the storage units may be DDR SDRAM (English: Double Data Rate SDRAM, double-rate synchronous dynamic random access memory).

DDR不需要提高时钟频率就能加倍提高SDRAM的速度。DDR允许在时钟脉冲的上升沿和下降沿读出数据。DDR的速度是标准SDRAM的两倍。在一个实施例中,所述存储装置可以包括4组所述存储单元。每一组所述存储单元可以包括多个DDR4颗粒(芯片)。在一个实施例中,所述芯片内部可以包括4个72位DDR4控制器,上述72位DDR4控制器中64bit用于传输数据,8bit用于ECC校验。可以理解,当每一组所述存储单元中采用DDR4-3200颗粒时,数据传输的理论带宽可达到25600MB/s。DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include four sets of the storage units. Each group of the memory cells may include a plurality of DDR4 granules (chips). In one embodiment, the chip may include four 72-bit DDR4 controllers, and 64 bits of the above 72-bit DDR4 controllers are used for data transmission, and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of the memory cells, the theoretical bandwidth of data transmission can reach 25600MB/s.

在一个实施例中,每一组所述存储单元包括多个并联设置的双倍速率同步动态随机存储器。DDR在一个时钟周期内可以传输两次数据。在所述芯片中设置控制DDR的控制器,用于对每个所述存储单元的数据传输与数据存储的控制。In one embodiment, each set of said memory cells includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling the DDR is provided in the chip for controlling data transmission and data storage of each of the memory cells.

所述接口装置与所述芯片封装结构内的芯片电连接。所述接口装置用于实现所述芯片与外部设备(例如服务器或计算机)之间的数据传输。例如在一个实施例中,所述接口装置可以为标准PCIE接口。比如,待处理的数据由服务器通过标准PCIE接口传递至所述芯片,实现数据转移。优选的,当采用PCIE 3.0X 16接口传输时,理论带宽可达到16000MB/s。在另一个实施例中,所述接口装置还可以是其他的接口,本申请并不限制上述其他的接口的具体表现形式,所述接口单元能够实现转接功能即可。另外,所述芯片的计算结果仍由所述接口装置传送回外部设备(例如服务器)。The interface device is electrically connected to the chip in the chip package structure. The interface device is used to realize data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted by the server to the chip through a standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device may also be other interfaces, and the present application does not limit the specific manifestations of the above-mentioned other interfaces, as long as the interface unit can realize the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (such as a server) by the interface device.

所述控制器件与所述芯片电连接。所述控制器件用于对所述芯片的状态进行监控。具体的,所述芯片与所述控制器件可以通过SPI接口电连接。所述控制器件可以包括单片机(Micro Controller Unit,MCU)。如所述芯片可以包括多个处理芯片、多个处理核或多个处理电路,可以带动多个负载。因此,所述芯片可以处于多负载和轻负载等不同的工作状态。通过所述控制装置可以实现对所述芯片中多个处理芯片、多个处理和或多个处理电路的工作状态的调控。The control device is electrically connected to the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a Micro Controller Unit (MCU). For example, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, and may drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light-load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and or multiple processing circuits in the chip.

电子设备包括数据处理装置、机器人、电脑、打印机、扫描仪、平板电脑、智能终端、手机、行车记录仪、导航仪、传感器、摄像头、服务器、云端服务器、相机、摄像机、投影仪、手表、耳机、移动存储、可穿戴设备、交通工具、家用电器、和/或医疗设备。Electronic equipment includes data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors, watches, headphones , mobile storage, wearable devices, vehicles, home appliances, and/or medical equipment.

所述交通工具包括飞机、轮船和/或车辆;所述家用电器包括电视、空调、微波炉、冰箱、电饭煲、加湿器、洗衣机、电灯、燃气灶、油烟机;所述医疗设备包括核磁共振仪、B超仪和/或心电图仪。The vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lamps, gas stoves, and range hoods; the medical equipment includes nuclear magnetic resonance instruments, B-ultrasound and/or electrocardiograph.

参见图9,图9为本发明实施例提供的一种执行机器学习计算的方法,所述方法包括:Referring to FIG. 9, FIG. 9 is a method for performing machine learning calculation provided by an embodiment of the present invention, and the method includes:

S901、计算装置获取第一输入数据和计算指令。S901. The computing device acquires first input data and a computing instruction.

其中,上述第一输入数据包括输入神经元和权值。Wherein, the above-mentioned first input data includes input neurons and weights.

S902、计算装置解析所述计算指令,以得到数据转换指令和多个运算指令。S902. The computing device parses the computing instruction to obtain a data conversion instruction and a plurality of operation instructions.

其中,所述数据转换指令包括数据转换指令包括操作域和操作码,该操作码用于指示所述数据类型转换指令的功能,所述数据类型转换指令的操作域包括小数点位置、用于指示第一输入数据的数据类型的标志位和数据类型的转换方式。Wherein, the data conversion instruction includes a data conversion instruction including an operation field and an operation code, the operation code is used to indicate the function of the data type conversion instruction, and the operation field of the data type conversion instruction includes a decimal point position, used to indicate the first A flag bit of the data type of the input data and the conversion method of the data type.

S903、计算装置根据所述数据转换指令将所述第一输入数据转换为第二输入数据,该第二输入数据为定点数据。S903. The computing device converts the first input data into second input data according to the data conversion instruction, where the second input data is fixed-point data.

其中,所述根据所述数据转换指令将所述第一输入数据转换为第二输入数据,包括:The converting the first input data into the second input data according to the data conversion instruction includes:

解析所述数据转换指令,以得到所述小数点位置、所述用于指示第一输入数据的数据类型的标志位和数据类型的转换方式;Parsing the data conversion instruction to obtain the decimal point position, the flag bit for indicating the data type of the first input data, and the conversion mode of the data type;

根据所述第一输入数据的数据类型标志位确定所述第一输入数据的数据类型;Determine the data type of the first input data according to the data type flag bit of the first input data;

根据所述小数点位置和所述数据类型的转换方式,将所述第一输入数据转换为第二输入数据,所述第二输入数据的数据类型与所述第一输入数据的数据类型不一致。According to the decimal point position and the conversion method of the data type, the first input data is converted into second input data, and the data type of the second input data is inconsistent with the data type of the first input data.

其中,当所述第一输入数据和所述第二输入数据均为定点数据时,所述第一输入数据的小数点位置和所述第二输入数据的小数点位置不一致。Wherein, when both the first input data and the second input data are fixed-point data, the position of the decimal point of the first input data is inconsistent with the position of the decimal point of the second input data.

在一种可行的实施例中,当所述第一输入数据为定点数据时,所述方法还包括:In a feasible embodiment, when the first input data is fixed-point data, the method further includes:

根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。According to the decimal point position of the first input data, the decimal point position of one or more intermediate results is derived, wherein the one or more intermediate results are obtained by operation according to the first input data.

S904、计算装置根据所述多个运算指令对所述第二输入数据执行计算得到计算指令的结果。S904. The computing device performs computation on the second input data according to the plurality of operation instructions to obtain a result of the computation instruction.

其中,上述运算指令包括正向运算指令和反向训练指令,即上述计算装置在执行正向运算指令和或反向训练指令(即该计算装置进行正向运算和/或反向训练)过程中,上述计算装置可根据上述图9所示实施例将参与运算的数据转换为定点数据,进行定点运算。Wherein, the above-mentioned operation instruction includes a forward operation instruction and a reverse training instruction, that is, the above-mentioned computing device is in the process of executing the forward operation instruction and or the reverse training instruction (that is, the computing device performs forward operation and/or reverse training). , the above-mentioned computing device can convert the data involved in the operation into fixed-point data according to the above-mentioned embodiment shown in FIG. 9 to perform fixed-point operation.

需要说明的是,上述步骤S901-S904具体描述可参见图1-8所示实施例的相关描述,在此不再叙述。It should be noted that, for the specific description of the above steps S901-S904, reference may be made to the relevant descriptions of the embodiments shown in FIGS. 1-8, which are not described herein again.

在一个具体的应用场景中,上述计算装置将参与运算的数据转换为定点数据,并对定点数据的小数点位置进行调整,具体过程参见图10,如图10所示,该方法包括:In a specific application scenario, the above-mentioned computing device converts the data involved in the operation into fixed-point data, and adjusts the decimal point position of the fixed-point data. The specific process is shown in FIG. 10 . As shown in FIG. 10 , the method includes:

S1001、计算装置获取第一输入数据。S1001. The computing device acquires first input data.

其中,上述第一输入数据为参与多层网络模型的第m层运算的数据,该第一输入数据为任意类型的数据。比如该第一输入数据为定点数据、浮点数据、整型数据或离散数据,m为大于0的整数。Wherein, the above-mentioned first input data is data participating in the operation of the mth layer of the multi-layer network model, and the first input data is any type of data. For example, the first input data is fixed-point data, floating-point data, integer data or discrete data, and m is an integer greater than 0.

其中,上述多层网络模型的第m层为线性层,该线性层包括但不限定于卷积层和全连接层。上述第一输入数据包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数。Wherein, the mth layer of the above-mentioned multi-layer network model is a linear layer, and the linear layer includes but is not limited to a convolutional layer and a fully connected layer. The above-mentioned first input data includes input neurons, weights, output neurons, derivatives of input neurons, derivatives of weights, and derivatives of output neurons.

S1002、计算装置确定第一输入数据的小数点位置和定点数据的位宽。S1002. The computing device determines the position of the decimal point of the first input data and the bit width of the fixed-point data.

其中,上述第一输入数据的定点数据的位宽为以定点数据表示的第一输入数据所占的比特位,上述小数点位置为以定点数据表示的第一数据数据的小数部分所占的比特位。该小数点位置用于表征定点数据的精度。具体参见图2A的相关描述。Wherein, the bit width of the fixed-point data of the first input data is the bits occupied by the first input data represented by the fixed-point data, and the position of the decimal point is the bits occupied by the fractional part of the first data data represented by the fixed-point data . The decimal point position is used to characterize the precision of fixed-point data. Please refer to the related description of FIG. 2A for details.

具体地,第一输入数据可以为任意类型的数据,该第一输入数据a根据上述小数点位置和定点数据的位宽转换为第二输入数据

Figure BDA0001995399720000311
具体如下:Specifically, the first input data may be any type of data, and the first input data a is converted into the second input data according to the position of the decimal point and the bit width of the fixed-point data
Figure BDA0001995399720000311
details as follows:

Figure BDA0001995399720000321
Figure BDA0001995399720000321

其中,当上述第一输入数据a满足条件neg≤a≤pos时,上述第二输入数据

Figure BDA0001995399720000322
为|a/2s|*2s;当上述第一输入数据a大于pos时,上述第二输入数据
Figure BDA0001995399720000323
为pos;当上述第一输入数据a小于neg时,上述第二输入数据
Figure BDA0001995399720000324
为neg。Wherein, when the first input data a satisfies the condition neg≤a≤pos, the second input data
Figure BDA0001995399720000322
is |a/2s |*2s ; when the above-mentioned first input data a is greater than pos, the above-mentioned second input data
Figure BDA0001995399720000323
is pos; when the above-mentioned first input data a is less than neg, the above-mentioned second input data
Figure BDA0001995399720000324
for neg.

在一种实施例中,对于卷积层和全连接层的输入神经元、权值、输出神经元、输入神经元导数、输出神经元导数和权值导数均采用定点数据进行表示。In one embodiment, the input neurons, weights, output neurons, input neuron derivatives, output neuron derivatives, and weight derivatives of the convolutional layer and the fully connected layer are all represented by fixed-point data.

可选地,上述输入神经元采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述输入神经元采用的定点数据的位宽为8。Optionally, the bit width of the fixed-point data used by the above-mentioned input neurons may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used by the above input neuron is 8.

可选地,上述权值采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述权值采用的定点数据的位宽为8。Optionally, the bit width of the fixed-point data used by the above weights may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used for the above weights is 8.

可选地,上述输入神经元导数采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述输入神经元导数采用的定点数据的位宽为16。Optionally, the bit width of the fixed-point data used for the input neuron derivative may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used for the above input neuron derivative is 16.

可选地,上述输出神经元导数采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述输出神经元导数采用的定点数据的位宽为24。Optionally, the bit width of the fixed-point data used for the above-mentioned output neuron derivative may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used for the above-mentioned output neuron derivative is 24.

可选地,上述权值导数采用的定点数据的位宽可为8、16、32、64或者其他值。进一步地,上述权值导数采用的定点数据的位宽为24。Optionally, the bit width of the fixed-point data used for the weight derivative may be 8, 16, 32, 64 or other values. Further, the bit width of the fixed-point data used in the weight derivative is 24.

在一种实施例中,对于参与上述多层网络模型运算的数据中数值较大的数据a可采用多种定点表示方法,具体参见图2B的相关描述。In an embodiment, multiple fixed-point representation methods may be used for the data a with a larger value in the data participating in the above-mentioned multi-layer network model operation. For details, please refer to the relevant description of FIG. 2B .

具体地,第一输入数据可以为任意类型的数据,该第一输入数据a根据上述小数点位置和定点数据的位宽转换为第二输入数据

Figure BDA0001995399720000325
具体如下:Specifically, the first input data may be any type of data, and the first input data a is converted into the second input data according to the position of the decimal point and the bit width of the fixed-point data
Figure BDA0001995399720000325
details as follows:

Figure BDA0001995399720000326
Figure BDA0001995399720000326

其中,当上述第一输入数据a满足条件neg≤a≤pos时,上述第二输入数据

Figure BDA0001995399720000327
Figure BDA0001995399720000328
Figure BDA0001995399720000329
当上述第一输入数据a大于pos时,上述第二输入数据
Figure BDA00019953997200003210
为pos;当上述第一输入数据a小于neg时,上述第二输入数据
Figure BDA00019953997200003211
为neg。Wherein, when the first input data a satisfies the condition neg≤a≤pos, the second input data
Figure BDA0001995399720000327
for
Figure BDA0001995399720000328
and
Figure BDA0001995399720000329
When the first input data a is greater than pos, the second input data
Figure BDA00019953997200003210
is pos; when the above-mentioned first input data a is less than neg, the above-mentioned second input data
Figure BDA00019953997200003211
for neg.

S903、计算装置初始化第一输入数据的小数点位置和调整第一输入数据的小数点位置。S903, the computing device initializes the decimal point position of the first input data and adjusts the decimal point position of the first input data.

其中,上述小数点位置s需要根据不同类别的数据、不同神经网络层的数据,处于不同迭代轮次的数据进行初始化和动态调整。The above-mentioned decimal point position s needs to be initialized and dynamically adjusted according to different types of data, data of different neural network layers, and data in different iteration rounds.

下面具体介绍第一输入数据的小数点位置s的初始化过程,即确定进行第一次将第一输入数据转换时定点数据所采用的小数点位置s。The following specifically describes the initialization process of the decimal point position s of the first input data, that is, determining the decimal point position s used by the fixed-point data when converting the first input data for the first time.

其中,上述计算装置第一输入数据的小数点位置s的初始化包括:根据第一输入数据绝对值最大值初始化第一输入数据的小数点位置s;根据第一输入数据绝对值的最小值初始化第一输入数据的小数点位置s;根据第一输入数据中不同数据类型间关系初始化第一输入数据的小数点位置s;根据经验值常量初始化第一输入数据的小数点位置s。Wherein, the initialization of the decimal point position s of the first input data of the computing device includes: initializing the decimal point position s of the first input data according to the maximum absolute value of the first input data; initializing the first input data according to the minimum value of the absolute value of the first input data. The decimal point position s of the data; the decimal point position s of the first input data is initialized according to the relationship between different data types in the first input data; the decimal point position s of the first input data is initialized according to the empirical value constant.

具体地,下面分别具体介绍上述初始化过程。Specifically, the above initialization processes are described in detail below.

a)、上述计算装置根据第一输入数据绝对值的最大值初始化第一输入数据的小数点位置s:a), the above-mentioned computing device initializes the decimal point position s of the first input data according to the maximum value of the absolute value of the first input data:

上述计算装置具体通过以下公式初始化上述第一输入数据的小数点位置s:。The above-mentioned computing device specifically initializes the decimal point position s of the above-mentioned first input data by the following formula: .

Figure BDA0001995399720000331
Figure BDA0001995399720000331

其中,上述amax为上述第一输入数据绝对值的最大值,上述bitnum为上述第一输入数据转换为定点数据的位宽,上述sa为上述第一输入数据的小数点位置。The amax is the maximum absolute value of the first input data, the bitnum is the bit width of the first input data converted to fixed-point data, and the sa is the decimal point position of the first input data.

其中,参与运算的数据按类别与网络层次可分为:第l层的输入神经元X(l)、输出神经元Y(l)、权值W(l)、输入神经元导数

Figure BDA0001995399720000332
输出神经元导数
Figure BDA0001995399720000333
和权值导数
Figure BDA0001995399720000334
寻找绝对值最大值时,可以按数据类别寻找;可以分层、分类别寻找;可以分层、分类别、分组寻找。第一输入数据绝对值的最大值的确定方法包括:Among them, the data involved in the operation can be divided into: the input neuron X(l) of the lth layer, the output neuron Y(l) , the weight W(l) , the input neuron derivative
Figure BDA0001995399720000332
output neuron derivative
Figure BDA0001995399720000333
and weight derivatives
Figure BDA0001995399720000334
When looking for the maximum absolute value, you can search by data category; you can search by layers and categories; you can search by layers, categories, and groups. The method for determining the maximum value of the absolute value of the first input data includes:

a.1)、上述计算装置按数据类别寻找绝对值最大值a.1), the above computing device finds the absolute maximum value according to the data category

具体地,第一输入数据包括向量/矩阵中的每个元素为ai(l),其中,该a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA0001995399720000335
或输出神经元导数
Figure BDA0001995399720000336
或权值导数
Figure BDA0001995399720000337
换言之,上述第一输入数据包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数,上述第一输入数据的小数点位置包括输入神经元的小数点位置、权值的小数点位置、输出神经元的小数点位置、输入神经元导数的小数点位置、权值导数的小数点位置和输出神经元导数的小数点位置。该输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数均以矩阵或者向量形式表示的。计算装置通过遍历上述多层网络模型的每一层的向量/矩阵中所有元素,获取每种类别数据的绝对值最大值,即
Figure BDA0001995399720000338
通过公式
Figure BDA0001995399720000339
确定每种类别数据a转换为定点数据的小数点位置sa。Specifically, the first input data includes that each element in the vector/matrix is ai(l) , where a(l) can be an input neuron X(l) or an output neuron Y(l) or a weight value W(l) or input neuron derivative
Figure BDA0001995399720000335
or output neuron derivative
Figure BDA0001995399720000336
or weight derivative
Figure BDA0001995399720000337
In other words, the first input data includes input neurons, weights, output neurons, input neuron derivatives, weight derivatives, and output neuron derivatives, and the decimal point position of the first input data includes the decimal point position of the input neuron, the weight value The decimal point position of the value, the decimal point position of the output neuron, the decimal point position of the input neuron derivative, the decimal point position of the weight derivative, and the decimal point position of the output neuron derivative. The input neuron, the weight, the output neuron, the input neuron derivative, the weight derivative and the output neuron derivative are all represented in the form of a matrix or a vector. The computing device obtains the maximum absolute value of each category of data by traversing all elements in the vector/matrix of each layer of the above-mentioned multi-layer network model, that is,
Figure BDA0001995399720000338
by formula
Figure BDA0001995399720000339
Determine the decimal point position sa for converting each category of data a to fixed-point data.

a.2)、上述计算装置按照分层分类别寻找绝对值最大值a.2), the above-mentioned computing device finds the absolute maximum value according to the hierarchical classification

具体地,第一输入数据向量/矩阵中的每个元素为ai(l),其中,该a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA00019953997200003310
或输出神经元导数
Figure BDA00019953997200003311
或权值导数
Figure BDA00019953997200003312
换言之,上述多层网络模型的每层均包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数。上述第一输入数据的小数点位置包括输入神经元的小数点位置、权值的小数点位置、输出神经元的小数点位置、输入神经元导数的小数点位置、权值导数的小数点位置和输出神经元导数的小数点位置。该输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数均以矩阵/向量表示。上述计算装置通过遍历多层网络模型的每层的每种数据的向量/矩阵中的所有元素,获取每种类别数据的绝对值的最大值,即
Figure BDA00019953997200003313
通过公式:
Figure BDA00019953997200003314
确定在第l层每种类别数据a的小数点位置
Figure BDA00019953997200003315
Specifically, each element in the first input data vector/matrix is ai(l) , where a(l) can be an input neuron X(l) or an output neuron Y(l) or a weight W(l) or input neuron derivative
Figure BDA00019953997200003310
or output neuron derivative
Figure BDA00019953997200003311
or weight derivative
Figure BDA00019953997200003312
In other words, each layer of the above-mentioned multi-layer network model includes input neurons, weights, output neurons, derivatives of input neurons, derivatives of weights, and derivatives of output neurons. The position of the decimal point of the first input data includes the position of the decimal point of the input neuron, the position of the decimal point of the weight, the position of the decimal point of the output neuron, the position of the decimal point of the derivative of the input neuron, the position of the decimal point of the derivative of the weight value, and the decimal point of the derivative of the output neuron. Location. The input neuron, weight, output neuron, input neuron derivative, weight derivative, and output neuron derivative are all represented by a matrix/vector. The above computing device obtains the maximum value of the absolute value of each type of data by traversing all elements in the vector/matrix of each type of data in each layer of the multi-layer network model, that is,
Figure BDA00019953997200003313
Via the formula:
Figure BDA00019953997200003314
Determine the position of the decimal point for each category of data a in the lth layer
Figure BDA00019953997200003315

a.3)、上述计算装置按照分层分类别分组进寻找绝对值最大值a.3), the above-mentioned computing device is grouped according to the hierarchical classification to find the maximum absolute value

具体地,第一输入数据向量/矩阵中的每个元素为ai(l),其中a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA00019953997200003316
或输出神经元导数
Figure BDA00019953997200003317
或权值导数
Figure BDA00019953997200003318
换言之,上述多层网络模型的每层的数据类别包括输入神经元、权值、输出神经元、输入神经元导数、权值导数和输出神经元导数。上述计算装置将上述多层网络模型的每层的每种类型数据分为g组,或者通过其他任意分组规则进行分组。然后遍历上述多层网络模型中每层每种类型数据对应的g组数据中每组数据的每个元素,获取该组数据中绝对值最大的元素,即
Figure BDA00019953997200003319
通过公式
Figure BDA00019953997200003320
确定每层中每种数据类别对应的g组数据每组的小数点位置
Figure BDA0001995399720000341
Specifically, each element in the first input data vector/matrix is ai(l) , where a(l) can be an input neuron X(l) or an output neuron Y(l) or a weight W(l ) or the input neuron derivative
Figure BDA00019953997200003316
or output neuron derivative
Figure BDA00019953997200003317
or weight derivative
Figure BDA00019953997200003318
In other words, the data categories of each layer of the above-mentioned multi-layer network model include input neurons, weights, output neurons, derivatives of input neurons, derivatives of weights, and derivatives of output neurons. The above-mentioned computing device divides each type of data of each layer of the above-mentioned multi-layer network model into g groups, or groups according to other arbitrary grouping rules. Then traverse each element of each group of data in the g group of data corresponding to each type of data in each layer in the above-mentioned multi-layer network model, and obtain the element with the largest absolute value in the group of data, that is,
Figure BDA00019953997200003319
by formula
Figure BDA00019953997200003320
Determine the decimal point position of each group of g data corresponding to each data category in each layer
Figure BDA0001995399720000341

其中,上述任意分组规则包括但不限定于根据数据范围进行分组、根据数据训练批次进行分组等规则。Wherein, the above arbitrary grouping rules include but are not limited to rules such as grouping according to data range, grouping according to data training batches, and the like.

b)上述计算装置根据第一输入数据的绝对值最小值初始化该第一输入数据的小数点位置s:b) The above-mentioned computing device initializes the decimal point position s of the first input data according to the minimum absolute value of the first input data:

具体地,上述计算装置找到待量化数据的绝对值最小值amin,通过以下公式确定定点化精度s。Specifically, the above-mentioned computing device finds the absolute minimum value amin of the data to be quantized, and determines the fixed point precision s by the following formula.

Figure BDA0001995399720000342
Figure BDA0001995399720000342

其中,上述amin为上述第一输入数据的绝对值最小值。获取amin的过程具体可参见上述步骤a.1)、a.2)、a.3)。Wherein, the above amin is the minimum absolute value of the above first input data. For details of the process of obtaining amin , please refer to the above steps a.1), a.2), and a.3).

c)上述计算装置根据第一输入数据中不同数据类型间关系初始化所述第一输入数据的小数点位置s:c) The above-mentioned computing device initializes the decimal point position s of the first input data according to the relationship between different data types in the first input data:

具体地,多层网络模型中的任一层(比如第l层)的数据类型a(l)的小数点位置

Figure BDA0001995399720000343
可以由上述计算装置根据第l层的数据类型b(l)的小数点位置
Figure BDA0001995399720000344
和公式
Figure BDA0001995399720000345
确定。Specifically, the decimal point position of the data type a(l) of any layer (such as the lth layer) in the multi-layer network model
Figure BDA0001995399720000343
The decimal point position of the data type b(l) of the lth layer can be determined by the above-mentioned computing means
Figure BDA0001995399720000344
and formula
Figure BDA0001995399720000345
Sure.

其中,a(l)和b(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA0001995399720000346
或输出神经元导数
Figure BDA0001995399720000347
或权值导数
Figure BDA0001995399720000348
其中,a(l)和b(l)为整数常数。where a(l) and b(l) can be input neuron X(l) or output neuron Y(l) or weight W(l) or input neuron derivative
Figure BDA0001995399720000346
or output neuron derivative
Figure BDA0001995399720000347
or weight derivative
Figure BDA0001995399720000348
where a(l) and b(l) are integer constants.

d)上述计算装置根据经验值常量初始化第一输入数据的小数点位置s:d) The above-mentioned computing device initializes the decimal point position s of the first input data according to the empirical value constant:

具体地,上述多层网络模型的任一层(比如第l层)的数据类型a(l)的小数点位置sa(l)可人为设定sa(l)=c,其中c为整数常数,上述a(l)可为输入神经元X(l)或输出神经元Y(l)或权值W(l)或输入神经元导数

Figure BDA0001995399720000349
或输出神经元导数
Figure BDA00019953997200003410
或权值导数
Figure BDA00019953997200003411
Specifically, the decimal point position sa(l) of the data type a(l) of any layer (such as the lth layer) of the above-mentioned multi-layer network model can be manually set as sa(l) = c, where c is an integer constant , the above a(l) can be input neuron X(l) or output neuron Y(l) or weight W(l) or input neuron derivative
Figure BDA0001995399720000349
or output neuron derivative
Figure BDA00019953997200003410
or weight derivative
Figure BDA00019953997200003411

进一步地,上述输入神经元的小数点位置初始化值和输出神经元的小数点位置初始化值均可在[-8,8]范围内选取;权值的小数点位置初始化值可在[-17,8]范围内选取,输入神经元导数的小数点位置初始化值和输出神经元导数的小数点位置初始化值均可在[-40,-20]范围内选取。权值导数的小数点位置初始化值可在[-48,-12]范围内选取。Further, the initialization value of the decimal point position of the input neuron and the initialization value of the decimal point position of the output neuron can be selected in the range of [-8, 8]; the initialization value of the decimal point position of the weight can be in the range of [-17, 8]. The initial value of the decimal point position of the input neuron derivative and the initial value of the decimal point position of the output neuron derivative can be selected within the range of [-40,-20]. The initial value of the decimal point position of the weight derivative can be selected in the range of [-48,-12].

下面具体介绍上述计算装置动态调整数据上述小数点位置s的方法。The method for dynamically adjusting the position s of the decimal point of the data by the above-mentioned computing device will be specifically described below.

上述计算装置动态调整小数点位置s的方法包括向上调整s(s变大),和向下调整s(s变小)。具体包括根据第一输入数据绝对值最大值单步向上调整;根据第一输入数据绝对值最大值逐步向上调整;根据第一输入数据分布单步向上调整;根据第一输入数据分布逐步向上调整;根据第一输入数据绝对值最大值向下调整。The above-mentioned method for dynamically adjusting the decimal point position s by the computing device includes adjusting s upward (s becomes larger), and adjusting s downward (s becomes smaller). Specifically, it includes a single-step upward adjustment according to the absolute maximum value of the first input data; a step-by-step upward adjustment according to the absolute maximum value of the first input data; a single-step upward adjustment according to the first input data distribution; and a step-by-step upward adjustment according to the first input data distribution; Adjust downward according to the maximum value of the absolute value of the first input data.

a)、上述计算装置根据第一输入数据中数据绝对值的最大值单步向上调整:a), the above-mentioned computing device is adjusted upward in a single step according to the maximum value of the absolute value of the data in the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos]。其中,pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。当上述第一输入数据中数据绝对值的最大值amax≥pos时,则调整之后的小数点位置为

Figure BDA00019953997200003412
否则不调整上述小数点位置,即s_new=s_old。Assuming that the position of the decimal point is s_old before adjustment, the fixed-point data corresponding to the position of the decimal point s_old can indicate that the data range is [neg, pos]. Wherein, pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum-1 -1)*2s_old . When the maximum value of the absolute value of the data in the first input data is amax ≥ pos, the adjusted decimal point position is
Figure BDA00019953997200003412
Otherwise, the position of the decimal point is not adjusted, that is, s_new=s_old.

b)、上述计算装置根据第一输入数据中数据绝对值的最大值逐步向上调整:b), the above-mentioned computing device is adjusted upward step by step according to the maximum value of the absolute value of the data in the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。当上述第一输入数据中数据绝对值的最大值amax≥pos时,则调整之后的小数点位置为s_new=s_old+1;否则不调整上述小数点位置,即s_new=s_old。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . When the maximum value amax ≥ pos of the absolute value of the data in the first input data, the adjusted decimal point position is s_new=s_old+1; otherwise, the decimal point position is not adjusted, that is, s_new=s_old.

c)、上述计算装置根据第一输入数据分布单步向上调整:c), the above-mentioned computing device is adjusted upward in a single step according to the first input data distribution:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。计算第一输入数据的绝对值的统计量,如绝对值的均值amean和绝对值的标准差astd。设置数据的最大范围amax=amean+nastd。当amax≥pos时,

Figure BDA0001995399720000351
否则不调整上述小数点位置,即s_new=s_old。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . Statistics of absolute values of the first input data are calculated, such as the mean amean of the absolute values and the standard deviation astd of the absolute values. Set the maximum range of data amax =amean +nastd . When amax ≥ pos,
Figure BDA0001995399720000351
Otherwise, the position of the decimal point is not adjusted, that is, s_new=s_old.

进一步地,上述n可取2或者3Further, the above n can take 2 or 3

d)、上述计算装置根据第一输入数据分布逐步向上调整:d), the above-mentioned computing device is gradually adjusted upwards according to the distribution of the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。计算第一输入数据的绝对值的统计量,如绝对值的均值amean和绝对值的标准差astd。设置数据的最大范围amax=amean+nastd,n可取3。当amax≥pos时,s_new=s_old+1,否则不调整上述小数点位置,即s_new=s_old。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . Statistics of absolute values of the first input data are calculated, such as the mean amean of the absolute values and the standard deviation astd of the absolute values. Set the maximum range of data amax =amean +nastd , and n can take 3. When amax ≥ pos, s_new=s_old+1, otherwise, the position of the decimal point is not adjusted, that is, s_new=s_old.

e)、上述计算装置根据第一输入数据绝对值最大值向下调整:e), the above-mentioned computing device is adjusted downward according to the absolute maximum value of the first input data:

假设上述小数点位置调整之前为s_old,该小数点位置s_old对应的定点数据可表示数据范围是[neg,pos],其中pos=(2bitnum-1-1)*2s_old,neg=-(2bitnum-1-1)*2s_old。当第一输入数据的绝对值最大值amax<2s_old+(bitnum-n)且s_old≥smin时,s_new=s_old-1,其中n为整数常数,smin可以是整数,也可以是负无穷。Assuming that the decimal point position is s_old before adjustment, the fixed-point data corresponding to the decimal point position s_old can represent the data range [neg, pos], where pos=(2bitnum-1 -1)*2s_old , neg=-(2bitnum- 1 -1)*2s_old . When the absolute maximum value of the first input data amax <2s_old+(bitnum-n) and s_old≥smin , s_new=s_old-1, where n is an integer constant, and smin can be an integer or negative infinity .

进一步地,上述n为3,上述smin为-64。Further, the above n is 3, and the above smin is -64.

可选地,对于调整上述小数点位置的频率,可以是永远不调整第一输入数据的小数点位置;或者是每隔n个第一训练周期(即iteration)调整一次,n为常量;或者每隔n个第二训练周期(即epoch)调整一次,n为常量;或者是每隔n个第一训练周期或n个第二训练周期调整一次第一输入数据的小数点位置,每隔n个第一训练周期或第二训练周期调整一次第一输入数据的小数点位置,然后调整n=αn,其中α大于1;或者是每隔n个第一训练周期或第二训练周期调整一次第一输入数据的小数点位置,随着训练轮数递增,逐渐减小n。Optionally, for the frequency of adjusting the position of the decimal point, the position of the decimal point of the first input data can be never adjusted; or it is adjusted once every n first training periods (ie iteration), where n is a constant; or every n The second training cycle (ie epoch) is adjusted once, and n is a constant; or the decimal point position of the first input data is adjusted every n first training cycles or n second training cycles, and every n first training cycles are adjusted. Adjust the decimal point position of the first input data once in a period or the second training period, and then adjust n=αn, where α is greater than 1; or adjust the decimal point of the first input data every n first training periods or second training periods position, and gradually decrease n as the number of training epochs increases.

进一步地,每隔100个第一训练周期调整一次输入神经元的小数点位置、权值的小数点位置和输出神经元的小数点位置。每隔20个第一训练周期调整一次输入神经元导数的小数点位置和输出神经元导数的小数点位置。Further, the decimal point position of the input neuron, the decimal point position of the weight and the decimal point position of the output neuron are adjusted every 100 first training cycles. Adjust the decimal point position of the input neuron derivative and the decimal point position of the output neuron derivative every 20 first training epochs.

需要说明的是,上述第一训练周期为训练一批次样本所需的时间,第二训练周期为对所有训练样本进行一次训练所需的时间。It should be noted that the above-mentioned first training period is the time required to train a batch of samples, and the second training period is the time required to perform one training on all the training samples.

需要说明的是,上述通过上述数据绝对值的平均值或者中间值,初始化和调整上述数据的小数点位置,具体可参见上述通过数据的绝对值的最大值初始化和调整上述数据的小数点位置的相关描述,在此不再叙述。It should be noted that the above-mentioned initialization and adjustment of the decimal point position of the above-mentioned data through the average or intermediate value of the absolute value of the above-mentioned data may refer to the above-mentioned initialization and adjustment of the decimal point position of the above-mentioned data through the maximum value of the absolute value of the data. , will not be described here.

需要说明的是,对于前述的各方法实施例,为了简单描述,故将其都表述为一系列的动作组合,但是本领域技术人员应该知悉,本申请并不受所描述的动作顺序的限制,因为依据本申请,某些步骤可以采用其他顺序或者同时进行。其次,本领域技术人员也应该知悉,说明书中所描述的实施例均属于可选实施例,所涉及的动作和模块并不一定是本申请所必须的。It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Because in accordance with the present application, certain steps may be performed in other orders or concurrently. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

在本申请所提供的几个实施例中,应该理解到,所揭露的装置,可通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个系统,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性或其它的形式。In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components may be combined or Integration into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical or other forms.

所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

另外,在本申请各个实施例中的各功能单元可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现,也可以采用软件程序模块的形式实现。In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, and can also be implemented in the form of software program modules.

所述集成的单元如果以软件程序模块的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储器中。基于这样的理解,本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储器中,包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储器包括:U盘、只读存储器(ROM,Read-Only Memory)、随机存取存储器(RAM,Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。The integrated unit, if implemented in the form of a software program module and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art, or all or part of the technical solution, and the computer software product is stored in a memory, Several instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成,该程序可以存储于一计算机可读存储器中,存储器可以包括:闪存盘、ROM、RAM、磁盘或光盘等。Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash disk , ROM, RAM, disk or CD, etc.

以上对本申请实施例进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的方法及其核心思想;同时,对于本领域的一般技术人员,依据本申请的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本申请的限制。The embodiments of the present application have been introduced in detail above, and specific examples are used to illustrate the principles and implementations of the present application. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application; at the same time, for Persons of ordinary skill in the art, according to the idea of the present application, will have changes in the specific implementation manner and application scope. In conclusion, the contents of this specification should not be construed as a limitation on the present application.

Claims (66)

Translated fromChinese
1.一种计算装置,其特征在于,包括:存储单元、转换单元、运算单元以及控制器单元;所述存储单元包括缓存和寄存器,1. A computing device, comprising: a storage unit, a conversion unit, an arithmetic unit and a controller unit; the storage unit includes a cache and a register,所述控制器单元,用于确定第一输入数据的小数点位置和定点数据的位宽;所述定点数据的位宽为所述第一输入数据转换为定点数据的位宽;The controller unit is configured to determine the decimal point position of the first input data and the bit width of the fixed-point data; the bit width of the fixed-point data is the bit width of the first input data converted into the fixed-point data;所述运算单元,用于初始化所述第一输入数据的小数点位置和调整所述第一输入数据的小数点位置;并将调整后的第一输入数据的小数点位置存储至所述存储单元的缓存中,The arithmetic unit is used to initialize the decimal point position of the first input data and adjust the decimal point position of the first input data; and store the adjusted decimal point position of the first input data in the cache of the storage unit ,所述控制器单元,用于从所述寄存器中获取第一输入数据和多个运算指令,并从所述缓存中获取所述调整后的第一输入数据的小数点位置;将所述调整后的第一输入数据的小数点位置及所述第一输入数据传输至所述转换单元;The controller unit is configured to obtain the first input data and a plurality of operation instructions from the register, and obtain the decimal point position of the adjusted first input data from the cache; The decimal point position of the first input data and the first input data are transmitted to the conversion unit;所述转换单元,用于根据所述调整后的第一输入数据的小数点位置将所述第一输入数据转换为第二输入数据;the conversion unit, configured to convert the first input data into the second input data according to the position of the decimal point of the adjusted first input data;其中,所述运算单元初始化所述第一输入数据的小数点位置,包括:Wherein, the operation unit initializes the decimal point position of the first input data, including:根据经验值常量初始化所述第一输入数据的小数点位置。The decimal point position of the first input data is initialized according to an empirical value constant.2.根据权利要求1所述的装置,其特征在于,所述运算单元调整所述第一输入数据的小数点位置,包括:2. The device according to claim 1, wherein the operation unit adjusts the decimal point position of the first input data, comprising:根据所述第一输入数据中数据绝对值的最大值单步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward in a single step according to the maximum value of the absolute value of the data in the first input data, or;根据所述第一输入数据中数据绝对值的最大值逐步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward step by step according to the maximum value of the absolute value of the data in the first input data, or;根据所述第一输入数据分布单步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward in a single step according to the distribution of the first input data, or;根据所述第一输入数据分布逐步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward step by step according to the distribution of the first input data, or;根据所述第一输入数据绝对值最大值向下调整所述第一输入数据的小数点位置。The decimal point position of the first input data is adjusted downward according to the maximum absolute value of the first input data.3.根据权利要求1或2任一项所述的装置,其特征在于,所述计算装置用于执行机器学习计算,3. The device according to any one of claims 1 or 2, wherein the computing device is configured to perform machine learning calculations,所述控制器单元,还用于将所述多个运算指令传输至所述运算单元;the controller unit, further configured to transmit the plurality of operation instructions to the operation unit;所述转换单元,还用于将所述第二输入数据传输至所述运算单元;the conversion unit, further configured to transmit the second input data to the operation unit;所述运算单元,还用于根据所述多个运算指令对所述第二输入数据进行运算,以得到运算结果。The operation unit is further configured to perform an operation on the second input data according to the plurality of operation instructions to obtain an operation result.4.根据权利要求3所述的装置,其特征在于,所述机器学习计算包括:人工神经网络运算,所述第一输入数据包括:输入神经元数据和权值数据;所述运算结果为输出神经元数据。4. The device according to claim 3, wherein the machine learning calculation comprises: artificial neural network operation, the first input data comprises: input neuron data and weight data; the operation result is an output neuron data.5.根据权利要求3所述的装置,其特征在于,所述运算单元包括一个主处理电路和多个从处理电路;5. The device according to claim 3, wherein the arithmetic unit comprises a master processing circuit and a plurality of slave processing circuits;所述主处理电路,用于对所述第二输入数据进行执行前序处理以及与所述多个从处理电路之间传输数据和所述多个运算指令;the master processing circuit, configured to perform pre-processing on the second input data and transmit data and the multiple operation instructions with the multiple slave processing circuits;所述多个从处理电路,用于依据从所述主处理电路传输第二输入数据以及所述多个运算指令并执行中间运算得到多个中间结果,并将多个中间结果传输给所述主处理电路;The plurality of slave processing circuits are configured to obtain a plurality of intermediate results according to transmitting the second input data and the plurality of operation instructions from the main processing circuit and performing intermediate operations, and transmit the plurality of intermediate results to the master processing circuit;所述主处理电路,用于对所述多个中间结果执行后续处理得到所述运算结果。The main processing circuit is configured to perform subsequent processing on the plurality of intermediate results to obtain the operation result.6.根据权利要求4所述的装置,其特征在于,所述运算单元包括一个主处理电路和多个从处理电路;6. The device according to claim 4, wherein the arithmetic unit comprises a master processing circuit and a plurality of slave processing circuits;所述主处理电路,用于对所述第二输入数据进行执行前序处理以及与所述多个从处理电路之间传输数据和所述多个运算指令;the master processing circuit, configured to perform pre-processing on the second input data and transmit data and the multiple operation instructions with the multiple slave processing circuits;所述多个从处理电路,用于依据从所述主处理电路传输第二输入数据以及所述多个运算指令并执行中间运算得到多个中间结果,并将多个中间结果传输给所述主处理电路;The plurality of slave processing circuits are configured to obtain a plurality of intermediate results according to transmitting the second input data and the plurality of operation instructions from the main processing circuit and performing intermediate operations, and transmit the plurality of intermediate results to the master processing circuit;所述主处理电路,用于对所述多个中间结果执行后续处理得到所述运算结果。The main processing circuit is configured to perform subsequent processing on the plurality of intermediate results to obtain the operation result.7.根据权利要求5所述的装置,其特征在于,所述计算装置还包括:直接内存访问DMA单元,7. The device according to claim 5, wherein the computing device further comprises: a direct memory access DMA unit,所述缓存,还用于存储所述第一输入数据;其中,所述缓存包括高速暂存缓存;The cache is also used to store the first input data; wherein, the cache includes a high-speed temporary cache;所述寄存器,还用于存储所述第一输入数据中标量数据;The register is also used to store scalar data in the first input data;所述DMA单元,用于从所述存储单元中读取数据或者向所述存储单元存储数据。The DMA unit is configured to read data from the storage unit or store data to the storage unit.8.根据权利要求6所述的装置,其特征在于,所述计算装置还包括:直接内存访问DMA单元,8. The device according to claim 6, wherein the computing device further comprises: a direct memory access DMA unit,所述缓存,还用于存储所述第一输入数据;其中,所述缓存包括高速暂存缓存;The cache is also used to store the first input data; wherein, the cache includes a high-speed temporary cache;所述寄存器,还用于存储所述第一输入数据中标量数据;The register is also used to store scalar data in the first input data;所述DMA单元,用于从所述存储单元中读取数据或者向所述存储单元存储数据。The DMA unit is configured to read data from the storage unit or store data to the storage unit.9.根据权利要求3所述的装置,其特征在于,当所述第一输入数据为定点数据时,所述运算单元还包括:9. The apparatus according to claim 3, wherein when the first input data is fixed-point data, the operation unit further comprises:推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.10.根据权利要求4所述的装置,其特征在于,当所述第一输入数据为定点数据时,所述运算单元还包括:10. The apparatus according to claim 4, wherein when the first input data is fixed-point data, the operation unit further comprises:推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.11.根据权利要求5所述的装置,其特征在于,当所述第一输入数据为定点数据时,所述运算单元还包括:11. The apparatus according to claim 5, wherein when the first input data is fixed-point data, the operation unit further comprises:推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.12.根据权利要求6所述的装置,其特征在于,当所述第一输入数据为定点数据时,所述运算单元还包括:12. The apparatus according to claim 6, wherein when the first input data is fixed-point data, the operation unit further comprises:推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.13.根据权利要求7所述的装置,其特征在于,当所述第一输入数据为定点数据时,所述运算单元还包括:13. The apparatus according to claim 7, wherein when the first input data is fixed-point data, the operation unit further comprises:推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.14.根据权利要求8所述的装置,其特征在于,当所述第一输入数据为定点数据时,所述运算单元还包括:14. The apparatus according to claim 8, wherein when the first input data is fixed-point data, the operation unit further comprises:推导单元,用于根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。A deriving unit, configured to derive the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.15.根据权利要求9所述的装置,其特征在于,所述运算单元还包括:15. The apparatus according to claim 9, wherein the arithmetic unit further comprises:数据缓存单元,用于缓存所述一个或多个中间结果。A data cache unit for caching the one or more intermediate results.16.根据权利要求10所述的装置,其特征在于,所述运算单元还包括:16. The apparatus according to claim 10, wherein the arithmetic unit further comprises:数据缓存单元,用于缓存所述一个或多个中间结果。A data cache unit for caching the one or more intermediate results.17.根据权利要求11所述的装置,其特征在于,所述运算单元还包括:17. The apparatus according to claim 11, wherein the arithmetic unit further comprises:数据缓存单元,用于缓存所述一个或多个中间结果。A data cache unit for caching the one or more intermediate results.18.根据权利要求12所述的装置,其特征在于,所述运算单元还包括:18. The apparatus according to claim 12, wherein the arithmetic unit further comprises:数据缓存单元,用于缓存所述一个或多个中间结果。A data cache unit for caching the one or more intermediate results.19.根据权利要求13所述的装置,其特征在于,所述运算单元还包括:19. The apparatus according to claim 13, wherein the arithmetic unit further comprises:数据缓存单元,用于缓存所述一个或多个中间结果。A data cache unit for caching the one or more intermediate results.20.根据权利要求14所述的装置,其特征在于,所述运算单元还包括:20. The apparatus according to claim 14, wherein the arithmetic unit further comprises:数据缓存单元,用于缓存所述一个或多个中间结果。A data cache unit for caching the one or more intermediate results.21.根据权利要求5所述的装置,其特征在于,所述运算单元包括:树型模块,所述树型模块包括:一个根端口和多个支端口,所述树型模块的根端口连接所述主处理电路,所述树型模块的多个支端口分别连接多个从处理电路中的一个从处理电路;21. The device according to claim 5, wherein the operation unit comprises: a tree module, the tree module comprises: a root port and a plurality of branch ports, and the root port of the tree module is connected to In the master processing circuit, a plurality of branch ports of the tree module are respectively connected to one slave processing circuit among the multiple slave processing circuits;所述树型模块,用于转发所述主处理电路与所述多个从处理电路之间的数据以及运算指令;The tree module is used to forward data and operation instructions between the master processing circuit and the plurality of slave processing circuits;其中,所述树型模块为n叉树结构,所述n为大于或等于2的整数。Wherein, the tree module is an n-ary tree structure, and the n is an integer greater than or equal to 2.22.根据权利要求6所述的装置,其特征在于,所述运算单元包括:树型模块,所述树型模块包括:一个根端口和多个支端口,所述树型模块的根端口连接所述主处理电路,所述树型模块的多个支端口分别连接多个从处理电路中的一个从处理电路;22. The device according to claim 6, wherein the operation unit comprises: a tree-type module, the tree-type module comprises: a root port and a plurality of branch ports, and the root port of the tree-type module is connected to In the master processing circuit, a plurality of branch ports of the tree module are respectively connected to one slave processing circuit among the multiple slave processing circuits;所述树型模块,用于转发所述主处理电路与所述多个从处理电路之间的数据以及运算指令;The tree module is used to forward data and operation instructions between the master processing circuit and the plurality of slave processing circuits;其中,所述树型模块为n叉树结构,所述n为大于或等于2的整数。Wherein, the tree module is an n-ary tree structure, and the n is an integer greater than or equal to 2.23.根据权利要求7所述的装置,其特征在于,所述运算单元包括:树型模块,所述树型模块包括:一个根端口和多个支端口,所述树型模块的根端口连接所述主处理电路,所述树型模块的多个支端口分别连接多个从处理电路中的一个从处理电路;23. The device according to claim 7, wherein the operation unit comprises: a tree-type module, the tree-type module comprises: a root port and a plurality of branch ports, and the root port of the tree-type module is connected to In the master processing circuit, a plurality of branch ports of the tree module are respectively connected to one slave processing circuit among the multiple slave processing circuits;所述树型模块,用于转发所述主处理电路与所述多个从处理电路之间的数据以及运算指令;The tree module is used to forward data and operation instructions between the master processing circuit and the plurality of slave processing circuits;其中,所述树型模块为n叉树结构,所述n为大于或等于2的整数。Wherein, the tree module is an n-ary tree structure, and the n is an integer greater than or equal to 2.24.根据权利要求8所述的装置,其特征在于,所述运算单元包括:树型模块,所述树型模块包括:一个根端口和多个支端口,所述树型模块的根端口连接所述主处理电路,所述树型模块的多个支端口分别连接多个从处理电路中的一个从处理电路;24. The apparatus according to claim 8, wherein the operation unit comprises: a tree-type module, the tree-type module comprises: a root port and a plurality of branch ports, and the root port of the tree-type module is connected to In the master processing circuit, a plurality of branch ports of the tree module are respectively connected to one slave processing circuit among the multiple slave processing circuits;所述树型模块,用于转发所述主处理电路与所述多个从处理电路之间的数据以及运算指令;The tree module is used to forward data and operation instructions between the master processing circuit and the plurality of slave processing circuits;其中,所述树型模块为n叉树结构,所述n为大于或等于2的整数。Wherein, the tree module is an n-ary tree structure, and the n is an integer greater than or equal to 2.25.根据权利要求5所述的装置,其特征在于,所述运算单元还包括分支处理电路,25. The apparatus according to claim 5, wherein the arithmetic unit further comprises a branch processing circuit,所述主处理电路,具体用于确定输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块、广播数据以及多个运算指令中的至少一个运算指令发送给所述分支处理电路;The main processing circuit is specifically used to determine that the input neuron is broadcast data, the weight is distribution data, allocate one distribution data into multiple data blocks, and assign at least one data block and broadcast data to at least one of the multiple data blocks. And at least one operation instruction in the plurality of operation instructions is sent to the branch processing circuit;所述分支处理电路,用于转发所述主处理电路与所述多个从处理电路之间的数据块、广播数据以及运算指令;The branch processing circuit is configured to forward data blocks, broadcast data and operation instructions between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据该运算指令对接收到的数据块以及广播数据执行运算得到中间结果,并将中间结果传输给所述分支处理电路;The plurality of slave processing circuits are configured to perform operations on the received data blocks and broadcast data according to the operation instructions to obtain intermediate results, and transmit the intermediate results to the branch processing circuits;所述主处理电路,还用于将所述分支处理电路发送的中间结果进行后续处理得到所述运算指令的结果,将所述运算指令的结果发送至所述控制器单元。The main processing circuit is further configured to perform subsequent processing on the intermediate result sent by the branch processing circuit to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.26.根据权利要求6所述的装置,其特征在于,所述运算单元还包括分支处理电路,26. The apparatus according to claim 6, wherein the arithmetic unit further comprises a branch processing circuit,所述主处理电路,具体用于确定所述输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块、广播数据以及多个运算指令中的至少一个运算指令发送给所述分支处理电路;The main processing circuit is specifically configured to determine that the input neuron is broadcast data, the weight is distribution data, allocate one distribution data into multiple data blocks, and divide at least one data block, sending broadcast data and at least one operation instruction among the plurality of operation instructions to the branch processing circuit;所述分支处理电路,用于转发所述主处理电路与所述多个从处理电路之间的数据块、广播数据以及运算指令;The branch processing circuit is configured to forward data blocks, broadcast data and operation instructions between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据该运算指令对接收到的数据块以及广播数据执行运算得到中间结果,并将中间结果传输给所述分支处理电路;The plurality of slave processing circuits are configured to perform operations on the received data blocks and broadcast data according to the operation instructions to obtain intermediate results, and transmit the intermediate results to the branch processing circuits;所述主处理电路,还用于将所述分支处理电路发送的中间结果进行后续处理得到所述运算指令的结果,将所述运算指令的结果发送至所述控制器单元。The main processing circuit is further configured to perform subsequent processing on the intermediate result sent by the branch processing circuit to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.27.根据权利要求7所述的装置,其特征在于,所述运算单元还包括分支处理电路,27. The apparatus according to claim 7, wherein the arithmetic unit further comprises a branch processing circuit,所述主处理电路,具体用于确定输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块、广播数据以及多个运算指令中的至少一个运算指令发送给所述分支处理电路;The main processing circuit is specifically used to determine that the input neuron is broadcast data, the weight is distribution data, allocate one distribution data into multiple data blocks, and assign at least one data block and broadcast data to at least one of the multiple data blocks. And at least one operation instruction in the plurality of operation instructions is sent to the branch processing circuit;所述分支处理电路,用于转发所述主处理电路与所述多个从处理电路之间的数据块、广播数据以及运算指令;The branch processing circuit is configured to forward data blocks, broadcast data and operation instructions between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据该运算指令对接收到的数据块以及广播数据执行运算得到中间结果,并将中间结果传输给所述分支处理电路;The plurality of slave processing circuits are configured to perform operations on the received data blocks and broadcast data according to the operation instructions to obtain intermediate results, and transmit the intermediate results to the branch processing circuits;所述主处理电路,还用于将所述分支处理电路发送的中间结果进行后续处理得到所述运算指令的结果,将所述运算指令的结果发送至所述控制器单元。The main processing circuit is further configured to perform subsequent processing on the intermediate result sent by the branch processing circuit to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.28.根据权利要求8所述的装置,其特征在于,所述运算单元还包括分支处理电路,28. The apparatus according to claim 8, wherein the arithmetic unit further comprises a branch processing circuit,所述主处理电路,具体用于确定输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块、广播数据以及多个运算指令中的至少一个运算指令发送给所述分支处理电路;The main processing circuit is specifically used to determine that the input neuron is broadcast data, the weight is distribution data, allocate one distribution data into multiple data blocks, and assign at least one data block and broadcast data to at least one of the multiple data blocks. And at least one operation instruction in the plurality of operation instructions is sent to the branch processing circuit;所述分支处理电路,用于转发所述主处理电路与所述多个从处理电路之间的数据块、广播数据以及运算指令;The branch processing circuit is configured to forward data blocks, broadcast data and operation instructions between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据该运算指令对接收到的数据块以及广播数据执行运算得到中间结果,并将中间结果传输给所述分支处理电路;The plurality of slave processing circuits are configured to perform operations on the received data blocks and broadcast data according to the operation instructions to obtain intermediate results, and transmit the intermediate results to the branch processing circuits;所述主处理电路,还用于将所述分支处理电路发送的中间结果进行后续处理得到所述运算指令的结果,将所述运算指令的结果发送至所述控制器单元。The main processing circuit is further configured to perform subsequent processing on the intermediate result sent by the branch processing circuit to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.29.根据权利要求5所述的装置,其特征在于,所述多个从处理电路呈阵列分布;每个从处理电路与相邻的其他从处理电路连接,所述主处理电路连接所述多个从处理电路中的K个从处理电路,所述K个从处理电路为:第1行的n个从处理电路、第m行的n个从处理电路以及第1列的m个从处理电路;29. The apparatus according to claim 5, wherein the plurality of slave processing circuits are distributed in an array; each slave processing circuit is connected to other adjacent slave processing circuits, and the master processing circuit is connected to the plurality of slave processing circuits. K slave processing circuits in the slave processing circuits, the K slave processing circuits are: n slave processing circuits in the first row, n slave processing circuits in the mth row, and m slave processing circuits in the first column ;所述K个从处理电路,用于在所述主处理电路以及多个从处理电路之间的数据以及指令的转发;The K slave processing circuits are used for data and instruction forwarding between the master processing circuit and a plurality of slave processing circuits;所述主处理电路,还用于确定输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块以及多个运算指令中的至少一个运算指令发送给所述K个从处理电路;The main processing circuit is further configured to determine that the input neuron is broadcast data, the weight is distribution data, distribute one distribution data into multiple data blocks, and assign at least one data block and multiple data blocks among the multiple data blocks. at least one operation instruction in the operation instructions is sent to the K slave processing circuits;所述K个从处理电路,用于转换所述主处理电路与所述多个从处理电路之间的数据;the K slave processing circuits for converting data between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据所述运算指令对接收到的数据块执行运算得到中间结果,并将运算结果传输给所述K个从处理电路;The multiple slave processing circuits are configured to perform operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the K slave processing circuits;所述主处理电路,用于将所述K个从处理电路发送的中间结果进行处理得到该运算指令的结果,将该运算指令的结果发送给所述控制器单元。The main processing circuit is configured to process the K intermediate results sent from the processing circuits to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.30.根据权利要求6所述的装置,其特征在于,所述多个从处理电路呈阵列分布;每个从处理电路与相邻的其他从处理电路连接,所述主处理电路连接所述多个从处理电路中的K个从处理电路,所述K个从处理电路为:第1行的n个从处理电路、第m行的n个从处理电路以及第1列的m个从处理电路;30. The apparatus according to claim 6, wherein the plurality of slave processing circuits are distributed in an array; each slave processing circuit is connected to other adjacent slave processing circuits, and the master processing circuit is connected to the plurality of slave processing circuits. K slave processing circuits in the slave processing circuits, the K slave processing circuits are: n slave processing circuits in the first row, n slave processing circuits in the mth row, and m slave processing circuits in the first column ;所述K个从处理电路,用于在所述主处理电路以及多个从处理电路之间的数据以及指令的转发;The K slave processing circuits are used for data and instruction forwarding between the master processing circuit and a plurality of slave processing circuits;所述主处理电路,还用于确定所述输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块以及多个运算指令中的至少一个运算指令发送给所述K个从处理电路;The main processing circuit is further configured to determine that the input neuron is broadcast data, the weight is distribution data, distribute one distribution data into a plurality of data blocks, and assign at least one data block of the plurality of data blocks and at least one operation instruction in the plurality of operation instructions is sent to the K slave processing circuits;所述K个从处理电路,用于转换所述主处理电路与所述多个从处理电路之间的数据;the K slave processing circuits for converting data between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据所述运算指令对接收到的数据块执行运算得到中间结果,并将运算结果传输给所述K个从处理电路;The multiple slave processing circuits are configured to perform operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the K slave processing circuits;所述主处理电路,用于将所述K个从处理电路发送的中间结果进行处理得到该运算指令的结果,将该运算指令的结果发送给所述控制器单元。The main processing circuit is configured to process the K intermediate results sent from the processing circuits to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.31.根据权利要求7所述的装置,其特征在于,所述多个从处理电路呈阵列分布;每个从处理电路与相邻的其他从处理电路连接,所述主处理电路连接所述多个从处理电路中的K个从处理电路,所述K个从处理电路为:第1行的n个从处理电路、第m行的n个从处理电路以及第1列的m个从处理电路;31. The device according to claim 7, wherein the plurality of slave processing circuits are distributed in an array; each slave processing circuit is connected to other adjacent slave processing circuits, and the master processing circuit is connected to the plurality of slave processing circuits. K slave processing circuits in the slave processing circuits, the K slave processing circuits are: n slave processing circuits in the first row, n slave processing circuits in the mth row, and m slave processing circuits in the first column ;所述K个从处理电路,用于在所述主处理电路以及多个从处理电路之间的数据以及指令的转发;The K slave processing circuits are used for data and instruction forwarding between the master processing circuit and a plurality of slave processing circuits;所述主处理电路,还用于确定输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块以及多个运算指令中的至少一个运算指令发送给所述K个从处理电路;The main processing circuit is further configured to determine that the input neuron is broadcast data, the weight is distribution data, distribute one distribution data into multiple data blocks, and assign at least one data block and multiple data blocks among the multiple data blocks. at least one operation instruction in the operation instructions is sent to the K slave processing circuits;所述K个从处理电路,用于转换所述主处理电路与所述多个从处理电路之间的数据;the K slave processing circuits for converting data between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据所述运算指令对接收到的数据块执行运算得到中间结果,并将运算结果传输给所述K个从处理电路;The multiple slave processing circuits are configured to perform operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the K slave processing circuits;所述主处理电路,用于将所述K个从处理电路发送的中间结果进行处理得到该运算指令的结果,将该运算指令的结果发送给所述控制器单元。The main processing circuit is configured to process the K intermediate results sent from the processing circuits to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.32.根据权利要求8所述的装置,其特征在于,所述多个从处理电路呈阵列分布;每个从处理电路与相邻的其他从处理电路连接,所述主处理电路连接所述多个从处理电路中的K个从处理电路,所述K个从处理电路为:第1行的n个从处理电路、第m行的n个从处理电路以及第1列的m个从处理电路;32. The apparatus according to claim 8, wherein the plurality of slave processing circuits are distributed in an array; each slave processing circuit is connected to other adjacent slave processing circuits, and the master processing circuit is connected to the plurality of slave processing circuits. K slave processing circuits in the slave processing circuits, the K slave processing circuits are: n slave processing circuits in the first row, n slave processing circuits in the mth row, and m slave processing circuits in the first column ;所述K个从处理电路,用于在所述主处理电路以及多个从处理电路之间的数据以及指令的转发;The K slave processing circuits are used for data and instruction forwarding between the master processing circuit and a plurality of slave processing circuits;所述主处理电路,还用于确定输入神经元为广播数据,权值为分发数据,将一个分发数据分配成多个数据块,将所述多个数据块中的至少一个数据块以及多个运算指令中的至少一个运算指令发送给所述K个从处理电路;The main processing circuit is further configured to determine that the input neuron is broadcast data, the weight is distribution data, distribute one distribution data into multiple data blocks, and assign at least one data block and multiple data blocks among the multiple data blocks. at least one operation instruction in the operation instructions is sent to the K slave processing circuits;所述K个从处理电路,用于转换所述主处理电路与所述多个从处理电路之间的数据;the K slave processing circuits for converting data between the master processing circuit and the plurality of slave processing circuits;所述多个从处理电路,用于依据所述运算指令对接收到的数据块执行运算得到中间结果,并将运算结果传输给所述K个从处理电路;The multiple slave processing circuits are configured to perform operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the K slave processing circuits;所述主处理电路,用于将所述K个从处理电路发送的中间结果进行处理得到该运算指令的结果,将该运算指令的结果发送给所述控制器单元。The main processing circuit is configured to process the K intermediate results sent from the processing circuits to obtain the result of the operation instruction, and send the result of the operation instruction to the controller unit.33.根据权利要求21所述的装置,其特征在于,33. The apparatus of claim 21, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.34.根据权利要求22所述的装置,其特征在于,34. The apparatus of claim 22, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.35.根据权利要求23所述的装置,其特征在于,35. The apparatus of claim 23, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.36.根据权利要求24所述的装置,其特征在于,36. The apparatus of claim 24, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.37.根据权利要求25所述的装置,其特征在于,37. The apparatus of claim 25, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.38.根据权利要求26所述的装置,其特征在于,38. The apparatus of claim 26, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.39.根据权利要求27所述的装置,其特征在于,39. The apparatus of claim 27, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.40.根据权利要求28所述的装置,其特征在于,40. The apparatus of claim 28, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.41.根据权利要求29所述的装置,其特征在于,41. The device of claim 29, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.42.根据权利要求30所述的装置,其特征在于,42. The apparatus of claim 30, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.43.根据权利要求31所述的装置,其特征在于,43. The apparatus of claim 31, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.44.根据权利要求32所述的装置,其特征在于,44. The apparatus of claim 32, wherein所述主处理电路,具体用于将多个处理电路发送的中间结果进行组合排序得到该运算指令的结果;The main processing circuit is specifically configured to combine and sort the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction;或所述主处理电路,具体用于将多个处理电路的发送的中间结果进行组合排序以及激活处理后得到该运算指令的结果。Or the main processing circuit is specifically configured to combine, sort and activate the intermediate results sent by the multiple processing circuits to obtain the result of the operation instruction.45.根据权利要求21所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;45. The apparatus of claim 21, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.46.根据权利要求22所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;46. The apparatus of claim 22, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.47.根据权利要求23所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;47. The apparatus of claim 23, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.48.根据权利要求24所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;48. The apparatus of claim 24, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.49.根据权利要求25所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;49. The apparatus according to claim 25, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.50.根据权利要求26所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;50. The apparatus of claim 26, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.51.根据权利要求27所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;51. The apparatus according to claim 27, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.52.根据权利要求28所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;52. The apparatus of claim 28, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.53.根据权利要求29所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;53. The apparatus of claim 29, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.54.根据权利要求30所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;54. The apparatus of claim 30, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.55.根据权利要求31所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;55. The apparatus of claim 31, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.56.根据权利要求32所述的装置,其特征在于,所述主处理电路包括:激活处理电路和加法处理电路中的一种或任意组合;56. The apparatus of claim 32, wherein the main processing circuit comprises: one or any combination of an activation processing circuit and an addition processing circuit;所述激活处理电路,用于执行主处理电路内数据的激活运算;The activation processing circuit is used to execute the activation operation of the data in the main processing circuit;所述加法处理电路,用于执行加法运算或累加运算;The addition processing circuit is used to perform addition operation or accumulation operation;所述从处理电路包括:The slave processing circuit includes:乘法处理电路,用于对接收到的数据块执行乘积运算得到乘积结果;a multiplication processing circuit, which is used to perform a multiplication operation on the received data block to obtain a multiplication result;累加处理电路,用于对该乘积结果执行累加运算得到该中间结果。The accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.57.一种机器学习运算装置,其特征在于,所述机器学习运算装置包括一个或多个如权利要求3-56任一项所述的计算装置,用于从其他处理装置中获取待运算数据和控制信息,并执行指定的机器学习运算,将执行结果通过I/O接口传递给其他处理装置;57. A machine learning computing device, characterized in that the machine learning computing device comprises one or more computing devices according to any one of claims 3-56, for obtaining data to be computed from other processing devices and control information, and execute the specified machine learning operation, and transmit the execution result to other processing devices through the I/O interface;当所述机器学习运算装置包含多个所述计算装置时,所述多个所述计算装置间可以通过特定的结构进行连接并传输数据;When the machine learning computing device includes a plurality of the computing devices, the plurality of the computing devices can be connected through a specific structure and data can be transmitted;其中,多个所述计算装置通过快速外部设备互连总线PCIE总线进行互联并传输数据,以支持更大规模的机器学习的运算;多个所述计算装置共享同一控制系统或拥有各自的控制系统;多个所述计算装置共享内存或者拥有各自的内存;多个所述计算装置的互联方式是任意互联拓扑。Wherein, a plurality of the computing devices are interconnected and transmit data through the fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; a plurality of the computing devices share the same control system or have their own control systems ; A plurality of the computing devices share memory or have their own memory; the interconnection mode of the plurality of computing devices is any interconnection topology.58.一种组合处理装置,其特征在于,所述组合处理装置包括如权利要求57所述的机器学习运算装置,通用互联接口、存储装置和其他处理装置;58. A combined processing device, characterized in that the combined processing device comprises the machine learning computing device as claimed in claim 57, a universal interconnection interface, a storage device and other processing devices;所述机器学习运算装置与所述其他处理装置进行交互,共同完成用户指定的计算操作;The machine learning computing device interacts with the other processing devices to jointly complete the computing operation specified by the user;所述存储装置分别与所述机器学习运算装置和所述其他处理装置连接,用于保存所述机器学习运算装置和所述其他处理装置的数据。The storage device is respectively connected to the machine learning computing device and the other processing device, and is used for saving the data of the machine learning computing device and the other processing device.59.一种神经网络芯片,其特征在于,所述神经网络芯片包括如权利要求57所述的机器学习运算装置或如权利要求58所述的组合处理装置。59. A neural network chip, wherein the neural network chip comprises the machine learning computing device as claimed in claim 57 or the combined processing device as claimed in claim 58.60.一种电子设备,其特征在于,所述电子设备包括如权利要求59所述的芯片。60. An electronic device, wherein the electronic device comprises the chip of claim 59.61.一种板卡,其特征在于,所述板卡包括:存储器件、接口装置和控制器件以及如权利要求59所述的神经网络芯片;61. A board, characterized in that the board comprises: a storage device, an interface device, a control device, and a neural network chip as claimed in claim 59;其中,所述神经网络芯片与所述存储器件、所述控制器件以及所述接口装置分别连接;Wherein, the neural network chip is respectively connected with the storage device, the control device and the interface device;所述存储器件,用于存储数据;the storage device for storing data;所述接口装置,用于实现所述芯片与外部设备之间的数据传输;the interface device for realizing data transmission between the chip and an external device;所述控制器件,用于对所述芯片的状态进行监控;the control device for monitoring the state of the chip;其中,所述存储器件包括:多组存储单元,每一组所述存储单元与所述芯片通过总线连接,所述存储单元为:DDR SDRAM;Wherein, the storage device includes: multiple groups of storage units, each group of the storage units is connected to the chip through a bus, and the storage units are: DDR SDRAM;所述芯片包括:DDR控制器,用于对每个所述存储单元的数据传输与数据存储的控制;The chip includes: a DDR controller for controlling data transmission and data storage of each of the storage units;所述接口装置为:标准PCIE接口。The interface device is: a standard PCIE interface.62.一种计算方法,其特征在于,包括:62. A computing method, characterized in that, comprising:控制器单元确定第一输入数据的小数点位置和定点数据的位宽,所述定点数据的位宽为所述第一输入数据转换为定点数据的位宽;The controller unit determines the decimal point position of the first input data and the bit width of the fixed-point data, and the bit width of the fixed-point data is the bit width of the first input data converted into the fixed-point data;运算单元初始化所述第一输入数据的小数点位置和调整所述第一输入数据的小数点位置;The arithmetic unit initializes the decimal point position of the first input data and adjusts the decimal point position of the first input data;转换单元获取调整后的第一输入数据的小数点位置,并根据调整后的小数点位置将所述第一输入数据转换为第二输入数据;The conversion unit obtains the decimal point position of the adjusted first input data, and converts the first input data into the second input data according to the adjusted decimal point position;其中,所述运算单元初始化所述第一输入数据的小数点位置,包括:Wherein, the operation unit initializes the decimal point position of the first input data, including:根据经验值常量初始化所述第一输入数据的小数点位置。The decimal point position of the first input data is initialized according to an empirical value constant.63.根据权利要求62所述的方法,其特征在于,所述运算单元调整所述第一输入数据的小数点位置,包括:63. The method according to claim 62, wherein the operation unit adjusts the decimal point position of the first input data, comprising:根据所述第一输入数据中数据绝对值的最大值单步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward in a single step according to the maximum value of the absolute value of the data in the first input data, or;根据所述第一输入数据中数据绝对值的最大值逐步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward step by step according to the maximum value of the absolute value of the data in the first input data, or;根据所述第一输入数据分布单步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward in a single step according to the distribution of the first input data, or;根据所述第一输入数据分布逐步向上调整所述第一输入数据的小数点位置,或者;Adjust the decimal point position of the first input data upward step by step according to the distribution of the first input data, or;根据所述第一输入数据绝对值最大值向下调整所述第一输入数据的小数点位置。The decimal point position of the first input data is adjusted downward according to the maximum absolute value of the first input data.64.根据权利要求62或63所述的方法,其特征在于,所述计算方法为用于执行机器学习计算的方法,所述方法还包括:64. The method according to claim 62 or 63, wherein the computing method is a method for performing machine learning computing, the method further comprising:所述运算单元根据多个运算指令对所述第二输入数据进行运算,以得到运算结果。The operation unit operates on the second input data according to a plurality of operation instructions to obtain an operation result.65.根据权利要求64所述的方法,其特征在于,所述机器学习计算包括:人工神经网络运算,所述第一输入数据包括:输入神经元和权值;所述运算结果为输出神经元。65. The method according to claim 64, wherein the machine learning calculation comprises: an artificial neural network operation, the first input data comprises: input neurons and weights; the operation result is an output neuron .66.根据权利要求65所述的方法,其特征在于,当所述第一输入数据为定点数据时,所述方法还包括:66. The method according to claim 65, wherein when the first input data is fixed-point data, the method further comprises:所述运算单元根据所述第一输入数据的小数点位置,推导得到一个或者多个中间结果的小数点位置,其中所述一个或多个中间结果为根据所述第一输入数据运算得到的。The operation unit derives the decimal point position of one or more intermediate results according to the decimal point position of the first input data, wherein the one or more intermediate results are obtained by operation according to the first input data.
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