Detailed Description
The present invention relates to circuits. More specifically, embodiments of the present invention provide a Variable Gain Amplifier (VGA) device including a low gain adjustment portion and a high gain adjustment portion. The low gain adjustment section includes both a resistor element and a transistor element. The high gain adjustment section includes a transistor element and is activated when the output gain is greater than a predetermined threshold level. Other embodiments also exist.
As described above, VGA devices have various applications. In the past, various VGA designs have been proposed. For example, FIG. 1 is a diagram illustrating a conventional open-loop VGA 100. As shown, a pair of differential inputs vin+ and Vin-are coupled to transistor 102 and transistor 103, respectively. Each transistor (102 and 103) is characterized by its own transconductance (Gm) value. More specifically, an input voltage is utilized as an input received by the transistor 102 and the transistor 103, which effectively function as a current source, the amount of current of which is based on both the input voltage and the transistor characteristics.
The output voltages at nodes 104 and 105 (for negative and positive output voltages, respectively) are based on load resistor RL And pass switch (i.e. switch C1 To Cn ) Voltage distribution between the controlled resistor arrays. For example by opening switch c2 Two R' s2 The resistor is functionally removed from the device. The load resistor is arranged between the supply voltages Vdd 101 and Vss 108. VGA100 further includes transistors 106 and 107 that provide a bias voltage. To change the output voltage and thus adjust the gain of VGA100, the switches at the resistor array are selectively closed or opened. For example, the resistor array may be uniformly treated as having R with respect to the output terminalsx Is a value of (2). Because there are discrete and preconfigured numbers of resistors, possible R of the resistor arrayx The values are discrete and predetermined.
The low frequency gain of the VGA can be described in equation 1 below:
equation 1:
in equation 1, Vo Is the output voltage and Vi Is the input voltage. As explained above, the variable Gm is the transconductance value of transistor 102 and/or transistor 103. Variable RL Is the value of the load resistor. Variable RX Is the effective resistance value of the resistor array.
Various disadvantages and drawbacks exist with respect to the design of VGA100 shown in fig. 1. Wherein, since the adjustment of the gain depends on the resistor array having a discrete number of switches and their corresponding resistors, the resistance value Rx (and thus VGA gain) can be adjusted in only a limited and discrete number of ways. In addition, resistors generally occupy valuable real estate on a circuit chip, and are therefore expensive to implement (especially when there are a large number of resistors).
In some applications, the resistor is implemented using a transistor (or voltage-controlled resistor) instead of a resistor. Fig. 2 is a diagram illustrating a transistor-based VGA device 200. As shown in fig. 2, transistor 205 replaces the resistor array of fig. 1. Among other properties, the transistor 205 functions as a VCR and receives a control voltage v that adjusts the equivalent resistance value of the transistor 205tune . It will be appreciated that the control voltage v applied to transistor 205tune Fine tuning is possible and continuously adjustable (i.e., not limited by the number of switches and resistors in fig. 1). The gain of VGA 200 can be represented by equation 1 above, where the term "Rx" is replaced by the resistance value of transistor 205. Note that in fig. 2, a voltage (coupled to the pumping voltage vpmp Transistor 201 and transistor 202 replace the load resistor Rl And these transistors are functionally equivalent to load resistors. Referring back to equation 1, the resistance value RL By item (1/Gm)load ) Replacement, wherein Gmload Is the transconductance value of load transistors 201 and 202.
A number of advantages are provided by the use of transistor 205. Unfortunately, there are also drawbacks associated with using transistor 205. Wherein transistor 205 may be nonlinear and may have a high level of Total Harmonic Distortion (THD) under certain operating parameters. For example, the transistor 205 is implemented using a CMOS device, which introduces distortion of THD in the low gain setting.
The distortion of VGA 200 in fig. 2 can be illustrated by the following equation. Assuming that the input transconductance (Gm) of transistors 203 and 204 is high, the small signal values at nodes 206 and 207 may be represented by the following equation:
equation 2A:
equation 2B:
as shown in fig. 2, the voltage across transistor 205 is the voltage between node 206 and node 207 (i.e., between vx+ and vx ").
The distortion (THD) of VGA 200 can be represented by the following equation1 )：
Equation 3: i=k (V* Vin-Vin2 /n)
Wherein: "I" is the drain-source current of transistor 205;
according to e.g. v=vtune- (vx)+ +vx- ) The "V x" is the regulated voltage "vtune" applied to the gate of transistor 205;
"Vin" is the input voltage (i.e., vin+ and/or Vin-); and
"n" is the slope.
Equation 4: vin=acos (ωt)
Wherein: "A" is the input sinusoidal amplitude
Equation 5:
where "K" is the transistor gain
Equation 6:
based on equation 6, it can be seen that the distortion THD1 Proportional to "a" and inversely proportional to "V". This means that a small V results in high distortion, or when VGA gain is low (e.g., 0dB or even lower). For example, operating in a low gain setting, VGA 200 in fig. 2 can have a higher level of THD than the THD of VGA 100. On the other hand, when the regulated voltage V is high, THD is low. Thus, for operation in a high gain setting, THD of VGA 200 is low when V is high and the effective resistance of transistor 205 is low.
It should be appreciated that embodiments of the present invention provide a linear VGA apparatus that operates to provide linearity, tunability, and low distortion. Fig. 3 is a diagram illustrating an open-loop linear VGA 300 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. The linear VGA device 300 includes a switching resistor portion and a transistor 307 for adjusting the gain (i.e., the ratio between the output voltage and the input voltage). Input voltage vin+ And vin- Are connected to the gate terminals of transistors 305 and 306, respectively. For example, the transistors 305 and 306 are implemented using CMOS transistors. Transistors 305 and 306 are characterized by their transconductance values, and transistors 305 and 306 effectively provide a current based on the input voltage.
The output of VGA 300 is provided at nodes 303 and 304. More specifically, node 303 provides a negative output vo- And node 304 provides a positive output vo+ . As described above, the output voltage of the VGA 300 depends on both the load portion and the adjustment portion (i.e., the resistor portion 311 and the transistor 307). For example, the transistors 301 and 302 are implemented as output load sections. It should be understood that the load section may also be implemented using other electronic components, such as the load resistor shown in fig. 1. In addition, the load section may be implemented as a combination of a resistor and a transistor.
Transistors 305 and 306 are coupled to a resistor portion 311 and a transistor 307. Transistor 307 is configured between node 308 and node 309. For example, the transistor 307 includes a CMOS transistor and functions as a variable-impedance element (or voltage-controlled resistor) whose impedance value is controlled by a control signal v coupled to the gate of the transistor 307gch And (5) controlling. The resistor portion 311 is disposed in a parallel configuration with respect to the transistor 307 because, as shown, the switched resistor portion is also coupled to the node 308 and the node 309. Transistor 310 is configured between two resistors each having a resistance value of Rx/2 (i.e., so the total resistance is Rx because the two resistors are configured in series with respect to each other). Depending on the implementation, transistor 310 may be used as a switch (i.e., closed or open as shown in fig. 1) or as a tunable transistor (i.e., functionally identical to transistor 307). For example, when used as a switch, the control signal vgcl Providing that transistor 310 is closedOr a binary control of disconnection. With its equivalent impedance value used as an adjustable transistor, control signal vgcl Providing a regulated voltage that adjusts the impedance value of transistor 310.
In various implementations, the adjustment portion 311 and the transistor 307 together provide a continuously adjustable resistance value. For example, when operating in the low gain setting, the transistor 310 of the adjusting section 311 is turned on and continuously changes its resistance value (by adjusting the signal vgcl Controlled). When VGA 300 changes from a low gain setting to a high gain setting, wherein the low gain setting and the high gain setting are separated by a predetermined threshold, transistor 307 is activated and responsive to adjustment signal vgch Adjusting its resistance. It should be noted that when operating in the high gain setting, transistor 310 remains on, allowing the gain of VGA 300 to be linear even during the transition from low gain to high gain.
V across the device of VGA 300DS The voltage (a') is no longer approximately equal to the input voltage (as is typical in VGA 200 in fig. 2). In addition, transistor 307 operates with a higher regulated voltage (than transistor 205 of VGA 200) because the required device resistance is reduced by a factor of "Rx" from regulator 311. And it should be appreciated that these two effects reduce distortion. The performance of VGA 300 can be represented using the following equation:
equation 7A: a' noteqvin
Equation 7B:
wherein: "A" is the input sinusoidal amplitude;
"A'" is V at both ends of the deviceDS A voltage;
"Vin" is the input voltage;
“R’sw "is the resistance of the switching transistor; and
"Rx" is the series resistance of the adjustment section 311.
Equation 8:
where "K'" is the transistor gain; and
"V '" is as V' =vgcl- (vx)+ +vx- ) The effective regulated voltage of VGA 300 defined by/2, and V' for VGA 300 is higher than V for VGA 200.
Equation 9:
wherein, "THD2 "is the total harmonic distortion of VGA 300.
As can be seen by comparing equation 9 and equation 6, THD2 Specific THD1 Low 2Rx K 'V' times. For example, as far as THD is concerned, the improvement provided by VGA 300 over VGA 200 is represented by the following equation 10:
equation 10:
it should be appreciated that the improvement described in equation 10 has been tested in a practical implementation. For example, when operating with 0dB gain, THD performance improves from-33 dB for VGA 200 architecture to-55 dB for VGA 300 architecture. The THD of 9dB gain remains above-50 dB for VGA 300. Therefore, as shown in fig. 3, by using the transistor 307 for high gain operation and the adjusting section 311 for low gain operation, distortion can be effectively reduced.
Fig. 4 is a diagram illustrating a VGA system 400 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. The system 400 includes a control module 410 that provides digital control signals in the form of DAC codes for DACs 413 and 414, the DACs 413 and 414 providing analog control signals for an amplifier section 420 of the VGA 400. More specifically, DAC413 provides an analog control signal "v" for transistor 421gch ". DAC 414 supplies analog control signal "v" for adjusting section 423gcl ", and the control signal is coupled to the transistor422. The control module 410 receives the "IncDec" signal as an input signal for increasing or decreasing amplification, which the control module 410 uses to generate DAC codes for the DAC413 and the DAC 414. The control module 410 includes a state machine that provides digital codewords for the DAC413 and the DAC 414. In various embodiments, DAC413 and DAC 414 are high resolution DACs (e.g., 9-bit DACs) that process the 9-bit digital codeword from control module 410. The control module generates a digital codeword using predetermined logic and parameters. For example, the minimum and maximum DAC codes are preconfigured and calibrated for the operating parameters of the amplifier portion 420 of VGA 400. Exemplary behavior of the control module 410 is shown in FIG. 5. Wherein the control module 410 includes at least a representation (1) of the conditions for opening the DACs 413 and 414; (2) Correlation between output gain of VGA400 and DAC code; and (3) maximum and minimum output voltages (or control voltages applied to transistors 421 and 422). For example, when operating in a low gain condition (i.e., a gain below a predetermined threshold), control module 410 provides DAC code only to DAC 414 and DAC413 is turned off. When a predetermined output gain threshold is reached, the control module 410 provides a DAC code to both DAC413 and DAC 414.
Fig. 5 is a diagram illustrating the operation of the control module 410 of fig. 4. This diagram is merely an example, which should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Graph 502 depicts the control module generating a DAC code for DAC413 which in turn provides an analog control signal for transistor 421. Graph 501 depicts the control module generating a DAC code for DAC 414, which DAC 414 in turn provides an analog control signal for transistor 422 that acts as a voltage-controlled resistor. For example, DAC413 and DAC 414 in fig. 4 are sigma delta DAC devices that operate with a DAC code above 64 (e.g., to account for aliasing effects).
As shown in graph 501, when the output gain is set to 64, the DAC code increases from its minimum value of 64 (the vertical axis represents the DAC code). As shown, the DAC code peak peaks at a value of 480 when the output gain reaches 480, and even when the output gain is 6The DAC code is also maintained 480 at 66. This translates to turning on transistor 422 at the lowest output setting and maintaining the increment control signal "vgcl "until the control signal for transistor 422 reaches a maximum value (maximum out) at the output gain setting of 480. DAC code output (and thus control signal "vgcl ") is substantially linear between the output gain settings 63 and 480, which means that the change in the resistance value of the adjustment portion 423 is substantially linear.
As for the high gain operation, the transistor 421 (serving as a voltage-controlled resistor) is turned on and adjusted according to a desired output setting. The DAC code values for transistor 421 are shown in graph 502. The DAC code remains at a minimum of 64 until the output gain on the horizontal axis is 250. The DAC code increases from a minimum value 64 to a maximum value 480 of the gain setting 250 (when the output gain is 666). For example, when the output gain is 250, graph 502 translates to turning on transistor 421. Because the output gain increases from 250 to 666, the DAC code for DAC413 increases linearly until a maximum value is reached. It should be noted that as the output gain of the DAC code for DAC413 begins to ramp up at 250, the DAC code for DAC 412 (in graph 501) also increases. More specifically, as the output gain moves from 250 to 480, the DAC code for both DAC413 and DAC 414 increases, meaning that transistors 421 and 422 both receive an increased control voltage at their respective gates. When the output gain reaches 480, transistor 422 receives its maximum control voltage. As suggested in graph 502, transistor 421 receives its maximum control voltage when the output gain reaches 666.
When reducing VGA gain, the DAC code to DAC413 and the output of DAC 414 follow graphs 501 and 502 (right to left at this time) similarly. For example, as the output gain decreases from maximum gain, the DAC code for DAC413 remains reduced until the gain is 250, at gain 250, the DAC code remains at its minimum value of 64; during the same period, the DAC code for DAC 414 maintains its maximum value and begins to decrease linearly as the gain drops to 480.
Reference is now back made to fig. 4. As can be seen in fig. 4, the state machine of the control module 410And DACs 413 and 414 to provide control signals v for controlling the high gain transistor 421 and the low gain transistor 422, respectivelygch And vgcl . It should be appreciated that, according to various embodiments, the control signal (in some cases more than two signals) may also be generated in other ways, as described below. For example, the integrated control unit may generate a plurality of analog control signals to adjust the resistances of the transistors and the adjustment portion (e.g., a resistor with an "on/off" switch or a resistor with a transistor serving as a voltage-controlled resistor).
According to embodiments of the present invention, distortion may be minimized and optimized by appropriately adjusting the upper and lower threshold voltages (e.g., the behavior describing the high and low control signals provided in graphs 501 and 502) determined from the analog and/or measurement of the VGA device. In particular embodiments, VGA system 400 includes a digitally programmable gain threshold. For example, the DACs (e.g., DACs 413 and 414) may be implemented using a one-time second order sigma delta DAC with a passive filter. Other types of DACs may also be used, depending on the implementation. For example, various types of analog circuits provide the above-described tap control voltages.
It should be appreciated that VGA devices and techniques according to embodiments of the present invention can provide a high degree of linearity and maintainability. Fig. 6 is a graph showing a relationship between VGA gain and DAC code for VGA 400. For purposes of illustration, the DAC code on the horizontal axis is the DAC code combined with the 250 code offset, and the gain on the vertical axis is the VGA gain in decibels. As can be seen in fig. 6, the relationship between the combined DAC code and VGA is substantially linear and continuous.
Fig. 7 is a graph showing the combined gain digital code range and the control signal for VGA400 generated by the DAC. Graph line 701 is the correlation v for low gain transistor 422gcl A control signal. Graph line 702 is vsgch A high gain control signal 421 is associated. The combined digital range of the horizontal axes is related to the control signals for transistors 421 and 422. For example, thresholds for low gain transistor 422 and high gain transistor 421The values (i.e., 64 and 250) are consistent with graphs 501 and 502 in fig. 5.
Fig. 8 is a graph showing the combined gain digital code range with the corresponding DSM code for VGA 400. Graph line 801 is the associated DSM code for DAC 414. Chart line 802 is associated with the DSM code for DAC 413. For example, the thresholds (i.e., 64 and 250) for DACs 414 and 413 are consistent with graphs 501 and 502 in fig. 5.
Fig. 9 is a simplified block diagram illustrating a VGA system 900 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, VGA 300 and VGA400 are exemplary implementations, and embodiments of the invention may be implemented in other ways. As shown in fig. 9, VGA system 900 includes a control module 901. Depending on the implementation, the control module 901 may receive various forms of input gain signals. For example, the gain signal may be an analog signal from another electronic component or logic component to indicate an increase or decrease in the output gain of the VGA system 900. The input gain signal may also be a digital signal representing the target output gain as a digital value. In addition, the control module 901 includes a logic unit for generating a control signal. For example, the logic unit for generating the control signals may be a state machine as shown in fig. 4, but other implementations may be used, such as a microprocessor-based controller or the like. The logic unit provides a setting of which regulating part is turned on and how strong the control signal is, which in turn adjusts the impedance value of the individual regulating parts.
The range of impedance values of the adjustment portions (e.g., 908 a-908 n) is predetermined and programmed into the logic cells. For example, the logic unit of the control module indicates that the control signal C1 is active for a gain range of 0dB to 5dB, and that both control signals C1 and C2 are active within a gain range of 5dB to 10dB, etc. For example, as for the n adjustment sections, the control module 901 supplies at least n control signals. The impedance value of the impedance of the adjustment portion may be continuous and/or binary, depending on the implementation. As for the adjustment portion including only the adjustable transistor (e.g., implemented with the transistor 421) serving as the variable resistor, the impedance value is continuously adjustable. Similarly, as for the adjustment portion (e.g., adjustment portion 422) having a resistor and an adjustable transistor, the impedance value is continuously adjustable, with the minimum resistance value provided by the resistor. A binary adjustment section similar to the adjustment section shown in fig. 1 may also be utilized, wherein the switch receives a control signal indicating whether the adjustment section is on or off.
In providing the control signal for the adjustment portion, the control module 901 may be implemented in various ways. For example, the control module 901 may provide various control signals for adjusting and/or switching transistors of the adjustment section. For example, the control module 901 may provide different control codes and/or control signals to the adjustment portion. In particular embodiments, control module 901 adjusts each adjustment section using a single control code, wherein the Most Significant Bit (MSB) is used to switch one or more adjustment sections and the Least Significant Bit (LSB) is used to continuously adjust the impedance value of one or more transistors.
There may be a different number of adjustment portions. As described above, the adjustment section will include at least a low gain section (with the actual resistive element) and a high gain section. The additional adjustment may be configured to provide a high level of linearity. For example, the adjustment portion may be specifically adjusted for high level of linearity and maintainability (e.g., making the gain curve shown in fig. 5 more straight). At the same time, the large number of adjustment portions may result in excessively complex circuits and controls.
The amplifier portion 910 of VGA 900 includes input terminals 906 and 907. For example, input terminals 906 and 907 are configured to receive a pair of differential inputs including a positive input vin+ and a negative input Vin-. The amplifier section 910 further includes a load 902 and a load 903. In various embodiments, load 902 and load 903 are implemented with matched impedance values. For example, the load 902 and the load 903 may be implemented using transistors and/or resistors.
In various implementations, the input terminals 906 and 907 are implemented using transistors (e.g., CMOS devices, etc.). For example, the input terminal acts as a current source and the output gain at the output terminals 904 and/or 905 depends on the transconductance characteristics of the input transistor. Various types of transistors may be used for the input terminals.
The output terminal 904 is placed between the load 902 and the input terminal 906. The output terminal 905 is disposed between the load 903 and the input 907. For example, the output terminals are pairs including a positive output terminal vout+ and a negative output terminal Vout-. Additional electronic components may also be used to implement the output terminals.
As shown, the amplifier section 910 also includes a bias module 909. For example, the bias module may include bias transistors (e.g., bias transistors 106 and 107 shown in fig. 1) and a voltage source (e.g., vss 108).
Fig. 10 is a graph showing a combined gain digital code range for a plurality of adjustment sections and a corresponding control signal generated by a DAC according to an embodiment of the invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. With respect to fig. 10, the horizontal axis corresponds to the combined digital range and the vertical axis corresponds to the DSM output voltage. For example, the "Vgc1" signal is for the adjustment section having the lowest digital code setting, and starts to ramp up and reaches its maximum value before the other adjustment sections. The "Vgc2" signal is for an adjustment section having a higher digital setting (e.g., a higher gain adjustment section) and begins to ramp up after the "Vgc1" signal begins to ramp up but before the "Vgc1" signal reaches a maximum. It should be noted that the overlapping ramping pattern shared between the "Vgc1" signal and the "Vgc2" signal allows for continuous output. Similarly, the signals "Vgc3", "Vgc4", and "Vgc5" are stacked in a similar manner, allowing for a large adjustment range.