CN110097902B - Read-write control module and method for same port and dual-port memory - Google Patents
Read-write control module and method for same port and dual-port memoryDownload PDFInfo
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- CN110097902B CN110097902BCN201910298680.2ACN201910298680ACN110097902BCN 110097902 BCN110097902 BCN 110097902BCN 201910298680 ACN201910298680 ACN 201910298680ACN 110097902 BCN110097902 BCN 110097902B
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- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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Abstract
Description
Technical Field
The disclosure belongs to the technical field of read-write control of memory data, and relates to a read-write control module and method for the same port and a dual-port memory.
Background
Memory is one of the devices commonly used in digital systems. Dual port memories typically have two ports and an array of memory cells that can be accessed simultaneously from the ports if the memory cells accessed from one side are different from the memory cells of the other side.
Meanwhile, the high-speed data acquisition and processing system has high requirements on the processing capacity of a large amount of rapidly-inserted multivariable data and the real-time performance of the system. In some data storage applications, dual port memory implementations are required to read old data before writing new data.
In the prior art, a dual-port memory has two means for realizing the function of reading old data first and then writing new data, one means is realized by using two ports, at the moment, one port reads the old data first, and the other port writes the new data, and the method occupies port resources of the dual-port memory and causes adverse effect on the data processing capacity of the memory; one is to use one port, but it needs to use two clock cycles to complete, i.e. two clock cycles are used to implement the function of reading old data and then writing new data, which reduces the real-time performance of data.
Therefore, for the dual port memory, the most important technical defects of the existing read-write control method are as follows: the method comprises the following steps that firstly, port resources of a dual-port memory are occupied by adopting a mode of two ports, so that the dual-port memory becomes a single-port memory for practical application, and in addition, read-out and written-in data can appear in different physical ports, so that the hardware design becomes more complex; and secondly, the real-time performance of the data is reduced by adopting a mode of one port and two clock cycles.
Therefore, it is necessary to provide a method for directly reading and writing in one clock cycle for the same port of the dual port memory.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a read/write control module and method for a same port, and a dual port memory, so as to at least partially solve the above-mentioned technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a read-write control module 1 for a same port, including: a clockdelay generating module 11 for generating a read timing and a write timing; a read-writepulse generating module 12, configured to correspondingly generate a read pulse signal and a write pulse signal with staggered time sequences under the clock control of the read time sequence and the write time sequence, where the read pulse signal and the write pulse signal respectively include a plurality of read pulses and write pulses, and at least one read pulse and one write pulse are included in the same clock cycle; a read-write controlsignal generation module 14, configured to output a read-write control signal according to the control of the port enable signal; and a word line controlsignal generating module 13, configured to generate a word line control signal according to the input port read-write control signal, the read pulse signal, and the write pulse signal.
In some embodiments of the present disclosure, in the read/write control module 1, the port enable signal includes: a read/write enable signal wren and a read-then-write function signal same _ port _ read if the same port is required.
In some embodiments of the present disclosure, the read/write controlsignal generating module 14 includes: aninverter 141, an orgate 143, and abuffer 142; the read-write enable signal wren is respectively connected to the input ends of theinverter 141 and thebuffer 142, the output end of theinverter 141 is connected to one input end of the orgate 143, and whether the read-then-write function signal same _ port _ read needs to be input to the other input end of the orgate 143 through the same port or not is determined, or the output end of the orgate 143 outputs the read control signal read _ en; the output port of the buffer outputs a write control signal write _ en.
In some embodiments of the present disclosure, the word line controlsignal generating module 13 includes three nand gates, i.e., afirst nand gate 131, asecond nand gate 132, and athird nand gate 133; the port read-write control signal comprises a port read control signal and a port write control signal; the input end of thefirst nand gate 131 is connected to the port read control signal read _ en and the read pulse signal r _ pulse respectively; the input end of thesecond nand gate 132 is respectively connected with the port write control signal write _ en and the write pulse signal w _ pulse; the outputs of thefirst nand gate 131 and thesecond nand gate 132 are both connected to the input of thethird nand gate 133; the output terminal of thethird nand gate 133 serves as the output terminal of the word line controlsignal generating module 13, and outputs a word line control signal word _ en.
In some embodiments of the present disclosure, the read-writepulse generating module 12 includes a readpulse generating module 121 and a writepulse generating module 122, where the readpulse generating module 121 is a first register with a zero clearing function, and the writepulse generating module 122 is a second register with a zero clearing function; the clockdelay generation module 11 includes delay modules with different four-stage delay sizes, a clock signal input port and a clear port of the first register are respectively connected with the two-stage delay modules, and a clock signal input port and a clear port of the second register are respectively connected with the other two-stage delay modules.
In some embodiments of the present disclosure, the delay module is a fixed delay module or an adjustable delay module.
According to another aspect of the present disclosure, there is provided a read-write control method for a same port, including: generating a read timing and a write timing; under the clock control of the read timing and the write timing, correspondingly generating a read pulse signal and a write pulse signal with staggered timing, wherein the read pulse signal and the write pulse signal respectively comprise a plurality of read pulses and write pulses, and the same clock cycle at least comprises one read pulse and one write pulse; outputting port read-write control signals according to the control of the port enabling signals; and generating a word line control signal according to the input port read-write control signal, the read pulse signal and the write pulse signal.
In some embodiments of the present disclosure, in the read/write control method, the port enable signal includes: read-write enable signals and whether the same port is needed to realize read-then-write functional signals.
In some embodiments of the present disclosure, the control method is implemented based on any one of the read-write control modules 1 mentioned in the present disclosure, and the read-write control module 1 is software and/or hardware.
According to still another aspect of the present disclosure, a dual port memory is provided, which includes any one of the read-write control modules mentioned in the present disclosure.
(III) advantageous effects
According to the technical scheme, the read-write control module and method for the same port and the dual-port memory provided by the disclosure have the following beneficial effects:
1. the read-write control module for the same port can regulate and control the read timing and the write timing by configuring each stage of delay of the clockdelay generation module 11, so that the read-writepulse generation module 12 generates a read pulse signal and a write pulse signal with staggered timing, the port read-write control signal generated by the read-write controlsignal generation module 14 respectively controls the read pulse signal and the write pulse signal to be read or written, and the word line controlsignal generation module 13 generates a word line control signal. The read pulse signal comprises a plurality of read pulses which are periodically distributed in time, the write pulse signal comprises a plurality of write pulses which are periodically distributed in time, the number of the read pulses and the number of the write pulses in one period can be flexibly set according to actual read-write requirements, so that word line control signals in different modes can be generated, and read-write control in one period can be realized at the same port, for example, data can be read first and written later in one clock period without other ports or one period delay.
2. The dual-port memory can generate normal read word line control signals and write word line control signals by utilizing the read-write control signal generating module, the clock delay generating module, the read-write pulse generating module and the word line control signal generating module according to different port modes, and is compatible with the normal read-write mode of the memory. And the method can be compatible with the data operation of another port, and realizes the read-write operation of the two ports to the same address.
Drawings
Fig. 1 is a schematic diagram of a read/write control module for the same port according to an embodiment of the disclosure.
Fig. 2 is a schematic circuit diagram of a read/write control signal generation module according to an embodiment of the disclosure.
Fig. 3A is a schematic circuit diagram of a clock delay generation module according to an embodiment of the disclosure.
Fig. 3B is a schematic structural diagram of a delay module according to an embodiment of the disclosure.
FIG. 4 is a diagram of a read/write pulse generation module according to an embodiment of the disclosure.
FIG. 5 is a block diagram of a word line control signal generating module according to an embodiment of the disclosure.
Fig. 6 is a timing diagram illustrating a read function implemented by the read/write control module according to an embodiment of the disclosure.
FIG. 7 is a timing diagram illustrating a write function implemented by the read/write control module according to an embodiment of the disclosure.
Fig. 8 is a timing diagram illustrating a read-write control module implementing a read-then-write function of the same port according to an embodiment of the disclosure.
Fig. 9 is a flowchart of a read/write control method for the same port according to an embodiment of the disclosure.
[ notation ] to show
1-a read-write control module;
11-a clock delay generation module;
111-a first level delay module; 112-a second stage delay module;
113-third stage delay module; 114-a fourth stage delay block;
12-read-write pulse generation module;
121-read pulse generation module; 122-write pulse generation module;
13-word line control signal generation module;
131-a first nand gate; 132-a second nand gate;
133-a third nand gate;
14-read-write control signal generation module;
141-an inverter; 142-a buffer;
143-or gate;
clk represents a clock signal;
wren denotes a read/write enable signal;
the same port is used for realizing a read-then-write function signal or not;
write _ en represents a port write control signal;
read _ en represents a port read control signal;
in represents the input signal;
out represents the output signal;
r _ pulse represents a read pulse signal;
w _ pulse represents a write pulse signal;
word _ en represents a word line control signal;
d1, D2, D3, D4 represent clock signals with different delays;
d in the register represents a data input port, and Q represents a data output port; clk represents a clock signal input port; clr denotes a clear port.
Detailed Description
In the dual-port memory, the reading and writing of data of the same port of the dual-port memory can be selectively completed in one clock period at one port. Meanwhile, the read-write control module aiming at the same port can be compatible with the data operation of the other port, and the read-write operation of the two ports to the same address is realized. The dual-port memory can generate normal read word line control signals and write word line control signals by utilizing the read-write control signal generating module, the clock delay generating module, the read-write pulse generating module and the word line control signal generating module according to different port modes, and is compatible with the normal read-write mode of the memory.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
First embodiment
In a first exemplary embodiment of the present disclosure, a read-write control module for a same port is provided.
Fig. 1 is a schematic diagram of a read/write control module for the same port according to an embodiment of the disclosure.
Referring to fig. 1, a read/write control module 1 for a same port according to the present disclosure includes: a clockdelay generating module 11 for generating a read timing and a write timing; a read-writepulse generating module 12, configured to correspondingly generate a read pulse signal and a write pulse signal with staggered time sequences under the clock control of the read time sequence and the write time sequence, where the read pulse signal and the write pulse signal respectively include a plurality of read pulses and write pulses, and at least one read pulse and one write pulse are included in the same clock cycle; a read-write controlsignal generating module 14, configured to output a port read-write control signal according to control of a port enable signal (including a read-write enable signal of a memory port and a signal indicating whether a read-then-write function needs to be implemented on the same port); and a word line controlsignal generating module 13, configured to generate a word line control signal according to the input port read-write control signal, the read pulse signal, and the write pulse signal.
The following describes each constituent module of the read/write control module for the same port in this embodiment in detail with reference to the accompanying drawings.
Referring to fig. 1, an input end of aclock delay module 11 is used as a clock input end of the read-write control module 1, a clock signal clk is accessed, and an output end of theclock delay module 11 is connected to a clock input end of a read-writepulse generation module 12; the input end of the read/write controlsignal generation module 14 is used as the port enable signal (including wren and same _ port _ read) input end of the read/write control module; the output end of the read-write controlsignal generation module 14 and the output end of the read-writepulse generation module 12 are respectively connected to the control signal input end and the data input end of the word line controlsignal generation module 13, and the output end of the wordline control signal 13 is used as the signal output end of the read-write control module 1.
Fig. 2 is a schematic circuit diagram of a read/write control signal generation module according to an embodiment of the disclosure.
In this embodiment, the read-write controlsignal generating module 14 is configured to output the read-write control signal according to the read-write enable signal wren of the memory port and whether the same port needs to realize control of the read-then-write function signal same _ port _ read. Referring to fig. 2, the read/write controlsignal generating module 14 includes: the read-write control circuit comprises aninverter 141, an orgate 143 and abuffer 142, wherein a read-write enable signal wren is respectively connected to input ends of theinverter 141 and thebuffer 142, an output end of theinverter 141 is connected to one input end of the orgate 143, and whether a read-then-write function signal same _ port _ read needs to be input to the other input end of the orgate 143 through the same port or not is required, or an output end of the orgate 143 outputs a read control signal read _ en; the output port of the buffer outputs a write control signal write _ en.
For convenience of description, the read-write enable signal wren indicates the read-write enable of a port in the dual-port memory, for example, where wren is 1 indicates that the port performs a write operation, and where wren is 0 indicates that the port performs a read operation. A value of 1 for the same _ port _ read indicates that the old data needs to be read before the new data is written, and a value of 0 for the same _ port _ read indicates that this function is not required. Specifically, wren is connected to the input of theinverter 141, and the output of theinverter 141 is connected to one input of the orgate 142; while the same name _ port _ read is connected to the other input ofor-gate 143. The output of ORgate 143 is port read enable, 1 for read operations and 0 for no reads. While wren is connected to the input ofbuffer 142, the buffer output is port write enable, 1 for write operations and 0 for no writes.
Of course, the definition of the port may be different in other circuits, for example, where wren is 0 indicates that the port is performing a read operation, and where wren is 1(bit logic value) indicates that the port is performing a write operation.
Fig. 3A is a schematic circuit diagram of a clock delay generation module according to an embodiment of the disclosure. Fig. 3B is a schematic structural diagram of a delay module according to an embodiment of the disclosure.
In this embodiment, the clockdelay generating module 11 is configured to generate a read timing and a write timing. Referring to fig. 3A and 3B, the clockdelay generation module 11 includes four stages of delay modules with different delays, respectively: the delay circuit comprises a first-stage delay module 111, a second-stage delay module 112, a third-stage delay module 113 and a fourth-stage delay module 114, wherein the specific delay size of each stage of delay module is determined by the circuit timing design requirement. As shown in fig. 3A, the clock signal clk is connected to the input end of the firststage delay module 111, and the output end of the firststage delay module 111 is defined as D1; meanwhile, the output end D1 of the first-stage delay module 111 is connected to the input end of the second-stage delay module 112, and the output end of the second-stage delay module 112 is defined as D2; meanwhile, the output end D2 of the second-stage delay module 112 is connected to the input end of the third-stage delay module 113, and the output end of the third-stage delay module 113 is defined as D3; meanwhile, the output end D3 of the thirdstage delay module 113 is connected to the input end of the fourthstage delay module 114, and the output end of the fourthstage delay module 114 is defined as D4. It should be noted that D1, D2, D3 and D4 are used to represent the clock signals output by the clockdelay generation module 11 when fig. 6-8 are described below.
In an embodiment of the present disclosure, the four stages of delay modules have the same structure, and one of the delay modules is taken as an example, referring to fig. 3B, the first stage ofdelay module 111 includes several inverters, in this example, the number of inverter stages is an even number. Of course, in practical applications, the specific number of stages is determined by the design requirements. The input signal in is connected with the input end of the first-stage phase inverter, the output end of the first-stage phase inverter is connected with the input end of the second-stage phase inverter, and by analogy, the output end of the even-stage phase inverter is the output end of the first-stage delay module, and the required fixed delay is obtained.
It should be noted that the delay module in the present disclosure is only configured to meet the requirement of adjusting the read timing and the write timing, and is not limited to the structure including the inverter shown in this embodiment, and here, the typical structure is taken as an example, the delay chain formed by the inverters is only one form of generating the delay chain, and the delay chain may also be generated by using a metal or oxide resistor, etc.; similarly, the delay module may be of other types or structures, and is not limited to the chain structure in the example; of course, a fixed delay or an adjustable delay is also possible.
FIG. 4 is a diagram of a read/write pulse generation module according to an embodiment of the disclosure.
In this embodiment, the read-writepulse generating module 12 is configured to correspondingly generate a read pulse signal and a write pulse signal with staggered time sequences under the clock control of the read time sequence and the write time sequence output by theclock generating module 11, where the read pulse signal and the write pulse signal respectively include a plurality of read pulses and write pulses, and at least one read pulse and one write pulse are included in the same clock cycle.
Referring to fig. 4, the read/writepulse generation module 12 includes: the readpulse generating module 121 and the writepulse generating module 122, the readpulse generating module 121 and the writepulse generating module 122 are registers with zero clearing ends, and the readpulse generating module 121 and the writepulse generating module 122 are described below with theregister 121 generating a read pulse and theregister 122 generating a write pulse. In a specific example, the data input port D of theregister 121 generating the read pulse is connected to a fixed logic 1, the clock signal input port Clk of theregister 121 generating the read pulse is connected to the output terminal D1 of the first-stage delay module 111, the clear port clr of theregister 121 generating the read pulse is connected to the output terminal D2 of the second-stage delay module 112, and a read timing sequence is obtained under the clock control of the first-stage delay module 111 and the second-stage delay module 112, where the read timing sequence enables the data output port Q of theregister 121 generating the read pulse to output the read pulse signal r _ pulse. Similarly, the data input port D of theregister 122 generating the write pulse is connected to a fixed logic 1, the clock signal input port Clk of theregister 122 generating the write pulse is connected to the output terminal D3 of the third-stage delay module 113, the clear port clr of theregister 122 generating the write pulse is connected to the output terminal D4 of the fourth-stage delay module 114, and a write timing sequence is obtained under the clock control of the third-stage delay module 113 and the fourth-stage delay module 114, where the write timing sequence enables the data output port Q of theregister 122 generating the write pulse to output a write pulse signal w _ pulse.
FIG. 5 is a block diagram of a word line control signal generating module according to an embodiment of the disclosure.
In this embodiment, the word line controlsignal generating module 13 is configured to generate a word line control signal according to an input port read-write control signal, a read pulse signal, and a write pulse signal.
Referring to fig. 5, the word line controlsignal generating module 13 includes three nand gates, namely afirst nand gate 131, asecond nand gate 132 and athird nand gate 133. The input ends of thefirst nand gate 131 are respectively connected to the port read control signal read _ en and the read pulse signal r _ pulse. The input ends of thesecond nand gate 132 are respectively connected to the port write control signal write _ en and the write pulse signal w _ pulse. The outputs of thefirst nand-gate 131 and thesecond nand-gate 132 are both connected to the input of thethird nand-gate 133. The output terminal of thethird nand gate 133 serves as the output terminal of the word line controlsignal generating module 13, and outputs a word line control signal word _ en.
In this embodiment, the definition of each port is as follows:
1. read/write enable signal wren: when wren is a 1-bit logic value, the function of the memory port is write; its value is negated, indicating that the memory port function is read.
2. In the read-write pulse signals, when the write pulse signal w _ pulse is an lbit logic value, the word line of the memory is started, and the memory can perform write operation; the value is negated, which indicates that the word line of the memory is closed and the memory cannot perform write operation; when the read pulse signal r _ pulse is a 1-bit logic value, the word line of the memory is started, and the memory can perform read operation; the value is negated, indicating that the memory word line is off and the memory cannot be read.
3. When the word line control signal word _ en is a 1-bit logic value, the word line is opened, and the memory can be normally read and written; the value is negated, indicating that the memory cannot be read or written.
4. In the port read-write control signals, when the port write control signal write _ en is a 1-bit logic value, the memory port is indicated to be in write operation; the value is negated, and the port of the memory is represented as a non-write operation; when the port reading control signal read _ en is a 1-bit logic value, the port reading control signal read _ en indicates that the port of the memory is in reading operation; its value is negated, indicating that the memory port is not read.
It is emphasized again that the above embodiments are for better illustration of the module functionality, the definition of the memory ports is taken as an example, and different circuit implementations may be used if the port definitions are different.
Second embodiment
In a second exemplary embodiment of the present disclosure, a dual port memory is provided, which includes a read-write control module of the present disclosure for a same port.
In this embodiment, based on the read-write control module 1 of the first embodiment, a dual port memory including the read-write control module 1 is provided.
According to the port definition in the embodiment, the port functions of the dual port memory including the read/write control module for the same port in the present disclosure are divided into the following three types: read function, write function, and read-first-write-to-port function (in one clock cycle).
The function of a dual port memory including a read/write control block for the same port is described below with reference to fig. 6-8. In fig. 6-8, clk represents a clock signal, D1, D2, D3 and D4 represent clock signals output by the clockdelay generation module 11, r _ pulse represents a read pulse signal output by the read-writepulse generation module 12, w _ pulse represents a write pulse signal output by the read-writepulse generation module 12, read _ en represents a port read control signal output by the read-write controlsignal generation module 14, write _ en represents a port write control signal output by the read-write controlsignal generation module 14, and word _ en represents a word line control signal output by the word linecontrol generation module 13.
Fig. 6 is a timing diagram illustrating a read function implemented by the read/write control module according to an embodiment of the disclosure.
Referring to fig. 6, in the read/write control module in this embodiment, wren of the port enable signal is 0, and same _ port _ read is 0; the port read control signal read _ en generated by the read-write controlsignal generation module 14 is 1, and the port write control signal write _ en is 0. The clock signal clk passes through the clockdelay generation module 11 to generate clock signals with different delays D1 to D4, and the clock signals D1 to D4 pass through the read/writepulse generation module 12 to generate read/write pulse signals. The read-write pulse signal and the port read-write control signal respectively generate a word line control signal word _ en in the word line controlsignal generation module 13, so that the read-write control module 1 realizes a read function, which is the same as the read function of a normal memory.
FIG. 7 is a timing diagram illustrating a write function implemented by the read/write control module according to an embodiment of the disclosure.
Referring to fig. 7, in the read/write control module in this embodiment, wren of the port enable signal is 1, and same _ port _ read is 0; the port read control signal read _ en generated by the read-write controlsignal generation module 14 is 0, and the port write control signal write _ en is 1. The clock signal clk passes through the clockdelay generation module 11 to generate clock signals with different delays D1 to D4, and the clock signals D1 to D4 pass through the read/writepulse generation module 12 to generate read/write pulse signals. The read-write pulse signal and the port read-write control signal respectively generate a word line control signal word _ en in the word line controlsignal generation module 13, so that the read-write control module 1 realizes a write function, which is the same as the write function of a normal memory.
Fig. 8 is a timing diagram illustrating a read-write control module implementing a read-then-write function of the same port according to an embodiment of the disclosure.
Referring to fig. 8, in the read/write control module in this embodiment, wren of the port enable signal is 1, and same _ port _ read is 1; the port read control signal read _ en generated by the read-write controlsignal generation module 14 is 1, and the port write control signal write _ en is 1. The clock signal clk passes through the clockdelay generation module 11 to generate clock signals with different delays D1 to D4, and the clock signals D1 to D4 pass through the read/writepulse generation module 12 to generate read/write pulse signals. The read-write pulse signal and the port read-write control signal respectively generate a word line control signal word _ en in the word line controlsignal generation module 13, so that the read-write control module 1 realizes the read-first and write-later functions in one clock cycle.
In summary, the read/write control module for the same port can regulate and control the read timing and the write timing by configuring each stage of delay of the clockdelay generation module 11, so that the read/writepulse generation module 12 generates the read pulse signal and the write pulse signal with staggered timing, and the port read/write control signal generated by the read/write controlsignal generation module 14 respectively controls reading or writing of the read pulse signal and the write pulse signal, thereby generating the word line control signal at the word line controlsignal generation module 13. The read pulse signal comprises a plurality of read pulses which are periodically distributed in time, the write pulse signal comprises a plurality of write pulses which are periodically distributed in time, and the number of the read pulses and the number of the write pulses in one period can be flexibly set according to actual read-write requirements.
The dual-port memory can generate normal read word line control signals and write word line control signals by utilizing the read-write control signal generating module, the clock delay generating module, the read-write pulse generating module and the word line control signal generating module according to different port modes, and is compatible with the normal read-write mode of the memory. And the method can be compatible with the data operation of another port, and realizes the read-write operation of the two ports to the same address.
Furthermore, the above definitions of the various elements and methods are not limited to the particular structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by one of ordinary skill in the art, for example:
(1) the delay module adopted in the present disclosure functions to satisfy the adjustment of the read timing and the write timing, and the specific structure and constituent elements are not limited to the embodiments. Meanwhile, the adoption of the phase inverter to form the delay chain is only one form of generating the delay chain, and the delay chain can also be generated by using metal or oxide resistors and the like.
(2) The nand gate and the or gate used in the present disclosure are not limited to the circuit of the design selector, and may take other forms.
(3) The circuit adopted by the present disclosure is based on a circuit schematic diagram designed under the above port definition, and different circuit implementation manners may be adopted if the port definition is different, and of course, the register with the clear end is only to satisfy the clear function under the above port definition, and if the port definition is different, the register with the clear end may be replaced by another register with the clear end, and only the pulse clear function needs to be realized.
(4) The constituent structures of the respective modules in the embodiments are only examples, and software and/or hardware that can realize the corresponding functions are within the scope of the present disclosure.
Third embodiment
In a third exemplary embodiment of the present disclosure, a read-write control method for the same port is provided.
Fig. 9 is a flowchart of a read/write control method for the same port according to an embodiment of the disclosure.
Referring to fig. 9, the read/write control method for the same port of the present disclosure includes:
step S31: generating a read timing and a write timing;
in this embodiment, a read timing and a write timing are generated based on the clockdelay generation block 11 in the first embodiment.
Of course, other ways of generating the timing may be possible.
Step S32: under the clock control of the read timing and the write timing, correspondingly generating a read pulse signal and a write pulse signal with staggered timing, wherein the read pulse signal and the write pulse signal respectively comprise a plurality of read pulses and write pulses, and the same clock cycle at least comprises one read pulse and one write pulse;
in this embodiment, the read/write pulse signal with a staggered timing sequence is generated based on the read/writepulse generation module 12 in the first embodiment.
Of course, the read/write pulse signals with staggered timing can be generated by other structures or types of circuits.
Step S33: outputting port read-write control signals according to the control of the port enabling signals;
in this embodiment, the function of step S33 is implemented based on the read/write controlsignal generating module 14 in the first embodiment, where the port enable signal includes: read-write enable signals and whether the same port is needed to realize read-then-write functional signals.
Step S34: generating a word line control signal according to the input port read-write control signal, the read pulse signal and the write pulse signal;
in the present embodiment, the function of step S34 is realized based on the word line controlsignal generation block 13 in the first embodiment.
Of course, any form capable of implementing the above method is within the scope of the present disclosure.
In summary, the present disclosure provides a read-write control module and method for a same port, and a dual port memory, which can generate a normal read word line control signal and a write word line control signal by using a read-write control signal generation module, a clock delay generation module, a read-write pulse generation module, and a word line control signal generation module, and is compatible with a normal read-write mode of a memory, and implement reading and writing of data of the same port in one clock cycle, and has the advantages of simple structure, convenient and efficient regulation and control, and high real-time performance of data, thereby avoiding complex design of hardware due to different physical ports; meanwhile, the data operation of a certain port in the dual-port memory of the read-write control module can be compatible with the data operation of the other port, so that the read-write operation of the two ports to the same address is realized.
It should be noted that the use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element, nor do they represent the order of an element and another element, or the order of fabrication methods, and are used merely to distinguish one element having a certain name from another element having a same name.
Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
Those skilled in the art will appreciate that the modules of the embodiments may be combined into one module and further that they may be divided into multiple sub-modules. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or device so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (9)
1. A read-write control module (1) for the same port, characterized in that it comprises:
a clock delay generating module (11) for generating a read timing and a write timing;
a read-write pulse generating module (12) for correspondingly generating a read pulse signal and a write pulse signal with staggered time sequences under the clock control of the read time sequence and the write time sequence, wherein the read pulse signal and the write pulse signal respectively comprise a plurality of read pulses and write pulses, and at least one read pulse and one write pulse are contained in the same clock cycle;
the read-write control signal generation module (14) is used for outputting port read-write control signals according to the control of the port enable signals; and
the word line control signal generating module (13) is used for generating a word line control signal according to an input port read-write control signal, a read pulse signal and a write pulse signal;
the read-write pulse generation module (12) comprises a read pulse generation module (121) and a write pulse generation module (122), wherein the read pulse generation module (121) is a first register with a zero clearing function, and the write pulse generation module (122) is a second register with the zero clearing function; the clock delay generation module (11) comprises delay modules with different four-stage delay sizes, a clock signal input port and a zero clearing port of the first register are respectively connected with the two stages of the delay modules, and a clock signal input port and a zero clearing port of the second register are respectively connected with the other two stages of the delay modules.
2. Read-write control module (1) according to claim 1, characterized in that said port enable signal comprises:
a read-write enable signal (wren) and whether a read-before-write function signal (same _ port _ read) needs to be implemented with the same port.
3. The read-write control module (1) according to claim 2, wherein the read-write control signal generating module (14) comprises: an inverter (141), an OR gate (143), and a buffer (142);
the read-write enable signal (wren) is respectively connected to the input ends of the inverter (141) and the buffer (142), the output end of the inverter (141) is connected to one input end of the or gate (143), and whether a read-then-write function signal (same _ port _ read) needs to be input to the other input end of the or gate (143) through the same port or not is realized, or the output end of the or gate (143) outputs a read control signal (read _ en); the output port of the buffer outputs a write control signal (write _ en).
4. The read-write control module (1) according to claim 1, wherein the word line control signal generation module (13) comprises three nand gates, a first nand gate (131), a second nand gate (132) and a third nand gate (133); the port read-write control signal comprises a port read control signal and a port write control signal;
the input end of the first NAND gate (131) is respectively connected with a port reading control signal (read _ en) and a reading pulse signal (r _ pulse); the input end of the second NAND gate (132) is respectively connected with a port writing control signal (write _ en) and a writing pulse signal (w _ pulse); the output ends of the first NAND gate (131) and the second NAND gate (132) are connected to the input end of the third NAND gate (133); the output end of the third NAND gate (133) is used as the output end of the word line control signal generation module (13) to output a word line control signal (word _ en).
5. The read-write control module (1) according to claim 1, characterized in that the delay module is a fixed delay module or an adjustable delay module.
6. Read-write control module (1) according to any of claims 1 to 5, characterized in that the read-write control module (1) is software and/or hardware.
7. A read-write control method for the same port implemented on the basis of the read-write control module (1) of any one of claims 1 to 6, comprising:
generating a read timing and a write timing;
under the clock control of the read timing and the write timing, correspondingly generating a read pulse signal and a write pulse signal with staggered timing, wherein the read pulse signal and the write pulse signal respectively comprise a plurality of read pulses and write pulses, and the same clock cycle at least comprises one read pulse and one write pulse;
outputting port read-write control signals according to the control of the port enabling signals; and
and generating a word line control signal according to the input port read-write control signal, the read pulse signal and the write pulse signal.
8. The read-write control method according to claim 7, wherein the port enable signal includes:
read-write enable signals and whether the same port is needed to realize read-then-write functional signals.
9. A dual port memory comprising the read-write control module of any one of claims 1 to 6.
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| CN112767977B (en)* | 2020-12-31 | 2023-09-26 | 深圳市紫光同创电子有限公司 | Read and write window calibration circuit and method, memory, FPGA chip |
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