技术领域technical field
本发明属于集成电路技术领域，具体涉及一种过流保护电路模块。The invention belongs to the technical field of integrated circuits, and in particular relates to an overcurrent protection circuit module.
背景技术Background technique
电源作为一切电子产品的供电设备，除了性能要满足供电产品的要求外，其自身的保护措施也非常重要，如过压、过流、过热保护等。一旦电子产品出现故障时，如电子产品输入侧短路或输出侧过流或短路时，电源则必须关闭其输出电压，才能保护功率MOSFET和输出装设备等不被烧毁，否则可能引起电子产品的进一步损坏，甚至引起操作人员的触电及火灾等现象。因此，电源的过流保护功能一定要完善。现有技术的主要缺点：As the power supply equipment of all electronic products, the power supply must not only meet the requirements of the power supply products, but also its own protection measures are also very important, such as overvoltage, overcurrent, overheating protection, etc. Once the electronic product fails, such as the input side of the electronic product is short-circuited or the output side is overcurrent or short-circuited, the power supply must turn off its output voltage to protect the power MOSFET and output equipment from being burned, otherwise it may cause further damage to the electronic product. damage, and even cause electric shock and fire of the operator. Therefore, the overcurrent protection function of the power supply must be perfected. The main disadvantages of the existing technology:
（1）需要单独供电，电源的变压器需增加一组辅助绕组，导致变压器的体积增大。(1) A separate power supply is required, and a set of auxiliary windings needs to be added to the transformer of the power supply, resulting in an increase in the volume of the transformer.
（2）使用的元器件多，电路复杂，一般采用打嗝模式保护，其过流保护时间不能任意设定。(2) There are many components used and the circuit is complex. Generally, hiccup mode protection is adopted, and the overcurrent protection time cannot be set arbitrarily.
因此，亟需一种解决电源的过流保护问题，电路简单，保护时间可自由设定的过流保护电路模块。Therefore, there is an urgent need for an overcurrent protection circuit module that solves the problem of overcurrent protection of the power supply, has a simple circuit, and can freely set the protection time.
发明内容SUMMARY OF THE INVENTION
为解决现有技术存在的缺陷，本发明提供一种过流保护电路模块。In order to solve the defects existing in the prior art, the present invention provides an overcurrent protection circuit module.
为了解决上述技术问题，本发明提供了如下的技术方案：In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:
本发明一种过流保护电路模块，电流采样电路和过流保护延迟电路，电流采样电路包括采样电路、基准电路和比较器，采样电路、基准电路的输出端与比较器的输入端电连接，采样电路用于侦测电路中电流的大小，比较器将采样值与基准值进行比较，在采样值大于基准值时发出过流信号给过流保护延迟电路；过流保护延迟电路包括过流保护时间设置单元和过流回路MOS管控制单元，用于控制过流回路中的MOS管及保护时间。The present invention provides an overcurrent protection circuit module, a current sampling circuit and an overcurrent protection delay circuit, the current sampling circuit comprises a sampling circuit, a reference circuit and a comparator, the output ends of the sampling circuit and the reference circuit are electrically connected with the input end of the comparator, The sampling circuit is used to detect the magnitude of the current in the circuit, the comparator compares the sampling value with the reference value, and sends an overcurrent signal to the overcurrent protection delay circuit when the sampling value is greater than the reference value; the overcurrent protection delay circuit includes overcurrent protection The time setting unit and the overcurrent loop MOS tube control unit are used to control the MOS tube and the protection time in the overcurrent loop.
作为本发明的一种优选技术方案，电流采样电路具体包括第一电容C1、第二电容C2、比较器U1、第一MOS管Q1、第一电阻R1、第二电阻R2和第三电阻R3，第一电容C1的一端与V+相连，第一电容C1的另一端接地；比较器U1的1脚与第一电阻R1的一端、第二电阻R2的一端、第二电容C2的一端相连，第一电阻R1的另一端与V+相连，第二电阻R2的另一端接地，第二电容C2的另一端与第三电阻R3的一端、比较器U1的3脚、第一MOS管Q1的3脚相连，第三电阻R3的另一端接地；比较器U1的2脚接地；比较器U1的4脚与第二MOS管Q2的1脚相连；比较器U1的5脚与V+相连；As a preferred technical solution of the present invention, the current sampling circuit specifically includes a first capacitor C1, a second capacitor C2, a comparator U1, a first MOS transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3, One end of the first capacitor C1 is connected to V+, and the other end of the first capacitor C1 is grounded; the 1 pin of the comparator U1 is connected to one end of the first resistor R1, one end of the second resistor R2, and one end of the second capacitor C2. The other end of the resistor R1 is connected to V+, the other end of the second resistor R2 is grounded, and the other end of the second capacitor C2 is connected to one end of the third resistor R3, the 3-pin of the comparator U1, and the 3-pin of the first MOS transistor Q1, The other end of the third resistor R3 is grounded; the 2-pin of the comparator U1 is grounded; the 4-pin of the comparator U1 is connected to the 1-pin of the second MOS transistor Q2; the 5-pin of the comparator U1 is connected to V+;
过流保护延迟电路具体包括计时器U2、第二MOS管Q2、第四电阻R4，计时器U2的1脚与V+相连，计时器U2的2脚、4脚和6脚接地，计时器U2的3脚与第四电阻R4的一端、第二MOS管Q2的2脚相连，第四电阻R4的另一端接地，第二MOS管Q2的3脚与V+相连；计时器U2的5脚与第一MOS管Q1的1脚相连，第一MOS管Q1的3脚与第三电阻R3相连，第一MOS管Q1的2脚与负载相连，负载的另一端与V+相连。The overcurrent protection delay circuit specifically includes a timer U2, a second MOS transistor Q2, and a fourth resistor R4. The 1 pin of the timer U2 is connected to V+, the 2 pins, 4 pins and 6 pins of the timer U2 are grounded, and the timer U2 pin is connected to the ground. Pin 3 is connected to one end of the fourth resistor R4 and pin 2 of the second MOS transistor Q2, the other end of the fourth resistor R4 is grounded, and the 3 pin of the second MOS transistor Q2 is connected to V+; the 5 pin of the timer U2 is connected to the first Pin 1 of the MOS transistor Q1 is connected, pin 3 of the first MOS transistor Q1 is connected to the third resistor R3, pin 2 of the first MOS transistor Q1 is connected to the load, and the other end of the load is connected to V+.
作为本发明的一种优选技术方案，比较器U1采用TLV1701比较器。As a preferred technical solution of the present invention, the comparator U1 adopts a TLV1701 comparator.
作为本发明的一种优选技术方案，计时器U2采用TPL5110-Q1计时器。As a preferred technical solution of the present invention, the timer U2 adopts a TPL5110-Q1 timer.
作为本发明的一种优选技术方案，第一MOS管Q1为N型MOS管，第一MOS管Q1的1脚为栅极，第一MOS管Q1的2脚为漏极，第一MOS管Q1的3脚为源极。As a preferred technical solution of the present invention, the first MOS transistor Q1 is an N-type MOS transistor, the 1 pin of the first MOS transistor Q1 is the gate, the 2 pin of the first MOS transistor Q1 is the drain, and the first MOS transistor Q1 The 3 feet are the source.
作为本发明的一种优选技术方案，第二MOS管Q2为P型MOS管，第二MOS管Q2的1脚为栅极，第二MOS管Q2的2脚为漏极，第二MOS管Q2的3脚为源极。As a preferred technical solution of the present invention, the second MOS transistor Q2 is a P-type MOS transistor, the 1 pin of the second MOS transistor Q2 is the gate, the 2 pin of the second MOS transistor Q2 is the drain, and the second MOS transistor Q2 The 3 feet are the source.
本发明的有益效果是：本发明解决电源的过流、短路等问题，该电路简单，保护时间可自由设定，不需增加辅助电路等优点，提高了电源电路的安全性及稳定性。The beneficial effects of the present invention are: the present invention solves the problems of overcurrent and short circuit of the power supply, the circuit is simple, the protection time can be set freely, the auxiliary circuit does not need to be added, and the safety and stability of the power supply circuit are improved.
附图说明Description of drawings
图1是本发明提供的一种过流保护电路模块的原理图。FIG. 1 is a schematic diagram of an overcurrent protection circuit module provided by the present invention.
图2是本发明提供的一种过流保护电路模块中TLV1701比较器的功能框图；2 is a functional block diagram of a TLV1701 comparator in an overcurrent protection circuit module provided by the present invention;
图3是本发明提供的一种过流保护电路模块中TPL5110-Q1计时器的时序图。FIG. 3 is a timing diagram of a TPL5110-Q1 timer in an overcurrent protection circuit module provided by the present invention.
图4是本发明提供的一种过流保护电路模块的工作流程图。FIG. 4 is a working flow chart of an overcurrent protection circuit module provided by the present invention.
具体实施方式Detailed ways
以下结合附图对本发明的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, but not to limit the present invention.
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“相连”为电连接，应做广义理解。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。In the description of the present invention, it should be noted that, unless otherwise expressly specified and limited, the term "connected" refers to electrical connection, which should be understood in a broad sense. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.
为了达到本发明的目的，如图1至图4所示，在本发明的其中一种实施方式中提供一种过流保护电路模块，电流采样电路和过流保护延迟电路，电流采样电路包括采样电路、基准电路和比较器，采样电路、基准电路的输出端与比较器的输入端电连接，采样电路用于侦测电路中电流的大小，比较器将采样值与基准值进行比较，在采样值大于基准值时发出过流信号给过流保护延迟电路；过流保护延迟电路包括过流保护时间设置单元和过流回路MOS管控制单元，用于控制过流回路中的MOS管及保护时间。In order to achieve the purpose of the present invention, as shown in FIGS. 1 to 4 , an overcurrent protection circuit module, a current sampling circuit and an overcurrent protection delay circuit are provided in one of the embodiments of the present invention, and the current sampling circuit includes a sampling A circuit, a reference circuit and a comparator. The output end of the sampling circuit and the reference circuit are electrically connected to the input end of the comparator. The sampling circuit is used to detect the magnitude of the current in the circuit. The comparator compares the sampled value with the reference value. When the value is greater than the reference value, an overcurrent signal is sent to the overcurrent protection delay circuit; the overcurrent protection delay circuit includes an overcurrent protection time setting unit and an overcurrent loop MOS tube control unit, which are used to control the MOS tube and the protection time in the overcurrent loop. .
为了进一步地优化本发明的实施效果，在本发明的另一种实施方式中，在前述内容的基础上，电流采样电路具体包括第一电容C1、第二电容C2、比较器U1、第一MOS管Q1、第一电阻R1、第二电阻R2和第三电阻R3，第一电容C1的一端与V+相连，第一电容C1的另一端接地；比较器U1的1脚与第一电阻R1的一端、第二电阻R2的一端、第二电容C2的一端相连，第一电阻R1的另一端与V+相连，第二电阻R2的另一端接地，第二电容C2的另一端与第三电阻R3的一端、比较器U1的3脚、第一MOS管Q1的3脚相连，第三电阻R3的另一端接地；比较器U1的2脚接地；比较器U1的4脚与第二MOS管Q2的1脚相连；比较器U1的5脚与V+相连。In order to further optimize the implementation effect of the present invention, in another embodiment of the present invention, on the basis of the foregoing content, the current sampling circuit specifically includes a first capacitor C1, a second capacitor C2, a comparator U1, a first MOS Tube Q1, first resistor R1, second resistor R2 and third resistor R3, one end of the first capacitor C1 is connected to V+, and the other end of the first capacitor C1 is grounded; the 1 pin of the comparator U1 is connected to one end of the first resistor R1 , One end of the second resistor R2 is connected to one end of the second capacitor C2, the other end of the first resistor R1 is connected to V+, the other end of the second resistor R2 is grounded, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 , The 3-pin of the comparator U1 and the 3-pin of the first MOS transistor Q1 are connected, and the other end of the third resistor R3 is grounded; the 2-pin of the comparator U1 is grounded; the 4-pin of the comparator U1 is connected with the 1-pin of the second MOS transistor Q2 Connected; pin 5 of comparator U1 is connected to V+.
电流采样电路的工作原理如下：The working principle of the current sampling circuit is as follows:
电路回路中的电流就第三电阻R3进行采样，采样电压值与第一电阻R1、第二电阻R2分压值进行比较，当回路中的电流值大于设定值时，比较器U1的3脚电压大于1脚的电压，此时比较器U1的4脚输出低电平，从而控制第二MOS管Q2导通，通过计时器U2控制第一MOS管Q1的导通，从而起到过流保护作用。The current in the circuit loop is sampled by the third resistor R3, and the sampled voltage value is compared with the voltage division value of the first resistor R1 and the second resistor R2. When the current value in the loop is greater than the set value, the comparator U1 pin 3 The voltage is greater than the voltage of pin 1. At this time, pin 4 of the comparator U1 outputs a low level, so as to control the conduction of the second MOS transistor Q2, and control the conduction of the first MOS transistor Q1 through the timer U2, thereby achieving overcurrent protection. effect.
另外，过流保护延迟电路具体包括计时器U2、第二MOS管Q2、第四电阻R4，计时器U2的1脚与V+相连，计时器U2的2脚、4脚和6脚接地，计时器U2的3脚与第四电阻R4的一端、第二MOS管Q2的2脚相连，第四电阻R4的另一端接地，第二MOS管Q2的3脚与V+相连；计时器U2的5脚与第一MOS管Q1的1脚相连，第一MOS管Q1的3脚与第三电阻R3相连，第一MOS管Q1的2脚与负载相连，负载的另一端与V+相连。In addition, the overcurrent protection delay circuit specifically includes a timer U2, a second MOS transistor Q2, a fourth resistor R4, the 1 pin of the timer U2 is connected to V+, the 2 pins, 4 pins and 6 pins of the timer U2 are grounded, and the timer U2 pins are grounded. Pin 3 of U2 is connected to one end of the fourth resistor R4 and pin 2 of the second MOS transistor Q2, the other end of the fourth resistor R4 is grounded, and pin 3 of the second MOS transistor Q2 is connected to V+; pin 5 of the timer U2 is connected to Pin 1 of the first MOS transistor Q1 is connected, pin 3 of the first MOS transistor Q1 is connected to the third resistor R3, pin 2 of the first MOS transistor Q1 is connected to the load, and the other end of the load is connected to V+.
过流保护延迟电路的工作原理如下：The working principle of the overcurrent protection delay circuit is as follows:
计时器U2设定为单触发模式，当电路过流时，比较器U1的4脚给出低电平，第二MOS管Q2导通，计时器U2的3脚为高电平，此时计时器U2的5脚为低电平，第一MOS管Q1关断，经过设定的保护时间后，计时器U2的5脚恢复高电平，第一MOS管Q1导通，保护消除，计时器U2的5脚控制第一MOS管Q1的通断，第一MOS管Q1的关断时间即为延迟时间，保护时间由第四电阻R4的值决定。The timer U2 is set to one-shot mode. When the circuit is overcurrent, the 4-pin of the comparator U1 gives a low level, the second MOS transistor Q2 is turned on, and the 3-pin of the timer U2 is a high level, and the timing is at this time. The 5 pin of the timer U2 is low level, the first MOS transistor Q1 is turned off, after the set protection time, the 5 pin of the timer U2 returns to a high level, the first MOS transistor Q1 is turned on, the protection is eliminated, the timer Pin 5 of U2 controls the on-off of the first MOS transistor Q1, the off time of the first MOS transistor Q1 is the delay time, and the protection time is determined by the value of the fourth resistor R4.
具体地，比较器U1采用TLV1701比较器。Specifically, the comparator U1 adopts the TLV1701 comparator.
具体地，计时器U2采用TPL5110-Q1计时器。Specifically, the timer U2 adopts the TPL5110-Q1 timer.
具体地，第一MOS管Q1为N型MOS管，第一MOS管Q1的1脚为栅极，第一MOS管Q1的2脚为漏极，第一MOS管Q1的3脚为源极。Specifically, the first MOS transistor Q1 is an N-type MOS transistor, the 1 pin of the first MOS transistor Q1 is the gate, the 2 pin of the first MOS transistor Q1 is the drain, and the 3 pin of the first MOS transistor Q1 is the source.
具体地，第二MOS管Q2为P型MOS管，第二MOS管Q2的1脚为栅极，第二MOS管Q2的2脚为漏极，第二MOS管Q2的3脚为源极。Specifically, the second MOS transistor Q2 is a P-type MOS transistor, the 1 pin of the second MOS transistor Q2 is the gate, the 2 pin of the second MOS transistor Q2 is the drain, and the 3 pin of the second MOS transistor Q2 is the source.
如图4所示，下面对本实施方式的整体工作流程作进一步说明，具体包括以下步骤：As shown in Figure 4, the overall workflow of this embodiment is further described below, which specifically includes the following steps:
S1、开始；S1, start;
S2、电流采样，采样电路侦测电路中电流的大小；S2, current sampling, the sampling circuit detects the size of the current in the circuit;
S3、判断是否过流，比较器U1将采样值与基准值进行比较，若采样值大于基准值，发出过流信号给计时器U2，若采样值不大于基准值，则返回步骤S2；S3. Determine whether there is overcurrent. The comparator U1 compares the sampled value with the reference value. If the sampled value is greater than the reference value, an overcurrent signal is sent to the timer U2. If the sampled value is not greater than the reference value, return to step S2;
S4、计时器U2触发定时信号，第一MOS管S1关断；S4. The timer U2 triggers the timing signal, and the first MOS transistor S1 is turned off;
S5、经过计时器U2设定的保护时间后，计时器U2的5脚恢复高电平，第一MOS管Q1导通，保护结束，进入步骤S2继续进行电流采样。S5. After the protection time set by the timer U2, pin 5 of the timer U2 returns to a high level, the first MOS transistor Q1 is turned on, the protection ends, and the process proceeds to step S2 to continue current sampling.
最后应说明的是：以上所述仅为本发明的优选实施例而已，并不用于限制本发明，尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。Finally, it should be noted that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, the The technical solutions described in the foregoing embodiments may be modified, or some technical features thereof may be equivalently replaced. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910463792.9ACN110061484B (en) | 2019-05-30 | 2019-05-30 | Overcurrent protection circuit module |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910463792.9ACN110061484B (en) | 2019-05-30 | 2019-05-30 | Overcurrent protection circuit module |
| Publication Number | Publication Date |
|---|---|
| CN110061484Atrue CN110061484A (en) | 2019-07-26 |
| CN110061484B CN110061484B (en) | 2024-10-22 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910463792.9AActiveCN110061484B (en) | 2019-05-30 | 2019-05-30 | Overcurrent protection circuit module |
| Country | Link |
|---|---|
| CN (1) | CN110061484B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111007310A (en)* | 2019-12-26 | 2020-04-14 | 上海贝岭股份有限公司 | Intelligent Internet of things chip and current detection circuit thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110199062A1 (en)* | 2007-08-20 | 2011-08-18 | Austriamicrosystems Ag | DC/DC Converter Arrangement and Method for DC/DC Conversion |
| CN202172253U (en)* | 2011-05-27 | 2012-03-21 | 唐山松下产业机器有限公司 | Peak current detection and protection circuit |
| JP2017046570A (en)* | 2015-08-27 | 2017-03-02 | ローム株式会社 | Overcurrent protection device, electronic equipment, integrated circuit, and signal transmission circuit |
| CN208316285U (en)* | 2018-06-06 | 2019-01-01 | 深圳华德电子有限公司 | A kind of current foldback circuit of Switching Power Supply |
| CN209692346U (en)* | 2019-05-30 | 2019-11-26 | 中国电子科技集团公司第五十八研究所 | A kind of over-current protection circuit module |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110199062A1 (en)* | 2007-08-20 | 2011-08-18 | Austriamicrosystems Ag | DC/DC Converter Arrangement and Method for DC/DC Conversion |
| CN202172253U (en)* | 2011-05-27 | 2012-03-21 | 唐山松下产业机器有限公司 | Peak current detection and protection circuit |
| JP2017046570A (en)* | 2015-08-27 | 2017-03-02 | ローム株式会社 | Overcurrent protection device, electronic equipment, integrated circuit, and signal transmission circuit |
| CN208316285U (en)* | 2018-06-06 | 2019-01-01 | 深圳华德电子有限公司 | A kind of current foldback circuit of Switching Power Supply |
| CN209692346U (en)* | 2019-05-30 | 2019-11-26 | 中国电子科技集团公司第五十八研究所 | A kind of over-current protection circuit module |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111007310A (en)* | 2019-12-26 | 2020-04-14 | 上海贝岭股份有限公司 | Intelligent Internet of things chip and current detection circuit thereof |
| Publication number | Publication date |
|---|---|
| CN110061484B (en) | 2024-10-22 |
| Publication | Publication Date | Title |
|---|---|---|
| CN201383668Y (en) | Overcurrent protection circuit and motor controller applying same | |
| CN100561813C (en) | Suppression method of hot-swapping inrush current in post-stage circuit and its buffered asynchronous start-up circuit | |
| CN201846066U (en) | A kind of undervoltage protection circuit with hysteresis function | |
| CN101436771B (en) | Power supply under-voltage protection circuit and power supply containing the same | |
| CN103683206B (en) | Input over-and under-voltage protection circuit and method with high voltage startup | |
| CN203180783U (en) | Boosted circuit | |
| CN105281422A (en) | Method and circuit for automatically switching off power supply switch | |
| CN210898523U (en) | An airborne anti-surge active clamp protection circuit | |
| CN204886147U (en) | An Overcurrent Protection Circuit with Adjustable Intermittent Time | |
| WO2019019505A1 (en) | CIRCUIT STRUCTURE FOR REMOVING AN OVERVOLTAGE CURRENT | |
| CN104218531A (en) | Short circuit protecting circuit and method | |
| CN101651332A (en) | Power protection circuit preventing controlled silicon effect | |
| CN209692346U (en) | A kind of over-current protection circuit module | |
| CN205453082U (en) | Anti latch circuit based on current detection | |
| CN101309004A (en) | An overcurrent protection circuit | |
| CN100561816C (en) | Surge current suppression circuit and power supply device using same | |
| CN110061484A (en) | A kind of over-current protection circuit module | |
| CN203166499U (en) | IGBT overvoltage protection circuit of electromagnetic oven | |
| CN207304369U (en) | High-reliability power source circuit for Beidou communication base station | |
| CN103692058B (en) | With the soft-start circuit of power factor correction circuit inverter type welder | |
| CN107645180B (en) | A kind of low starting current power-supply circuit for cable monitoring | |
| CN205960624U (en) | Switch power -supply overvoltage protecting circuit | |
| CN108963999B (en) | Surge current suppressor | |
| CN209608555U (en) | DC power supply with dual-path overvoltage protection | |
| CN205489489U (en) | A drive circuit for servo controller |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |