CN110047833B - Memory, working method and forming method thereof - Google Patents

Abstract

A memory, method of operation and method of forming thereof, wherein the memory comprises: a first well region in the substrate, the first well region having first dopant ions therein; the second well region is positioned on the top surface of the first well region, and is provided with second doped ions, and the conductivity type of the second doped ions is opposite to that of the first doped ions; a gate structure on a surface of the second well region, the gate structure including opposing first and second sides; a first doped region in the second well region on the first side of the gate structure, the first doped region having a third dopant ion therein, the third dopant ion having a conductivity type opposite to a conductivity type of the second dopant ion; and a source line electrically connected to the second well region. The energy consumption of the memory is low.

Description

Memory, working method and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a memory, a working method thereof, and a forming method thereof.

Background

With the development of information technology, the amount of stored information has increased dramatically. The increase in the amount of information stored has prompted the rapid development of memory, while also placing higher demands on the performance of memory.

Because static memory (SRAM) can store data stored therein without requiring refresh circuitry, power consumption is small, making SRAM applications more and more widespread. A conventional SRAM memory cell is generally composed of six MOS transistors or four MOS transistors, and the number of MOS transistors in the memory cell is large, resulting in a large size of the MOS transistors. In order to reduce the volume of the memory and improve the integration level, a single transistor static memory (1T SRAM) is proposed.

However, existing single transistor static memories are relatively power consuming.

Disclosure of Invention

The invention solves the problem of providing a memory, a working method and a forming method thereof, which can reduce the energy consumption of the memory.

In order to solve the above problems, the present invention provides a memory comprising: a substrate; a first well region in the substrate, the first well region having first dopant ions therein; the second well region is positioned on the top surface of the first well region, and is provided with second doped ions, and the conductivity type of the second doped ions is opposite to that of the first doped ions; a gate structure on a surface of the second well region, the gate structure including opposing first and second sides; a first doped region in the second well region on the first side of the gate structure, the first doped region having a third dopant ion therein, the third dopant ion having a conductivity type opposite to a conductivity type of the second dopant ion; a word line electrically connected to the gate structure; a bit line electrically connected to the first doped region; and a source line electrically connected to the second well region.

Optionally, the first doped ion is an N-type ion, the second doped ion is a P-type ion, and the third doped ion is an N-type ion; or the first doping ion is a P-type ion, the second doping ion is an N-type ion, and the third doping ion is a P-type ion.

Optionally, the memory includes a plurality of memory units, the memory units including: the first well region, the second well region, the gate structure, and the first doped region.

Optionally, the plurality of memory cells are arranged as a memory array; the grid structures of the memory cells in the same row in the memory array are electrically connected with each other through the same word line; the first doped regions of the memory cells in the same column in the memory array are electrically connected with each other through the same bit line; the second doped regions of the memory cells of the same row in the memory array are electrically connected to each other through the same source line.

Optionally, the method further comprises: the second doped region is positioned in the second well region at the second side of the grid structure, fourth doped ions are arranged in the second doped region, the fourth doped ions have the same conductive type as the second doped ions, and the concentration of the fourth doped ions in the second doped region is larger than that of the second doped ions in the second well region; the source line is electrically connected with the second doped region.

Optionally, the method further comprises: the first dielectric layer covers the grid structure, the second doped region and the first doped region; the first plug penetrates through the first dielectric layer and is in contact with the first doped region, and the bit line is located on the surfaces of the first dielectric layer and the first plug; the second dielectric layer is positioned on the surfaces of the bit line and the first dielectric layer; a second plug penetrating from the first dielectric layer to the second dielectric layer, the second plug being in contact with the second doped region; the source line is positioned on the surfaces of the second plug and the second dielectric layer.

Correspondingly, the invention also provides a working method of the memory, which comprises the following steps: providing a memory; applying a first potential to the first well region to reverse bias a PN junction between the first well region and the second well region; performing a write operation to the memory, the method of the write operation comprising: applying a second potential to the bit line to enable the voltage between the first doped region and the second well region to be a first voltage; applying a third potential to the word line to enable the voltage between the gate structure and the second well region to be a second voltage, wherein the second voltage is the same as the first voltage in positive and negative; after the write operation, performing a read operation on the memory, the method of the read operation comprising: applying a first read potential to the bit line; applying a second read potential to the source line, the first and second read potentials forward biasing a PN junction between the first doped region and the second well region; after a first reading potential is applied to the bit line and a second reading potential is applied to the source line, reading data is acquired through a reading current in the bit line.

Optionally, the first doped ions are N-type ions, and the first potential is greater than the potential of the second well region; or the first doped ions are P-type ions, and the first potential is smaller than the potential of the second well region.

Optionally, the method of writing operation further includes: suspending the source line or applying a fourth potential to the source line, wherein the fourth potential is zero potential; when the first doping ions are N-type ions, the first potential is 1.8V-2.2V; the second potential is 0.7V-0.9V, and the third potential is 0.7V-0.9V; alternatively, the second potential is-0.55V to-0.45V, and the third potential is-0.55V to-0.45V.

Optionally, the memory includes a plurality of memory units, the memory units including: the first well region, the second well region, the gate structure and the first doped region; the plurality of memory cells are arranged into a memory array; the grid structures of the memory cells in the same row in the memory array are electrically connected with each other through the same word line; the first doped regions of the memory cells in the same column in the memory array are electrically connected with each other through the same bit line; the second doped regions of the memory cells in the same row in the memory array are electrically connected with each other through the same source line; the word lines comprise a first word line and a second word line, and the first word line is connected with a memory cell for writing operation; the bit line comprises a first bit line and a second bit line, and the first bit line is connected with a memory cell for writing operation; the method for applying the second potential to the bit line comprises the following steps: applying a second potential to the first bit line; the method of applying a third potential to the word line includes: applying a third potential to the first word line; the method of writing operation further comprises: applying zero potential to the second bit line or suspending the second bit line; applying zero potential to the second word line or suspending the second word line.

Optionally, the first doped ion is an N-type ion, and the first reading potential is smaller than the second reading potential; or the first doped ions are P-type ions, and the first reading potential is greater than the second reading potential.

Optionally, the first doped ion is an N-type ion; writing data "1" when the first voltage is greater than zero and the second voltage is greater than zero; or the first doping ions are P-type ions; writing data "1" when the first voltage is less than zero and the second voltage is less than zero; the method for acquiring the read data comprises the following steps: when the read current is greater than a preset current, the read data is "1"; when the read current is less than a preset current, the read data is "0".

Optionally, the first doped ion is an N-type ion; the method of the read operation further includes: applying zero potential to the word line or suspending the word line; the first reading potential is-0.8V to-0.7V; the second read potential is zero potential.

Optionally, the memory includes a plurality of memory units, the memory units including: the first well region, the second well region, the gate structure and the first doped region; the plurality of memory cells are arranged into a memory array; the grid structures of the memory cells in the same row in the memory array are electrically connected with each other through the same word line, the first doped regions of the memory cells in the same column in the memory array are electrically connected with each other through the same bit line, and the second doped regions of the memory cells in the same row are electrically connected with each other through the same source line; the source line comprises a first source line and a second source line, and the first source line is connected with a memory cell for reading operation; the bit line comprises a third bit line and a fourth bit line, and the third bit line is connected with a memory cell for reading operation; the method of applying a first read potential to the bit line includes: applying a first read potential to the third bit line; the method for applying the second reading potential to the source line comprises the following steps: applying a second read potential to the first source line, the second read potential and the first read potential forward biasing a PN junction between the second well region and the first doped region; the method of the read operation further includes: suspending the fourth bit line; and suspending the second source line.

The technical scheme of the invention also provides a method for forming the memory, which comprises the following steps: providing a substrate; forming a first well region in the substrate, wherein the first well region is provided with first doping ions; forming a second well region on the top surface of the first well region, wherein second doped ions are arranged in the second well region, and the second doped ions have opposite conductivity types with the first doped ions; forming a gate structure on the surface of the second well region, and forming a first doped region in the second well region, wherein the gate structure comprises a first side and a second side which are opposite, the first doped region is positioned in the second well region on the first side of the gate structure, and third doped ions are arranged in the first doped region and have opposite conductivity types with the second doped ions; forming a word line electrically connected to the gate structure; forming a bit line electrically connected to the first doped region; and forming a source line electrically connected with the second well region.

Optionally, after forming the gate structure, forming the first doped region; the method of forming the first doped region further comprises: forming a first mask layer covering a second well region on the second side of the gate structure; and performing first source-drain ion implantation on the second side second well region by taking the first mask layer and the grid structure as masks, and implanting third doping ions in the second well region, wherein the conductivity types of the third doping ions are opposite to those of the second doping ions.

Optionally, the method further comprises: and forming a second doped region in the second well region, wherein the second doped region is positioned on the second side of the gate structure, fourth doped ions are arranged in the second doped region, the fourth doped ions have the same conductivity type as the second doped ions, and the concentration of the fourth doped ions in the second doped region is larger than that of the second doped ions in the second well region.

Optionally, after forming the gate structure, forming the second doped region; the method for forming the second doped region comprises the following steps: forming a second mask layer covering the second well region on the first side of the gate structure; and performing second source-drain ion implantation on the second well region by taking the second mask layer and the grid electrode structure as masks, and implanting fourth doping ions in the second well region, wherein the conductivity types of the fourth doping ions are the same as that of the second doping ions.

Optionally, before forming the bit line, the method further includes: forming a first dielectric layer covering the gate structure, the second doped region and the first doped region; forming a first plug in the first dielectric layer, wherein the first plug penetrates through the first dielectric layer and is in contact with the first doped region; the bit line is positioned on the first dielectric layer and the first plug surface; after forming the bit line, further comprising: forming a second dielectric layer on the bit line and the surface of the first dielectric layer; forming a second plug penetrating from the first dielectric layer to the second dielectric layer, wherein the second plug is in contact with the second doped region; the bit line is positioned on the surfaces of the second plug and the second dielectric layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the memory provided by the technical scheme of the invention, the word line can apply potential to the grid structure; a potential can be applied to the first doped region through the bit line such that a charge can be injected into the second well region through the gate structure and the potential on the first doped region, or such that the charge in the second well region is released, thereby enabling the memory to store data "1" and "0". The memory includes a source line electrically connected to the second well region, and a potential can be applied to the second well region by applying a potential to the source line. Since the second doped ions and the third doped ions have opposite conductive types, the second well region and the first doped region form a diode, and different potentials are applied to the bit line and the source line, so that the diode formed by the second well region and the first doped region is conducted forward, and a current is formed in the bit line. The data stored in the memory can be read according to the current in the bit line. Because the diode formed by the second well region and the first doped region is conducted forward in the process of reading the data in the memory, the voltage drop of the forward conduction of the diode is small, so that the energy consumption of the memory is low.

Further, the memory includes: the second doped region is positioned in the second well region at the second side of the gate structure; and the source line is electrically connected with the second well region through the second plug and the second doped region. Because the concentration of the fourth doping ions in the second doping region is greater than that of the second doping ions in the second well region, ohmic contact is easy to form between the second plug and the second doping region, so that the contact resistance between the second plug and the second doping region can be reduced, and the energy consumption of the formed memory is reduced.

In the working method of the memory provided by the technical scheme of the invention, the second voltage is the same as the first voltage in positive and negative, the inversion layer is formed by inversion of the second well region at the bottom of the grid structure, and the PN junction between the first doped region and the second well region is reversely biased; or the bottom inversion layer of the gate structure disappears, and the PN junction between the first doped region and the second well region is forward biased. When the second well region at the bottom of the gate structure is in inversion form to form an inversion layer, and a PN junction between the first doped region and the second well region is reversely biased, injecting charges into the second well region at the bottom of the inversion layer; and when the inversion layer at the bottom of the gate structure disappears and the PN junction between the first doped region and the second well region is forward biased, releasing charges in the second well region. Therefore, the memory can represent different storage states by whether charges are injected into the second well region or not, and further can store data of 1 and 0, so that a storage function is realized.

During the reading operation, the PN junction between the first doped region and the second well region is forward biased by the first reading potential and the second reading potential, so that the diode formed by the first doped region and the second well region is conducted, and the reading current is generated in the bit line. When charges are injected into the second well region in the writing operation process and an inversion layer is formed in the second well region below the gate structure, the inversion layer, the first doped region and the second well region form a diode in the reading operation process, and the inversion layer can increase the contact area of a P-type region and an N-type region in the diode, so that the reading current is larger; conversely, the read current is smaller when the second well region is caused to discharge charge during a write operation. Therefore, the data stored in the memory can be read by the magnitude of the read current. In addition, in the process of reading the data in the memory, the diode formed by the second well region and the first doped region is conducted in the forward direction, so that the read data is obtained. The voltage drop of the forward conduction of the diode is small, so that the energy consumption of the memory is small.

Drawings

FIG. 1 is a schematic diagram of a structure of a single transistor static memory;

FIGS. 2 and 3 are schematic diagrams of the structure of an embodiment of the memory of the present invention;

FIGS. 4-7 are schematic diagrams illustrating steps of an embodiment of a method for operating a memory according to the present invention;

FIG. 8 is a graph of read current versus read voltage during a read operation of the memory of the present invention;

fig. 9 to 13 are schematic structural diagrams illustrating steps in an embodiment of a method for forming a memory according to the present invention.

Detailed Description

There are a number of problems with storage, for example: the memory has higher energy consumption and poorer performance.

The reason why the energy consumption of the single transistor static memory is high is analyzed by combining the single transistor static memory:

fig. 1 is a schematic diagram of a structure of a single transistor static memory.

Referring to fig. 1, the memory includes a plurality of memory cells, the memory cells include: asubstrate 10, an n-well 13 and a p-well 14 in thesubstrate 10, the p-well 14 and the n-well 13 being arranged in a direction perpendicular to a surface of thesubstrate 10; a gate structure 15 located on the surface of the p-well 14; a word line WL connected to the gate structure 15; the source region 11 and thedrain region 12 are positioned at two sides of the gate structure 15, and the source region 11 and thedrain region 12 are n-type ion doped regions; a source line SL connected to the second doped region; bit line BL connected to thedrain region 12; and a well line DNWL connected with the n-well.

The method for reading the memory comprises the following steps: applying a positive potential on the word line WL; applying a positive or negative potential on the bit line BL; applying a zero potential on the source line; measuring the current in the bit line BL to obtain a read current; and acquiring the data stored in the memory cell according to the read current. Since a positive potential is applied to the word line WL, a channel at the bottom of the gate structure is turned on, thereby turning on the source region 11 and thedrain region 12, and when the source line SL is different from the bit line BL, a read current is generated at the bit line BL. According to the magnitude of the read current, the data stored in the memory cell can be acquired.

However, since the memory needs to have the channel under the gate structure 15 turned on during the reading process, the voltage value on the gate structure 15 is greater than the threshold voltage of the transistor formed by the gate structure 15, the source region 11 and the first doped region 11, resulting in a larger power consumption of the memory.

In order to solve the technical problem, the present invention provides a memory, including: a gate structure on a surface of the second well region, the gate structure including opposing first and second sides; a first doped region in the second well region on the first side of the gate structure, the first doped region having a third dopant ion therein, the third dopant ion having a conductivity type opposite to a conductivity type of the second dopant ion; and a source line electrically connected to the second well region. The energy consumption of the memory is low.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 2 and 3 are schematic structural diagrams of an embodiment of a memory according to the present invention.

Referring to fig. 2 and 3, fig. 2 is a cross-sectional view of thearea 10 along 21-22 in fig. 3. This embodiment provides a memory, comprising: asubstrate 200; afirst well region 211 in thesubstrate 200, thefirst well region 211 having first dopant ions therein; asecond well region 212 located on the top surface of thefirst well region 211, wherein thesecond well region 212 has second doped ions therein, and the second doped ions have a conductivity type opposite to that of the first doped ions; agate structure 201 on a surface of thesecond well region 212, thegate structure 201 including opposite first and second sides; a firstdoped region 202 located in thesecond well region 212 on the first side of thegate structure 201, wherein the firstdoped region 202 has a third doped ion therein, and the conductivity type of the third doped ion is opposite to the conductivity type of the second doped ion; a word line WL electrically connected to thegate structure 201; a bit line BL electrically connected to the firstdoped region 202; and a source line SL electrically connected to thesecond well region 212.

A potential can be applied to thegate structure 201 through the word line WL; a potential can be applied to the firstdoped region 202 through the bit line BL, thereby enabling charge injection into thesecond well region 212 through thegate structure 201 and the potential on the firstdoped region 202, or releasing the charge in thesecond well region 212, thereby enabling the memory to store data "1" and "0". The memory includes a source line SL electrically connected to thesecond well region 212, and thus, a potential can be applied to thesecond well region 212 by applying a potential to the source line SL. Since the second doped ions and the third doped ions have opposite conductivity types, thesecond well region 212 and the firstdoped region 202 form a diode, and a current can be formed in the bit line BL by applying different potentials to the bit line BL and the source line SL to forward-turn on the diode formed by thesecond well region 212 and the firstdoped region 202. The data stored in the memory can be read according to the current in the bit line BL. Since the diode formed by thesecond well region 212 and the firstdoped region 202 is turned on in the forward direction during the process of reading the data in the memory, the voltage drop of the forward direction conduction of the diode is small, so that the energy consumption of the memory is low.

Thesubstrate 200 includes: a plurality of memory cell regions and isolation regions between adjacent memory cell regions.

The memory cell area is used for forming a memory cell; the isolation region is used for realizing electrical isolation between adjacent memory cell regions.

The memory includes a plurality of memory cells respectively located in the memory cell areas, the memory cells including: thefirst well region 211, thesecond well region 212, thegate structure 201, and the firstdoped region 202.

In this embodiment, the memory further includes: a seconddoped region 203 in thesecond well region 212 on the second side of thegate structure 202, wherein the seconddoped region 203 has fourth doped ions therein, the fourth doped ions have the same conductivity type as the second doped ions, and the concentration of the fourth doped ions in the seconddoped region 203 is greater than the concentration of the second doped ions in thesecond well region 212; the source line SL is electrically connected to the seconddoped region 203.

The memory further includes: a first dielectric layer (not shown) covering thegate structure 201, the seconddoped region 203 and the firstdoped region 202; a first plug (not shown) in the first dielectric layer, the first plug penetrating the first dielectric layer and contacting the firstdoped region 202, the bit line BL being located on the first dielectric layer and the first plug surface; the second dielectric layer is positioned on the surfaces of the bit line BL and the first dielectric layer; a second plug penetrating from the first dielectric layer to the second dielectric layer, the second plug being in contact with the seconddoped region 203; the source line SL is positioned on the surfaces of the second plug and the second dielectric layer; and the gate plugs are positioned in the first dielectric layer and the second dielectric layer, the gate plugs are in contact with the gate structure, and the word lines WL are positioned on the surfaces of the gate plugs and the second dielectric layer.

The word line WL is connected to the gate plug; the bit line BL is connected with the first plug; the source line SL is connected to the second plug.

The word line WL is used to apply a potential to thegate structure 201 through the gate plug; the bit line BL is used for applying a potential to the firstdoped region 202 through the first plug; the source line SL is used to apply a potential to the seconddoped region 203 through a second plug.

The memory includes a seconddoped region 203 located in asecond well region 212 on a second side of thegate structure 201; the source line SL is electrically connected to thesecond well region 212 through the second plug and the seconddoped region 203. Since the concentration of the fourth doping ions in the seconddoped region 203 is greater than the concentration of the second doping ions in thesecond well region 212, ohmic contact is easily formed between the second plug and the seconddoped region 203, so that the contact resistance between the second plug and the seconddoped region 203 can be reduced, and the energy consumption of the formed memory can be reduced.

The second plug, the first plug and the gate plug are made of tungsten, aluminum or copper.

In this embodiment, thegate structure 201 spans across a plurality of memory cell regions along the extending direction of thegate structure 201, so that thegate structures 201 of a plurality of memory cells along the extending direction of thegate structure 201 are connected to each other.

The plurality of memory cells are arranged into a memory array; thegate structures 201 of the memory cells in the same row in the memory array are electrically connected to each other through the same word line WL; the firstdoped regions 202 of the memory cells in the same column in the memory array are electrically connected to each other through the same bit line BL; the seconddoped regions 203 of the memory cells in the same row in the memory array are electrically connected to each other by the same source line SL.

The well line DNWL is used to supply power to the memory cell, thereby preventing the data stored in the memory from disappearing; the combination of the bit line BL and the word line WL is used for selecting a memory cell for writing; the combination of the bit line BL and the source line SL is used to select a memory cell for a read operation.

By controlling the potential across thegate structure 201 and thesecond well region 212, it is possible to inject charges into thesecond well region 212 at the bottom of thegate structure 201 or to discharge charges in thesecond well region 212. Thus, the memory may represent different memory states by whether charges are injected in thesecond well region 212, thereby storing data "1" and "0".

The potential of thefirst well region 211 is used to reverse bias the PN junction formed by thesecond well region 212 and thefirst well region 211, thereby reducing the discharge of charges in thesecond well region 212 through thefirst well region 211 and preventing the stored data from disappearing.

In this embodiment, the first doped ion is an N-type ion, the second doped ion is a P-type ion, the third doped ion is an N-type ion, and the fourth doped ion is a P-type ion. In other embodiments, the first dopant ion is a P-type ion, the second dopant ion is an N-type ion, the third dopant ion is a P-type ion, and the fourth dopant ion is an N-type ion.

In this embodiment, when holes are injected into thesecond well region 212, the stored data of the memory cell is "1"; when thesecond well region 212 does not have holes injected therein, the stored data of the memory cell is "0". In other embodiments, the first doped ion is an N-type ion, and when holes are injected into the second well region, the stored data of the memory cell is "0"; when the second well region does not have holes injected therein, the stored data of the memory cell is "1". Or the first doped ions are P-type ions, when electrons are injected into the second well region, the stored data of the storage unit is 0, and when no injected electrons are in the second well region, the stored data of the storage unit is 1; or the first doped ions are P-type ions, when electrons are injected into the second well region, the stored data of the memory cell is 1, and when no injected electrons are in the second well region, the stored data of the memory cell is 0.

In this embodiment, the principle of writing data "1" to the memory cell includes: making a voltage between a word line WL and a source line SL connected to a memory cell performing a write operation greater than zero; the voltage on the bit line BL and the source line SL connecting the memory cells for writing operation is made larger than zero. The potential of the word line WL connected to the memory cell not performing the write operation is equal to the potential of the source line SL, and the potential of the bit line BL connected to the memory cell not performing the write operation is equal to the potential of the source line SL. In this embodiment, if the potentials of the source lines SL are the same, the word lines WL and the bit lines BL can uniquely identify the memory cells to be written. When the voltage between the word line WL and the source line SL connected to the memory cell performing the writing operation is greater than zero, thesecond well region 212 at the bottom of thegate structure 201 is inversion-formed into an inversion layer, and holes are injected into thesecond well region 212 at the bottom of the inversion layer. Since the voltage between the bit line BL and the source line SL connected to the memory cell performing the writing operation is greater than zero, the PN junction between the firstdoped region 202 and thesecond well region 212 of the memory cell is reverse biased, and since the PN junction formed by thefirst well region 211 and thesecond well region 212 is reverse biased, holes injected in thesecond well region 212 are confined in thesecond well region 212, thereby writing data "1" in the memory cell.

The process of writing data "0" into the memory cell is a process of releasing the hollow in thesecond well region 212, and is the same as the process of erasing data "1" in the memory cell. Specifically, the principle of writing data "0" to a memory cell includes: making the voltage between the word line WL and the source line SL connecting the memory cells performing the write operation smaller than zero; the voltage between the bit line BL and the source line SL connected to the memory cell performing the write operation is made smaller than zero. The voltage between the word line WL and the source line SL connecting the memory cells that do not perform the write operation is equal to zero; the voltage between the bit line BL and the source line SL connecting the memory cells which do not perform the write operation is equal to zero. The source line SL is applied with the same potential or is suspended. The memory cell to which "0" is written can be uniquely determined by the word line WL and the bit line BL. When the voltage between the word line WL and the source line SL of the memory cell connected for writing operation is less than zero, the inversion layer at the bottom of thegate structure 201 disappears, and the thickness of thesecond well region 212 increases. Since the voltage between the bit line BL and the source line SL connected to the memory cell for writing is smaller than zero, the PN junction between the firstdoped region 202 and thesecond well region 212 of the memory cell is forward biased, and electrons in the firstdoped region 202 are injected into thesecond well region 212. Because the thickness of thesecond well region 212 is larger, electrons injected into thesecond well region 212 are not easy to diffuse into thefirst well region 211, and therefore electrons injected into thesecond well region 212 are easy to recombine with holes in thesecond well region 212, so that the concentration of holes in thesecond well region 212 is reduced, and the memory cell writes data "0".

The reading process of the memory comprises the following steps: by applying a potential to the bit line BL and the source line SL connected to the memory cell performing the read operation, the PN junction between thesecond well region 212 and the firstdoped region 202 is forward biased even though the potential on the bit line BL is smaller than the potential on the source line SL; the bit line BL and the source line SL connecting the memory cells which do not perform the write operation are floating. The memory cell performing a read operation can be uniquely determined by the source line SL and the bit line BL. The potential on the bit line BL is smaller than the potential on the source line SL, so that the PN junction between thesecond well region 212 and the firstdoped region 202 is forward biased, and the bit line BL and the source line SL are turned on, thereby generating a read current in the bit line BL, and the data stored in the memory cell can be acquired according to the read current.

If the data stored in the memory cell is "1", the concentration of holes in thesecond well region 212 of the memory cell is higher and the concentration of electrons in the inversion layer is higher, the conductivity type of the inversion layer is N-type. The inversion layer, the firstdoped region 202 and thesecond well region 212 form a diode, and the inversion layer and the firstdoped region 202 are in contact with thesecond well region 212, so that the PN junction area of the diode is increased; in addition, the concentration of holes in thesecond well region 212 is high, and the width of the PN junction depletion layer of the diode is small. In summary, when the data stored in the memory cell is "1", the read current is larger; conversely, if the data stored in the memory cell is "0", the read current is small. Therefore, by analyzing the read current, the data stored in the memory cell can be read.

Similarly, in other embodiments, the first dopant ions are P-type ions; the second doping ions are N-type ions; the third doped ion is a P-type ion.

When electrons are injected into the second well region, the data stored by the storage unit is 1; when no injected electrons exist in the second well region, the data stored in the memory cell is "0".

The principle of writing data "1" to a memory cell includes: making the voltage between the word line and the source line connected to the memory cell for writing operation smaller than zero; the voltage between the bit line and the source line connecting the memory cells for writing operation is made smaller than zero. The voltage between the word line and the source line connecting the memory cells that do not perform a write operation is equal to zero, and the voltage between the bit line and the source line connecting the memory cells that do not perform a write operation is equal to zero. The same potential is applied to all source lines or all source lines are floating. The memory cells to be written to can be uniquely determined by the word lines and bit lines. And when the voltage between the word line and the source line of the memory cell connected for writing is smaller than zero, the second well region at the bottom of the gate structure is in inversion form into an inversion layer, and electrons are injected into the second well region at the bottom of the inversion layer. Since the voltage between the bit line and the source line connected with the memory cell is smaller than zero, the PN junction between the first doped region and the second well region of the memory cell is reversely biased, and since the PN junction formed by the first well region and the second well region is reversely biased, electrons injected in the second well region are limited in the second well region, so that data '1' is written in the memory cell.

The process of writing data "0" into the memory cell is a process of releasing electrons in the second well region, and is the same as the process of erasing data "1" in the memory cell. Specifically, the principle of writing data "0" to a memory cell includes: making the voltage between the word line and the source line connected to the memory cell for writing operation greater than zero; the voltage between the bit line and the source line connecting the memory cells for writing is made greater than zero. The same potential is applied to all source lines or all source lines are floating. The memory cells to be written to can be uniquely determined by the word lines and bit lines. When the voltage between the word line and the source line connected to the memory cell performing the writing operation is greater than zero, the inversion layer at the bottom of the gate structure disappears, and the thickness of the second well region increases. Since the voltage between the bit line and the source line connected to the memory cell for writing operation is greater than zero, the PN junction between the first doped region and the second well region of the memory cell is forward biased, and holes in the first doped region are injected into the second well region. And because the thickness of the second well region is larger, holes injected into the second well region are not easy to diffuse into the first well region, so that the holes injected into the second well region are easy to recombine with electrons in the second well region, the concentration of electrons in the second well region is reduced, and the memory unit writes data '0'.

The reading process of the memory comprises the following steps: applying a potential to a bit line and a source line connected to a memory cell for a read operation to forward bias a PN junction between the second well region and the first doped region even if the potential on the bit line is greater than the potential on the source line; the bit line and source line connecting the memory cells that do not perform a write operation are floating. The memory cell to be read can be uniquely determined by the source line and the bit line. And if the potential on the bit line is greater than the potential on the source line, the junction between the second well region and the first doped region is forward biased, and the bit line and the source line are conducted, so that a reading current is generated in the bit line, and the data stored in the memory cell can be acquired according to the reading current.

The first doped ions are P-type ions, and when electrons are injected into the second well region in the writing process, the storage data of the storage unit is 1. If the data stored in the memory cell is "1", the concentration of electrons in the second well region of the memory cell is higher and the concentration of holes in the inversion layer is higher, the conductivity type of the inversion layer being P-type. The inversion layer, the first doping region and the second well region form a diode, and the inversion layer and the first doping region are in contact with the second well region, so that the PN junction area of the diode is increased; in addition, the electron concentration in the second well region is higher, and the width of the PN junction depletion layer of the diode is smaller. In summary, when the data stored in the memory cell is "1", the read current is larger; conversely, if the data stored in the memory cell is "0", the read current is small. Therefore, by analyzing the read current, the data stored in the memory cell can be read.

In this embodiment, thesubstrate 200 is a planar substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. In other embodiments, the substrate may further include a base and a fin on the base; the gate structure spans the fin, and covers part of the side wall and the top surface of the fin; the second well region is located in the fin, and the first well region is located in one or a combination of the fin and the substrate.

Thegate structure 201 includes: the gate dielectric layer is positioned on the surface of thesecond well region 212; the grid electrode is positioned on the grid dielectric layer; and the side wall is positioned on the surface of the side wall of the grid electrode.

In this embodiment, the gate dielectric layer is made of silicon oxide. The gate is made of polysilicon, polycrystalline germanium or polycrystalline silicon germanium.

In other embodiments, the gate dielectric layer material may be a high-k dielectric material. The grid electrode is made of metal.

In this embodiment, the material of the side wall is silicon nitride.

The memory cell further includes: anisolation well region 231 located in the isolation region, wherein theisolation well region 231 has isolation ions therein, and the isolation ions have a conductivity type opposite to that of the second doped ions;isolation structures 230 in thesubstrate 200 between the isolation well regions and the memory cell region secondwell region 212.

Theisolation structure 230 is made of silicon oxide, silicon nitride or silicon oxynitride.

Theisolation well region 231 and theisolation structure 230 are used to achieve electrical isolation between the secondwell regions 212 of adjacent memory cell regions a.

The embodiment of the invention also provides a working method of the memory.

Referring to fig. 4, a memory is provided.

The memory in this embodiment is the same as the memory shown in fig. 2 and 3 in the previous embodiment, and will not be described here again.

With continued reference to FIG. 4, thefirst well region 211 is connected to a first potential V₀₁ The first potential V₀₁ The PN junction between thefirst well region 211 and thesecond well region 212 is reverse biased.

The first potential V₀₁ The PN junction between thefirst well region 211 and thesecond well region 212 is reverse biased, so that the charge release in thesecond well region 212 can be prevented, thereby reducing the leakage current.

Specifically, in this embodiment, by making the followingThe well line DNWL is connected with a first potential V₀₁ Thereby connecting thefirst well region 211 to a first potential V₀₁ 。

In this embodiment, the first doped ion is an N-type ion. In other embodiments, the first dopant ions are P-type ions.

In this embodiment, the first potential V₀₁ For reverse biasing the PN junction between thefirst well region 211 and thesecond well region 212, the first potential V₀₁ Greater than the potential of thesecond well region 212. In other embodiments, the first doped ion is a P-type ion, and the first potential is less than the potential of the second well region.

If the first potential V₀₁ Too small a potential difference with thesecond well region 212 is disadvantageous for maintaining the PN junction reverse bias between thefirst well region 211 and thesecond well region 212; if the first potential V₀₁ Too small a potential difference with thesecond well region 212 tends to increase the power consumption of the memory. Specifically, in this embodiment, the first potential V₀₁ The potential difference with thesecond well region 212 is too small to be 1.8V to 2.2V, for example, 2V. In this embodiment, in the subsequent write operation and read operation, the source line SL is connected to zero potential, or the source line SL is suspended, the first potential V₀₁ 1.8V to 2.2V, for example, 2V.

Referring to fig. 5 and 6 in combination, a write operation is performed on the memory, and a method of the write operation includes: applying a second potential V to the firstdoped region 202₀₂ The second potential V₀₂ Making the voltage between thegate structure 201 and thesecond well region 212 be the first voltage; applying a third potential V to thegate structure 201₀₃ The third potential V₀₃ The voltage between the firstdoped region 203 and thesecond well region 212 is made to be a second voltage, which is the same as the positive and negative of the first voltage.

The write operation includes: a write data "1" operation and a write data "0" operation.

When the second voltage is the same as the first voltage, thesecond well region 212 at the bottom of thegate structure 201 is inverted to form an inversion layer, and the PN junction between the firstdoped region 202 and thesecond well region 212 is reverse biased; or the inversion layer at the bottom of thegate structure 201 disappears and the PN junction between the firstdoped region 202 and thesecond well region 212 is forward biased. When thesecond well region 212 at the bottom of thegate structure 201 is inverted and the PN junction between the firstdoped region 202 and thesecond well region 212 is reverse biased, charges are injected into thesecond well region 212 at the bottom; when the bottom inversion layer of thegate structure 201 disappears and the PN junction between the firstdoped region 202 and thesecond well region 212 is forward biased, the charge in thesecond well region 212 is released. Thus, the memory may represent different memory states by whether charges are injected in thesecond well region 212, thereby storing data "1" and "0".

Specifically, in this embodiment, when holes are injected into thesecond well region 212, the stored data of the memory cell is "1"; when thesecond well region 212 does not have holes injected therein, the stored data of the memory cell is "0".

In other embodiments, the first doped ion is an N-type ion, and when holes are injected into the second well region, the stored data of the memory cell is "0"; when the second well region does not have holes injected therein, the stored data of the memory cell is "1". Or the first doped ions are P-type ions, and when electrons are injected into the second well region, the stored data of the memory unit is 1; when the second well region does not have injected electrons therein, the stored data of the memory cell is "0". Or the first doped ions are P-type ions, and when electrons are injected into the second well region, the stored data of the memory unit is 0; when the second well region does not have injected electrons therein, the stored data of the memory cell is "1".

The method of writing operation further comprises: applying a fourth potential V to the source line SL₀₄ Or the source line SL is suspended.

In this embodiment, the fourth potential V₀₄ At zero potential or the source line SL is suspended. Specifically, the present embodimentIn an example, the fourth potential V₀₄ Is at zero potential. Applying zero potential to the source line SL can stabilize the potential on the source line SL, thereby reducing interference of noise. And the fourth potential is zero potential, which can reduce energy consumption.

In this embodiment, the fourth potential V₀₄ At zero potential, or floating the source line SL, the second potential V during the reading operation₀₂ And a third potential V₀₃ Is the same as positive and negative.

In this embodiment, the principle of writing the data "1" into the memory cell is the same as that of the previous embodiment, and will not be described herein.

In this embodiment, the first doped ion is an N-type ion. When writing data "1", the second potential V₀₂ Greater than the potential on the source line SL; the third potential V₀₃ Is larger than the potential on the source line SL. Specifically, when writing data "1", the potential of the source line SL is zero potential 0, the second potential V₀₂ Greater than 0, the third potential V₀₃ Greater than 0.

In this embodiment, the first doped ion is an N-type ion. When writing data "0", the second potential V₀₂ Less than the potential on the source line SL; the third potential V₀₃ Less than the potential on the source line SL. Specifically, the potential of the source line SL is zero potential 0; when writing data "0", the second potential V₀₂ Less than 0, the third potential V₀₃ Less than 0.

In other embodiments, the potential on the source line is a non-zero value.

The plurality of memory cells are arranged in a memory array; thegate structures 201 of the memory cells in the same row in the memory array are electrically connected to each other through the same word line WL; the firstdoped regions 202 of the memory cells in the same column in the memory array are electrically connected to each other through the same bit line BL; the seconddoped regions 203 of the memory cells in the same row in the memory array are electrically connected to each other by the same source line SL.

Applying a fourth to the source line SLPotential V₀₄ The method of (1) comprises: applying a fourth potential V to the source lines SL of all memory cells₀₄ The method comprises the steps of carrying out a first treatment on the surface of the The method for suspending the source line SL comprises the following steps: the source lines SL of all memory cells are floating.

The word lines comprise a first word line and a second word line, and the first word line is connected with a memory cell for writing operation; the bit lines include a first bit line and a second bit line, the first bit line connecting memory cells for a write operation.

When writing one or more memory cells, a second potential V is applied to the bit line BL₀₂ The method of (1) comprises: applying a second potential V to the first bit line₀₂ The method comprises the steps of carrying out a first treatment on the surface of the Applying a third potential V to the word line WL₀₃ The method of (1) comprises: applying a third potential V to the first word line₀₃ 。

The method of writing operation further comprises: applying zero potential 0 to the second bit line or suspending the second bit line; applying a zero potential 0 to the second word line or floating the second word line.

Since thegate structures 201 of the memory cells in the same row in the memory array are electrically connected to each other by the same word line WL, thegate structures 201 of the memory cells in the same column are electrically insulated; the firstdoped regions 202 of the memory cells in the same column in the memory array are electrically connected to each other through the same bit line BL, and the firstdoped regions 202 of the memory cells in the same row are electrically insulated, so that one memory cell can be uniquely determined by a group of word lines WL and bit lines BL.

Therefore, in this embodiment, the source line SL is connected to the zero potential or is floating, and when the potential of one or both of the word line WL and the bit line BL connected to the memory cell is zero potential 0, the memory state of the memory cell is unchanged. Therefore, the memory cell connected simultaneously to the word line WL and the bit line BL having positive potential writes data "1"; the memory cells connected simultaneously to the word line WL and the bit line BL, both of which have negative potentials, write data "0". Therefore, the memory cell performing the write operation can be selected by the voltages of the bit line BL and the word line WL.

During the writing of data "1", if saidThe first voltage is too small, which easily causes holes injected in thesecond well region 202 to diffuse into the firstdoped region 202, thereby generating leakage current; if the first voltage is too large, power consumption is easily increased. Specifically, in this embodiment, the first voltage is 0.7V to 0.9V, for example, 0.8V. Specifically, the bit line of the source line SL is at zero potential, or the source line SL is suspended, the second potential V₀₂ From 0.7V to 0.9V, for example 0.8V.

In other embodiments, the first dopant ions are P-type ions, and data "1" is written when electrons are implanted in the second well region. During writing of data "1", the first voltage is less than 0. Specifically, the first voltage is-0.55V to-0.45V, for example-0.5V.

In writing data "1", if the second voltage is too small, it is easy to cause the concentration of holes in thesecond well region 212 to be low, thereby causing a read error when reading "1" or "0", the read current difference is small; if the second voltage is too large, it is easy to increase the power consumption for writing "1", and it is easy to cause the concentration of holes in thesecond well region 212 to be too high, and the absolute value of the potential at the time of erasing data to be too high, thereby increasing the power consumption for writing "0". In this embodiment, the second voltage is 0.7V to 0.9V, for example, 0.8V. Specifically, the potential on the source line SL is zero, or the source line SL is suspended, the third potential V₀₃ From 0.7V to 0.9V, for example 0.8V.

In other embodiments, the first dopant ions are P-type ions, and data "1" is written when electrons are implanted in the second well region. When writing data "0", the third potential is smaller than 0. Specifically, the second voltage is-0.55V to-0.45V, for example-0.5V.

In this embodiment, when writing data "0", the potential on the source line SL is zero potential, or the source line SL is suspended; the second potential V₀₂ And a third potential V₀₃ Are all less than 0.

When writing data "0", if the absolute value of the first voltage is too small, the first voltage is not good for theThe release of holes in thesecond well region 212 easily results in a higher concentration of holes in thesecond well region 212, which easily results in a smaller read current gap when reading a "1" or a "0", which easily results in a read error; if the absolute value of the first voltage is too large, the power consumption is easily increased. In this embodiment, the first voltage is-0.55V to-0.45V. Specifically, the potential on the source line SL is zero potential, or the source line SL is suspended; the second potential V₀₂ is-0.55V to-0.45V.

In other embodiments, the first dopant ions are P-type ions, and data "0" is written when electrons in the second well region are released. During writing of data "0", the second potential is greater than 0. Specifically, the second potential is 0.7V to 0.9V, for example, 0.8V.

When writing data "0", if the absolute value of the second voltage is too small, the inversion layer is not easy to disappear, thereby being unfavorable for releasing charges in thesecond well region 212; and the thickness of thesecond well region 212 is easily reduced, when writing data "0", electrons entering thesecond well region 212 from the firstdoped region 202 are easily diffused into thefirst well region 211, thereby being unfavorable for releasing holes in thesecond well region 212; if the absolute value of the second voltage is too large, the power consumption is easily increased. In this embodiment, the second voltage is-0.55V to-0.45V, for example-0.5V. Specifically, the potential on the source line SL is zero potential, or the source line SL is suspended; the third potential V₀₃ is-0.55V to-0.45V, such as-0.5V.

In other embodiments, the first dopant ions are P-type ions, and data "0" is written when electrons in the second well region are released. During writing of data "0", the second voltage is greater than 0. Specifically, the second voltage is 0.7V to 0.9V, for example, 0.8V.

Referring to fig. 7, after the write operation, a read operation is performed on the memory, and the method of the read operation includes: applying a first read potential V to the bit line BL₁₁ The method comprises the steps of carrying out a first treatment on the surface of the Applying a second reading potential V to the source line SL₁₂ The first readingPotential V is taken₁₁ And a second reading potential V₁₂ Forward biasing the PN junction between the firstdoped region 202 and thesecond well region 212; applying a first read potential V to the bit line BL₁₁ Thereafter, a second reading potential V is applied to the source line SL₁₂ Then, read data is acquired by the read current in the bit line BL.

During a read operation, the first read potential V₁₁ And a second reading potential V₁₂ The PN junction between the firstdoped region 202 and thesecond well region 212 is forward biased, so that the diode formed by the firstdoped region 202 and thesecond well region 212 is conducted, and a read current is generated in the bit line BL. When charges are injected into thesecond well region 212 during a write operation and an inversion layer is formed in thesecond well region 212 under thegate structure 201, the inversion layer, the firstdoped region 202 and thesecond well region 212 constitute a diode during a read operation, and the inversion layer can increase an area of a PN junction in the diode, thereby making the read current larger; conversely, the read current is smaller when thesecond well region 212 is caused to discharge charge during a write operation. Therefore, the data stored in the memory can be read by the magnitude of the read current. In addition, during the process of reading the data in the memory, thesecond well region 212 and the diode formed by the firstdoped region 202 are conducted in the forward direction, so that the read data is obtained. The voltage drop of the forward conduction of the diode is small, so that the energy consumption of the memory is low.

In this embodiment, the first dopant ions are N-type ions, and the first reading potential V₁₁ Less than the second reading potential V₁₂ . In other embodiments, the first dopant ions are P-type ions and the first read potential is greater than the second read potential.

Specifically, in this embodiment, the first doping ion is an N-type ion, and the first reading potential V₁₁ Is negative; the second reading potential V₁₂ Is at zero potential. In other embodiments, the first read potential is zero potential; the second reading potential is positive。

In this embodiment, the principle of the reading operation of the memory is the same as that of the previous embodiment, and will not be described herein.

In this embodiment, the second reading potential V₁₂ With the first reading potential V₁₁ The difference of (2) is the read voltage. The read voltage is greater than zero. In other embodiments, the first dopant ions are P-type ions and the read voltage is less than zero.

FIG. 8 is a graph of read current versus read voltage for a memory of the present invention during a read operation; curve b is a graph of the relationship between the read current and the read voltage when the data stored in the memory cell is "1"; curve a is a graph of the relationship between the read current and the read voltage when the data stored in the memory cell is "0".

As can be seen from fig. 8, the read current when the data stored in the memory cell is "1" is greater than the read current when the data stored in the memory cell is "0". Thus, the data stored in the read memory cell can be acquired by reading the value of the current.

In this embodiment, the memory cell for a read operation is selected by the potentials on the source line SL and the bit line BL.

In the reading operation process, the source line SL comprises a first source line and a second source line, and the first source line is connected with a memory cell for reading operation; the bit line BL comprises a third bit line and a fourth bit line; the third bit line is connected to a memory cell performing a read operation.

Specifically, the method for reading operation includes: applying a first read potential V to the third bit line₁₁ The method comprises the steps of carrying out a first treatment on the surface of the Applying a second reading potential V to the first source line₁₂ The second reading potential V₁₂ With the first reading potential V₁₁ Forward biasing the PN junction between the firstdoped region 202 and thesecond well region 212; suspending the second source line; and suspending the fourth bit line.

When the combination of one of the source line SL and the bit line BL and both thereof is floating, no current is formed in the memory cell connecting the source line SL and the bit line BL. When the diode formed by thesecond well region 212 and the firstdoped region 202 of the memory cell is turned on by the potential of the source line SL and the bit line BL connected to the same memory cell, a current is generated in the bit line BL connected to the memory cell. Therefore, a memory cell performing a read operation can be selected by potentials on the bit line BL and the source line SL.

In this embodiment, the method for acquiring the read data by the read current includes: when the read current is greater than a preset current, the read data is 1; when the read current is smaller than the preset current, the read data is 0.

In other embodiments, the first dopant ions are N-type ions; writing data "1" when the first voltage is less than zero and the second voltage is less than zero; writing data '0' when the first voltage is greater than zero and the second voltage is greater than zero; the method for acquiring the read data comprises the following steps: when the read current is smaller than a preset current, the read data is 1; when the read current is greater than a preset current, the read data is "0".

Or the first doping ions are P-type ions; writing data "1" when the first voltage is less than zero and the second voltage is less than zero; writing data '0' when the first voltage is greater than zero and the second voltage is greater than zero; the method for acquiring the read data comprises the following steps: when the read current is greater than a preset current, the read data is "1"; when the read current is less than a preset current, the read data is "0".

Or the first doping ions are P-type ions; writing data "1" when the first voltage is greater than zero and the second voltage is greater than zero; writing data "0" when the first voltage is less than zero and the second voltage is less than zero; the method for acquiring the read data comprises the following steps: when the read current is smaller than a preset current, the read data is 1; when the read current is greater than a preset current, the read data is "0".

In this embodiment, the first doped ion is an N-type ion, and when the read voltage is greater than zero, the memory cell is read.

If the second reading potential V₁₂ The absolute value of (2) is too large, and the energy consumption is liable to increase. Specifically, in this embodiment, the second reading potential V₁₂ At zeropotential 0.

If the first reading potential V₁₁ Too small an absolute value of (a) tends to cause the read current to be too small, thereby reducing the sensitivity of the memory; if the first reading potential V₁₁ Is too large, is liable to increase the power consumption, and as can be seen from FIG. 8, the first reading potential V₁₁ When the absolute value of (a) is excessively large, the difference in read current when the data stored in the memory cell is "1" or "0" is small, so that a read error is liable to occur. Specifically, in this embodiment, the first reading potential V₁₁ is-0.8V to-0.7V, for example-0.75V. In other embodiments, the first doping ion is a P-type ion, the first reading potential is greater than zero, and specifically, the first reading potential is 0.7V to 0.8V.

Fig. 9 to 13 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 9, asubstrate 200 is provided.

Thesubstrate 200 includes a plurality of memory cell regions a and isolation regions B between adjacent memory cell regions a. Each memory cell area a is used to form a memory cell.

In this embodiment, thesubstrate 200 is aplanar substrate 200, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. In other embodiments, the method comprises: a substrate and a fin on the substrate.

The isolation region B surrounds the memory cell region a.

With continued reference to fig. 9, afirst well region 211 is formed in thesubstrate 200, thefirst well region 211 having first dopant ions therein; asecond well region 212 is formed on the top surface of thefirst well region 211, and thesecond well region 212 has second doped ions therein, wherein the second doped ions have a conductivity type opposite to that of the first doped ions.

In this embodiment, the forming method further includes: anisolation well region 232 is formed in the isolationregion B substrate 200, theisolation well region 232 is located on the top surface of thefirst well region 211, and isolation ions are located in theisolation well region 232, and the conductivity type of the isolation ions is opposite to that of the second doped ions.

Theisolation well region 232 is used to electrically isolate adjacent secondwell regions 212.

In this embodiment, after thefirst well region 211 is formed, thesecond well region 212 and theisolation well region 232 are formed.

Specifically, first doping ions are implanted into thesubstrate 200 through a first ion implantation process, so as to form afirst well region 211.

The method for forming thesecond well region 212 includes: forming a first pattern layer on the isolationregion B substrate 200; and performing second ion implantation on thesubstrate 200 by taking the first pattern layer as a mask, and forming asecond well region 212 in the memory cellregion A substrate 200 on the top of thefirst well region 211.

The method for forming theisolation well region 232 includes: forming a second pattern layer on the memory cell region asubstrate 200; and performing third ion implantation on thesubstrate 200 by taking the second pattern layer as a mask, and forming anisolation well region 232 in the isolationregion B substrate 200 at the top of thefirst well region 211.

In this embodiment, the first doped ion is an N-type ion, such as a phosphorus ion or an arsenic ion; the second doping ion is a P-type ion such as boron ion or BF₂⁺ Ions; the spacer ions are N-type ions, such as phosphorus ions or arsenic ions. In other embodiments, the first dopant ion is a P-type ion, such as boron ion or BF₂⁺ Ions; the second doping ion is an N-type ion, such as phosphorus ion or arsenic ion; the isolating ion is a P-type ion, such as boron ion or BF₂⁺ Ions.

Referring to fig. 10, anisolation structure 230 is formed in thesubstrate 200 between theisolation well region 232 and the memory cell region Bsecond well region 212.

Theisolation structure 230 is made of silicon oxide.

A gate structure is then formed on the surface of thesecond well region 212, and a first doped region is formed in thesecond well region 212, wherein the gate structure includes a first side and a second side opposite to each other, the firstdoped region 202 is located in thesecond well region 212 on the first side of the gate structure, and the firstdoped region 202 has a third doped ion therein, and the third doped ion has a conductivity type opposite to that of the second doped ion.

The forming method further includes: forming a second doped region in thesecond well region 212, the second doped region being located in thesecond well region 212 on the second side of the gate structure

In this embodiment, the gate structure, the first doped region and the second doped region are formed by a front gate process. In other embodiments, the gate structure, the first doped region, and the second doped region may be formed by a back gate process.

Specifically, in this embodiment, the method for forming the gate structure, the second doped region and the first doped region is shown in fig. 11 and fig. 12.

Referring to fig. 11, agate structure 201 is formed on a surface of thesecond well region 212, where thegate structure 201 includes a first side and a second side opposite to each other.

Thegate structure 201 includes a gate dielectric layer on the surface of thesecond well region 212; the grid electrode is positioned on the surface of the grid dielectric layer; and the side wall is positioned on the surface of the side wall of the grid electrode.

In this embodiment, the gate dielectric layer is made of silicon oxide. The gate is made of polysilicon, polycrystalline germanium or polycrystalline silicon germanium. In other embodiments, the gate dielectric layer is made of a high-k dielectric material; and if the material of the grid electrode is metal, forming the grid electrode structure and the first doping region comprises a front grid electrode process or a back grid electrode process.

In this embodiment, the material of the side wall is silicon nitride or silicon oxynitride.

With continued reference to fig. 11, a firstdoped region 202 is formed in thesecond well region 212 on the first side of thegate structure 202, the firstdoped region 202 having a third dopant ion therein having a conductivity type opposite to the conductivity type of the second dopant ion.

The method of forming the firstdoped region 202 includes: forming a first mask layer covering asecond well region 212 on a second side of thegate structure 201; and performing first source-drain ion implantation on thesecond well region 212 on the second side by taking the first mask layer and thegate structure 201 as masks, and implanting third doped ions in thesecond well region 212, wherein the conductivity types of the third doped ions are opposite to those of the second doped ions.

In this embodiment, the second doped ion is a P-type ion, and the third doped ion is an N-type ion, such as a phosphorus ion or an arsenic ion. In other embodiments, the second dopant ion is an N-type ion and the third dopant ion is a P-type ion, such as boron ion or BF₂⁺ Ions.

Referring to fig. 12, a seconddoped region 203 is formed in thesecond well region 212 on the second side of thegate structure 202, and the seconddoped region 203 has a fourth doped ion therein, wherein the conductivity type of the fourth doped ion is the same as that of the second doped ion.

The method of forming the seconddoped region 203 includes: forming a second mask layer covering thesecond well region 212 on the first side of thegate structure 201; and performing second source-drain ion implantation on the second side secondwell region 212 by taking the second mask layer and thegate structure 201 as masks, and implanting fourth doping ions in thesecond well region 212, wherein the fourth doping ions have the same conductivity type as the second doping ions.

In this embodiment, the second dopant ion is a P-type ion, and the fourth dopant ion is a P-type ion, such as boron ion or BF ion₂⁺ Ions. In other embodiments, the second dopant ion is an N-type ion and the fourth dopant ion is an N-type ion, such as a phosphorus ion or an arsenic ion.

Thefirst well region 211, thesecond well region 212, thegate structure 202, the seconddoped region 203, and the firstdoped region 202 of one memory cell region a constitute one memory cell.

The semiconductor structure comprises a plurality of memory cell areas A, wherein the memory cell areas A are arranged into a memory array; the number of the storage units is a plurality, and the storage units are arranged into a storage array.

In this embodiment, thegate structures 201 span the memory cell regions of the same row in the memory array, so that thegate structures 201 of the memory cells of the same row are connected to each other.

In other embodiments, the substrate includes a base and a fin on the base. The gate structure spans the fin and covers the fin portion sidewalls and top surface. The first well region is located in one or a combination of the substrate and the fin; the second well region is located in the fin.

Referring to fig. 13, a word line (not shown) electrically connected to thegate structure 201 is formed; forming a bit line BL electrically connected to the firstdoped region 202; forming a source line SL electrically connected to thesecond well region 212; a well line (not shown) electrically connected to thefirst well region 211 is formed.

Thegate structures 201 of the memory cells in the same row in the memory array are electrically connected to the same word line; the seconddoped regions 203 of the memory cells in the same row in the memory array are electrically connected to the same source line SL; the firstdoped regions 202 of the memory cells of the same column in the memory array are electrically connected to the same bit line BL.

The forming method further comprises the following steps: forming a dielectric layer covering thegate structure 201, the seconddoped region 203 and the firstdoped region 202; forming asecond plug 243 in the dielectric layer, thesecond plug 243 being in contact with the seconddoped region 203; the source line SL is located on the surface of thesecond plug 243.

In this embodiment, the dielectric layer includes: a firstdielectric layer 251 covering thegate structure 201, the seconddoped region 203, and the firstdoped region 202; asecond dielectric layer 252 on thefirst dielectric layer 251; a first plug in thefirst dielectric layer 251, the first plug penetrating the first dielectric layer, and thefirst plug 241 contacting the firstdoped region 202; a gate plug and asecond plug 243 in thefirst dielectric layer 251 and thesecond dielectric layer 252, thesecond plug 243 penetrating from thefirst dielectric layer 251 to thesecond dielectric layer 252 and thesecond plug 243 contacting the seconddoped region 203, the gate plug penetrating from thefirst dielectric layer 251 to thesecond dielectric layer 252 and the gate plug contacting thegate structure 201.

The bit line BL is positioned on the surface of thefirst dielectric layer 251 and thefirst plug 241; the word line WL is located on the surface of the gate plug and thesecond dielectric layer 252; the source line SL is located on the surface of thesecond dielectric layer 252 and thesecond plug 243.

Specifically, in this embodiment, the method for forming the dielectric layer, the second plug 243, the source line SL, the first plug 241, the bit line BL, the gate plug and the word line includes: forming a first dielectric layer 251 covering the gate structure 201, the second doped region and the first doped region; forming a first contact hole in the first dielectric layer 251, wherein the bottom of the first contact hole exposes the first doped region 202; forming a first plug 241 in the first contact hole; forming bit lines BL on the surfaces of the first plugs 241 and the first dielectric layer 251; forming a second dielectric layer 252 on the surfaces of the first dielectric layer 251 and the bit line BL; forming a second contact hole penetrating from the first dielectric layer 251 to the second dielectric layer 252, wherein the bottom of the second contact hole exposes the gate structure 201; forming a third contact hole penetrating from the first dielectric layer 251 to the second dielectric layer 252, wherein the bottom of the third contact hole exposes the second doped region 203; forming a second plug 243 in the third contact hole; forming word lines WL on the surface of the second dielectric layer 252 and the surface of the gate plugs 241; forming a second plug 243 in the third contact hole; source lines SL are formed on the surface of the second dielectric layer 252 and the surface of the second plugs 243.

The word line WL is not in contact with the source line SL.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (13)

1. A method of operating a memory, comprising:

providing a memory, the memory comprising: a substrate; a first well region in the substrate, the first well region having first dopant ions therein; the second well region is positioned on the top surface of the first well region, and is provided with second doped ions, and the conductivity type of the second doped ions is opposite to that of the first doped ions; a gate structure on a surface of the second well region, the gate structure including opposing first and second sides; a first doped region in the second well region on the first side of the gate structure, the first doped region having a third dopant ion therein, the third dopant ion having a conductivity type opposite to a conductivity type of the second dopant ion; a word line electrically connected to the gate structure; a bit line electrically connected to the first doped region; a source line electrically connected to the second well region;

Applying a first potential to the first well region to reverse bias a PN junction between the first well region and the second well region;

performing a write operation to the memory, the method of the write operation comprising: applying a second potential to the bit line to enable the voltage between the first doped region and the second well region to be a first voltage; applying a third potential to the word line to enable the voltage between the gate structure and the second well region to be a second voltage, wherein the second voltage is the same as the first voltage in positive and negative;

after the write operation, performing a read operation on the memory, the method of the read operation comprising: applying a first read potential to the bit line; applying a second read potential to the source line, the first and second read potentials forward biasing a PN junction between the first doped region and the second well region; after a first reading potential is applied to the bit line and a second reading potential is applied to the source line, reading data is acquired through a reading current in the bit line.

2. The method of claim 1, wherein the first dopant ion is an N-type ion, the second dopant ion is a P-type ion, and the third dopant ion is an N-type ion;

Or the first doping ion is a P-type ion, the second doping ion is an N-type ion, and the third doping ion is a P-type ion.

3. The method of operation of a memory of claim 1, wherein the memory comprises a plurality of memory cells, the memory cells comprising: the first well region, the second well region, the gate structure, and the first doped region.

4. A method of operating a memory as claimed in claim 3, wherein the plurality of memory cells are arranged as a memory array; the grid structures of the memory cells in the same row in the memory array are electrically connected with each other through the same word line; the first doped regions of the memory cells in the same column in the memory array are electrically connected with each other through the same bit line; the second doped regions of the memory cells of the same row in the memory array are electrically connected to each other through the same source line.

5. The method of operation of a memory of claim 1, further comprising: the second doped region is positioned in the second well region at the second side of the grid structure, fourth doped ions are arranged in the second doped region, the fourth doped ions have the same conductive type as the second doped ions, and the concentration of the fourth doped ions in the second doped region is larger than that of the second doped ions in the second well region;

The source line is electrically connected with the second doped region.

6. The method of operation of a memory of claim 5, further comprising: the first dielectric layer covers the grid structure, the second doped region and the first doped region; the first plug penetrates through the first dielectric layer and is in contact with the first doped region, and the bit line is located on the surfaces of the first dielectric layer and the first plug; the second dielectric layer is positioned on the surfaces of the bit line and the first dielectric layer; a second plug penetrating from the first dielectric layer to the second dielectric layer, the second plug being in contact with the second doped region; the source line is positioned on the surfaces of the second plug and the second dielectric layer.

7. The method of claim 1, wherein the first dopant ions are N-type ions, and the first potential is greater than the second well region;

or the first doped ions are P-type ions, and the first potential is smaller than the potential of the second well region.

8. The method of operation of a memory of claim 1, wherein the method of writing operation further comprises: suspending the source line or applying a fourth potential to the source line, wherein the fourth potential is zero potential;

When the first doping ions are N-type ions, the first potential is 1.8V-2.2V;

the second potential is 0.7V-0.9V, and the third potential is 0.7V-0.9V; alternatively, the second potential is-0.55V to-0.45V, and the third potential is-0.55V to-0.45V.

9. The method of operation of a memory of claim 1, wherein the memory comprises a plurality of memory cells, the memory cells comprising: the first well region, the second well region, the gate structure and the first doped region; the plurality of memory cells are arranged into a memory array; the grid structures of the memory cells in the same row in the memory array are electrically connected with each other through the same word line; the first doped regions of the memory cells in the same column in the memory array are electrically connected with each other through the same bit line; the second doped regions of the memory cells in the same row in the memory array are electrically connected with each other through the same source line;

the word lines comprise a first word line and a second word line, and the first word line is connected with a memory cell for writing operation; the bit line comprises a first bit line and a second bit line, and the first bit line is connected with a memory cell for writing operation; the method for applying the second potential to the bit line comprises the following steps: applying a second potential to the first bit line; the method of applying a third potential to the word line includes: applying a third potential to the first word line;

The method of writing operation further comprises: applying zero potential to the second bit line or suspending the second bit line; applying zero potential to the second word line or suspending the second word line.

10. The method of claim 1, wherein the first dopant ions are N-type ions, and the first read potential is less than the second read potential;

or the first doped ions are P-type ions, and the first reading potential is greater than the second reading potential.

11. The method of claim 1, wherein the first dopant ions are N-type ions; writing data "1" when the first voltage is greater than zero and the second voltage is greater than zero; or the first doping ions are P-type ions; writing data "1" when the first voltage is less than zero and the second voltage is less than zero;

the method for acquiring the read data comprises the following steps: when the read current is greater than a preset current, the read data is "1"; when the read current is less than a preset current, the read data is "0".

12. The method of claim 11, wherein the first dopant ions are N-type ions; the method of the read operation further includes: applying zero potential to the word line or suspending the word line;

The first reading potential is-0.8V to-0.7V; the second read potential is zero potential.

13. The method of operation of a memory of claim 1, wherein the memory comprises a plurality of memory cells, the memory cells comprising: the first well region, the second well region, the gate structure and the first doped region; the plurality of memory cells are arranged into a memory array; the grid structures of the memory cells in the same row in the memory array are electrically connected with each other through the same word line, the first doped regions of the memory cells in the same column in the memory array are electrically connected with each other through the same bit line, and the second doped regions of the memory cells in the same row are electrically connected with each other through the same source line;

the source line comprises a first source line and a second source line, and the first source line is connected with a memory cell for reading operation; the bit line comprises a third bit line and a fourth bit line, and the third bit line is connected with a memory cell for reading operation;

the method of applying a first read potential to the bit line includes: applying a first read potential to the third bit line; the method for applying the second reading potential to the source line comprises the following steps: applying a second read potential to the first source line, the second read potential and the first read potential forward biasing a PN junction between the second well region and the first doped region;

The method of the read operation further includes: suspending the fourth bit line; and suspending the second source line.

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