技术领域technical field
本发明属于人工智能技术领域，涉及一种半导体元件，该半导体元件包含可用于执行或支持乘积和运算的电路。The present invention belongs to the technical field of artificial intelligence, and relates to a semiconductor element comprising a circuit that can be used to perform or support a sum-of-products operation.
背景技术Background technique
在神经形态运算系统，机器学习系统和用于依据线性代数的一些计算类型的电路中，乘积和函数可以是重要的元件。函数可以表示如下：Products and functions can be important elements in neuromorphic computing systems, machine learning systems, and circuits for some types of computations based on linear algebra. The function can be represented as follows:
在该表达式中，每个乘积项是可变输入Xi和权重Wi的乘积。权重Wi可以在术语之间变化，对应于例如可变输入Xi的系数。In this expression, each product term is the product of the variable input Xi and the weight Wi. The weightsWi may vary between terms, corresponding toeg the coefficients of the variable input Xi.
乘积和函数可以通过利用含有交叉点阵列架构的电路操作来实现，其中阵列单元的电特性实现该功能。The sum-of-products function can be implemented by utilizing circuit operations that include a cross-point array architecture, where the electrical properties of the array elements enable the function.
对于高速实现，期望具有非常大的阵列，使得许多操作可以并行执行，或者非常大的乘积和系列可以执行。在系统中，有非常大数量的输入和输出，使总电流消耗可能非常大。For high-speed implementations, it is desirable to have very large arrays so that many operations can be performed in parallel, or very large product-sum series can be performed. In a system, there is a very large number of inputs and outputs, so that the total current consumption can be very large.
本发明期望提供适用于在大阵列中实现的乘积和函数的结构，并且可以更加有效节能。The present invention contemplates providing structures suitable for product-sum functions implemented in large arrays, and which can be more energy efficient.
发明内容SUMMARY OF THE INVENTION
本发明描述了一种半导体元件，该半导体元件为一包括可变电阻单元阵列的装置，其中在阵列中一可变电阻单元包括一可编程阈值晶体管和并联电阻。该装置可以操作，使得施加到晶体管的输入电压和晶体管的可编程阈值可以表示乘积和运算的变化。在本文描述的实施例中，每个可变电阻单元的可变电阻是施加到单元中可编程阈值晶体管的控制栅极的电压和电阻的函数。The present invention describes a semiconductor device that is a device comprising an array of variable resistance cells, wherein a variable resistance cell in the array includes a programmable threshold transistor and a parallel resistor. The apparatus is operable such that the input voltage applied to the transistor and the programmable threshold of the transistor can represent a change in the sum-of-products operation. In the embodiments described herein, the variable resistance of each variable resistance cell is a function of the voltage and resistance applied to the control gates of the programmable threshold transistors in the cell.
在一些实施例中，该装置包括电压感测放大器，用以感测通过可变电阻单元而产生的电压作为施加电流和可变电阻单元的电阻的函数。以这种方式，电流产生的大小来产出的乘积和可以被限制或固定，并降低功耗。In some embodiments, the apparatus includes a voltage sense amplifier to sense the voltage developed through the variable resistance unit as a function of the applied current and the resistance of the variable resistance unit. In this way, the magnitude of the current generation to yield the sum of products can be limited or fixed, and power consumption is reduced.
利用由一个晶体管和一个电阻(1T-1R)组成的单元的阵列可以实现于二维(2D)和三维(3D)阵列中。此外，本文描述的实施例可以将电阻实现为具有单一可变阈值晶体管的布局覆盖区的埋藏式注入电阻，实际上制造一个晶体管(1T)单元的阵列，以配置于具有电压感测的乘积和运算的非常紧凑的布局。Two-dimensional (2D) and three-dimensional (3D) arrays can be implemented using arrays of cells consisting of one transistor and one resistor (1T-1R). Furthermore, the embodiments described herein can implement the resistors as buried implant resistors with a layout footprint of a single variable threshold transistor, in effect fabricating an array of transistor (IT) cells to be configured in a product sum with voltage sensing Very compact layout of operations.
本发明描述了阵列中可变电阻单元配置于串联可变电阻单元的多个串线路(String)的实施例。多个字线可耦接到串联可变电阻单元串线路的这些串线路。字线驱动器连接到多个字线，以施加可变栅极电压至可变电阻单元中的可编程阈值晶体管。The present invention describes an embodiment in which the variable resistance units in the array are arranged in a plurality of string lines (String) of the variable resistance units in series. A plurality of word lines may be coupled to these string lines of series variable resistance cell string lines. Word line drivers are connected to the plurality of word lines to apply variable gate voltages to programmable threshold transistors in the variable resistance cells.
本发明实施例描述了可变电阻单元中的可编程阈值晶体管包括电荷俘获储存晶体管，例如是浮动栅极电荷俘获储存晶体管或介电电荷俘获晶体管。The embodiments of the present invention describe that the programmable threshold transistors in the variable resistance unit include charge trapping storage transistors, such as floating gate charge trapping storage transistors or dielectric charge trapping transistors.
本发明实施例描述了可变电阻单元中的电阻包括串联的可编程阈值晶体管的载流端子的埋藏式注入电阻；载流端子例如是源极和漏极。The embodiment of the present invention describes that the resistance in the variable resistance unit includes a buried injection resistance of the current-carrying terminals of the series-connected programmable threshold transistors; the current-carrying terminals are, for example, the source and the drain.
本发明还提供一种半导体元件，该半导体元件为一用于产生乘积和数据的装置，该装置包括可变电阻单元阵列，阵列中的各可变电阻单元，每个单元包括可编程阈值晶体管和并联的电阻，该阵列包括具有串联的单元串线路的n行单元及m列单元。控制和偏压电路耦接到该阵列，该控制和偏压电路包括用于阵列中利用对应于相应单元的权重因子数值Wmn的阈值来编程可编程阈值晶体管的逻辑。输入驱动器耦接至m个列单元的对应列，输入驱动器选择性地施加输入Xm至m列。行驱动器被配置于施加电流In至n行单元的一对应行。电压感测电路可操作地耦接到行单元。The present invention also provides a semiconductor element, which is a device for generating product sum data, the device comprising a variable resistance unit array, each variable resistance unit in the array, each unit comprising a programmable threshold transistor and With parallel resistors, the array includes n rows of cells and m columns of cells with series-connected string lines of cells. Coupled to the array are control and bias circuits that include logic for programming programmable threshold transistors in the array with thresholds corresponding to the weight factor values Wmn of the respective cells. Input drivers are coupled to corresponding columns of the m column units, and the input drivers selectively apply inputs Xm to m columns. The row driver is configured to apply current In to a corresponding row ofn row cells. A voltage sensing circuit is operably coupled to the row cells.
本发明描述了一种包括存储器阵列和使用数据路径控制器互连的乘积和加速器阵列的系统。乘积和加速器阵列包括可编程电阻单元阵列。存储器阵列可以与乘积和加速器阵列协调使用，以用于配置与乘积和函数的运算。The present invention describes a system including a memory array and an array of products and accelerators interconnected using a datapath controller. The product and accelerator array includes an array of programmable resistive cells. A memory array may be used in coordination with an array of product-sum accelerators for configuration and operation of the product-sum function.
一种用于操作可变电阻单元阵列以产生乘积数据总和的方法，包括在阵列中利用对应于相应单元的权重因子数值的阈值来编程可编程阈值晶体管；选择性地施加输入至阵列中的列单元，施加电流至阵列中行单元的相应行；以及在阵列中行单元的一行或多行单元上感测电压。A method for operating an array of variable resistance cells to produce a sum of product data, comprising programming programmable threshold transistors in the array with thresholds corresponding to weighting factor values of corresponding cells; selectively applying an input to columns in the array cells, applying current to corresponding rows of row cells in the array; and sensing voltages on one or more row cells of the row cells in the array.
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图详细说明如下：In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail with the accompanying drawings as follows:
附图说明Description of drawings
图1绘示乘积和运算的功能图，乘积和运算可以是现有技术中已知的神经形态运算系统的基本元件。FIG. 1 shows a functional diagram of a sum-of-products operation, which may be an essential element of neuromorphic computing systems known in the art.
图2绘示配置于乘积和运算的可变电阻单元阵列的一部分图。FIG. 2 is a diagram showing a portion of an array of variable resistance cells configured for sum-of-products operations.
图3绘示根据本文描述的实施例的可变电阻单元的示意图。FIG. 3 shows a schematic diagram of a variable resistance unit according to embodiments described herein.
图4绘示包括浮动栅极储存晶体管和埋藏式注入电阻的可变电阻单元的简化剖面图。4 shows a simplified cross-sectional view of a variable resistance cell including a floating gate storage transistor and a buried implant resistor.
图5绘示包括介电电荷俘获储存晶体管和埋藏式注入电阻的可变电阻单元的简化剖面图。5 shows a simplified cross-sectional view of a variable resistance cell including a dielectric charge trap storage transistor and a buried injection resistor.
图6-图9绘示根据本文描述的实施例的可变电阻单元的制造流程图。6-9 illustrate a fabrication flow diagram of a variable resistance cell according to embodiments described herein.
图10A和图10B绘示可变电阻单元串联排列于NAND类(与非类，NAND-Like)结构的剖面图及布局图。10A and 10B illustrate a cross-sectional view and a layout view of variable resistance cells arranged in series in a NAND-like (NAND-like, NAND-Like) structure.
图11A和图11B绘示可变电阻单元的示例操作图。11A and 11B illustrate example operational diagrams of the variable resistance unit.
图12绘示配置实施于乘积和运算的可变电阻单元的串线路(String)。FIG. 12 illustrates a string configuration of variable resistance cells implemented in a product-sum operation.
图13绘示可与可变电阻单元阵列一起使用于乘积和运算的感测电路的简化方框图。13 shows a simplified block diagram of a sensing circuit that can be used with an array of variable resistance cells for sum-of-products operations.
图13A绘示利用图13电路的感测操作目的的原理图。FIG. 13A is a schematic diagram illustrating the purpose of the sensing operation using the circuit of FIG. 13 .
图14绘示可与如图13的感测电路一起使用的参考电压电路的简化图。FIG. 14 shows a simplified diagram of a reference voltage circuit that may be used with the sensing circuit of FIG. 13 .
图15绘示包括参考串(String)的可变电阻单元阵列的配置。FIG. 15 shows a configuration of a variable resistance cell array including a reference string (String).
图16绘示包括参考串和未使用单元的可变电阻单元阵列的另一种配置图。FIG. 16 shows another configuration diagram of a variable resistance cell array including reference strings and unused cells.
图17绘示包括两个参考串和未使用单元的可变电阻单元阵列的另一种配置图。FIG. 17 shows another configuration diagram of a variable resistance cell array including two reference strings and unused cells.
图18-图22绘示配置于利用多个位权重来实施乘积和运算项的可变电阻单元的功能组图。18-22 illustrate functional group diagrams of variable resistance cells configured to implement sum-of-product terms using multiple bit weights.
图23是包括可变电阻单元阵列应用的装置的简化方框图，例如是应用于神经形态存储器。Figure 23 is a simplified block diagram of an apparatus including a variable resistive cell array application, such as in neuromorphic memory.
图24-图26绘示包括乘积和加速器阵列及其不同操作的系统。24-26 illustrate a system including a product and accelerator array and its different operations.
图27是可变电阻单元的垂直U形NAND类串线路的示意电路图。27 is a schematic circuit diagram of a vertical U-shaped NAND string-like line of variable resistance cells.
图28是可变电阻单元的替代垂直NAND类串线路的示意电路图。28 is a schematic circuit diagram of an alternative vertical NAND-like string line for variable resistance cells.
图29是可变电阻单元的垂直U形NAND类串线路的3D阵列透视图。29 is a perspective view of a 3D array of vertical U-shaped NAND string-like lines of variable resistance cells.
图30是可变电阻单元的单一垂直U形NAND类串线路可变电阻单元串线路的剖面图，其可实施于如图29的阵列。30 is a cross-sectional view of a single vertical U-shaped NAND-like string line variable resistance cell string line of variable resistance cells, which may be implemented in the array of FIG. 29 .
图31还绘示如本文描述的可变电阻单元的垂直U形NAND类串线路的3D阵列的另一种类型。Figure 31 also illustrates another type of 3D array of vertical U-shaped NAND string-like lines of variable resistance cells as described herein.
图32绘示包含另一实施例的可变电阻单元的垂直U形NAND类串线路的垂直通道单栅极结构。FIG. 32 illustrates a vertical channel single gate structure of vertical U-shaped NAND string-like lines including variable resistance cells of another embodiment.
图33是图32阵列的可变电阻单元的放大图。FIG. 33 is an enlarged view of the variable resistance cells of the array of FIG. 32 .
图34是共享包括如本文所述的可变电阻单元的浮动栅极类型NAND类结构的垂直剖面图。34 is a vertical cross-sectional view sharing a floating gate type NAND-like structure including variable resistance cells as described herein.
图35是图34共享浮动栅极类型NAND类可变电阻单元串线路的放大图。FIG. 35 is an enlarged view of the shared floating gate type NAND type variable resistance cell string line of FIG. 34 .
图36是根据本文描述实施例的分离栅极可变电阻单元的示意图。36 is a schematic diagram of a split gate variable resistance cell according to embodiments described herein.
【符号说明】【Symbol Description】
12、35、3635：可编程阈值晶体管12, 35, 3635: Programmable Threshold Transistors
14、36、3636：电阻14, 36, 3636: Resistors
21、22、23、24：电流源21, 22, 23, 24: Current source
26：接地线26: Ground wire
30、3630：第一载流节点30, 3630: The first current-carrying node
31、3631：第二载流节点31, 3631: Second current-carrying node
32、3632：控制端子32, 3632: Control terminal
100、200、300、3105：基板100, 200, 300, 3105: Substrate
101、201：源极端子101, 201: Source terminal
102、202：漏极端子102, 202: Drain terminal
103：浮动栅极多晶硅层103: Floating gate polysilicon layer
104、204：控制栅极多晶硅层104, 204: control gate polysilicon layer
105、205：栅极介电层105, 205: Gate dielectric layer
106：内多晶硅介电质106: Inner polysilicon dielectric
107、108、207、208：接点107, 108, 207, 208: Contacts
109、209：接触层109, 209: Contact layer
110、210、304、451：埋藏式注入电阻110, 210, 304, 451: Buried injection resistors
112、114、212、214：电流路径112, 114, 212, 214: Current paths
113、213：p型通道区域203：介电电荷俘获层113, 213: p-type channel region 203: dielectric charge trapping layer
206：闭塞介电层206: Blocking Dielectric Layer
301、302：浅沟道隔离结构301, 302: Shallow trench isolation structure
303：边界303: Boundaries
310：源极区域310: Source region
311：漏极区域311: Drain region
315：浮动栅极315: Floating Gate
316：控制栅极316: Control Gate
320：侧壁320: Sidewall
321：刻蚀停止层321: Etch stop layer
322：内连接介电质322: Interconnect Dielectric
325、326：内连接接点325, 326: Internal connection contacts
400：可变电阻单元的串联串线路400: series string line of variable resistance unit
401、402：串线路选定字线401, 402: String line selected word line
410、411、412、413、414、415：字线栅极堆410, 411, 412, 413, 414, 415: word line gate stacks
420、421、422、423、424、425、426、427：n型注入物420, 421, 422, 423, 424, 425, 426, 427: n-type implants
450：p型保护层450: p-type protective layer
502：位线接点502: Bit line contact
503：源极线接点503: source line contact
504、505：有源区504, 505: Active area
600、601：载流节点600, 601: Current-carrying nodes
602：输入节点602: Input node
650：感测放大器650: Sense Amplifier
651：缓冲器651: Buffer
652、656、965、975：线652, 656, 965, 975: Line
655：参考电压电路655: Reference Voltage Circuit
660：缓存器660: Buffer
661：算术逻辑单元661: Arithmetic logic unit
665：参考行665: Reference line
666：电阻分压器666: Resistor Divider
667：选择器667: selector
680、690、700：操作串线路680, 690, 700: operating string lines
681：行参考串线路681: Line reference string line
691、701、702：参考串线路691, 701, 702: Reference string lines
692：参考行上的区域692: Region on reference line
703：阵列区域703: Array area
901：集成电路901: Integrated Circuits
905：数据总线905: Data bus
910：控制逻辑910: Control Logic
920、3410：方块920, 3410: Blocks
930：总线930: bus
940：字线驱动器940: Wordline driver
945、3006、3108、3205、3405a、3405b：字线945, 3006, 3108, 3205, 3405a, 3405b: word lines
960：神经形态的存储器阵列960: Neuromorphic memory arrays
970：行译码器970: Line Decoder
980：缓冲电路980: Buffer circuit
985：第二数据线985: Second data line
990：数据缓冲器990: Data Buffer
991：输入/输出电路991: Input/Output Circuits
993：数据路径993: data path
1000：系统1000: System
1001：乘积和加速器阵列1001: Product and Accelerator Arrays
1002：存储器阵列1002: Memory array
1003：数据路径控制器1003: Data Path Controller
2700：U形垂直NAND类串线路2700: U-shaped vertical NAND string-like line
2800：第一NAND类串线路2800: First NAND-like string line
2801：第二NAND类串线路2801: Second NAND-like string line
2901、3201：第一图案金属层2901, 3201: first pattern metal layer
2902、3202：第二图案金属层2902, 3202: the second pattern metal layer
2903、3106、3208：串线路选定线2903, 3106, 3208: Serial line selection line
2904、3107、3203：接地选定线2904, 3107, 3203: Ground selection line
2905：垂直通道结构2905: Vertical Channel Structure
2906：辅助栅极结构2906: Assisted Gate Structure
3001、3101、3401：位线3001, 3101, 3401: bit lines
3002、3402：源极线3002, 3402: source line
3003、3004、3403、3404：选定栅极3003, 3004, 3403, 3404: Selected gate
3005a、3005b、3103：垂直通道结构3005a, 3005b, 3103: Vertical channel structure
3007：后栅极3007: Back Gate
3102：内连接3102: Inner join
3104：共源极线扩散3104: Common Source Line Diffusion
3109：介电层3109: Dielectric Layer
3110、3206：电荷俘获层3110, 3206: charge trapping layer
3111：半导体材料薄膜3111: Thin Films of Semiconductor Materials
3112：掺杂多晶硅3112: Doped Polysilicon
3204：辅助栅极线3204: Auxiliary Gate Line
3207：薄膜通道层3207: Thin Film Channel Layer
3209：绝缘层3209: Insulation layer
3406：共享浮动栅极结构3406: Shared Floating Gate Structure
3407：多晶硅间介电层3407: Interpoly Dielectric Layer
3408：隧穿介电层3408: Tunneling Dielectric Layer
3409：掺杂半导体核心3409: Doped Semiconductor Core
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
图1-图36提供了对本发明实施例的详细描述。1-36 provide detailed descriptions of embodiments of the present invention.
图1是乘积和运算图，其中总和项是输入Xi与权重Wi的乘积，在该范例中，其中i从1至7。权量Wi可以不同于总和项。在操作中，权重可以被指定为一组系数，然后应用于计算总和变化的输入作为可变输入。此外，在执行学习过程的算法中，随着时间变化的权重作为学习过程以改变系数，学习得到可利用结果的总和。FIG. 1 is a graph of the sum of products operation, where the sum term is the product of the input Xi and the weight Wi , wherei is from 1 to 7 in this example. The weightWi can be different from the sum term. In operation, weights can be specified as a set of coefficients, which are then applied to calculate the sum of the changes in the input as variable input. In addition, in the algorithm that performs the learning process, the weights that change over time act as the learning process to change the coefficients, and learn to obtain the sum of the available results.
在绘示的范例中，总和的输出被应用于S形函数，以利用非线性方法产生介于最小值与最大值的范围的输出，例如介于0和1之间。这是用于神经形态运算中突触层的常见模型。其他激活函数(activation function)也能被利用，例如是逻辑函数。乘积和运算也可以应用于非神经形态的配置或者神经系统模型的考虑。In the illustrated example, the summed output is applied to a sigmoid function to produce an output that ranges between a minimum and maximum value, eg, between 0 and 1, using a non-linear method. This is a common model used for synaptic layers in neuromorphic computing. Other activation functions can also be used, such as logistic functions. The product-sum operation can also be applied to non-neuromorphic configurations or considerations of nervous system models.
图2是可变电阻单元阵列的示意图，其中阵列中的每个单元包括可编程阈值晶体管12与并联的电阻14。在该附图中，阵列包括四个串线路(String)可变电阻单元，其中各串线路包括在总和节点SUM1至SUM4之间四个串联的可变电阻单元与参考线，参考线例如是接地线26。四条字线WL1至WL4耦接到各串线路中可变电阻单元的控制端子。如图2所示，可以有任意数量的行与总和节点接至SUMn，以及任何数量的字线WLm。n行与m列的可变电阻单元具有的权重Wnm当作单元的可编程阈值Vt、单元的电阻Rnm以及行中的电流In的函数。FIG. 2 is a schematic diagram of an array of variable resistance cells, wherein each cell in the array includes a programmable threshold transistor 12 and a resistor 14 in parallel. In this figure, the array includes four string variable resistance units, wherein each string line includes four variable resistance units connected in series between summing nodes SUM1 to SUM4 and a reference line, such as ground, Line 26. The four word lines WL1 to WL4 are coupled to the control terminals of the variable resistance cells in each string. As shown in FIG. 2, there may be any number of row and sum nodes connected to SUMn, and any number of word lines WLm. The variable resistance cells of n rows and m columns have a weight Wnm as a function of the cell's programmable threshold Vt, the cell's resistance Rnm, and the current In in the row.
施加于字线的电压对应于可变输入X1到X4，...Xm。在这个方法中，串线路中的每个可变电阻单元的可变电阻是在字线的电压施加于单元的控制栅极、单元中可编程阈值晶体管的阈值，单元中的电流和电阻器的函数。The voltages applied to the word lines correspond to the variable inputs X1 to X4 , . . . Xm . In this method, the variable resistance of each variable resistance cell in the string line is the voltage at the word line applied to the control gate of the cell, the threshold of the programmable threshold transistors in the cell, the current in the cell and the difference of the resistors. function.
总和节点SUM1至SUM4，...SUMn耦接到电压感测放大器，以产生表示各串线路的乘积和输出的信号。在代表范例中，在感测操作期间，电流源21-24耦接到每个串线路，以施加固定电流至各串线路。Summing nodes SUM1 toSUM4 , . . .SUMn are coupled to voltage sense amplifiers to generate signals representing thesum -of-products output of the strings of lines. In a representative example, current sources 21-24 are coupled to each string line to apply a fixed current to each string line during a sensing operation.
图3是一个可变电阻单元的示意图，例如用于图2的阵列。可变电阻单元包括第一载流节点30、第二载流节点31和控制端子32。可编程阈值晶体管35和电阻36并联连接到第一载流节点和第二载流节点。可编程阈值晶体管具有连接至控制端子32的栅极。FIG. 3 is a schematic diagram of a variable resistance cell, such as used in the array of FIG. 2 . The variable resistance unit includes a first current-carrying node 30 , a second current-carrying node 31 and a control terminal 32 . A programmable threshold transistor 35 and a resistor 36 are connected in parallel to the first and second current-carrying nodes. The programmable threshold transistor has a gate connected to control terminal 32 .
控制端子32上的电压VG可以视为可编程阈值晶体管35的栅极电压。控制端子32可以对应于图2中阵列的字线。第一载流节点30上的电压VS可视为单元的源极电压。第二载流节点31上的电压VD可视为单元的漏极电压。The voltage VG on the control terminal 32 can be regarded as the gate voltage of the programmable threshold transistor 35 . Control terminals 32 may correspond to word lines of the array in FIG. 2 . The voltage VS on the first current-carrying node 30 can be regarded as the source voltage of the cell. The voltage VD on the second current-carrying node 31 can be regarded as the drain voltage of the cell.
在此范例中，将单元电流IC施加到具有设计或可调节电流振幅的第二载流节点31，以在单元中依据电阻36的单元中电压感测放大器的电压范围与电阻值建立电压降。电流振幅可依据特定阵列的实施例来调整，使一个有用的电压范围能被产生于串线路上以供应于总和节点。此外，电阻器的电阻大小和可编程阈值晶体管的配置可以设计成具有选定的电流级别和指定的感测范围来操作。In this example, the cell currentIC is applied to the second current-carrying node 31 with a designed or adjustable current amplitude to create a voltage drop in the cell according to the voltage range and resistance value of the in-cell voltage sense amplifier of the resistor 36 . The current amplitude can be adjusted according to the particular array embodiment so that a useful voltage range can be generated on the string lines to supply the summing node. Furthermore, the resistance size of the resistors and the configuration of the programmable threshold transistors can be designed to operate with selected current levels and specified sensing ranges.
可编程阈值晶体管35可使用浮动栅极存储单元、分离栅极浮动栅极存储单元、介电电荷俘获存储单元，例如SONOS元件或其它已知类型的介电电荷俘获存储单元如BE-SONOS和TANOS，以及分离栅极。其他可编程存储单元技术也能被使用，例如相变存储器、金属氧化物存储器等。Programmable threshold transistor 35 may use floating gate memory cells, split gate floating gate memory cells, dielectric charge trapping memory cells such as SONOS elements or other known types of dielectric charge trapping memory cells such as BE-SONOS and TANOS , and the split gate. Other programmable memory cell technologies can also be used, such as phase change memory, metal oxide memory, and the like.
此外，在本技术的实施例中，电阻36可以实施于可编程阈值晶体管35的源极和漏极端子之间的埋藏式注入电阻。Furthermore, in embodiments of the present technology, resistor 36 may be implemented as a buried injection resistor between the source and drain terminals of programmable threshold transistor 35 .
图36是一个分离栅极可变电阻单元的示意图，例如可以用于图2的阵列的修改版本中。可变电阻单元包括第一载流节点3630、第二载流节点3631和控制端子3632。控制端子通过电荷俘获层涵盖部分通道长度，以及通过没有电荷俘获的栅极介电质从该通道被分离，以用于在通道长度平衡中的数据储存。可编程阈值晶体管3635和电阻3636并联连接至第一载流节点和第二载流节点。可编程阈值晶体管具有连接到控制端子3632的栅极。FIG. 36 is a schematic diagram of a split gate variable resistance cell, such as may be used in a modified version of the array of FIG. 2 . The variable resistance unit includes a first current-carrying node 3630 , a second current-carrying node 3631 and a control terminal 3632 . The control terminal covers part of the channel length by a charge trapping layer and is separated from the channel by a gate dielectric without charge trapping for data storage in channel length balance. A programmable threshold transistor 3635 and a resistor 3636 are connected in parallel to the first and second current-carrying nodes. The programmable threshold transistor has a gate connected to control terminal 3632.
控制端子3632上的电压VG可视为可编程阈值晶体管3635的栅极电压。控制端子3632可以对应于图2所示的阵列中的字线。第一载流节点3630上的电压可视为单元的电压源。第二载流节点3631上的电压VD可视为单元的漏极电压。The voltage VG on the control terminal 3632 can be regarded as the gate voltage of the programmable threshold transistor 3635 . Control terminals 3632 may correspond to word lines in the array shown in FIG. 2 . The voltage on the first current-carrying node 3630 can be considered as the voltage source for the cell. The voltage VD on the second current-carrying node 3631 can be regarded as the drain voltage of the cell.
图4是具有并联连接至通道的电阻，以及该电阻被实施于利用离子注入而产生埋藏式注入电阻110的浮动栅极装置的简化剖面图。FIG. 4 is a simplified cross-sectional view of a floating gate device having a resistor connected in parallel to the channel and implemented in a floating gate device using ion implantation to create a buried implant resistor 110 .
在此范例中，该装置实现于基板100上，该基板100可以是p型基板。源极端子101和漏极端子102通过在基板100中n型离子注入来实施。源极端子101和漏极端子102具有其形成的接点107、108，耦接到具有电压VS的源极节点和具有电压VD的漏极节点。p型通道区域113设置在埋藏式注入电阻110和栅极介电层105(通道氧化物)之间，以覆盖在源极端子101和漏极端子102之间的基板100上。浮动栅极多晶硅层103设置于栅极介电层105上。设置于浮动栅极多晶硅层103上的内多晶硅介电质106于一些实施例中使用包含氧化硅，氮化硅和氧化硅层(ONO)的多层结构。控制栅极多晶硅层104设置在内多晶硅介电质106上。接触层109形成在控制栅极多晶硅层104上。侧壁结构(未编号)沿着栅极堆的侧壁形成。In this example, the device is implemented on a substrate 100, which may be a p-type substrate. The source terminal 101 and the drain terminal 102 are implemented by n-type ion implantation in the substrate 100 . The source terminal 101 and the drain terminal 102, with their formed contacts 107, 108, are coupled to a source node having a voltage VS and a drain node having a voltage VD. The p-type channel region 113 is disposed between the buried implant resistor 110 and the gate dielectric layer 105 (channel oxide) to cover the substrate 100 between the source terminal 101 and the drain terminal 102 . The floating gate polysilicon layer 103 is disposed on the gate dielectric layer 105 . The inner polysilicon dielectric 106 disposed on the floating gate polysilicon layer 103 uses a multi-layer structure comprising silicon oxide, silicon nitride and silicon oxide layers (ONO) in some embodiments. A control gate polysilicon layer 104 is disposed on the inner polysilicon dielectric 106 . A contact layer 109 is formed on the control gate polysilicon layer 104 . Sidewall structures (not numbered) are formed along the sidewalls of the gate stack.
图4绘示的结构可使用浮动栅极单元制造技术来实现，并通过额外掺杂的步骤来修改，以形成埋藏式注入电阻110。埋藏式注入电阻110连接源极端子101和漏极端子102，以作为被动电阻。在此方式中，浮动栅极装置和埋藏式注入电阻110提供可编程阈值晶体管和并联电阻于第一载流端子-源极端子101、和第二载流端子-漏极端子102之间。The structure shown in FIG. 4 can be implemented using floating gate cell fabrication techniques and modified with additional doping steps to form buried implant resistors 110 . The buried injection resistor 110 is connected to the source terminal 101 and the drain terminal 102 as a passive resistor. In this manner, the floating gate device and buried injection resistor 110 provide a programmable threshold transistor and parallel resistance between the first current-carrying terminal-source terminal 101 and the second current-carrying terminal-drain terminal 102 .
在图4中绘示了电流路径112，电流路径112通过源极端子101和漏极端子102之间的埋藏式注入电阻110。在图4中也绘示了电流路径114，当在浮动栅极中栅极电压与俘获电荷和源极电压VS结合时，电流路径114被激活，以使电流流经晶体管的通道。A current path 112 is depicted in FIG. 4 through a buried injection resistor 110 between the source terminal 101 and the drain terminal 102 . Also depicted in FIG. 4 is a current path 114 that is activated when the gate voltage combines with the trapped charge and source voltageVs in the floating gate to cause current to flow through the transistor's channel.
因此，该装置具有可变电阻(或可变电导)，可变电阻是埋藏式注入电阻110的电阻和浮动栅极装置通道的电阻的函数。浮动栅极装置通道的电阻是栅极电压和在浮动栅极中俘获电荷的函数。Thus, the device has a variable resistance (or variable conductance) that is a function of the resistance of the buried injection resistor 110 and the resistance of the floating gate device channel. The resistance of the floating gate device channel is a function of gate voltage and charge trapped in the floating gate.
图5是具有电阻并联连接至通道的介电电荷俘获装置的简化剖面图，以及实施于使用离子注入方法，以产生埋藏式注入电阻210。FIG. 5 is a simplified cross-sectional view of a dielectric charge trapping device with resistors connected in parallel to the channels, and implemented using an ion implantation method to create buried implant resistors 210 .
在此范例中，该装置实施于基板200上，基板200可以是p型基板。源极端子201和漏极端子202通过在基板200中n型离子注入来实施。源极端子201和漏极端子202具有其形成的接点207、208，并耦接到具有电压VS的源极节点和具有电压VD的漏极节点。p型通道区域213设置在埋藏式注入电阻210和栅极介电层205(通道氧化物)之间，以覆盖在源极端子201和漏极端子202之间的基板200上。介电电荷俘获层203设置在通道介电层205上。闭塞介电层206设置在介电电荷俘获层203上，控制栅极多晶硅层204设置在闭塞介电层206上。接触层209形成在控制栅极多晶硅层204上。侧壁结构(未编号)沿着栅极堆的侧壁形成。In this example, the device is implemented on a substrate 200, which may be a p-type substrate. The source terminal 201 and the drain terminal 202 are implemented by n-type ion implantation in the substrate 200 . The source terminal 201 and the drain terminal 202 have contacts 207, 208 formed therefrom and are coupled to a source node having a voltage VS and a drain node having a voltage VD. The p-type channel region 213 is disposed between the buried implant resistor 210 and the gate dielectric layer 205 (channel oxide) to cover the substrate 200 between the source terminal 201 and the drain terminal 202 . A dielectric charge trapping layer 203 is disposed on the channel dielectric layer 205 . The blocking dielectric layer 206 is disposed on the dielectric charge trapping layer 203 , and the control gate polysilicon layer 204 is disposed on the blocking dielectric layer 206 . A contact layer 209 is formed on the control gate polysilicon layer 204 . Sidewall structures (not numbered) are formed along the sidewalls of the gate stack.
图5绘示的结构可以使用介电电荷俘获存储单元制造技术来实现，可通过额外的掺杂步骤来修改，以形成埋藏式注入电阻210。埋藏式注入电阻210连接源极端子201和漏极端子202，以作为被动电阻。在这种方式中，介电电荷俘获装置和埋藏式注入电阻210提供可编程阈值晶体管和在源极端子201和漏极端子202之间的并联电阻。The structure shown in FIG. 5 can be implemented using dielectric charge trapping memory cell fabrication techniques and can be modified with additional doping steps to form buried implant resistor 210 . The buried injection resistor 210 is connected to the source terminal 201 and the drain terminal 202 as a passive resistor. In this manner, the dielectric charge trapping device and buried injection resistor 210 provide a programmable threshold transistor and parallel resistance between the source terminal 201 and the drain terminal 202 .
在图5中绘示了电流路径212，电流路径212通过源极端子201和漏极端子202之间的埋藏式注入电阻210。图5中也绘示了电流路径214，当在介电电荷俘获层中栅极电压与俘获电荷结合时，电流路径214被激活，以使电流流经装置通道。A current path 212 is depicted in FIG. 5 through a buried injection resistor 210 between the source terminal 201 and the drain terminal 202 . Also depicted in FIG. 5 is a current path 214, which is activated when the gate voltage combines with the trapped charge in the dielectric charge trapping layer to allow current to flow through the device channel.
因此，该装置具有可变电阻(或电导)，可变电阻是埋藏式注入电阻110的电阻和介电电荷俘获装置通道的电阻的函数。介电电荷俘获装置通道的电阻是栅极电压和在介电电荷俘获栅极中俘获电荷的函数。Thus, the device has a variable resistance (or conductance) that is a function of the resistance of the buried injection resistor 110 and the resistance of the dielectric charge trapping device channel. The resistance of the dielectric charge trapping device channel is a function of the gate voltage and the charge trapped in the dielectric charge trapping gate.
在图4和图5的两个实施例中绘示了由一个晶体管和一个电阻(1T-1R)组成的单元。此外，图4和图5的实施例可以将电阻器实施于单一可变阈值晶体管布局覆盖区内的埋藏式注入电阻，并有效地制造一个晶体管(1T)单元的阵列，以配置于具有电压感测的乘积和运算的非常紧凑的布局。A cell consisting of one transistor and one resistor (1T-1R) is shown in the two embodiments of FIGS. 4 and 5 . In addition, the embodiments of FIGS. 4 and 5 can implement resistors as buried injection resistors within the footprint of a single variable threshold transistor layout, and effectively fabricate an array of transistor (IT) cells to configure in a voltage-sensitive Very compact layout of the measured sum-of-products operation.
在操作中，在图4和图5中所绘示的单元可表示如下。In operation, the elements depicted in Figures 4 and 5 may be represented as follows.
当栅极至源极电压VGS小于阈值电压Vt时，电流可以流入埋藏式注入电阻，却没有形成于晶体管通道(“表面通道”)，仅允许电流IB流入于埋藏式注入电阻。因此，单元中的电流等于IB，而单元的电阻等于漏极至源极电压VDS除以电流IB。When the gate-to-source voltageVGS is less than the threshold voltageVt , current can flow into the buried injection resistor, but is not formed in the transistor channel (“surface channel”), allowing only currentIB to flow into the buried injection resistor. Therefore, the current in the cell is equal to IB , and the resistance of the cell is equal to the drain-to-source voltage VDS divided by the current IB .
当栅极至源极电压VGS大于阈值电压Vt时，表面通道电流IS和埋藏式电阻电流IB都被诱发。通道电阻可以远小于埋藏式电阻的电阻，而当晶体管导通时，Is可以控制。因此，行中的电流In被分成单元，使得电流In等于IS+IB的总和，并且单元电阻等于漏极至源极电压VDS除以电流In。When the gate-to-source voltageVGS is greater than the threshold voltageVt , both the surface channel currentIS and the buried resistor currentIB are induced. The channel resistance can be much smaller than that of the buried resistor, while Is can be controlled when the transistor is turned on. Therefore, the current In in the row is divided into cells such that the current In is equal to the sum of IS + IB , and the cell resistance is equal to the drain-to-source voltage VDS divided by the current In.
由于浮动栅极阈值或介电电荷俘获单元是可编程的，该单元电阻可仿真由栅极电压所表示的参数X(i)、以及由单元中电荷俘获、电阻器的电阻和单元电流所表示的参数W(i)的乘积。参数W(i)可以是二进制数，其中单元操作于两种状态之一(IB仅较高电阻状态和IB+IS较低电阻状态)。如果单元操作于场效晶体管行为的线性区域中，则参数W(i)可以是模拟，并且根据单元中电荷俘获的范围内变化。Since the floating gate threshold or dielectric charge trapping cell is programmable, the cell resistance can emulate the parameter X(i) represented by the gate voltage, as well as by the charge trapping in the cell, the resistance of the resistor and the cell current The product of the parameters W(i). The parameter W(i) can be a binary number where the cell operates in one of two states (IB only higher resistance state andIB +IS lower resistance state). If the cell operates in the linear region of field effect transistor behavior, the parameter W(i) can be analog and vary according to the extent of charge trapping in the cell.
图6-图9绘示了可用于实现类似图4单元的制造流程图。在图6中，绘示了提供单元的介电边界的浅沟道隔离结构301和302之后，基板300被显示出来。并注入已经被用来形成由提供该单元形成的基板300中的区域的边界303所表示的p型阱。在阵列中单元的相异方块可以在分离方块中实施，以允许阱的独立偏压用于分离方块。FIGS. 6-9 illustrate fabrication flow diagrams that may be used to implement a unit similar to that of FIG. 4 . In FIG. 6, the substrate 300 is shown after the shallow trench isolation structures 301 and 302 that provide the dielectric boundaries of the cells are shown. and implants have been used to form the p-type well represented by the boundary 303 of the region in the substrate 300 where the cell is formed. Distinct blocks of cells in the array can be implemented in separate blocks to allow independent biasing of the wells for the separate blocks.
图7绘示了n型掺杂剂(例如磷和砷)被用于形成在浅沟道隔离结构301和302之间的埋藏式注入电阻304之后的阶段。FIG. 7 shows a stage after n-type dopants (eg, phosphorous and arsenic) are used to form buried implant resistor 304 between shallow trench isolation structures 301 and 302 .
图8绘示了栅极堆结构(浮动栅极315、控制栅极316、通道介电和沿着侧壁320的多晶硅介电质)的形成以及使用n型掺杂剂注入的源极区域和漏极区域310和311形成之后的阶段。FIG. 8 illustrates the formation of the gate stack structure (floating gate 315, control gate 316, channel dielectric, and polysilicon dielectric along sidewall 320) and source regions and source regions implanted with n-type dopants and Stages after the formation of drain regions 310 and 311 .
图9绘示了在内连接介电质322和内连接接点325和326的形成之后的制造阶段。该结构使用在源极区域和漏极区域上形成硅化物接点的方法而形成于绘示的范例中，接着是在栅极堆以及源极区域与漏极区域310和311上方的薄介电质和刻蚀停止层321。内连接介电质322被沉积，并且孔被刻蚀以形成开口，其中内连接接点325和326由钨沉积或其他技术所形成。FIG. 9 illustrates the manufacturing stage after the formation of the interconnect dielectric 322 and interconnect contacts 325 and 326 . The structure is formed in the example shown using a method of forming silicide contacts on the source and drain regions, followed by a thin dielectric over the gate stack and source and drain regions 310 and 311 and etch stop layer 321. An interconnect dielectric 322 is deposited, and holes are etched to form openings, where interconnect contacts 325 and 326 are formed by tungsten deposition or other techniques.
可以看出如图4所示的可变电阻单元是依据这些步骤来制造。这些相同步骤可以被修改为如图5所示的制造单元的目的，这些相同步骤通过包括栅极介电质、电荷俘获层、阻挡层和控制栅极的栅极叠层来修改。It can be seen that the variable resistance unit shown in FIG. 4 is manufactured according to these steps. These same steps can be modified for the purpose of fabricating a cell as shown in FIG. 5 by the gate stack including the gate dielectric, charge trapping layer, blocking layer and control gate.
具有如图4和图5中所示结构的可变电阻单元可以使用连接于内连接接点325、326的图案导体层来串联排列。The variable resistance cells having the structures shown in FIGS. 4 and 5 may be arranged in series using pattern conductor layers connected to the internal connection contacts 325, 326.
图10A和图10B是2D NAND类(NAND-Like)结构中串联排列的可变电阻单元的剖面和布局视图。10A and 10B are cross-sectional and layout views of variable resistance cells arranged in series in a 2D NAND-like (NAND-Like) structure.
图10A绘示了基板的简化剖面，其中可变电阻单元的串联串线路400被形成。包括电荷俘获层(浮动栅极或介电质)和字线的字线栅极堆410-415迭置在基板，且延伸至图页方向垂直的字线元件。在代表性实施中，可能存在例如32或64个有源字线。在一些实施例中，串联串线路可包括较少数量的有源字线或较大数量的有源字线，以适用于特定实现。在一些情况下，可能存在一个或多个虚拟字线，其可以在串线路的相对端上，典型例子如高密度NAND闪存。虚拟字线可以实现于制造质量或偏置目的，但不用于串线路的乘积和运算。FIG. 10A shows a simplified cross-section of a substrate in which series string lines 400 of variable resistance cells are formed. Word line gate stacks 410-415 comprising charge trapping layers (floating gates or dielectrics) and word lines are stacked on the substrate and extend to word line elements perpendicular to the page direction. In a representative implementation, there may be, for example, 32 or 64 active word lines. In some embodiments, the series string lines may include a smaller number of active word lines or a larger number of active word lines, as appropriate for a particular implementation. In some cases, there may be one or more dummy word lines, which may be on opposite ends of the string lines, a typical example being high density NAND flash memory. Dummy word lines can be implemented for manufacturing quality or biasing purposes, but not for string line sum-of-products operations.
在此范例中，该基板是p型基板，并且可变电阻单元的载流端子(即源极/漏极端子)由n型注入物420-427来实施。在一些高密度实施例中，注入物不用于单元之间的载流端子，因此载流端子依赖于通道区域中电荷载体的反转。如图绘示的NAND类的实施例中，没有接点直接形成于所有单元之间的载流端子。In this example, the substrate is a p-type substrate, and the current-carrying terminals (ie, source/drain terminals) of the variable resistance cells are implemented by n-type implants 420-427. In some high density embodiments, implants are not used for current-carrying terminals between cells, so the current-carrying terminals rely on the inversion of charge carriers in the channel region. In the illustrated NAND-like embodiment, no contacts are formed directly between all the current-carrying terminals of the cells.
串线路选定字线401和402设置在串联串线路的相对端上。在基板中的有源区504和505包括用于串联串线路的位线与共源极线连接的n型注入物。有源区504和505相较于可变电阻单元的载流端子可以是更深注入物或更高导电率的注入物，位线接点502连接有源区504至覆盖图案导体层中的位线。源极线接点503连接有源区505至覆盖图案导体层中的源极线。String line selection word lines 401 and 402 are provided on opposite ends of the series string lines. Active regions 504 and 505 in the substrate include n-type implants for the connection of the bit lines and common source lines of the series string lines. Active regions 504 and 505 may be deeper implants or higher conductivity implants than the current-carrying terminals of the variable resistance cells, and bit line contacts 502 connect active regions 504 to bit lines in the overlying pattern conductor layer. The source line contact 503 connects the active region 505 to the source line in the overlying pattern conductor layer.
实施n型埋藏式注入电阻451，此范例中来自由位线侧串线路选定字线401控制的选定栅极的通道边缘延伸到由源极线侧串线路选定字线402控制的选定栅极的通道边缘。在这种方式中，选定栅极操作于将埋藏式注入电阻451连接和不连接至有源区504、505。An n-type buried implant resistor 451 is implemented, in this example the channel edge from the select gate controlled by the bit line side string line select word line 401 extends to the select gate controlled by the source line side string line select word line 402. Define the channel edge of the gate. In this manner, the selected gate operates to connect and disconnect the buried implant resistor 451 to the active regions 504,505.
在此范例中，具有比可变电阻单元的通道区域更高p型杂质浓度的p型保护层450设置于通道和埋藏式注入电阻451之间。p型保护层450有助于屏蔽埋藏式注入电阻451受于栅极电压，并保持并联电阻值的稳定性。In this example, a p-type protective layer 450 having a higher p-type impurity concentration than the channel region of the variable resistance unit is provided between the channel and the buried implant resistance 451 . The p-type protective layer 450 helps shield the buried injection resistor 451 from the gate voltage and maintains the stability of the parallel resistance value.
图10B是实现如图10A所示的可变电阻单元的串联串线路的平面图。公共参考标号(401、402、410-415)被给予至栅极堆(包括字线)和选定线。同样地，公共参考标号502、503被给予至位线和源极线接点。FIG. 10B is a plan view of a series string line implementing the variable resistance unit shown in FIG. 10A . Common reference numerals (401, 402, 410-415) are given to gate stacks (including word lines) and selected lines. Likewise, common reference numerals 502, 503 are given to the bit line and source line contacts.
图10B绘示了两个串联串线路被编排于并联位线500、501，其实施于字线栅极堆410-415上覆盖的图案化的导体层。FIG. 10B shows two series string lines arranged on parallel bit lines 500, 501 implemented in a patterned conductor layer overlying the word line gate stacks 410-415.
图27给示如本文描述的U形垂直NAND类串线路2700包含具有电阻(例如，2701)并联至可编程阈值、可操作电荷俘获存储单元(例如，2702)的可变电阻单元，作为乘积和加速器的示意图。在图27中，NAND类串线路包括耦接到位线BL的一U形串线路，其包括串联一串线路选择开关SSL、多个第一单元耦接到右侧上各自的字线WL、结构底部的辅助栅极AG。多个第二单元耦接到左侧上各自的字线WL，以及接地选择开关GSL耦接到源极参考线CS。操作的输入被施加于如本文所述的字线WL并进行配置如说明。使用电压和电流感测技术或其他感测技术，以感测位线或参考线的输出。FIG. 27 shows that a U-shaped vertical NAND-like string line 2700 as described herein includes variable resistance cells with a resistance (eg, 2701 ) connected in parallel to a programmable threshold, operable charge trap memory cell (eg, 2702 ) as a sum of products Schematic of the accelerator. In FIG. 27, a NAND-like string line includes a U-shaped string line coupled to a bit line BL, which includes a series string of line select switches SSL, a plurality of first cells coupled to respective word lines WL on the right side, a structure Auxiliary gate AG at the bottom. The plurality of second cells are coupled to the respective word lines WL on the left side, and the ground selection switch GSL is coupled to the source reference line CS. The inputs to the operations are applied to word lines WL as described herein and configured as illustrated. Voltage and current sensing techniques or other sensing techniques are used to sense the output of the bit line or reference line.
图28是包括第一NAND类串线路2800和第二NAND类串线路2801的替代垂直结构的示意图，其包括具有并联至可编程阈值、电荷俘获存储单元的电阻的可变电阻单元，可如本文所述的乘积和加速器的动作。在图29中，第一NAND类串线路延伸于第一位线BL和源极参考线CS之间，并且包括串线路选定栅极SSL、多个字线WL和串联的接地选定栅极GSL。同样地，第二NAND类串线路延伸于第二位线BL和源极参考线CS之间，并包括串线路选定栅极SSL、多个字线WL和串联的接地选定栅极GSL。操作输入被施加到如本文所述的字线WL和配置，使用电流感测技术或其他感测技术，可感测位线或参考线的输出。28 is a schematic diagram of an alternate vertical structure including a first NAND-like string line 2800 and a second NAND-like string line 2801 including variable resistance cells with resistances connected in parallel to programmable threshold, charge trapping memory cells, as described herein The action of the product and accelerator. In FIG. 29, a first NAND-like string line extends between the first bit line BL and the source reference line CS, and includes a string line select gate SSL, a plurality of word lines WL, and a grounded select gate connected in series GSL. Likewise, a second NAND-like string line extends between the second bit line BL and the source reference line CS, and includes a string line select gate SSL, a plurality of word lines WL, and a grounded select gate GSL in series. Operational inputs are applied to the word lines WL and configured as described herein, using current sensing techniques or other sensing techniques, the outputs of the bit lines or reference lines may be sensed.
图29-图35绘示了可用于实现垂直NAND类实施例的各种结构。在图29中，类似于图27的U形NAND类串线路实施于密集的3D阵列中。该结构包括被位线实施的第一图案金属层2901，第二图案金属层2902包括参考线。选定栅极层包括串线路选定线2903和接地选定线2904。垂直通道结构2905通过字线延伸至多个层。垂直通道结构连接至由辅助栅极结构2906支撑的U形图案。垂直通道结构包括具有自然电阻的数据储存层，例如电荷俘获结构，以及N型多晶硅掺杂垂直通道。垂直通道结构被结构的各层中的字线所环绕，从而形成所谓的全栅极可变电阻单元。因此，当字线的输入没有导通至电荷俘获单元时，则电阻由垂直通道的电阻率来决定。当字线的输入导通至电荷俘获单元时，电阻由电荷俘获单元的并联电阻和垂直通道的电阻率来确定。请参见Tanaka，H.，et al.，″Bit Cost ScalableTechnology with Punch and Plug Process for Ultra High Density Flash Memory，″2007 Symp.VLSI Tech.，Digest of Tech.Papers，pp 14-15.。29-35 illustrate various structures that may be used to implement vertical NAND-type embodiments. In Figure 29, a U-shaped NAND-like string line similar to that of Figure 27 is implemented in a dense 3D array. The structure includes a first patterned metal layer 2901 implemented by bit lines, and a second patterned metal layer 2902 including reference lines. The selected gate layer includes a string line select line 2903 and a ground select line 2904. The vertical channel structures 2905 extend through the word lines to multiple layers. The vertical channel structure is connected to the U-shaped pattern supported by the auxiliary gate structure 2906 . The vertical channel structure includes a data storage layer with natural resistance, such as a charge trapping structure, and an N-type polysilicon doped vertical channel. The vertical channel structure is surrounded by word lines in the layers of the structure, forming a so-called all-gate variable resistance cell. Therefore, when the input of the word line is not conducting to the charge trapping cell, then the resistance is determined by the resistivity of the vertical channel. When the input of the word line is turned on to the charge trapping cell, the resistance is determined by the parallel resistance of the charge trapping cell and the resistivity of the vertical channel. See Tanaka, H., et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory," 2007 Symp. VLSI Tech., Digest of Tech. Papers, pp 14-15.
图30绘示单一U形NAND类串线路，其可实施于类似图29的阵列。位线3001经由选定栅极3004连接到垂直通道结构3005a左侧上一系列的可变电阻单元，并且通过垂直通道结构的水平延伸部分和后栅极3007连接到相对垂直通道结构3005b上可变电阻单元的第二垂直串线路。可变电阻单元的第二垂直串线路通过选定栅极3003耦接到源极线3002。各串线路包括多个字线(例如3006)，以如本文所述的配置进行操作输入。在U形NAND类串线路的两侧上的垂直通道结构3005a、3005b可以包括n型掺杂多晶硅，以提供埋藏式注入电阻，该隐藏式注入电阻由原位掺杂或由注入所形成。FIG. 30 shows a single U-shaped NAND-like string line that can be implemented in an array like FIG. 29 . The bit line 3001 is connected via the selected gate 3004 to a series of variable resistance cells on the left side of the vertical channel structure 3005a, and is connected to the opposite vertical channel structure 3005b by the horizontal extension of the vertical channel structure and the back gate 3007. A second vertical string line of resistive cells. The second vertical string line of the variable resistance cell is coupled to the source line 3002 through the selected gate 3003 . Each string of lines includes a plurality of word lines (eg, 3006) for operating inputs in a configuration as described herein. The vertical channel structures 3005a, 3005b on both sides of the U-shaped NAND string-like lines may include n-type doped polysilicon to provide buried implant resistors formed by in-situ doping or by implantation.
图31绘示了实现类似图28电路的替代垂直NAND类串线路。在图31的结构中，位线3101实施于第一图案金属层中。位线3101通过内连接3102连接到垂直通道结构3103。垂直通道结构3103包括沿着垂直通道结构侧面延伸的半导体材料薄膜3111。在此实施例中垂直通道结构3103的内部包括掺杂多晶硅3112，以提供埋藏式注入电阻。垂直通道结构3103在多个导体堆之间延伸，这些导体堆被配置于串线路的相对端上与字线3108之间的串线路选定线3106和接地选定线3107。垂直通道结构3103耦接到共源极线扩散3104和基板3105。电荷俘获层3110设置在垂直通道结构3103中作为字线(例如3108)和半导体材料薄膜3111的导体之间。介电层3109分离导电材料串线路，以作为字线和串线路选定线。由于垂直通道结构3103相对侧上的串线路选定线3106是分开的，所以这些垂直NAND类串线路可以共享单一位线3101。请参见Jang，et al.，“Vertical Cell Array using TCAT(Terabit Cell ArrayTransistor)Technology for Ultra High Density NAND Flash Memory”，2009Symposium on VLSI Technology Digest of Technical Papers。FIG. 31 illustrates an alternative vertical NAND-like string circuit implementing a circuit similar to that of FIG. 28 . In the structure of FIG. 31, bit lines 3101 are implemented in the first patterned metal layer. The bit line 3101 is connected to the vertical channel structure 3103 by the interconnection 3102. The vertical channel structure 3103 includes a thin film 3111 of semiconductor material extending along the sides of the vertical channel structure. The interior of the vertical channel structure 3103 in this embodiment includes doped polysilicon 3112 to provide buried implant resistance. Vertical channel structures 3103 extend between a plurality of conductor stacks arranged on string line select lines 3106 and ground select lines 3107 between word lines 3108 on opposite ends of the string lines. The vertical channel structure 3103 is coupled to the common source line diffusion 3104 and the substrate 3105 . A charge trapping layer 3110 is disposed in the vertical channel structure 3103 as a conductor between the word lines (eg, 3108 ) and the thin film 3111 of semiconductor material. Dielectric layer 3109 separates the string lines of conductive material for use as word lines and string line selection lines. Since the string line select lines 3106 on opposite sides of the vertical channel structure 3103 are separated, these vertical NAND-like string lines can share a single bit line 3101. See Jang, et al., "Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory", 2009 Symposium on VLSI Technology Digest of Technical Papers.
图32绘示了密集3D阵列，密集3D阵列包括如本文所述的单栅极、包含与电荷俘获存储单元并联的电阻的可变电阻单元的U形垂直NAND类串线路。在此结构中，位线实施于第一图案金属层3201，源极线实施于第二图案金属层3202。位线和源极线通过内连接连接器连接到包含半导体材料的U形薄膜的垂直通道结构，垂直通道结构用于如本文实施例所述的通道和埋藏式注入电阻。垂直通道结构延伸于多个导体之间，垂直通道结构被配置为串线路选定线3208或接地选定线3203、字线(例如3205)和辅助栅极线3204。这些导体由绝缘材料来分开。垂直通道结构包括电荷俘获层3206以及延伸于U形图案的薄膜通道层3207。该结构覆盖于绝缘层3209。薄膜通道层3207可包括掺杂多晶硅，薄膜通道层3207通过多晶硅膜的原位掺杂或是掺杂多晶硅的沉积来形成。参见美国专利No.US9,698,156和美国专利No.9,524,980。32 depicts a dense 3D array comprising a single gate, U-shaped vertical NAND-like string line of variable resistance cells including a resistance in parallel with charge trapping memory cells as described herein. In this structure, the bit lines are implemented in the first pattern metal layer 3201 , and the source lines are implemented in the second pattern metal layer 3202 . The bit lines and source lines are connected by interconnecting connectors to vertical channel structures comprising U-shaped thin films of semiconductor material for the channels and buried implant resistors as described in the embodiments herein. Vertical channel structures extending between the plurality of conductors are configured as string line select lines 3208 or ground select lines 3203 , word lines (eg, 3205 ), and auxiliary gate lines 3204 . The conductors are separated by insulating material. The vertical channel structure includes a charge trapping layer 3206 and a thin film channel layer 3207 extending in a U-shaped pattern. This structure covers the insulating layer 3209 . The thin film channel layer 3207 may comprise doped polysilicon, and the thin film channel layer 3207 is formed by in-situ doping of a polysilicon film or deposition of doped polysilicon. See US Patent No. US 9,698,156 and US Patent No. 9,524,980.
图33绘示了耦接到字线3205的两个垂直通道可变电阻单元。每个可变电阻单元包括电荷俘获层3206和掺杂的薄膜通道层3207。FIG. 33 shows two vertical channel variable resistance cells coupled to word line 3205 . Each variable resistance cell includes a charge trapping layer 3206 and a doped thin film channel layer 3207.
叠层中的导体被配置为字线，字线可用于施加输入至NAND类串线路阵列的操作以作为乘积和加速器结构。The conductors in the stack are configured as word lines that can be used to apply input operations to the NAND-like string line array as a product-sum accelerator structure.
图34还绘示了包括如本文所述的可变电阻单元的另一种垂直NAND类结构。在此范例中，这一系列单元耦接于位线3401和源极线3402之间。一堆导体所包含导体被配置为选定栅极3403和3404的导体，以及导体被配置为字线(例如3405a和3405b)。共享浮动栅极结构(例如3406)设置在被配置为字线(例如3405a，3405b)的导体之间。垂直通道结构包括隧穿介电层3408和掺杂半导体核心3409，例如n型掺杂多晶硅，垂直通道结构掺杂表示为可变电阻单元的埋藏式注入电阻。多晶硅间介电层3407将配置为字线的导体从垂直通道结构和浮动栅极来分开。Figure 34 also illustrates another vertical NAND-like structure including variable resistance cells as described herein. In this example, the series of cells is coupled between bit line 3401 and source line 3402. A stack of conductors includes conductors configured as conductors for selected gates 3403 and 3404, and conductors configured as word lines (eg, 3405a and 3405b). Shared floating gate structures (eg, 3406) are disposed between conductors configured as word lines (eg, 3405a, 3405b). The vertical channel structure includes a tunneling dielectric layer 3408 and a doped semiconductor core 3409, such as n-type doped polysilicon, the vertical channel structure doped with a buried implant resistor represented as a variable resistance unit. The interpoly dielectric layer 3407 separates the conductors configured as word lines from the vertical channel structures and the floating gate.
图35绘示了来自图34方块3410的结构。可以看出，垂直通道结构由包含掺杂半导体核心3409和隧穿介电层3408所设置与环绕。导体配置为字线3405a和3405b，以及共享浮动栅极结构3406。多晶硅间介电层3407将配置为字线3405a和3405b的导体从垂直通道结构(包括掺杂半导体核心3409)和共享浮动栅极结构3406来分离，参见Seo，et al.，“A Novel3-D Vertical FG NAND Flash Memory Cell Arrays Using the Separated SidewallControl Gate(S-SCG)for Highly Reliable MLC Operation”，2011IEEE。FIG. 35 shows the structure from block 3410 of FIG. 34 . It can be seen that the vertical channel structure is provided and surrounded by a doped semiconductor core 3409 and a tunneling dielectric layer 3408. The conductors are configured as word lines 3405a and 3405b, and a shared floating gate structure 3406. Interpoly dielectric layer 3407 separates conductors configured as word lines 3405a and 3405b from vertical channel structures (including doped semiconductor core 3409) and shared floating gate structure 3406, see Seo, et al., "A Novel 3-D Vertical FG NAND Flash Memory Cell Arrays Using the Separated SidewallControl Gate (S-SCG) for Highly Reliable MLC Operation", 2011IEEE.
利用可变电阻单元的乘积和阵列实施例可以具有非常大的阵列，其包括具有数千或数百万个可变电阻单元阵列。被用于大规模2D和3D NAND装置的制造技术可以被应用，制造技术所具有的附加步骤用于埋藏式注入电阻或其他电阻结构，如图10A、图10B和图27-图36所示的NAND类结构中实施于大量乘积和阵列的制造。用以应用写入(编程和擦除)权重至可编程电阻单元的操作技术，类似于那些使用大规模NAND装置的操作技术。如上所述，可编程电阻单元可以被操作于仿真模式。在仿真模式中，用于感测电路和信号路由的外围电路可能很复杂。Product and array embodiments utilizing variable resistive cells can have very large arrays, including arrays with thousands or millions of variable resistive cells. Manufacturing techniques used for large scale 2D and 3D NAND devices can be applied with additional steps for buried implant resistors or other resistive structures, as shown in Figures 10A, 10B and 27-36 NAND-like structures are implemented in the manufacture of large numbers of products and arrays. The operating techniques used to apply write (program and erase) weights to programmable resistive cells are similar to those using large scale NAND devices. As described above, the programmable resistance cell can be operated in an emulation mode. In emulation mode, peripheral circuits for sensing circuits and signal routing can be complex.
外围电路可由可编程电阻单元配置于单元阵列中而被简化，以用“二进制”模式来操作。可编程阈值晶体管可以储存二进制状态。施加于行的电流可以是常数，或是施加固定数量的二进制级。可编程电阻单元中的电阻在整个阵列中可以是常数，或者实施于固定数量的二进制级电阻。The peripheral circuits can be simplified by configuring programmable resistive cells in a cell array to operate in a "binary" mode. Programmable threshold transistors can store binary states. The current applied to the row can be constant, or a fixed number of binary levels can be applied. The resistances in the programmable resistance cells can be constant throughout the array, or implemented as a fixed number of binary-level resistances.
二进制模式操作可通过减少需要编程于单元中阈值的可编程算法的复杂性来允许外围电路的简化，电流源用于施加电流至阵列中的行，以及感测电路用于产生输出值。Binary mode operation may allow for simplification of peripheral circuits by reducing the complexity of programmable algorithms that need to program thresholds in cells, current sources for applying current to rows in the array, and sense circuits for generating output values.
图11A表示出了单一可编程电阻单元的电路示意图。图11B可通过每单位一位中的单元操作、二进制模式来提供了1V曲线(电流-电压曲线)而被理解。单元作为载流节点600和601。输入节点602连接到如上所述的可编程晶体管栅极。单元中并联电阻的电阻设置为一数值Rmn，其中m对应于单元的列，并且n对应于单元的行。FIG. 11A shows a schematic circuit diagram of a single programmable resistance unit. FIG. 11B can be understood by the cell operation in one bit per unit, the binary mode provides a 1V curve (current-voltage curve). The cells act as current-carrying nodes 600 and 601 . Input node 602 is connected to the programmable transistor gate as described above. The resistance of the parallel resistors in the cell is set to a valueRmn , where m corresponds to the column of the cell and n corresponds to the row of the cell.
图11B表示了两个电压对电流曲线图。第一电压对电流曲线对应于“1”单元权重Wmn，其中单元具有低阈值Vt。第二曲线对应于“0”单元权重Wmn，其中单元具有高阈值Vt。当输入值低，因此低Vt大于输入电压，单元中的晶体管关闭，并且对于单元的二进制权重传导非常低的电流。当输入值高时，低Vt小于输入电压，输入电压小于高Vt，若对应到低Vt单元的权重为“1”，则单元中的晶体管导通，以及若对应到高Vt单元的权重为“0”，则单元中的晶体管截止。Figure 11B shows two graphs of voltage versus current. The first voltage versus current curve corresponds to a "1" cell weightWmn , where the cell has a low thresholdVt . The second curve corresponds to a "0" cell weightWmn , where the cell has a high thresholdVt . When the input value is low, and therefore the lowVt is greater than the input voltage, the transistors in the cell turn off and conduct very low current for the binary weight of the cell. When the input value is high, the lowVt is less than the input voltage, and the input voltage is less than the highVt , if the weight corresponding to the lowVt cell is "1", the transistor in the cell is turned on, and if the weight corresponding to the highVt cell is "1" The weight is "0", the transistor in the unit is turned off.
当晶体管截止时，由流经电阻I*Rmn的电流造成的电压降所支配的较大电压降VdLg被诱发。当晶体管导通时，由流经晶体管通道的电流造成的电压降所支配的较小的电压降VdSm被诱发，可视为接近于0V的较小的电压降VdSm由电流通过晶体管沟道引起的电压降所支配。这种关系由下面的表格1来说明。When the transistor is turned off, a larger voltage drop VdLg is induced, dominated by the voltage drop caused by the current flowing through the resistor I*Rmn . When the transistor is turned on, a small voltage drop VdSm dominated by the voltage drop caused by the current flowing through the transistor channel is induced, which can be seen as a small voltage drop VdSm close to 0V caused by the current passing through the transistor channel dominated by the resulting voltage drop. This relationship is illustrated by Table 1 below.
表格1Table 1
二进制操作可以扩展到如图12所示的可变电阻单元串线路。在图12中，三个单元被绘示在n行阵列中的单一串线路上。该行接收固定电流In和各列上的输入值X1至X3。行中的电压降取决于行中各单元的权重W1n、W2n和W3n以及输入值。此范例使用三个独立单元来实现乘积和运算的i从1到3的三个项XiWi，以产生代表总和的电压Vn。Binary operation can be extended to variable resistance cell string lines as shown in Figure 12. In Figure 12, three cells are shown on a single string of lines in an n-row array. The row receives the fixed current In and the input values X1 to X3on each column. The voltage drop in the row depends on the weights W1n , W2n and W3n of the cells in the row and the input value. This example uses three separate cells to implement the three terms Xi Wi of i from 1 to 3 for the sum of products operation to generate a voltage Vn representing the sum.
在第一行中表示出的三个输入变量，以及在表格的第二列中表示出的三个潜在权重，并且假设每个单元的固定电流和固定电阻值，在行中电压降Vn的变化可在表格2中看到(假设VdSm接近(“～”)于零)。With the three input variables represented in the first row, and the three potential weights represented in the second column of the table, and assuming a fixed current and fixed resistance value for each cell, the voltage dropVn in the row The change can be seen in Table 2 (assuming VdSm is close ("~") to zero).
表格2Form 2
通过依据这四个Vn电平来设置感测参考电压，可以将遍布行的电压转换为0和3之间的数字输出，如下面的表3所示。By setting the sense reference voltage in accordance with these fourVn levels, the voltage across the row can be converted to a digital output between 0 and 3, as shown in Table 3 below.
表格3Form 3
随着提供唯一输入的列数和单元行数的增加，阵列可以产生复合乘积和而依赖于单个可编程电阻单元的“二进制”操作(即，将晶体管编程为低阈值或高阈值)。As the number of columns and rows of cells providing unique inputs increases, the array can generate complex sums of products relying on "binary" operation of a single programmable resistive cell (ie, programming transistors to low or high thresholds).
在一些实施例中，多位二进制权重可以储存在阵列中的一些或所有单元中，以增加单元的可编程权重的进一步分辨率。In some embodiments, multi-bit binary weights may be stored in some or all cells in the array to increase the further resolution of the programmable weights of the cells.
图13是可以与配置于乘积和运算的可变电阻单元阵列，与如上所述的电压感测一起使用的感测电路方框图。该范例中的感测电路包括实施于使用运算放大器的范例或其他类型比较器的感测放大器650。感测放大器650的输入包括在线652上的电压Vn和参考电压Vref。电压Vn在选定行上产生，并且可以通过缓冲器651来传送。缓冲器651可实施于配置在运算放大器的单位增益的范例或电压放大器的电压。线652上的参考电压Vref由参考电压电路655提供，参考电压电路655被配置于通过对应于由感测放大器650响应于线656上序列信号所区分的各电压电平的一组参考电压的序列。参考电压电路655可以接收输入电压Vmax和Vmin，参考电压电路655可以决定在线652上产生的最小和最大电压为参考电压Vref。13 is a block diagram of a sensing circuit that may be used with an array of variable resistor cells configured for sum-of-products operations with voltage sensing as described above. The sense circuit in this example includes a sense amplifier 650 implemented in an example using an operational amplifier or other types of comparators. Inputs to sense amplifier 650 include voltageVn on line 652 and reference voltageVref . The voltageVn is developed on the selected row and can be delivered through buffer 651 . The buffer 651 may be implemented in a unity-gain example configured at an operational amplifier or at the voltage of a voltage amplifier. The reference voltageVref on line 652 is provided by reference voltage circuit 655 configured to pass through a set of reference voltages corresponding to the voltage levels differentiated by sense amplifier 650 in response to the sequence signal on line 656. sequence. The reference voltage circuit 655 may receive the input voltages Vmax and Vmin , and the reference voltage circuit 655 may determine the minimum and maximum voltages generated on the line 652 as the reference voltage Vref .
图13A是感测操作的原理图。图14电路的特定电压Vmax和Vmin在多级中可以产生具有如图表所示的感测范围的参考电压。在阵列中选定行上产生的电压Vn可以落在感测范围内的电平，电压Vn具有不同于上述电压Vmin的电压。感测电路决定电压Vn的电平。在这种情况下，电压Vn高于各参考电压V1至V5而低于参考电压V6。因此，可以指定对应于参考电压V6的电压数值Vn。13A is a schematic diagram of a sensing operation. The specific voltages Vmax and Vmin of the circuit of FIG. 14 can generate reference voltages in multiple stages with a sensing range as shown in the graph. The voltageVn developed on the selected row in the array may fall at a level within the sensing range, the voltageVn having a different voltage than the aforementioned voltageVmin . The sensing circuit determines the level of the voltageVn . In this case, the voltageVn is higher than the respective reference voltages V1 toV5 and lowerthan the reference voltageV6 . Therefore, a voltage valueVn corresponding to the reference voltageV6 can be specified.
感测放大器650的输出包括与输入参考电压电平相对应的信号排序。这些信号可以储存于缓存器660，缓存器660被提供至算术逻辑单元661或其他类似的通用处理器，其中算术运算可以进一步执行乘积和运算。例如，依据如下所讨论的可编程电阻单元阵列是如何配置，以使产生在阵列的多个行上的输出可以组合于产生乘积和运算的单一项的目的。The output of sense amplifier 650 includes a signal ordering corresponding to the input reference voltage level. These signals may be stored in a buffer 660, which is provided to an arithmetic logic unit 661 or other similar general-purpose processor, where the arithmetic operations may further perform sum-of-products operations. For example, depending on how the array of programmable resistive cells is configured as discussed below, outputs generated on multiple rows of the array may be combined for the purpose of generating a single term for a sum-of-product operation.
图14是可以与如图13所安排的感测放大器装置一起使用的参考电压电路的方框图。在图14中，可编程电阻单元阵列中一个参考行或多个参考行665，或是使用如那些应用于阵列中的单元结构，可以安排至提供电压Vmax和Vmin之一或两者。此范例的电压Vmax和Vmin被施加到电阻分压器666，电阻分压器666在电阻分压器666中电阻之间的节点处产生多个参考电压电平。响应于参考电压电平的节点耦接到选择器667。耦接到图13配置中的感测放大器650的选择器667响应于线656上的序列信号，以在线652上提供一序列的参考电压Vref。FIG. 14 is a block diagram of a reference voltage circuit that may be used with the sense amplifier arrangement as arranged in FIG. 13 . In Figure 14, a reference row or reference rows 665 in an array of programmable resistive cells, or using cell structures such as those applied in the array, may be arranged to provide either or both of the voltagesVmax andVmin . The voltagesVmax andVmin of this example are applied to a resistive divider 666 that produces a number of reference voltage levels at nodes in resistive divider 666 between the resistors. The node responsive to the reference voltage level is coupled to selector 667 . Selector 667 coupled to sense amplifier 650 in the configuration of FIG. 13 is responsive to the sequence signal on line 656 to provide a sequence of reference voltages Vref on line 652 .
图15绘示了配置于产生电压Vmin目的的参考行的一种配置，该配置可用于如图13和图14的参考所描述在应用于感测电路中产生参考电压的目的。在此范例中，n行上的三个单元操作串线路680被配置于乘积和运算，其中该单元具有输入X1到X3以及权重W1n，W2n和W3n。该权重依据乘积和运算项被编程到操作串线路680中，以被执行。由流经串线路的电流In所产生的电压表示为Vn。FIG. 15 illustrates one configuration of a reference row configured for the purpose of generating the voltageVmin , which may be used for the purpose of generating a reference voltage in a sensing circuit as described with reference to FIGS. 13 and 14 . In this example, three cells on row n operate string lines 680 configured for a sum-of-products operation, where the cell has inputs X1 to X3 and weights W1n , W2n and W3n . The weights are programmed into the operation string line 680 to be executed in accordance with the sum-of-products term. The voltage produced by the current In flowing through the string lineis denotedVn .
行参考串线路681实施于阵列中，行参考串线路681使用三个单元，该三个单元可具有匹配于操作串线路680中所使用的那三个单元的电特性。为了产生电压Vmin，在行参考串线路681表示为W1ref，W2ref和W3ref的单元权重都被设定成对应于低阈值状态的数值(在这种情况下为“1”)。行参考串线路681中单元的输入被绑在一起，并在操作期间耦接到电压VON，以使行参考串线路681中的所有单元都导通，并产生小电压降VdSm。因此，在此范例中电压Vmin约等于3*VdSm，或是在操作串线路680中使用的单位单元的小电压降的三倍。下面的表格4绘示了用于特定输入和操作串线路的权重配置(计算行)和参考行的操作范例。Row reference string lines 681 are implemented in the array using three cells that may have electrical characteristics that match those used in operating string lines 680 . To generate the voltageVmin , the cell weights forW1ref ,W2ref andW3ref are all set to the value corresponding to the low threshold state ("1" in this case) on the row reference string line 681. The inputs of the cells in row reference string line 681 are tied together and coupled to voltage VON during operation to turn on all cells in row reference string line 681 and produce a small voltage drop VdSm . Thus, the voltageVmin is approximately equal to 3*VdSm in this example, or three times the small voltage drop of the unit cell used in operating the string line 680. Table 4 below shows an example of the operation of the weight configuration (calculation row) and reference row for a particular input and operation string line.
表格4Form 4
在参考串线路仅用于产生Vmin的实施例中，用于参考电压电路的数值Vmax可以被设定为足够高的数值，以提供良好的操作幅度于装置。图15所绘示的范例是依据包括三个可变电阻单元的串线路。In embodiments where the reference string line is only used to generateVmin , the valueVmax for the reference voltage circuit can be set to a value high enough to provide a good operating range for the device. The example shown in FIG. 15 is based on a string line including three variable resistance units.
在本技术的实施例中，可变电阻单元可实施于使用NAND类技术的大规模阵列。因此，耦接到串线路中的任何特定的行单元可具有例如16、32、64或更多个单元。在任何特定乘积和运算的配置中，少于特定行中的所有单元可被使用。In embodiments of the present technology, variable resistance cells may be implemented in large scale arrays using NAND-like technology. Thus, any particular row of cells coupled into a string line may have, for example, 16, 32, 64 or more cells. In any particular configuration of product-sum operations, less than all cells in a particular row may be used.
图16绘示了包括在操作行和参考行上的区域692中具有多个未使用单元的操作行中操作行n和参考串线路691的操作串线路690的示例配置。此范例中参考行被配置于产生电压Vmin的目的，其可以被用作如图13和图14的参考所描述于应用在感测电路中产生参考电压的目的。16 illustrates an example configuration of an operation string line 690 including operation row n and reference string line 691 in an operation row having a plurality of unused cells in the region 692 on the operation row and reference row. The reference row in this example is configured for the purpose of generating the voltageVmin , which can be used for the purpose of generating the reference voltage in the sensing circuit as described with reference to FIGS. 13 and 14 .
在所示的范例中，操作行n上的三个单元操作串线路690被配置于乘积和运算，其中操作串线路690上的单元具有输入X1到X3以及权重W1n，W2n和W3n。这些权重依据乘积和运算项，被编程到操作串线路690中，以被执行。操作行n上未使用的单元为特定输入Y1和Y2以及权重W4n和W5n。由流经串线路的电流In所产生的电压表示为Vn。输入Y1和Y2以及权重W4n和W5n被配置，以便在乘积和运算期间操作行n中的未使用单元为导通。In the example shown, three cells on row n are configured for a sum-of-product operation, where cells on string line 690 have inputs X1 to X3 and weights W1n , W2n and W3n . These weights are programmed into the operation string circuit 690 to be executed in accordance with the product and operation terms. Unused cells on operation row n are specific inputs Y1 and Y2 and weights W4n and W5n . The voltage produced by the current In flowing through the string lineis denotedVn . Inputs Y1 and Y2 and weights W4n and W5n are configured so that unused cells in operating row n are turned on during the sum-of-products operation.
参考串线路691实施于阵列中或参考阵列中，在参考行中使用三个单元的参考串线路691可具有匹配于用在操作串线路690中那三个单元的电特性。参考行上包括参考串线路691的未使用单元具有权重W4ref和W5ref。为了产生电压Vmin，参考串线路691中的单元权重表示为W1ref、W2ref和W3ref，以及在行的未使用部分中具有权重W4ref和W5ref的单元权重都被设定为对应于低阈值状态的数值(在这种情况下“1”)。参考行上的区域692中行的未使用部分中参考串线路691的单元中的电阻可以具有一固定值R。该电阻匹配数值R于操作串线路690中的单元以及在同行中参考行上的区域692的单元数值R是操作串线路690。在操作期间参考串线路691中包括未使用单元的单元输入被绑在一起并且耦接到电压VON，使得行中包括参考串线路691的所有单元都导通，并产生小电压降VdSm。因此，在该范例的串线路中具有五个单元的电压Vmin约等于5*VdSm，或是操作串线路680中使用的单位单元的小电压降的五倍。随着串线路中有更多单元，Vmin值将相应地转移。Reference string lines 691 are implemented in an array or reference array, and reference string lines 691 using three cells in a reference row may have electrical characteristics that match those three cells used in operating string lines 690 . Unused cells on the reference row including reference string line 691 have weightsW4ref andW5ref . To generate the voltageVmin , the cell weights in the reference string line 691, denotedW1ref ,W2ref , andW3ref , and the cell weights in the unused portion of the row with weightsW4ref andW5ref are all set to correspond to The value of the low threshold state ("1" in this case). The resistance in the cells of the reference string line 691 in the unused portion of the row in the region 692 on the reference row may have a fixed value R. The resistance matching value R to the cell in the operating string line 690 and the cell value R of the region 692 on the reference line in the same row is the operating string line 690 . Cell inputs including unused cells in reference string line 691 are tied together and coupled to voltage VON during operation so that all cells in a row including reference string line 691 are turned on and produce a small voltage drop VdSm . Thus, the voltageVmin with five cells in this example string line is approximately equal to 5*VdSm , or five times the small voltage drop of the unit cells used in operating string line 680 . As there are more cells in the string line, theVmin value will shift accordingly.
下面的表格5绘示了对于图16配置的特定输入和操作串线路的权重配置(计算行)和参考行的操作范例。Table 5 below shows an example of the operation of the weight configuration (calculation row) and reference row for the specific input and operation string lines of the Figure 16 configuration.
表格5Form 5
图17绘示了电压Vmin和Vmax两者被产生的示例配置。在此配置中，操作行n中的操作串线路700包括如图15和图16范例中的三个单元。因此，操作行n被配置于乘积和运算，其中操作串线路700中的单元具有输入X1至X3和权重W1n，W2n和W3n。该权重依据乘积和运算项被编程到操作串线路700中，以被执行。操作行n上未使用单元被表示为输入Y1和Y2以及权重W4n和W5n。由流经串线路的电流In所产生的电压表示为Vn。输入Y1和Y2以及权重W4n和W5n被配置，以在乘积和运算期间操作行n中的未使用单元为导通。FIG. 17 shows an example configuration in which both voltagesVmin andVmax are generated. In this configuration, the operation string line 700 in operation row n includes three cells as in the example of FIGS. 15 and 16 . Thus, operation row n is configured for a sum-of-product operation, where cells in operation string line 700 have inputs X1 to X3 and weights W1n , W2n and W3n . The weights are programmed into the operation string circuit 700 to be executed in accordance with the sum-of-products term. Unused cells on operation row n are represented as inputs Y1 and Y2 and weights W4n and W5n . The voltage produced by the current In flowing through the string lineis denotedVn . Inputs Y1 and Y2 and weights W4n and W5n are configured to turn on unused cells in operating row n during sum-of-products operations.
在阵列区域703中Vmin参考行包括参考串线路701和未使用的单元。参考串线路701包含可具有匹配于用在操作串线路700中那三个单元的电特性。Vmin参考行上的未使用单元包括参考串线路691权重W4Lref和W5Lref。为了产生电压Vmin，参考串线路701中的单元权重表示为W1Lref、W2Lref和W3Lref，以及在行的未使用部分中具有权重W4Lref和W5Lref的未使用单元的权重都被设定为对应于低阈值状态的数值(在这种情况下“1”)。在参考串线路701的单元和行的未使用部分中的电阻可以具有一固定值R。该电阻匹配数值R于操作串线路700中的单元以及在阵列区域703的单元数值R是操作行n。在操作期间的Vmin参考行中包含参考串线路701和未使用单元的单元输入被绑在一起并且耦接到电压VON，使得在Vmin参考行中包括参考串线路701的所有单元都导通，并假设Iref等于In，以产生小电压降VdSm。因此，在该范例的串线路中具有五个单元的电压Vmin约等于5*VdSm，或是操作串线路700中使用的单位单元的小电压降的五倍。随着串线路中有更多单元，Vmin值将相应地转移。TheVmin reference row in array area 703 includes reference string lines 701 and unused cells. Reference string line 701 contains electrical characteristics that may be matched for those three cells used in operating string line 700 . Unused cells on theVmin reference row include reference string line 691 weightsW4Lref andW5Lref . To generate the voltageVmin , the cell weights in the reference string line 701, denotedW1Lref ,W2Lref , andW3Lref , and the weights of unused cells in the unused portion of the row with weightsW4Lref andW5Lref are all set is the value corresponding to the low threshold state ("1" in this case). Resistors in unused portions of cells and rows of reference string line 701 may have a fixed value R. The resistance matching value R for the cells in the operation string line 700 and the cell value R in the array area 703 is the operation row n. Cell inputs containing reference string line 701 and unused cells in theVmin reference row during operation are tied together and coupled to voltageVON such that all cells in theVmin reference row that contain reference string line 701 conduct on, and assumingIrefis equal to In to produce a small voltage drop VdSm . Thus, the voltageVmin with five cells in this example string line is approximately equal to 5*VdSm , or five times the small voltage drop of the unit cells used in operating string line 700 . As there are more cells in the string line, theVmin value will shift accordingly.
在阵列区域703中Vmax参考行包括参考串线路702和未使用的单元。参考串线路702包含可具有匹配于用在操作串线路700中那三个单元的电特性。Vmax参考行上包括参考串线路702的未使用单元权重和为了产生电压Vmax，参考串线路702中的单元权重表示为和以及在Vmax参考行的未使用部分中具有权重和的未使用单元的权重在Vmin行中都被设定为对应于高阈值状态的数值(在这种情况下“0”)。在参考串线路701的单元和行的未使用部分中的电阻可以具有一固定值R。该电阻匹配数值R于操作串线路700中的单元以及在阵列区域703的单元数值R是操作行n。在操作期间Vmax参考行中包含参考串线路702的单元输入被绑在一起并且耦接到电压VOFF，以及未使用部分耦接到电压VON，使得在行的三个单元中包括Vmax参考串线路701的晶体管都导通，并假设Iref等于In，以产生大电压降VdLg。因此，在此范例的串线路中具有五个单元的电压Vmax约等于3*VdLg，或是操作串线路700中使用的单位单元的大电压降的三倍。随着串线路中有更多单元，Vmax值将相应地转移。The Vmax reference row in array area 703 includes reference string lines 702 and unused cells. Reference string line 702 includes electrical characteristics that may be matched for those three cells used in operating string line 700 . Unused cell weights for reference string lines 702 are included on the Vmax reference line and To generate the voltage Vmax , the cell weights in the reference string line 702 are denoted as and as well as having weights in the unused part of theVmax reference row and The weights of unused cells in theVmin row are all set to the value corresponding to the high threshold state ("0" in this case). Resistors in unused portions of cells and rows of reference string line 701 may have a fixed value R. The resistance matching value R for the cells in the operation string line 700 and the cell value R in the array area 703 is the operation row n. During operation, the inputs of cells in theVmax reference row containing reference string line 702 are tied together and coupled to voltageVOFF , and the unused portion is coupled to voltageVON , such thatVmax is included in the three cells of the row The transistors of the reference string line 701 are all on, assumingIrefis equal to In, to produce a large voltage dropVdLg . Thus, the voltage Vmax with five cells in the string line of this example is approximately equal to 3*VdLg , or three times the large voltage drop of the unit cells used in operating string line 700 . As there are more cells in the string line, theVmax value will shift accordingly.
下面的表格6绘示了对于图17配置的特定输入和操作串线路的权重配置(计算行)和参考行的操作范例。Table 6 below shows an example of the operation of the weight configuration (calculation row) and reference row for the specific input and operation string lines of the Figure 17 configuration.
表格6Form 6
在参考图12和图15-图17描述的实施例中，可编程电阻单元阵列被配置成具有一输入Xi的功能组，并且包括一个成员单元，操作行中各单元实施于具有一位二进制权重Wi的项XiWi，XiWi由单元中的可编程阈值晶体管的阈值来决定。单元中电阻器的电阻R和串线路中的电流In是常数。In the embodiment described with reference to Figures 12 and 15-17, the programmable resistor cell array is configured as a functional group with an input Xi and includes a member cell, each cell in the operating row is implemented in a binary with one bit The terms Xi Wi, Xi Wi of the weight Wi aredetermined by the thresholds of the programmable threshold transistors in the cell. The resistanceR of the resistors in the cell and the current In in the string line are constant.
在一些实施例中，可编程电阻单元阵列可被配置成具有一个输入和多个成员的功能组，以实施乘积和运算的项XiWi，其中使用编程于单元中可编程晶体管中的单一位值的权重Xi可以是除了一二进制元“0”或“1”之外的值，例如多位二进制值。In some embodiments, an array of programmable resistive cells can be configured as a functional group with one input and multiple members to implement the terms Xi Wi of a sum-of-product operation using a single programmed in the programmable transistors in the cells The weight Xi of the bit value may be a value other than a binary "0" or "1", such as a multi-bit binary value.
图18-图22绘示了实现多位二进制值的功能组的一些范例配置。18-22 illustrate some example configurations of functional groups implementing multi-bit binary values.
图18绘示了在阵列的n行中的单一串线路上包括三个成员单元功能组。该行接收固定电流In。输入值Xm连接到所有三列中的单元中的晶体管栅极。在此范例中，组中三个单元中的电阻器R1，mn、R2，mn和R3，mn的电阻是不同的。因此，电阻器R3具有电阻R，电阻器R2具有电阻2*R，以及电阻器R1具有电阻4*R。因此，依据从0*R(功能组中的所有晶体管导通)至7*R(功能组中的所有晶体管截止)不等的有效电阻所产生的组合的功能组权重具有一个三位二进制值，范围从0到7。使用图18功能组来实现的乘积和运算项可以表示为Xm(W1*4R+W2*2R+W3*R)。在其他实施例中，如图18单元中的单元功能组可以具有多于三个成员，三个成员与共同输入Xm连接于行中。Figure 18 illustrates the inclusion of three member cell functional groups on a single string of lines in n rows of the array. The row receives a fixed currentIn . The input valueXm is connected to the transistor gates in the cells in all three columns. In this example, the resistances of resistors R1,mn , R2,mn and R3,mn in the three cells in the group are different. Thus, resistorR3 has resistance R, resistor R2 has resistance2 *R, and resistor R1 has resistance4 *R. Therefore, the combined functional group weights have a three-bit binary value based on effective resistances ranging from 0*R (all transistors in the functional group on) to 7*R (all transistors in the functional group are off), The range is from 0 to 7. The sum-of-products term implemented using the functional group of Figure 18 can be expressed as Xm (W1 *4R+W2 *2R+W3 *R). In other embodiments, a unit function group such as in the unit of FIG. 18 may have more than three members, three of which are connected in a row with a common inputXm .
如上所讨论的单元阵列可以使用逻辑电路来配置于实现乘积和运算，如上所讨论的单元阵列可以使用多个功能组来配置于运算项的形成。Cell arrays, as discussed above, may be configured using logic circuits to implement sum-of-products operations, and cell arrays, as discussed above, may be configured using multiple functional groups for the formation of operands.
图19绘示了阵列的三个不同行n1，n2和n3上一列阵列中包括三个成员单元的功能组。三行中的每一行接收固定电流In。输入值Xm连接到列中单元中的晶体管栅极。在此范例中，组中的三个单元中电阻器的电阻R1，mn、R2，mn和R3，mn是不同的。因此，电阻器R3具有电阻R，电阻器R2具有电阻2*R，以及电阻器R1具有电阻4*R。在各行中产生的电压Vn1，Vn2和Vn3总和于外围电路，以提供总和输出项。FIG. 19 illustrates a functional group comprising three member cells in a column array on three different rows n1 , n2 and n3 of the array. Each of the three rows receives a fixed currentIn . The input valueXm is connected to the gates of the transistors in the cells in the column. In this example, the resistances R1,mn , R2,mn and R3,mn of the resistors in the three cells in the group are different. Thus, resistorR3 has resistance R, resistor R2 has resistance2 *R, and resistor R1 has resistance 4*R. The voltagesVn1, Vn2 and Vn3generatedin each row are summed in peripheral circuits to provide a summed output term.
使用图19的功能组所实施的乘积和运算项可以表示为Xm(W1*I4R+W2*I2R+W3*IR)，其具有产生代表项的一部分电压的各行。因此，依据从0*IR(功能组中的所有晶体管导通)至7*IR(功能组中的所有晶体管截止)不等的电压所产生的组合的功能组权重具有一个三位二进制值，范围从0到7。The sum-of-products term implemented using the functional group of Figure 19 can be represented asXm (W1* I4R+ W2*I2R+W3*IR) with rows that generate a voltage representing a portion of the term. Thus, the combined functional group weights have a three-bit binary value in terms of voltages ranging from 0*IR (all transistors in the functional group on) to 7*IR (all transistors in the functional group are off) From 0 to 7.
配置于执行总和的周围电路可包括模拟总和放大器或数字逻辑。在一个范例中，各行上的电压可以依次被感测，并且添加于算术逻辑中的每个感测步骤结果如图13所示的范例。The surrounding circuitry configured to perform the summation may include analog summing amplifiers or digital logic. In one example, the voltages on each row can be sensed sequentially, and each sensing step added to the arithmetic logic results in the example shown in FIG. 13 .
在其他实施例中，如图19阵列中的单元功能组可以具有多于三个成员，三个成员与共同输入Xm连接于行中。In other embodiments, the unit function group as in the array of Figure 19 may have more than three members, three members connected in a row with a common inputXm .
图20绘示了阵列的三个不同行n1、n2和n3上一列阵列中包括三个成员单元的功能组。输入值Xm连接到列中单元中的晶体管栅极。在此范例中，组中的三个单元中电阻器的电阻R1，mn、R2，mn和R3，mn是相同的，三行中的每一行接收不同的固定电流In。因此，电流源提供具有电流I的I3至行3，电流源提供具有电流2*I的I2至行2，以及电流源提供具有电流4*I的I1至行1。在功能组的行中产生的电压Vn1、Vn2和Vn3被总和至外围电路，以提供总和输出项。因此，依据从0*IR(功能组中的所有晶体管导通)至7*IR(功能组中的所有晶体管截止)不等的输出所产生的组合的功能组权重具有一个三位二进制值，范围从0到7。Figure 20 illustrates a functional group comprising three member cells in a column array on three different rows n1, n2 and n3 of the array. The input valueXm is connected to the gates of the transistors in the cells in the column. In this example, the resistances R1,mn , R2,mn and R3,mnof the resistors in the three cells in the group are the same, and each of the three rows receives a different fixed current In. Thus, the current source provides I3 with current I to row 3, the current source provides I2 with current 2*I to row 2, and the current source provides I1 with current 4*I to row 1. The voltagesVn1, Vn2, and Vn3generatedin the rows of the functional groups are summed to the peripheral circuit to provide a summed output term. Thus, the combined functional group weights have a three-bit binary value in terms of outputs ranging from 0*IR (all transistors in the functional group on) to 7*IR (all transistors in the functional group off) From 0 to 7.
使用图20的功能组所实施的乘积和运算项可以表示为Xm(W1*4IR+W2*2IR+W3*IR)，其具有产生代表项的一部分电压的各行。The sum-of-products term implemented using the functional group of Figure 20 can be denoted asXm (W1* 4IR+ W2*2IR +W3*IR) with rows producing a voltage representing a portion of the term.
被配置于执行总和的外围电路可包括模拟总和放大器或数字逻辑。在一个范例中，各行上的电压可以依次被感测，并且添加于算术逻辑中的每个感测步骤结果如图13所示的范例。Peripheral circuits configured to perform summation may include analog summing amplifiers or digital logic. In one example, the voltages on each row can be sensed sequentially, and each sensing step added to the arithmetic logic results in the example shown in FIG. 13 .
在其他实施例中，如图20阵列中的单元功能组可以具有多于三个成员，三个成员与共同输入Xm连接于行中。In other embodiments, the unit functional group as in the array of Figure 20 may have more than three members, three members connected in a row with a common inputXm .
图21绘示了阵列的三个不同行n1、n2和n3上一列阵列中包括三个成员单元的功能组。输入值Xm连接到列中单元中的晶体管栅极。在此范例中，组中的三个单元中的电阻器的电阻R1，mn、R2，mn和R3，mn是相同的，三行中的每一行接收不同的固定电流In，在功能组的行中产生的电压Vn1、Vn2和Vn3分别被除以4、2和1，然后总和于外围电路，以提供总和输出项。因此，依据从0*IR(功能组中的所有晶体管导通)至7*IR(功能组中的所有晶体管截止)不等的输出所产生的组合的功能组权重具有一个三位二进制值，范围从0到7。Figure 21 illustrates a functional group comprising three member cells in a column array on three different rows n1, n2 and n3 of the array. The input valueXm is connected to the gates of the transistors in the cells in the column. In this example, the resistances R1,mn , R2,mn and R3,mnof the resistors in the three cells in the group are the same, and each of the three rows receives a different fixed current In, at The voltagesVn1, Vn2, and Vn3generatedin the rows of the functional group are divided by 4, 2, and 1, respectively, and then summed in peripheral circuits to provide a summed output term. Thus, the combined functional group weights have a three-bit binary value in terms of outputs ranging from 0*IR (all transistors in the functional group on) to 7*IR (all transistors in the functional group off) From 0 to 7.
使用图21的功能组所实施的乘积和运算项可以表示为Xm(W1*4IR+W2*2IR+W3*IR)，其具有产生被分成外围电路的电压的各行以代表项的一部分。The sum-of-products term implemented using the functional group of FIG. 21 can be represented asXm (W1* 4IR+ W2*2IR +W3*IR) with rows that generate voltages divided into peripheral circuits to represent the terms of part.
配置于执行总和的周围电路可包括模拟总和放大器或数字逻辑。在一个范例中，各行上的电压可以依次被感测，并且添加于算术逻辑中的每个感测步骤结果如图13所示的范例。The surrounding circuitry configured to perform the summation may include analog summing amplifiers or digital logic. In one example, the voltages on each row can be sensed sequentially, and each sensing step added to the arithmetic logic results in the example shown in FIG. 13 .
在其他实施例中，如图21阵列中的单元功能组可以具有多于三个成员，三个成员与共同输入Xm连接于行中。In other embodiments, the unit functional group as in the array of Figure 21 may have more than three members, three of which are connected in a row with a common input Xm.
图22绘示了阵列的两个不同行n1和n2上包含于一列阵列中的两个单元以及阵列第二列的两个单元的四个成员单元的功能组。输入值Xm连接至功能组的两列的所有单元中的晶体管栅极。在此范例中，组中的四个单元中的电阻器的电阻R1，mn、R2，mn、R3，mn和R4，mn是不同的。因此，电阻器R3和R4具有电阻R，电阻器R1和R2具有电阻4*R。在两行的每一个接收不同的固定电流In。因此，电流源提供具有电流I的I2至行2，电流源提供具有电流2*I的I1至行1。在功能组的两行中产生的电压Vn1、Vn2总和于外围电路，以提供总和输出项。Figure 22 shows a functional group of four member cells of two cells contained in one column of the array and two cells of the second column of the array on two different rowsn1 andn2 of the array. The input valueXm is connected to transistor gates in all cells of both columns of the functional group. In this example, the resistances R1,mn , R2,mn , R3,mn and R4,mn of the resistors in the four cells in the group are different. Therefore, resistors R3 and R4 have resistance R, and resistors R1 and R2 have resistance 4*R. Each of the two rows receives a different fixed currentIn . Thus, the current source provides I2 with current I to row 2, and the current source provides I1 with current 2*I to row 1. The voltagesVn1 ,Vn2 generated in the two rows of the functional group are summed in the peripheral circuit to provide a summed output term.
使用图22的功能组所实施的乘积和运算项可以表示为Xm(W1*2I*4R+W2*I*4R+W3*2I*R+W4*I*R)，其具有产生代表项的一部分电压的各行。因此，依据从0*IR(功能组中的所有晶体管导通)至15*IR(功能组中的所有晶体管截止)不等的输出所产生的组合的功能组权重具有一个四位二进制值，范围从0到15。The sum-of-products term implemented using the functional group of FIG. 22 can be expressed as Xm (W1 *2I*4R+W2 *I*4R+W3 *2I*R+W4 *I*R), which has Rows are generated that represent a portion of the voltage for the term. Therefore, the combined functional group weight has a four-bit binary value, ranging from 0*IR (all transistors in the functional group on) to 15*IR (all transistors in the functional group off) From 0 to 15.
配置于执行总和的周围电路可包括模拟总和放大器或数字逻辑。在一个范例中，各行上的电压可以依次被感测，并且添加于算术逻辑中的每个感测步骤结果如图13所示的范例。The surrounding circuitry configured to perform the summation may include analog summing amplifiers or digital logic. In one example, the voltages on each row can be sensed sequentially, and each sensing step added to the arithmetic logic results in the example shown in FIG. 13 .
在其他实施例中，如图22阵列中单元的功能组可具有多于三个成员，单元的功能组与共同输入Xm连接于行中。In other embodiments, the functional group of cells in the array of FIG. 22 may have more than three members, the functional group of cells being connected in a row with a common input Xm.
其他功能组配置也可以被使用。Other functional group configurations can also be used.
巨大的可编程电阻单元阵列可以配置在操作之间，以执行具有总和项的各种函数的复合乘积和运算，如同各计算执行的所需。此外，总和项的系数(即权重)能以非易失性的形式设置于单元的晶体管中，并且总和项的系数通过如各计算执行所需的编程和擦除操作来改变。A large array of programmable resistive cells can be configured between operations to perform compound product sum operations of various functions with sum terms, as required for each calculation to be performed. Furthermore, the coefficients (ie weights) of the summation terms can be set in the transistors of the cells in a non-volatile form, and the coefficients of the summation terms are changed by programming and erasing operations as required for each calculation execution.
图23是集成电路901的简化芯片方框图，集成电路901包括具有电压感测的乘积和阵列，以及如图5和图6与图10A/图10B所绘示的隐藏通道单元，隐藏通道单元被配置为神经形态的存储器阵列960。Figure 23 is a simplified chip block diagram of an integrated circuit 901 comprising a product-sum array with voltage sensing and a hidden channel cell as depicted in Figures 5 and 6 and Figures 10A/10B, which are configured The memory array 960 is neuromorphic.
字线驱动器940耦接到多个字线945。驱动器包括如在一些实施例中数字模拟转换器产生每个选定线的输入变量x(i)，或者在替代方案中，二进制字线驱动器可以应用于二进制输入。行译码器970经由线965耦接到神经形态的存储器阵列960中的行而排列的一层或多层的串联单元串线路，以用于选择读取乘积和数据串线路与将参数数据写入至神经形态的存储器阵列960。在总线930上来自控制逻辑(控制器)910的地址被提供至行译码器970和字线驱动器940。电压感测放大器经由线975耦接到行译码器，并且电压感测放大器依次耦接到缓冲电路980。施加负载电流In的电流源与感测电路耦接。编程缓冲器可以包含于缓冲电路980中的感测放大器中，以储存编程数据于单元中的编程阈值晶体管的两级或多级编程。此外，控制逻辑910可以包括用于选择性地使用编程以及禁止阵列中的串线路电压以响应于编程缓冲器中的编程数据值的电路。The word line driver 940 is coupled to the plurality of word lines 945 . The driver includes as in some embodiments a digital-to-analog converter to generate the input variable x(i) for each selected line, or in the alternative, a binary word line driver may be applied to the binary input. Row decoder 970 is coupled via line 965 to one or more layers of serial cell string lines arranged in rows in neuromorphic memory array 960 for selecting read product and data string lines and writing parameter data into the neuromorphic memory array 960. Addresses from control logic (controller) 910 on bus 930 are provided to row decoders 970 and word line drivers 940 . The voltage sense amplifier is coupled to the row decoder via line 975, and the voltage sense amplifier is in turn coupled to buffer circuit 980. A current source applying the load current Inis coupled to the sensing circuit. A programming buffer may be included in a sense amplifier in buffer circuit 980 to store programming data for two- or multi-level programming of programming threshold transistors in cells. Additionally, control logic 910 may include circuitry for selectively using programming and disabling string line voltages in the array in response to programmed data values in the programming buffer.
来自感测放大器的感测数据经由第二数据线985被提供至数据缓冲器990，数据缓冲器990经由数据路径993依次耦接到输入/输出电路991。感测放大器可包括被配置于施加单位增益或期望增益水平的运算放大器，以及提供模拟信号至数字模拟转换器或其他信号处理或信号路由电路。附加的算术单元和路由电路可以被包含，以提供于神经形态电路中多层单元串线路的排列。The sense data from the sense amplifier is provided via the second data line 985 to the data buffer 990 , which is in turn coupled to the input/output circuit 991 via the data path 993 . The sense amplifier may include an operational amplifier configured to apply unity gain or a desired gain level, and provide an analog signal to a digital-to-analog converter or other signal processing or signal routing circuit. Additional arithmetic units and routing circuits may be included to provide arrangements of multi-layered string lines in neuromorphic circuits.
此外，算术单元和路由电路可以被包含，以提供于矩阵乘法单元中的串线路层排列。Additionally, arithmetic units and routing circuits may be included to provide a string line layer arrangement in the matrix multiplication unit.
输入/输出电路991将数据驱动到集成电路901的外部目的地。输入/输出数据和控制信号经由数据总线905移动于输入/输出电路991、控制逻辑910和集成电路901上的输入/输出端口或其他内部数据源或集成电路901外部，例如通用处理器或专用应用电路，或提供由神经形态的存储器阵列960所支持的系统芯片功能的模块之间。Input/output circuitry 991 drives data to external destinations of integrated circuit 901 . Input/output data and control signals move via data bus 905 to input/output circuitry 991, control logic 910 and input/output ports on integrated circuit 901 or other internal data sources or external to integrated circuit 901, such as a general purpose processor or special purpose application circuits, or between modules that provide system-on-a-chip functionality supported by the neuromorphic memory array 960.
在图23所示的范例中，使用偏压配置状态机的控制逻辑910经由电压源来控制通过电压供应所产生或提供的供应电压的应用或在方块920的供应，以用于乘积和读取操作，以及设定参数的参数写入操作，例如由包括电荷俘获单元和浮动栅极单元、擦除、验证和编程偏压的电荷俘获电平所表示的单元权重。控制逻辑910耦接到数据缓冲器990和神经形态的存储器阵列960。In the example shown in FIG. 23, the control logic 910 using the bias configuration state machine controls the application of the supply voltage generated or provided by the voltage supply or the supply at block 920 via the voltage source for the product and read operations, and parametric write operations that set parameters, such as cell weights represented by charge trapping levels including charge trapping cells and floating gate cells, erase, verify, and program biases. Control logic 910 is coupled to data buffer 990 and neuromorphic memory array 960 .
使用本领域已知的专用逻辑电路可以实现控制逻辑910。在替代实施例中，控制逻辑包括通用处理器，控制逻辑可以被实施于同一集成电路上，该集成电路执行计算器程序以控制设备操作。在其他实施例中，专用逻辑电路和通用处理器的组合可用于控制逻辑的实施。Control logic 910 may be implemented using dedicated logic circuits known in the art. In alternative embodiments, the control logic includes a general-purpose processor, which may be implemented on the same integrated circuit that executes computer programs to control device operation. In other embodiments, a combination of special purpose logic circuits and general purpose processors may be used for the implementation of the control logic.
图24-图26绘示了系统1000的配置，系统1000包括使用数据路径控制器1003来互连的存储器阵列1002以及乘积和加速器阵列1001。乘积和加速器阵列1001包括依据上述任何实施例的可编程电阻单元阵列。存储器阵列可包括NAND快闪阵列、SRAM阵列、DRAM阵列、NOR快闪阵列或可与乘积和加速器阵列1001协调使用的其他类型存储器。24-26 illustrate the configuration of a system 1000 that includes a memory array 1002 and a product-sum accelerator array 1001 interconnected using a data path controller 1003. The product-sum accelerator array 1001 includes an array of programmable resistive cells according to any of the embodiments described above. The memory arrays may include NAND flash arrays, SRAM arrays, DRAM arrays, NOR flash arrays, or other types of memory that may be used in conjunction with product sum accelerator array 1001 .
系统可以从如图24所示的系统外接收输入/输出数据，并将数据路由至存储器阵列。数据可以包括用于配置为实现一个或多个乘积和运算项的单元功能组的配置数据、在阵列中用于操作的功能组权重、以及用于乘积和运算的输入值。The system can receive input/output data from outside the system as shown in Figure 24 and route the data to the memory array. The data may include configuration data for functional groups of cells configured to implement one or more sum-of-products terms, functional group weights for operations in the array, and input values for the sum-of-products operation.
如图25所示，来自存储器阵列1002的数据可以被传送到乘积和加速器阵列1001，其利用数据路径控制器1003所使用的直接数据路径可被控制。或者，通过数据路径控制器1003的数据路径可用于将来自存储器阵列1002的数据传送到乘积和加速器阵列1001，如适用于特定实现。As shown in FIG. 25 , data from memory array 1002 can be transferred to product-sum accelerator array 1001 , which can be controlled using the direct data path used by data path controller 1003 . Alternatively, a data path through data path controller 1003 may be used to transfer data from memory array 1002 to product-sum accelerator array 1001, as appropriate for the particular implementation.
如图26所示，来自乘积和加速器阵列的输出数据可以通过数据路径控制器1003施加到系统1000的输入输出数据路径。系统1000的输入输出数据路径可以耦接到处理单元，该处理单元被配置于计算权重，以提供输入并利用乘积和加速器阵列的输出。As shown in FIG. 26, the output data from the product sum accelerator array may be applied to the input and output data paths of the system 1000 through the data path controller 1003. The input and output data paths of the system 1000 may be coupled to a processing unit configured to compute the weights to provide the input and utilize the output of the product sum accelerator array.
此外，来自乘积和加速器阵列1001的输出数据可以通过数据路径控制器1003路由回存储器阵列1002，以用于迭代乘积和运算。Additionally, output data from the product-sum accelerator array 1001 may be routed back to the memory array 1002 through the datapath controller 1003 for iterative sum-of-products operations.
在一些实施例中，包含存储器、乘积和加速器阵列和数据路径逻辑的系统1000可以实施于单一集成电路。此外，系统1000可以包括相同或不同的集成电路、算术逻辑单元、数字信号处理器、通用CPU，状态机以及在计算器处理的执行时被配置于类似乘积和加速器阵列1001的利用。In some embodiments, system 1000 including memory, product and accelerator arrays and data path logic may be implemented on a single integrated circuit. In addition, system 1000 may include the same or different integrated circuits, arithmetic logic units, digital signal processors, general purpose CPUs, state machines, and utilizations that are configured to resemble product sum accelerator arrays 1001 in the execution of computer processing.
一种根据本文描述的任何实施例来使用可编程电阻单元阵列的方法可以使用如图24-图26的系统来执行，使用逻辑实施于同一集成电路，耦接到集成电路，或是执行配置步骤的两者组合，其中阵列中具有各自权重的单元功能组被编程，以及操作步骤，并且该阵列用于产生乘积和数据。A method of using an array of programmable resistive cells according to any of the embodiments described herein may be performed using the systems of FIGS. 24-26, using logic implemented on the same integrated circuit, coupled to an integrated circuit, or performing configuration steps A combination of both, where functional groups of cells with their respective weights in the array are programmed, and operating steps, and the array is used to generate the product sum data.
一种用于操作可变电阻单元阵列以产生乘积和数据的方法包括在阵列中编程具有对应于相应单元的权重因子数值的阈值的可编程阈值晶体管；选择性地施加输入到阵列中的列单元，施加电流至阵列中对应于行单元的一行；以及在阵列中的一行或多行单元上感测电压。A method for operating an array of variable resistance cells to produce sum-of-products data includes programming programmable threshold transistors in the array with thresholds corresponding to weighting factor values of corresponding cells; selectively applying an input to column cells in the array , applying a current to a row of the array corresponding to the row cells; and sensing a voltage on one or more row cells in the array.
这种方法可以包括将阵列中的单元配置成包括一个或多个功能单元组；其中功能组实施代表性的乘积和函数项。每个功能组可以接收相应的输入项，并且可以用权重编程，该权重是功能组的一个或多个功能组的可编程阈值的函数。功能组可以以各种方式配置，例如上述图18-图22的参考。在这种方式中，在阵列中具有被配置于利用一位二进制模式作为个别单元的权重的可编程电阻单元可被配置为具有多位权重的功能组，可以被配置于具有多位权重的功能组。多位权重可以被配置于使用具有不同电阻的各电阻器的单元功能组，在功能组中的相异行上的感测期间使用不同的电流电平，使用算术逻辑去结合在功能组中具有不同权重的各自行上所感测的电压，以及其他如本文所描述的方法。Such a method may include configuring the cells in the array to include one or more groups of functional cells; wherein the functional groups implement representative product and function terms. Each functional group can receive corresponding inputs and can be programmed with weights that are a function of programmable thresholds for one or more functional groups of the functional group. The functional groups may be configured in various ways, such as the reference to Figures 18-22 above. In this manner, programmable resistive cells in the array with weights configured to utilize a one-bit binary pattern as individual cells can be configured as functional groups with multi-bit weights, and can be configured as functional groups with multi-bit weights Group. Multi-bit weights can be configured in functional groups of cells using resistors with different resistances, using different current levels during sensing on distinct rows in the functional group, using arithmetic logic to combine the functions in the functional group with Voltages sensed on respective rows of different weights, and other methods as described herein.
此外，在一些实施例中，系统可以被操作于使用参考行单元来产生行参考电压，或低行参考电压和高行参考电压适用于特定实施方式。该方法可以包括产生感测参考电压以作为一个或多个行参考电压的函数。感测操作可以包括将选定行单元上的电压与感测参考电压进行比较，以产生表示在选定行上电压电平的输出。Furthermore, in some embodiments, the system may be operable to use reference row cells to generate row reference voltages, or a low row reference voltage and a high row reference voltage as applicable to particular implementations. The method may include generating a sense reference voltage as a function of one or more row reference voltages. The sensing operation may include comparing the voltage on the selected row of cells to a sensing reference voltage to generate an output indicative of the voltage level on the selected row.
尽管通过参考上文详述的优选实施方案和实施例公开了本发明，但应理解这些实施例旨在说明而不是限制。预期本领域技术人员将容易想到修改和组合，这些修改和组合将在本发明的精神和所附权利要求的范围内。While the invention has been disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended to be illustrative and not restrictive. It is expected that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will fall within the spirit of the inventions and the scope of the appended claims.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in further detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
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