技术领域technical field
本发明涉及一种时频域转换方法、系统、电子设备和介质。The present invention relates to a time-frequency domain conversion method, system, electronic device and medium.
背景技术Background technique
现场可编程门阵列(Field—Programmable Gate Array，FPGA)是一种高性能数字逻辑器件，其内部含有大量例如显示查找表(Look-Up-Table，LUT)、数字信号处理(DigitalSignal Processing，DSP)和随机存取存储器(random access memory，RAM)等资源，通过硬件描述语言编程开发可实现各类复杂运算。FPGA现在广泛应用于通信、雷达和高性能计算等领域。Field-Programmable Gate Array (FPGA) is a high-performance digital logic device, which contains a large number of internal look-up tables (Look-Up-Table, LUT), digital signal processing (Digital Signal Processing, DSP) and random access memory (random access memory, RAM) and other resources, various complex operations can be realized through hardware description language programming and development. FPGAs are now widely used in communications, radar, and high-performance computing.
传统利用FPGA进行算法开发流程为首先优化算法将运算结构整理成FPGA适合的硬件流水结构，然后通过verilog或者VHDL等硬件编程语言进行软件编程实现。例如在实现时频域转换方法过程中，采用硬件编程语言verilog算法实现。The traditional algorithm development process using FPGA is to first optimize the algorithm and organize the operation structure into a hardware pipeline structure suitable for FPGA, and then implement software programming through hardware programming languages such as verilog or VHDL. For example, in the process of realizing the time-frequency domain conversion method, the hardware programming language verilog algorithm is used to realize it.
但传统FPGA硬件实现流程有诸多缺点，集中表现为三点：一、硬件编程语言算法实现效率低。因为FPGA结构特点，在编写算法时要涉及大量的时序对齐工作，这些时序对齐工作会占据大量代码编写、调试和算法测试时间，从而导致硬件编程语言效率低。二、复杂算法实现能力差。FPGA是由大规模可编程逻辑组成，应用FPGA进行算法处理时它的运算机制与DSP和x86 CPU等冯诺依曼处理器有很大区别，DSP、x86 CPU它们是通过直接存储器访问(Direct Memory Access，DMA)或CPU完成与内存单元的数据交换，而FPGA没有相应的DMA或者CPU单元，它需要设计人员构造数据交换模块实现数据流控制，而在复杂算法中会涉及到大量迭代运算此时复杂的数据流控制会使算法实现过程极其复杂甚至无法实现。三、调试周期长。调试FPGA程序时无法像调试处理器一样用debug模式进行单步调试，它只能用ila、vio等硬件调试核通过抓取FPGA内部寄存器状态进行调试，调试效率会比处理器低很多，而且如果对工程设计进行小规模更改时，FPGA设计需要全面的进行综合实现，FPGA的综合实现也会占用大量时间。However, the traditional FPGA hardware implementation process has many shortcomings, which are concentrated in three points: First, the implementation efficiency of hardware programming language algorithms is low. Because of the structural characteristics of the FPGA, a lot of timing alignment work is involved when writing an algorithm. These timing alignment work will occupy a lot of code writing, debugging and algorithm testing time, resulting in low efficiency of the hardware programming language. Second, the ability to implement complex algorithms is poor. FPGA is composed of large-scale programmable logic. When FPGA is used for algorithm processing, its operation mechanism is very different from Von Neumann processors such as DSP and x86 CPU. DSP and x86 CPU use direct memory access (Direct Memory Access). Access, DMA) or CPU completes data exchange with the memory unit, while FPGA does not have a corresponding DMA or CPU unit, it requires designers to construct a data exchange module to achieve data flow control, and a large number of iterative operations are involved in complex algorithms. Complex data flow control will make the algorithm implementation process extremely complicated or even impossible. Third, the debugging cycle is long. When debugging an FPGA program, you cannot use the debug mode for single-step debugging like debugging a processor. It can only use hardware debugging cores such as ila and vio to debug by grabbing the state of the internal registers of the FPGA. The debugging efficiency will be much lower than that of the processor, and if When making small-scale changes to the engineering design, the FPGA design needs to be fully synthesized, and the FPGA synthesis implementation can also take a lot of time.
发明内容SUMMARY OF THE INVENTION
本发明的一个方面提供了一种时频域转换方法，所述方法包括：FPGA接收原始数据，并将所述原始数据发送至MicroBlaze软核处理器；MicroBlaze软核处理器采用浮点FFT算法对所述原始数据进行时频域转换得到运算结果，并将所述运算结果发送至FPGA。One aspect of the present invention provides a time-frequency domain conversion method, the method includes: an FPGA receives raw data, and sends the raw data to a MicroBlaze soft-core processor; the MicroBlaze soft-core processor uses a floating-point FFT algorithm to The original data is converted in the time-frequency domain to obtain an operation result, and the operation result is sent to the FPGA.
可选地，所述将所述原始数据发送至MicroBlaze软核处理器，包括：在所述MicroBlaze软核处理器上外接FIFO输入端口，FPGA接收原始数据并将其发送至FIFO输入端口，FIFO输入端口接收原始数据通过AXIS总线将其发送至MicroBlaze软核处理器内核。Optionally, the sending the raw data to the MicroBlaze soft-core processor includes: connecting an external FIFO input port on the MicroBlaze soft-core processor, the FPGA receives the raw data and sends it to the FIFO input port, and the FIFO input port The port receives raw data and sends it to the MicroBlaze soft processor core via the AXIS bus.
可选地，所述FIFO输入端口接收原始数据通过AXIS总线将其发送至MicroBlaze软核处理器内核，包括：FIFO输入端口接收原始数据，AXIS总线通过GPIO对MicroBlaze软核处理器内核发出信号，当所述信号为高电平时，MicroBlaze软核处理器内核读取通过AXIS总线发送的原始数据。Optionally, the FIFO input port receives the original data and sends it to the MicroBlaze soft-core processor core through the AXIS bus, including: the FIFO input port receives the original data, and the AXIS bus sends a signal to the MicroBlaze soft-core processor core through the GPIO. When the signal is high, the MicroBlaze soft core processor core reads the raw data sent through the AXIS bus.
可选地，所述MicroBlaze软核处理器采用浮点FFT算法对所述原始数据进行时频域转换得到运算结果，包括：将原始数据接收到缓冲区，待原始数据接收完毕，MicroBlaze软核处理器调整原始数据顺序，然后通过浮点FFT算法中的蝶形运算进行时频域转换得到运算结果。Optionally, the MicroBlaze soft-core processor uses a floating-point FFT algorithm to perform time-frequency domain conversion on the original data to obtain an operation result, including: receiving the original data into a buffer, and processing the MicroBlaze soft-core after the original data is received. The order of the original data is adjusted by the processor, and then the time-frequency domain conversion is performed by the butterfly operation in the floating-point FFT algorithm to obtain the operation result.
可选地，所述将所述运算结果发送至FPGA，包括：在所述MicroBlaze软核处理器上外接FIFO输出端口，MicroBlaze软核处理器内核将所述运算结果通过AXIS总线发送至FIFO输出端口，FIFO输出端口将其发送至FPGA。Optionally, the sending the operation result to the FPGA includes: connecting an external FIFO output port on the MicroBlaze soft-core processor, and the MicroBlaze soft-core processor core sends the operation result to the FIFO output port through the AXIS bus. , the FIFO output port sends it to the FPGA.
可选地，所述MicroBlaze软核处理器内核将所述运算结果通过AXIS总线发送至FIFO输出端口，包括：所述MicroBlaze软核处理器内核将所述运算结果通过AXIS总线发送至FIFO输出端口，并将与AXIS总线连接的GPIO置位为高电平，通知FPGA接收运算结果。Optionally, the MicroBlaze soft-core processor core sends the operation result to the FIFO output port through the AXIS bus, including: the MicroBlaze soft-core processor core sends the operation result to the FIFO output port through the AXIS bus, And set the GPIO connected to the AXIS bus to a high level to notify the FPGA to receive the operation result.
可选地，所述MicroBlaze软核处理器采用哈弗体系结构，64K数据指令空间，所述浮点FFT算法采用C语言。Optionally, the MicroBlaze soft-core processor adopts the Harvard architecture, 64K data instruction space, and the floating-point FFT algorithm adopts C language.
本发明的另一个方面提供了一种时频域转换系统，所述系统包括：数据传输模块，用于FPGA接收原始数据，并将所述原始数据发送至MicroBlaze软核处理器；数据处理模块，用于MicroBlaze软核处理器采用浮点FFT算法对所述原始数据进行时频域转换得到运算结果，并将所述运算结果发送至FPGA。Another aspect of the present invention provides a time-frequency domain conversion system, the system includes: a data transmission module, used for the FPGA to receive original data and send the original data to the MicroBlaze soft-core processor; a data processing module, The MicroBlaze soft-core processor uses the floating-point FFT algorithm to perform time-frequency domain conversion on the original data to obtain operation results, and sends the operation results to the FPGA.
本发明的再一个方面提供了一种电子设备，所述设备包括：处理器；存储器，其存储有计算机可执行程序，该程序在被所述处理器执行时，使得所述处理器执行如上文所述的时频域转换方法。Yet another aspect of the present invention provides an electronic device, the device comprising: a processor; and a memory storing a computer-executable program, which, when executed by the processor, causes the processor to execute as above The described time-frequency domain conversion method.
本发明的又一个方面提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如上文所述的时频域转换方法。Yet another aspect of the present invention provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the above-described time-frequency domain conversion method.
附图说明Description of drawings
为了更完整地理解本发明及其优势，现在将参考结合附图的以下描述，其中：For a more complete understanding of the present invention and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:
图1示意性示出了本发明实施例提供的时频域转换方法的方法流程图；1 schematically shows a method flowchart of a time-frequency domain conversion method provided by an embodiment of the present invention;
图2示意性示出了本发明实施例提供的时频域转换方法中MicroBlaze处理系统示意图；2 schematically shows a schematic diagram of a MicroBlaze processing system in a time-frequency domain conversion method provided by an embodiment of the present invention;
图3示意性示出了本发明实施例提供的时频域转换方法中MicroBlaze处理系统的工作流程图；FIG. 3 schematically shows a work flow diagram of a MicroBlaze processing system in a time-frequency domain conversion method provided by an embodiment of the present invention;
图4示意性示出了本发明实施例提供的时频域转换系统框图；4 schematically shows a block diagram of a time-frequency domain conversion system provided by an embodiment of the present invention;
图5示意性示出了根据本发明实施例提供的电子设备框图。FIG. 5 schematically shows a block diagram of an electronic device provided according to an embodiment of the present invention.
具体实施方式Detailed ways
以下，将参照附图来描述本发明的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本发明实施例的全面理解。然而，明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present invention. In the following detailed description, for convenience of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, that one or more embodiments may be practiced without these specific details. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention.
在此使用的术语仅仅是为了描述具体实施例，而并非意在限制本发明。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。The terminology used herein is for the purpose of describing specific embodiments only, and is not intended to limit the present invention. The terms "comprising", "comprising" and the like as used herein indicate the presence of stated features, steps, operations and/or components, but do not preclude the presence or addition of one or more other features, steps, operations or components.
本发明的一个实施例提供了一种时频域转换方法，参见图1，所述方法包括步骤S101～步骤S102的内容：An embodiment of the present invention provides a time-frequency domain conversion method. Referring to FIG. 1 , the method includes the contents of steps S101 to S102:
步骤S101，FPGA接收原始数据，并将所述原始数据发送至MicroBlaze软核处理器。Step S101, the FPGA receives the original data, and sends the original data to the MicroBlaze soft-core processor.
利用FPGA资源生成MicroBlaze软核处理器，由于MicroBlaze是可在FPGA上配置实现的处理器软核，该软核有很大的设计灵活性，可通过相关EDA工具完成处理器结构，数据指令寻址空间配置，即利用xilinx公司的EDA工具vivado构造MicroBlaze处理系统，如图2所示，图2为MicroBlaze处理系统示意图。Use FPGA resources to generate MicroBlaze soft-core processors. Since MicroBlaze is a processor soft-core that can be configured and implemented on FPGA, the soft-core has great design flexibility. The processor structure and data instruction addressing can be completed through related EDA tools. The space configuration is to use the EDA tool vivado of xilinx company to construct the MicroBlaze processing system, as shown in Figure 2, which is a schematic diagram of the MicroBlaze processing system.
步骤S102，MicroBlaze软核处理器采用浮点快速傅氏变换算法FFT(Fast FourierTransformation，浮点FFT算法)对所述原始数据进行时频域转换得到运算结果，并将所述运算结果发送至FPGA。Step S102 , the MicroBlaze soft-core processor uses a floating-point Fast Fourier Transform (Fast Fourier Transform, floating-point FFT algorithm) to perform time-frequency domain conversion on the original data to obtain an operation result, and sends the operation result to the FPGA.
时频域转换具体地可以通过MicroBlaze软核处理器的浮点FFT算法进行实现，由此可见，本发明通过在FPGA上配置MicroBlaze软核处理器，实现了对原始数据的时频域转换，避免了现有技术中只采用FPGA硬件，而需通过verilog或者VHDL等硬件编程语言进行软件编程实现时频域转换，造成的硬件编程语言算法实现效率低等问题。The time-frequency domain conversion can be specifically implemented by the floating-point FFT algorithm of the MicroBlaze soft-core processor. It can be seen that the present invention realizes the time-frequency domain conversion of the original data by configuring the MicroBlaze soft-core processor on the FPGA, avoiding the need for In the prior art, only FPGA hardware is used, and software programming is required to implement time-frequency domain conversion through hardware programming languages such as verilog or VHDL, which causes problems such as low implementation efficiency of hardware programming language algorithms.
具体地，参见图2，上文所述将所述原始数据发送至MicroBlaze软核处理器，包括：Specifically, referring to FIG. 2, the above-mentioned sending of the raw data to the MicroBlaze soft-core processor includes:
在所述MicroBlaze软核处理器上外接FIFO输入端口，FPGA接收原始数据并将其发送至FIFO输入端口，FIFO输入端口接收原始数据通过AXIS总线将其发送至MicroBlaze软核处理器内核。其中，FIFO输入端口接收原始数据，AXIS总线通过GPIO对MicroBlaze软核处理器内核发出信号，当所述信号为高电平时，MicroBlaze软核处理器内核读取通过AXIS总线发送的原始数据。An external FIFO input port is connected to the MicroBlaze soft-core processor, the FPGA receives the original data and sends it to the FIFO input port, and the FIFO input port receives the original data and sends it to the MicroBlaze soft-core processor core through the AXIS bus. The FIFO input port receives raw data, and the AXIS bus sends a signal to the MicroBlaze soft-core processor core through GPIO. When the signal is high, the MicroBlaze soft-core processor core reads the raw data sent through the AXIS bus.
参见图3，该时频转换系统的工作流程为，原始数据(即待处理数据)输入S_AXIS接口时，通过GPIO对MicroBlaze发出通知信号，MicroBlaze收到GPIO管脚的信号，当该信号为高电平时，MicroBlaze软核处理器内核开始读取连接到AXIS接口的fifo数据。当数据接收完毕后开始进行时频转换处理，时频转换通过C语言实现。Referring to Figure 3, the work flow of the time-frequency conversion system is that when the original data (that is, the data to be processed) is input to the S_AXIS interface, a notification signal is sent to the MicroBlaze through the GPIO, and the MicroBlaze receives the signal from the GPIO pin. When the signal is high Normally, the MicroBlaze soft core processor core starts to read the fifo data connected to the AXIS interface. When the data is received, the time-frequency conversion process starts, and the time-frequency conversion is realized by C language.
需要说明的是，所述MicroBlaze软核处理器采用浮点FFT算法对所述原始数据进行时频域转换得到运算结果，包括：将原始数据接收到缓冲区，待原始数据接收完毕，MicroBlaze软核处理器调整原始数据顺序，然后通过浮点FFT算法中的蝶形运算进行时频域转换得到运算结果。It should be noted that the MicroBlaze soft-core processor uses the floating-point FFT algorithm to perform time-frequency domain conversion on the original data to obtain an operation result, including: receiving the original data into the buffer, and after receiving the original data, the MicroBlaze soft-core The processor adjusts the original data order, and then performs time-frequency domain conversion through the butterfly operation in the floating-point FFT algorithm to obtain the operation result.
然后，将所述运算结果发送至FPGA，包括：在所述MicroBlaze软核处理器上外接FIFO输出端口，MicroBlaze软核处理器内核将所述运算结果通过AXIS总线发送至FIFO输出端口，FIFO输出端口将其发送至FPGA。其中，所述MicroBlaze软核处理器内核将所述运算结果通过AXIS总线发送至FIFO输出端口，并将与AXIS总线连接的GPIO置位为高电平，通知FPGA接收运算结果。Then, sending the operation result to the FPGA includes: connecting an external FIFO output port on the MicroBlaze soft-core processor, and the MicroBlaze soft-core processor core sends the operation result to the FIFO output port through the AXIS bus, and the FIFO output port send it to the FPGA. The MicroBlaze soft-core processor core sends the operation result to the FIFO output port through the AXIS bus, and sets the GPIO connected to the AXIS bus to a high level to notify the FPGA to receive the operation result.
继续参见图3，经过时频转换处理后，该时频转换系统的工作流程为，处理后的结果数据通过AXIS总线传输到输出fifo中并置位GPIO电平值为高电平，通知后续处理电路或者系统接收处理结果。Continue to refer to Figure 3, after the time-frequency conversion processing, the work flow of the time-frequency conversion system is that the processed result data is transmitted to the output fifo through the AXIS bus, and the GPIO level value is set to a high level, and the subsequent processing is notified. The circuit or system receives the processing result.
另外，所述MicroBlaze软核处理器采用哈弗体系结构，64K数据指令空间，在外设资源上使用AXIS总线连接输入和输出两个FIFO，两个FIFO的数据输入和输出可以通过MICROBLAZE软核直接控制，以实现低延时和跨时钟域的高效数据传输，通过AXI总线连接位宽为32bit的GPIO模块，硬件资源设计采用xilinx公司block design。In addition, the MicroBlaze soft-core processor adopts the Harvard architecture, 64K data instruction space, and uses the AXIS bus to connect the input and output two FIFOs on the peripheral resources. The data input and output of the two FIFOs can be directly controlled by the MICROBLAZE soft core, In order to achieve low latency and efficient data transmission across clock domains, the GPIO module with a bit width of 32bit is connected through the AXI bus, and the hardware resource design adopts the block design of xilinx company.
综上所述，本发明采用上述技术方案，具有以下有益效果：To sum up, the present invention adopts the above-mentioned technical scheme, and has the following beneficial effects:
(1)提高FPGA软件算法实现效率，利用处理器软核结合C语言完成高可移植的算法实现。(1) Improve the efficiency of FPGA software algorithm implementation, and use the processor soft core combined with C language to complete the highly portable algorithm implementation.
(2)提升算法可维护性，利用MicroBlaze处理器特点在算法调试维护时可用单步运行等调试手段，在更改算法时不需要变更FPGA硬件资源配置，只需将软件重编译下载到目标板卡上即可。(2) Improve the maintainability of the algorithm. Using the characteristics of the MicroBlaze processor, debugging methods such as single-step operation can be used during algorithm debugging and maintenance. When changing the algorithm, there is no need to change the FPGA hardware resource configuration. Just recompile and download the software to the target board. on.
(3)降低FPGA内部数字逻辑时序压力。由于一旦确定MicroBlaze配置资源，那么该处理器所占的资源即为固定，它不会随着算法复杂度提升而增加，因此应用该方法实现复杂算法会降低FPGA内部数字逻辑时序压力。(3) Reduce the timing pressure of digital logic inside FPGA. Since once the MicroBlaze configuration resource is determined, the resource occupied by the processor is fixed, and it will not increase with the complexity of the algorithm. Therefore, applying this method to implement complex algorithms will reduce the timing pressure of the digital logic inside the FPGA.
(4)功能可扩展性强。该方法使设计在FPGA硬件逻辑和软件算法上都可以单独进行拓展，从两个维度提升设计的功能可扩展性。(4) The function has strong scalability. This method enables the design to be independently expanded in both FPGA hardware logic and software algorithm, and improves the functional scalability of the design from two dimensions.
(5)统一开发环境，便于工程管理。该方法的软硬件均在xilinx公司的vivado开发环境中通过各类语言编程实现。(5) Unified development environment to facilitate project management. The software and hardware of this method are implemented by various language programming in the vivado development environment of xilinx company.
另外，本发明还对本发明实施例采用的方法进行了性能测试，测试结果如表1所示。In addition, the present invention also conducts a performance test on the method adopted in the embodiment of the present invention, and the test results are shown in Table 1.
表1性能测试结果Table 1 Performance test results
由此可见，本发明实施例的时频域转换方法的处理时间均较短。It can be seen that the processing time of the time-frequency domain conversion methods in the embodiments of the present invention is short.
参见图4，图4示例性示出了根据本发明实施例的时频域转换系统，所述系统400包括：数据传输模块401，用于FPGA接收原始数据，并将所述原始数据发送至MicroBlaze软核处理器；数据处理模块402，用于MicroBlaze软核处理器采用浮点FFT算法对所述原始数据进行时频域转换得到运算结果，并将所述运算结果发送至FPGA。Referring to FIG. 4, FIG. 4 exemplarily shows a time-frequency domain conversion system according to an embodiment of the present invention. The system 400 includes: a data transmission module 401, used for the FPGA to receive original data and send the original data to MicroBlaze A soft-core processor; the data processing module 402 is used for the MicroBlaze soft-core processor to perform time-frequency domain conversion on the original data by using a floating-point FFT algorithm to obtain an operation result, and send the operation result to the FPGA.
根据本发明的实施例的模块、子模块、单元、子单元中的任意多个、或其中任意多个的至少部分功能可以在一个模块中实现。根据本发明实施例的模块、子模块、单元、子单元中的任意一个或多个可以被拆分成多个模块来实现。Any of the modules, sub-modules, units, sub-units, or at least part of the functions of any of them according to embodiments of the present invention may be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of the present invention may be divided into multiple modules for implementation.
图5示意性示出了根据本发明实施例的电子设备的框图。FIG. 5 schematically shows a block diagram of an electronic device according to an embodiment of the present invention.
如图5所示，电子设备500包括处理器501和存储器502。该电子设备500可以执行根据本发明实施例的方法。As shown in FIG. 5 , the electronic device 500 includes a processor 501 and a memory 502 . The electronic device 500 may execute the method according to the embodiment of the present invention.
具体地，处理器501例如可以包括通用微处理器、指令集处理器和/或相关芯片组和/或专用微处理器(例如，专用集成电路(ASIC))，等等。处理器501还可以包括用于缓存用途的板载存储器。处理器501可以是用于执行根据本发明实施例的方法流程的不同动作的单一处理单元或者是多个处理单元。Specifically, the processor 501 may include, for example, a general-purpose microprocessor, an instruction set processor and/or a related chipset and/or a special-purpose microprocessor (eg, an application specific integrated circuit (ASIC)), and the like. The processor 501 may also include on-board memory for caching purposes. The processor 501 may be a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present invention.
存储器502，例如可以是能够包含、存储、传送、传播或传输指令的任意介质。例如，可读存储介质可以包括但不限于电、磁、光、电磁、红外或半导体系统、装置、器件或传播介质。可读存储介质的具体示例包括：磁存储装置，如磁带或硬盘(HDD)；光存储装置，如光盘(CD-ROM)；存储器，如随机存取存储器(RAM)或闪存；和/或有线/无线通信链路。其存储有计算机可执行程序，该程序在被所述处理器执行时，使得所述处理器执行如上文所述的时频域转换方法。Memory 502, for example, can be any medium that can contain, store, communicate, propagate, or transmit instructions. For example, a readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of readable storage media include: magnetic storage devices, such as magnetic tapes or hard disks (HDDs); optical storage devices, such as compact disks (CD-ROMs); memories, such as random access memory (RAM) or flash memory; and/or wired /Wireless communication link. It stores a computer-executable program that, when executed by the processor, causes the processor to execute the time-frequency domain conversion method as described above.
本发明还提供了一种计算机可读介质，该计算机可读介质可以是上述实施例中描述的设备/装置/系统中所包含的；也可以是单独存在，而未装配入该设备/装置/系统中。上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被执行时，实现根据本发明实施例的方法。The present invention also provides a computer-readable medium, which may be included in the device/apparatus/system described in the above-mentioned embodiments; or may exist alone without being assembled into the apparatus/apparatus/system. in the system. The above-mentioned computer-readable medium carries one or more programs, and when the above-mentioned one or more programs are executed, the method according to the embodiment of the present invention is implemented.
根据本发明的实施例，计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本发明中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本发明中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、有线、光缆、射频信号等等，或者上述的任意合适的组合。According to an embodiment of the present invention, the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples of computer readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable Programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device . Program code embodied on a computer readable medium may be transmitted using any suitable medium including, but not limited to, wireless, wireline, optical fiber cable, radio frequency signals, etc., or any suitable combination of the foregoing.
本领域技术人员可以理解，本发明的各个实施例和/或权利要求中记载的特征可以进行多种组合或/或结合，即使这样的组合或结合没有明确记载于本发明中。特别地，在不脱离本发明精神和教导的情况下，本发明的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本发明的范围。Those skilled in the art will appreciate that various combinations or/or combinations of features recited in the various embodiments and/or claims of the present invention may be performed, even if such combinations or combinations are not expressly recited in the present invention. In particular, various combinations and/or combinations of the features recited in the various embodiments of the invention and/or the claims may be made without departing from the spirit and teachings of the invention. All such combinations and/or combinations fall within the scope of the present invention.
尽管已经参照本发明的特定示例性实施例示出并描述了本发明，但是本领域技术人员应该理解，在不背离所附权利要求及其等同物限定的本发明的精神和范围的情况下，可以对本发明进行形式和细节上的多种改变。因此，本发明的范围不应该限于上述实施例，而是应该不仅由所附权利要求来进行确定，还由所附权利要求的等同物来进行限定。While the invention has been shown and described with reference to specific exemplary embodiments of the invention, those skilled in the art will appreciate that, without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents Various changes in form and detail were made in the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the appended claims, but also by their equivalents.
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| CN201910315598.6ACN110046324A (en) | 2019-04-18 | 2019-04-18 | A kind of time-frequency domain conversion method, system, electronic equipment and medium |
| Application Number | Priority Date | Filing Date | Title |
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| CN201910315598.6ACN110046324A (en) | 2019-04-18 | 2019-04-18 | A kind of time-frequency domain conversion method, system, electronic equipment and medium |
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| CN110046324Atrue CN110046324A (en) | 2019-07-23 |
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| CN201910315598.6APendingCN110046324A (en) | 2019-04-18 | 2019-04-18 | A kind of time-frequency domain conversion method, system, electronic equipment and medium |
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| CN (1) | CN110046324A (en) |
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