CN109920802B - Display device, driving backboard, transistor device and manufacturing method thereof - Google Patents

Abstract

The disclosure provides a display panel, a driving back plate, a transistor device and a manufacturing method thereof, and relates to the technical field of display. The transistor device comprises a thin film transistor, a tunneling transistor, a first electrode and a second electrode which are arranged on the same side of a substrate. The thin film transistor comprises a first active layer and a first grid electrode, wherein the first active layer comprises a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region; the first grid and the first channel region are arranged oppositely. The tunneling transistor comprises a second active layer and a second grid electrode, the second active layer comprises a second channel region, a third doping region and a fourth doping region, the third doping region and the fourth doping region are separated from two sides of the second channel region and are different in doping type, and the second doping region is connected with the third doping region and is consistent in doping type; the second grid is opposite to the second channel region. The first electrode is connected with the first doping region; the second electrode is connected with the fourth doped region.

Description

Display device, driving backboard, transistor device and manufacturing method thereof

Technical Field

The disclosure relates to the technical field of display, in particular to a display device, a driving back plate, a transistor device and a manufacturing method of the transistor device.

Background

In a display panel, a thin film transistor is a very common driving device, and generally includes a low temperature polysilicon thin film transistor, an amorphous silicon thin film transistor, and the like, where the low temperature polysilicon thin film transistor has relatively high mobility and stability, and thus is widely applied. At present, the thin film transistor has the problem of large leakage current, which affects the normal operation of driving and the display effect.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a display device, a driving backplane, a transistor device and a method for manufacturing the transistor device, which can reduce leakage current and ensure a display effect.

According to an aspect of the present disclosure, a transistor device is provided, which includes a thin film transistor, a tunneling transistor, a first electrode, and a second electrode disposed on the same side of a substrate, wherein:

the thin film transistor comprises a first active layer and a first grid electrode, wherein the first active layer comprises a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region; the first grid electrode is opposite to the first channel region;

the tunneling transistor comprises a second active layer and a second grid electrode, the second active layer comprises a second channel region, a third doped region and a fourth doped region, the third doped region and the fourth doped region are separated from two sides of the second channel region and are different in doping type, and the second doped region is connected with the third doped region and is consistent in doping type; the second grid electrode is opposite to the second channel region;

the first electrode is connected with the first doped region;

the second electrode is connected with the fourth doped region.

In an exemplary embodiment of the present disclosure, the first active layer and the second active layer are different portions of the same semiconductor layer, and the second doped region and the third doped region are both located between the first channel region and the second channel region.

In an exemplary embodiment of the present disclosure, the transistor device further includes:

the grid insulating layer covers the semiconductor layer, and the first grid electrode and the second grid electrode are positioned on the surface, far away from the semiconductor layer, of the grid insulating layer;

a dielectric layer covering the gate insulating layer, the first gate electrode and the second gate electrode;

the first electrode and the second electrode are arranged on the surface, far away from the gate insulating layer, of the dielectric layer, the first electrode is connected with the first doping area through a first through hole, and the second electrode is connected with the fourth doping area through a second through hole.

In an exemplary embodiment of the present disclosure, the transistor device further includes:

the gate insulating layer covers the first active layer, and the first gate is positioned on the surface of the gate insulating layer far away from the first active layer;

a dielectric layer covering the gate insulating layer and the first gate electrode;

the connecting layer is arranged on the surface, far away from the gate insulating layer, of the dielectric layer and is connected with the fourth doping region through a connecting through hole; the second active layer is arranged on the surface, far away from the dielectric layer, of the connecting layer, and the third doped region, the second channel region and the fourth doped region are sequentially stacked along the direction far away from the connecting layer;

the first flat layer covers the connecting layer and the dielectric layer, and the second channel region and the fourth doped region protrude out of the first flat layer; the second grid electrode is arranged on the surface, far away from the connecting layer, of the first flat layer and is opposite to the second channel region;

a second planarization layer covering the first planarization layer, the second gate electrode, and the second active layer;

the first electrode and the second electrode are both arranged on the surface, far away from the first flat layer, of the second flat layer, the first electrode is connected with the first doping region through a first through hole, and the second electrode is connected with the fourth doping region through a second through hole.

In one exemplary embodiment of the present disclosure, a material of at least one of the first active layer and the second active layer includes polysilicon.

According to an aspect of the present disclosure, there is provided a method of manufacturing a transistor device, including:

providing a substrate;

forming a thin film transistor and a tunneling transistor on the same side of the substrate; the thin film transistor comprises a first active layer and a first grid electrode, wherein the first active layer comprises a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region; the first grid electrode is opposite to the first channel region; the tunneling transistor comprises a second active layer and a second grid electrode, the second active layer comprises a second channel region, a third doped region and a fourth doped region, the third doped region and the fourth doped region are separated from two sides of the second channel region and are different in doping type, and the second doped region is connected with the third doped region and is consistent in doping type; the second grid electrode is opposite to the second channel region;

forming a first electrode connected with the first doped region;

and forming a second electrode connected with the fourth doped region.

In an exemplary embodiment of the present disclosure, forming the thin film transistor and the tunneling transistor includes:

forming a semiconductor layer on one side of the substrate, wherein the semiconductor layer comprises a first region and a second region;

doping a part of the first region to obtain a first active layer, wherein the first active layer comprises a first channel region, a first doping region and a second doping region, and the first doping region and the second doping region are separated from two sides of the first channel region;

doping a part of the second region to obtain a second active layer, wherein the second active layer comprises a second channel region, a third doping region and a fourth doping region, the third doping region and the fourth doping region are separated from two sides of the second channel region and have different doping types, and the second doping region is connected with the third doping region and has the same doping type; and the second doped region and the third doped region are both located between the first channel region and the second channel region.

In an exemplary embodiment of the present disclosure, forming the thin film transistor and the tunneling transistor further includes:

forming a gate insulating layer covering the semiconductor layer;

forming the first grid electrode and the second grid electrode on the surface of the grid insulating layer far away from the semiconductor layer;

forming a dielectric layer covering the first gate electrode, the second gate electrode and the gate insulating layer;

and forming a first electrode and a second electrode on the surface of the dielectric layer far away from the gate insulating layer, wherein the first electrode is connected with the first doped region through a first through hole, and the second electrode is connected with the fourth doped region through a second through hole.

In an exemplary embodiment of the present disclosure, forming the thin film transistor and the tunneling transistor includes:

forming a first active layer on one side of the substrate, wherein the first active layer comprises a first channel region, a first doping region and a second doping region, the first doping region and the second doping region are separated from two sides of the first channel region, and the doping types of the first doping region and the second doping region are different;

forming a gate insulating layer covering the first active layer;

forming a first grid electrode on the surface of the grid insulating layer far away from the first active layer;

forming a dielectric layer covering the first gate electrode and the gate insulating layer;

forming a connecting layer on the surface of the dielectric layer far away from the gate insulating layer, wherein the connecting layer is connected with the second doping region through a connecting through hole;

forming a second active layer on the surface of the connecting layer far away from the dielectric layer, wherein the second active layer comprises a third doped region, a second channel region and a fourth doped region which are sequentially stacked along the direction far away from the connecting layer, the doping types of the third doped region and the fourth doped region are different, and the doping types of the third doped region and the second doped region are consistent;

forming a first flat layer covering the connection layer and the dielectric layer, wherein the second channel region and the fourth doped region protrude from the first flat layer;

forming a second grid electrode on the surface of the first flat layer far away from the connecting layer, wherein the second grid electrode is arranged opposite to the second channel region;

forming a second planarization layer covering the first planarization layer, the second gate electrode, and the second active layer;

and forming a first electrode and a second electrode on the surface of the second flat layer far away from the first flat layer, wherein the first electrode is connected with the first doping region through a first through hole, and the second electrode is connected with the fourth doping region through a second through hole.

In one exemplary embodiment of the present disclosure, a material of at least one of the first active layer and the second active layer includes polysilicon.

According to an aspect of the present disclosure, there is provided a driving backplane comprising the transistor device of any one of the above.

According to an aspect of the present disclosure, there is provided a display panel including the driving backplane of any one of the above.

According to the display device, the driving backboard, the transistor device and the manufacturing method thereof, the second doping area of the thin film transistor is connected with the third doping area of the tunneling transistor and the doping types are consistent, the first electrode is connected with the first doping area of the thin film transistor, the second electrode is connected with the fourth doping area of the tunneling transistor, and therefore the thin film transistor and the tunneling transistor can be connected between the first electrode and the second electrode in series; when the tunneling transistor does not work, the first electrode and the second electrode are in an open circuit state, so that the thin film transistor is in the open circuit state, the leakage current of the thin film transistor can be greatly reduced, and the display effect is ensured.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of a first embodiment of a transistor device of the present disclosure.

Fig. 2 is a schematic diagram of a second embodiment of a transistor device of the present disclosure.

Fig. 3 is a schematic diagram of a third embodiment of a transistor device of the present disclosure.

Fig. 4 is a flow chart of a method of fabricating a transistor device of the present disclosure.

Fig. 5 is a flow chart of a first embodiment of a manufacturing method of the present disclosure.

Fig. 6 is a flow chart of a second embodiment of a manufacturing method of the present disclosure.

Fig. 7 is a schematic view corresponding to step S1210 in the first embodiment of the manufacturing method of the present disclosure.

Fig. 8 is a schematic view corresponding to step S1230 in the first embodiment of the manufacturing method of the present disclosure.

Fig. 9 is a schematic view corresponding to step S1220 in the first embodiment of the manufacturing method of the present disclosure.

Fig. 10 is a schematic view corresponding to step S1250 in the first embodiment of the manufacturing method of the present disclosure.

Fig. 11 is a schematic view corresponding to step S1240 in the second embodiment of the manufacturing method of the present disclosure.

Fig. 12 is a schematic view corresponding to step S1250 in the second embodiment of the manufacturing method of the present disclosure.

Fig. 13 is a schematic view corresponding to step S1260 in the second embodiment of the manufacturing method of the present disclosure.

Fig. 14 is a schematic view corresponding to step S1280 in the second embodiment of the manufacturing method of the present disclosure.

Description of reference numerals:

100. a substrate; 200. a semiconductor layer; 300. a buffer layer; 1. a thin film transistor; 11. a first active layer; 111. a first channel region; 112. a first doped region; 113. a second doped region; 12. a first gate electrode; 2. a tunneling transistor; 21. a second active layer; 211. a second channel region; 212. a third doped region; 213. a fourth doped region; 214. a fifth doped region; 22. a second gate electrode; 3. a first electrode; 4. a second electrode; 5. a gate insulating layer; 6. a dielectric layer; 7. a connecting layer; 8. a first planar layer; 9. a second planar layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," "third," and "fourth" are used merely as labels, and are not limiting as to the number of their objects.

The embodiment of the present disclosure provides a transistor device, which can be used for a driving backplane of a display panel, where the display panel can be an OLED display panel, but not limited thereto, and can also be an LCD display panel, etc.

As shown in fig. 1 to fig. 3, the transistor device of the embodiment of the present disclosure includes a thin film transistor 1, a tunneling transistor 2, afirst electrode 3, and asecond electrode 4, where the thin film transistor 1 and the tunneling transistor 2 are disposed on the same side of asubstrate 100, where:

the thin film transistor 1 includes a firstactive layer 11 and afirst gate electrode 12, the firstactive layer 11 includes afirst channel region 111, a firstdoped region 112 and a seconddoped region 113, the firstdoped region 112 and the seconddoped region 113 are separated from two sides of thefirst channel region 111; thefirst gate electrode 12 is disposed opposite to thefirst channel region 111.

The tunneling transistor 2 includes a secondactive layer 21 and asecond gate 22, the secondactive layer 21 includes asecond channel region 211, a thirddoped region 212 and a fourthdoped region 213, the thirddoped region 212 and the fourthdoped region 213 are separated from two sides of thesecond channel region 211 and have different doping types, and the seconddoped region 113 is connected with the thirddoped region 212 and has the same doping type; thesecond gate 22 is disposed opposite to thesecond channel region 211.

Thefirst electrode 3 is connected to thefirst doping region 112, and thesecond electrode 4 is connected to thefourth doping region 213.

In the transistor device according to the embodiment of the present disclosure, since the seconddoped region 113 and the thirddoped region 212 are connected and have the same doping type, thefirst electrode 3 is connected to the firstdoped region 112, and thesecond electrode 4 is connected to the fourthdoped region 213, the thin film transistor 1 and the tunneling transistor 2 can be connected in series between thefirst electrode 3 and thesecond electrode 4; when the tunneling transistor 2 is not in operation, thefirst electrode 3 and thesecond electrode 4 are in an open circuit state, so that the thin film transistor 1 is in the open circuit state, thereby greatly reducing the leakage current of the thin film transistor 1 and ensuring the display effect.

Thesubstrate 100 may be a rigid substrate made of glass or the like, or may be a flexible substrate made of poly-p-phenylene terephthalate (PET) or the like, and the shape of the material is not particularly limited.

The thin film transistor 1 may be an N-type thin film transistor or a P-type thin film transistor, thefirst channel region 111 may be an N-type channel or a P-type channel, and the doping types of the firstdoped region 112 and the seconddoped region 113 may be both N-type doping or P-type doping, which may be determined by the type of the thin film transistor 1, and is not particularly limited herein. Meanwhile, the material of the firstactive layer 11 includes a polysilicon material and is formed through a low temperature polysilicon process, so that the thin film transistor 1 may be a low temperature polysilicon thin film transistor.

Thefirst gate electrode 12 may be disposed on a side of the firstactive layer 11 away from thesubstrate 100 and opposite to thefirst channel region 111, that is, an orthographic projection of thefirst gate electrode 12 on the firstactive layer 11 at least partially overlaps thefirst channel region 111.

The tunneling transistor 2 may be an N-type tunneling transistor or a P-type tunneling transistor, and thesecond channel region 211 may be an N-type channel or a P-type channel; the doping types of the thirddoped region 212 and the fourthdoped region 213 are different, for example, the thirddoped region 212 is doped N-type, and the fourthdoped region 213 is doped P-type; alternatively, the thirddoped region 212 is doped N-type, and the fourthdoped region 213 is doped P-type; the specific structure may depend on the type of the tunneling transistor 2, and is not particularly limited herein. Meanwhile, the material of the secondactive layer 21 includes a polysilicon material and is formed through a low temperature polysilicon process, so that the tunneling transistor 2 may be a low temperature polysilicon tunneling thin film transistor. The P type doping can be heavily P type doping or lightly P type doping, and the N type doping can be heavily N type doping or lightly N type doping.

Thesecond gate 22 may be disposed on a side of the secondactive layer 21 away from thesubstrate 100 and opposite to thesecond channel region 211, that is, an orthographic projection of thesecond gate 22 on the secondactive layer 21 at least partially coincides with thesecond channel region 211.

Thefirst electrode 3 and thesecond electrode 4 are both made of conductive materials such as metal, and one of them is a source electrode, and the other is a drain electrode, for example: thefirst electrode 3 connected to the firstdoped region 112 of the thin film transistor 1 is a source, and thesecond electrode 4 is a drain.

First embodiment of the transistor device of the present disclosure

As shown in fig. 1, abuffer layer 300 may be disposed on asubstrate 100, and a thin film transistor 1 and a tunneling transistor 2 may be disposed on a surface of thebuffer layer 300 away from thesubstrate 100 in the same layer, where the material of thebuffer layer 300 is not particularly limited, specifically:

as shown in fig. 1, the firstactive layer 11 and the secondactive layer 21 are included in thesame semiconductor layer 200, i.e. the firstactive layer 11 and the secondactive layer 21 are different portions of thesemiconductor layer 200, and thesemiconductor layer 200 is disposed on the surface of thebuffer layer 300 away from thesubstrate 100. Thesecond doping region 113 and thethird doping region 212 are both located between thefirst channel region 111 and thesecond channel region 211, and the doping types of thesecond doping region 113 and thethird doping region 212 are the same, for example, thesecond doping region 113 and thethird doping region 212 are both doped P-type, and thesecond doping region 113 and thethird doping region 212 are connected, so as to connect the thin film transistor 1 and the tunneling transistor 2 in series. Since the firstactive layer 11 and the secondactive layer 21 are included in thesame semiconductor layer 200, formation of different semiconductor layers for the firstactive layer 11 and the secondactive layer 21, respectively, is avoided, thereby simplifying the process.

As shown in fig. 1, thefirst gate 12 is disposed on a side of thesemiconductor layer 200 away from thesubstrate 100 and opposite to thefirst channel region 111, and thesecond gate 22 is disposed on a side of thesemiconductor layer 200 away from thesubstrate 100 and opposite to thesecond channel region 211.

Further, as shown in fig. 1, the transistor device of the present embodiment may further include agate insulating layer 5 and a dielectric layer 6, wherein:

thegate insulating layer 5 may cover thesemiconductor layer 200, and the material of thegate insulating layer 5 is not particularly limited as long as it is insulating.

Thefirst gate electrode 12 and thesecond gate electrode 22 are positioned on the surface of thegate insulating layer 5 away from thesemiconductor layer 200 and thus may be formed through a patterning process, which is advantageous in simplifying the process. Thefirst gate 12 is aligned with thefirst channel region 111, and thesecond gate 22 is aligned with thesecond channel region 211.

The dielectric layer 6 may cover thegate insulating layer 5, thefirst gate electrode 12, and thesecond gate electrode 22, and the material thereof is not particularly limited as long as it is an insulating material. The dielectric layer 6 is provided with a first via hole and a second via hole penetrating through the dielectric layer 6, the first via hole is opposite to the firstdoped region 112, that is, the orthographic projection of the first via hole on thesemiconductor layer 200 is at least partially overlapped with the firstdoped region 112; the second via is directly opposite to the fourthdoped region 213, i.e. the orthographic projection of the second via on thesemiconductor layer 200 at least partially coincides with the fourthdoped region 213.

Thefirst electrode 3 and thesecond electrode 4 are both arranged on the surface of the dielectric layer 6 far away from thegate insulating layer 5, and thefirst electrode 3 is connected with thefirst doping region 112 through a first via hole; thesecond electrode 4 is connected to the fourthdoped region 213 through the second via hole.

In this embodiment, thesecond channel region 211 is an N-type channel, the thirddoped region 212 is a P-type heavily doped region, the fourthdoped region 213 is an N-type doped region, thefirst electrode 3 is a source, and thesecond electrode 4 is a drain.

Of course, thebuffer layer 300 may not be provided, as long as the thin film transistor 1 and the tunneling transistor 2 can be provided on the same side of thesubstrate 100 in the same layer.

Second embodiment of the transistor device of the present disclosure

As shown in fig. 2, the thin film transistor 1 and the tunneling transistor 2 may be distributed on one side of thesubstrate 100 along a direction away from thesubstrate 100, for example:

thebuffer layer 300 may be disposed on thesubstrate 100, the thin film transistor 1 may be disposed on a surface of thebuffer layer 300 away from thesubstrate 100, the tunneling transistor 2 is disposed on a side of the thin film transistor 1 away from thesubstrate 100, and a material of thebuffer layer 300 is not limited in particular. Of course, thebuffer layer 300 may not be provided.

As shown in fig. 2, the firstactive layer 11 is disposed on one side of thesubstrate 100, and the specific structure of the firstactive layer 11 can refer to the firstactive layer 11 in the first embodiment, which will not be described in detail herein. Meanwhile, the transistor device may further include agate insulating layer 5, a dielectric layer 6, aconnection layer 7, afirst planarization layer 8, and a second planarization layer 9, wherein:

thegate insulating layer 5 covers the firstactive layer 11, and the material of thegate insulating layer 5 is not particularly limited as long as it is insulating.

Thefirst gate electrode 12 is disposed on a surface of thegate insulating layer 5 away from thesubstrate 100 and opposite to thefirst channel region 111 of the firstactive layer 11.

The dielectric layer 6 covers thegate insulating layer 5 and thefirst gate electrode 12, i.e., covers thefirst gate electrode 12 and a region of the surface of thegate insulating layer 5 remote from thesubstrate 100 not covered by thefirst gate electrode 12. The material of the dielectric layer 6 is not particularly limited as long as it is an insulating material. The dielectric layer 6 may be provided with a connecting via penetrating through the dielectric layer 6, the connecting via being directly opposite to the seconddoped region 113 of the firstactive layer 11, i.e. an orthographic projection of the connecting via on the firstactive layer 11 at least partially coincides with the seconddoped region 113.

The connectinglayer 7 may be disposed on a surface of the dielectric layer 6 away from thegate insulating layer 5, and connected to the seconddoped region 113 through a connecting via. The material of theconnection layer 7 may be metal or the like as long as it is conductive. Theconnection layer 7 may extend towards a side of the seconddoped region 113 away from thefirst channel region 111, i.e. towards an outer side of the firstactive layer 11, to avoid overlapping with the thin film transistor 1 in a direction perpendicular to thesubstrate 100.

As shown in fig. 2, the secondactive layer 21 may be disposed on the surface of theconnection layer 7 away from the dielectric layer 6, and the thirddoped region 212, thesecond channel region 211 and the fourthdoped region 213 are sequentially stacked along a direction away from theconnection layer 7, that is, the thirddoped region 212 is disposed on the surface of theconnection layer 7 away from the dielectric layer 6, thesecond channel region 211 is disposed on the surface of theconnection layer 7 of the thirddoped region 212, and the fourthdoped region 213 is disposed on the surface of thesecond channel region 211 away from the thirddoped region 212.

Thefirst planarization layer 8 covers theconnection layer 7 and the dielectric layer 6, but the surface of thefirst planarization layer 8 away from the dielectric layer 6 is located on the side of the surface of thesecond channel region 211 away from theconnection layer 7 close to the dielectric layer 6, so that thesecond channel region 211 and the fourthdoped region 213 protrude out of thefirst planarization layer 8 without being covered.

Thesecond gate 22 is disposed on the surface of thefirst planarization layer 8 away from theconnection layer 7 and opposite to and spaced from thesecond channel region 211, and thesecond gate 22 may be disposed on a side of thesecond channel region 211 close to or away from the firstactive layer 11. Meanwhile, the orthographic projection of thesecond gate 22 on the dielectric layer 6 is located within the range of theconnection layer 7.

The second planarization layer 9 covers thefirst planarization layer 8, thesecond gate electrode 22, and the secondactive layer 21, so that planarization is achieved. The material of the second flat layer 9 may be the same as or different from that of the firstflat layer 8, and is not particularly limited. It should be noted that a portion of the second planarization layer 9 located between thesecond gate 22 and thesecond channel region 211 may serve as a gate insulating layer of the tunneling transistor 2.

The second flat layer 9 may be provided with a first via hole and a second via hole, and the first via hole may penetrate through the second flat layer 9, the firstflat layer 8, the dielectric layer 6 and thegate insulating layer 5 and face the firstdoped region 112, that is, an orthographic projection of the first via hole on the firstactive layer 11 at least partially coincides with the firstdoped region 112; the second via hole may penetrate through the second planar layer 9 and directly face the fourthdoped region 213, that is, an orthographic projection of the second via hole on the secondactive layer 21 at least partially coincides with the fourthdoped region 213.

Thefirst electrode 3 and thesecond electrode 4 are both disposed on the surface of the second planar layer 9 away from the second planar layer 9, thefirst electrode 3 is connected to the firstdoped region 112 through the first via hole, and thesecond electrode 4 is connected to the fourthdoped region 213 through the second via hole.

In this embodiment, thesecond channel region 211 is an N-type channel, the thirddoped region 212 is a P-type heavily doped region, the fourthdoped region 213 is an N-type doped region, thefirst electrode 3 is a source, and thesecond electrode 4 is a drain.

In a third embodiment of the transistor device of the present disclosure, based on the first embodiment of the transistor device, as shown in fig. 3, thesemiconductor layer 200 may further include a third region, the third region is located at a side of the second region adjacent to the side far from the first region, the third region may be doped with a same doping type as thefirst doping region 112 and thesecond doping region 113, so as to obtain afifth doping region 214, thefifth doping region 214 belongs to the tunneling transistor 2 and is connected to thefourth doping region 213, the second via may be opposite to thefifth doping region 214, and thesecond electrode 4 is connected to thefifth doping region 214 through the second via, so as to be connected to thefourth doping region 213.

In the fourth embodiment of the transistor device of the present disclosure, the tunneling transistor 2 may be located between the thin film transistor 1 and thesubstrate 100, for example, the firstactive layer 11 and the secondactive layer 21 may be replaced with each other, and thesecond electrode 4 may be replaced with each other.

In other embodiments of the transistor device of the present disclosure, based on the second embodiment, the thirddoped region 212, thesecond channel region 211 and the fourthdoped region 213 of the secondactive layer 21 may be disposed on the surface of theconnection layer 7 away from the dielectric layer 6, and are not stacked in a direction away from theconnection layer 7, and other structures may be the same as the second embodiment, and are not described in detail herein.

Embodiments of the present disclosure provide a method of manufacturing a transistor device, which may be the transistor device in any of the embodiments of the transistor device described above. As shown in fig. 4, the manufacturing method includes:

step S110, providing a substrate;

step S120, forming a thin film transistor and a tunneling transistor on the same side of the substrate; the thin film transistor comprises a first active layer and a first gate, wherein the first active layer comprises a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region; the tunneling transistor comprises a second active layer and a second grid electrode, the second active layer comprises a second channel region, a third doping region and a fourth doping region, the third doping region and the fourth doping region are separated from two sides of the second channel region and are different in doping type, and the second doping region is connected with the third doping region and is consistent in doping type;

step S130, forming a first electrode connected to the first doped region;

and step S140, forming a second electrode connected with the fourth doped region.

The advantageous effects of the manufacturing method of the present disclosure can refer to the advantageous effects of the transistor device, and the specific structures of the thin film transistor and the tunneling transistor have been described in detail in the above embodiments of the transistor device, and are not described in detail here.

First embodiment of the manufacturing method of the present disclosure

As shown in fig. 5, the step S110 of forming the thin film transistor and the tunneling transistor includes steps S1210 to S1230, wherein:

step 1210, forming a semiconductor layer on one side of the substrate, wherein the semiconductor layer comprises a first region and a second region.

As shown in fig. 7, abuffer layer 300 may be disposed on thesubstrate 100, and the thin film transistor 1 and the tunneling transistor 2 may be disposed on the same layer on the surface of thebuffer layer 300 away from thesubstrate 100, and the material of thebuffer layer 300 is not limited herein.

Thesemiconductor layer 200 is formed on the surface of thebuffer layer 300 away from thesubstrate 100, and the material of thesemiconductor layer 200 may include polysilicon, which may be made by a low temperature polysilicon process. For example, an amorphous silicon layer may be formed on thesubstrate 100, and the amorphous silicon layer may be processed by a laser annealing process to obtain thesemiconductor layer 200 made of polysilicon. The first region and the second region are two separate regions that are contiguous.

Step S1220, doping a portion of the first region to obtain a first active layer, where the first active layer includes a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region.

As shown in fig. 10, the doping types of the firstdoped region 112 and the seconddoped region 113 may be both N-type doping or P-type doping, and may be determined according to the type of the thin film transistor 1, which is not particularly limited herein. For example, thesemiconductor layer 200 may be covered by a photoresist, and after exposure and development, the regions where the firstdoped region 112 and the seconddoped region 113 are to be formed are exposed; then, the regions where thefirst doping region 112 and thesecond doping region 113 are to be formed are doped by ion implantation or other means through one doping process. Of course, the doping can also be carried out in several portions.

Step S1230, doping a portion of the second region to obtain a second active layer, where the second active layer includes a second channel region, a third doped region and a fourth doped region, the third doped region and the fourth doped region are separated from two sides of the second channel region and have different doping types, and the second doped region is connected with the third doped region and has the same doping type; and the second doped region and the third doped region are both located between the first channel region and the second channel region.

As shown in fig. 8 and 9, the doping types of the thirddoped region 212 and the fourthdoped region 213 may be N-type doping or P-type doping, but the doping types of the thirddoped region 212 and the fourthdoped region 213 are different, which may be determined by the type of the tunneling transistor 2, and are not limited herein. For example, thesemiconductor layer 200 may be covered by a photoresist layer, exposed and developed to expose one of the thirddoped region 212 and the fourthdoped region 213, doped by ion implantation or other methods, and then removed. A photoresist layer covering thesemiconductor layer 200 is formed, and after exposure and development, the other of the thirddoped region 212 and the fourthdoped region 213 is exposed, and is doped by ion implantation or other methods, and the photoresist layer is removed again, so that the thirddoped region 212 and the fourthdoped region 213 are doped respectively, and the doping types are different. For example, the thirddoped region 212 is doped P-type, and the fourthdoped region 213 is doped N-type.

It should be noted that the steps S1230 and S1220 may be performed before the step S1220, or may be performed before the step S1220.

Further, as shown in fig. 5, forming the thin film transistor and the tunneling transistor, i.e., step S110, may further include steps S1240 to S1270, where:

and S1240, forming a gate insulating layer covering the semiconductor layer.

Thegate insulating layer 5 may cover thesemiconductor layer 200, and a material thereof is not particularly limited as long as it is insulating.

Step S1250, forming the first gate electrode and the second gate electrode on the surface of the gate insulating layer away from the semiconductor layer.

As shown in fig. 10, thefirst gate electrode 12 and thesecond gate electrode 22 are positioned on the surface of thegate insulating layer 5 away from thesemiconductor layer 200, and thus may be formed through a patterning process, which is advantageous in simplifying the process. For example, a gate material layer may be formed on the surface of thegate insulating layer 5 away from thesemiconductor layer 200, and thefirst gate electrode 12 and thesecond gate electrode 22 may be formed by a photolithography process, which is not described in detail herein. Thefirst gate 12 is aligned with thefirst channel region 111, and thesecond gate 22 is aligned with thesecond channel region 211. Of course, thefirst gate electrode 12 and thesecond gate electrode 22 may be formed by printing or the like. As shown in fig. 10, the step S1220 may be performed after the step S1250.

Step S1260, forming a dielectric layer covering the first gate electrode, the second gate electrode, and the gate insulating layer.

As shown in fig. 1, the material of the dielectric layer 6 is not particularly limited, and may be any insulating material. The dielectric layer 6 is provided with a first via hole and a second via hole penetrating through the dielectric layer 6, the first via hole is opposite to the firstdoped region 112, that is, the orthographic projection of the first via hole on thesemiconductor layer 200 is at least partially overlapped with the firstdoped region 112; the second via is directly opposite to the fourthdoped region 213, i.e. the orthographic projection of the second via on thesemiconductor layer 200 at least partially coincides with the fourthdoped region 213.

Step S1270, forming a first electrode and a second electrode on the surface of the dielectric layer away from the gate insulating layer, where the first electrode is connected to the first doped region through a first via hole, and the second electrode is connected to the fourth doped region through a second via hole.

As shown in fig. 1, thefirst electrode 3 and thesecond electrode 4 may be simultaneously formed through a single patterning process, and thefirst electrode 3 is connected to the firstdoped region 112 through a first via hole; thesecond electrode 4 is connected to the fourthdoped region 213 through the second via hole. For example, an electrode material layer may be formed on the surface of the dielectric layer 6 away from the gate insulating layer, the electrode material layer filling the first via hole and the second via hole; thefirst electrode 3 and thesecond electrode 4 may be simultaneously formed through a photolithography process. The specific steps of the photolithography process are not described in detail herein, and thefirst electrode 3 and thesecond electrode 4 may be formed by other methods such as printing.

In this embodiment, thesecond channel region 211 is an N-type channel, the thirddoped region 212 is a P-type heavily doped region, the fourthdoped region 213 is an N-type doped region, thefirst electrode 3 is a source, and thesecond electrode 4 is a drain.

Second embodiment of the manufacturing method of the present disclosure

As shown in fig. 6, forming the thin film transistor and the tunneling transistor, step S120, may include steps S1210 to S1310, where:

step 1210, forming a first active layer on one side of the substrate, where the first active layer includes a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region.

Thebuffer layer 300 may be disposed on thesubstrate 100, the thin film transistor 1 may be disposed on a surface of thebuffer layer 300 away from thesubstrate 100, the tunneling transistor 2 is disposed on a side of the thin film transistor away from thesubstrate 100, and a material of thebuffer layer 300 is not limited in particular. Of course, thebuffer layer 300 may not be provided.

The material of the firstactive layer 11 may include polysilicon, which may be made by a low temperature polysilicon process. The structure of the firstactive layer 11 can refer to the second embodiment of the transistor device described above, and will not be described in detail here. When the firstactive layer 11 is formed, a semiconductor material layer may be formed first, and then the photoresist shields the region where thefirst channel region 111 is to be formed, so as to dope both sides of thefirst channel region 111 simultaneously, and obtain the firstdoped region 112 and the seconddoped region 113, where the doping type is not particularly limited.

Step S1220 is to form a gate insulating layer covering the first active layer.

The material of thegate insulating layer 5 is not particularly limited as long as it is insulating.

In step S1230, a first gate electrode is formed on the surface of the gate insulating layer away from the first active layer.

A gate material layer may be formed on the surface of thegate insulating layer 5 away from thesubstrate 100, and then thefirst gate 12 is formed by a photolithography process, and thefirst gate 12 is disposed opposite to thefirst channel region 111 of the firstactive layer 11. Of course, thefirst gate electrode 12 may be formed by other methods such as printing.

And S1240, forming a dielectric layer covering the first grid electrode and the grid insulating layer.

As shown in fig. 11, the material of the dielectric layer 6 is not particularly limited, and may be any insulating material. The dielectric layer 6 may be provided with a connecting via penetrating through the dielectric layer 6, the connecting via being directly opposite to the seconddoped region 113 of the firstactive layer 11, i.e. an orthographic projection of the connecting via on the firstactive layer 11 at least partially coincides with the seconddoped region 113.

Step S1250, forming a connection layer on the surface of the dielectric layer away from the gate insulating layer, where the connection layer is connected to the fourth doped region through a connection via.

As shown in fig. 12, a conductive layer may be formed on the surface of the dielectric layer 6 away from thegate insulating layer 5, and the conductive layer may be made of metal or the like and is filled with the connecting via hole, the conductive layer may be patterned by a photolithography process to obtain a connectinglayer 7, and the connectinglayer 7 is connected to the seconddoped region 113 through the connecting via hole. Of course, theconnection layer 7 may be formed in other ways.

Theconnection layer 7 may extend towards a side of the seconddoped region 113 away from thefirst channel region 111, i.e. towards an outer side of the firstactive layer 11, to avoid overlapping with the thin film transistor 1 in a direction perpendicular to thesubstrate 100.

Step S1260, forming a second active layer on the surface of the connection layer away from the dielectric layer, where the second active layer includes a third doped region, a second channel region, and a fourth doped region stacked in sequence along a direction away from the connection layer, the third doped region and the fourth doped region have different doping types, and the third doped region and the second doped region have the same doping type.

As shown in fig. 13, the material of the secondactive layer 21 may include polysilicon, which may be made by a low temperature polysilicon process. The specific structure of the secondactive layer 21 can refer to the second embodiment of the transistor device, and will not be described in detail here. In forming the secondactive layer 21, the thirddoped region 212, thesecond channel region 211 and the fourthdoped region 213 may be sequentially stacked by depositing three semiconductor layers on the surface of theconnection layer 7 away from the dielectric layer 6 by plasma enhanced chemical vapor deposition or other means, and etching. If plasma enhanced chemical vapor deposition is used, the gases used may include phosphanes and boranes.

Step S1270, forming a first planar layer covering the connection layer and the dielectric layer, wherein the second channel region and the fourth doped region protrude from the first planar layer.

The surface of thefirst planarization layer 8 away from the dielectric layer 6 is located on the side of the surface of thesecond channel region 211 away from theconnection layer 7 close to the dielectric layer 6, so that thesecond channel region 211 and the fourthdoped region 213 protrude from thefirst planarization layer 8 without being covered.

Step S1280, forming a second gate on the surface of the first planar layer away from the connection layer, wherein the second gate is opposite to the second channel region.

As shown in fig. 14, a gate metal layer may be formed on the surface of thefirst planarization layer 8 away from theconnection layer 7, and then patterned by a photolithography process, thereby obtaining thesecond gate 22. Of course, thesecond gate 22 may be formed in other ways. Meanwhile, thesecond gate 22 is disposed opposite to and spaced apart from thesecond channel region 211. Thesecond gate electrode 22 may be positioned at a side of thesecond channel region 211 close to or distant from the firstactive layer 11. Furthermore, the orthographic projection of thesecond gate 22 on the dielectric layer 6 is located within the range of theconnection layer 7.

Step S1290, forming a second planarization layer covering the first planarization layer, the second gate electrode, and the second active layer.

As shown in fig. 2, the material of the second planarization layer 9 may be the same as or different from that of thefirst planarization layer 8, and is not limited herein. It should be noted that a portion of the second planarization layer 9 located between thesecond gate 22 and thesecond channel region 211 may serve as a gate insulating layer of the tunneling transistor 2.

A first via hole and a second via hole can be formed in the second flat layer 9 through a hole opening process, the first via hole can penetrate through the second flat layer 9, the firstflat layer 8, the dielectric layer 6 and thegate insulating layer 5 and is opposite to the firstdoped region 112, namely, the orthographic projection of the first via hole on the firstactive layer 11 is at least partially overlapped with the firstdoped region 112; the second via hole may penetrate through the second planar layer 9 and directly face the fourthdoped region 213, that is, an orthographic projection of the second via hole on the secondactive layer 21 at least partially coincides with the fourthdoped region 213.

Step S1310, forming a first electrode and a second electrode on the surface of the second planarization layer away from the first planarization layer, where the first electrode is connected to the first doped region through a first via hole, and the second electrode is connected to the fourth doped region through a second via hole.

As shown in fig. 2, thefirst electrode 3 and thesecond electrode 4 may be formed simultaneously on the surface of the second planarization layer 9 away from thefirst planarization layer 8 by a single patterning process, thefirst electrode 3 is connected to thefirst doping region 112 through a first via, and thesecond electrode 4 is connected to thefourth doping region 213 through a second via. For example, an electrode material layer may be formed on the surface of the second planarization layer 9 away from thefirst planarization layer 8, the electrode material layer filling the first via hole and the second via hole; thefirst electrode 3 and thesecond electrode 4 may be simultaneously formed through a photolithography process. The specific steps of the photolithography process are not described in detail herein, and thefirst electrode 3 and thesecond electrode 4 may be formed by other methods such as printing.

In this embodiment, thesecond channel region 211 is an N-type channel, the thirddoped region 212 is a P-type heavily doped region, the fourthdoped region 213 is an N-type doped region, thefirst electrode 3 is a source, and thesecond electrode 4 is a drain.

In the third embodiment of the manufacturing method of the present disclosure, the transistor device in the third embodiment of the transistor device can be formed, the detailed structure of the transistor device is not described herein, and as shown in fig. 3, thefifth doping region 214 can be doped and formed simultaneously with thefirst doping region 112 and thesecond doping region 113. The second via hole may be opposite to the fifthdoped region 214, and thesecond electrode 4 is connected to the fifthdoped region 214 through the second via hole, and thus connected to the fourthdoped region 213.

The embodiments of the present disclosure provide a driving backplane, including the transistor device of any of the above embodiments, and specific details and advantageous effects of the transistor device may refer to the embodiments of the transistor device described above, which are not described herein again. The driving backboard can be provided with a plurality of transistor devices which are distributed in an array, so that the pixels distributed in the array are driven to display images.

The display panel can be an OLED display panel, an LCD display panel, and the like, can be used for electronic devices such as a mobile phone, a television, a tablet computer, and the like, and can include the above-mentioned driving back plate, and certainly, can also include

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (12)

1. A transistor device, comprising a thin film transistor, a tunneling transistor, a first electrode and a second electrode disposed on the same side of a substrate, wherein:

the thin film transistor comprises a first active layer and a first grid electrode, wherein the first active layer comprises a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region; the first grid electrode is opposite to the first channel region;

the tunneling transistor comprises a second active layer and a second grid electrode, the second active layer comprises a second channel region, a third doped region and a fourth doped region, the third doped region and the fourth doped region are separated from two sides of the second channel region and are different in doping type, and the second doped region is connected with the third doped region and is consistent in doping type; the second grid electrode is opposite to the second channel region;

the first electrode is connected with the first doped region;

the second electrode is connected with the fourth doped region.

2. The transistor device of claim 1, wherein the first active layer and the second active layer are different portions of the same semiconductor layer, and wherein the second doped region and the third doped region are both located between the first channel region and the second channel region.

3. The transistor device of claim 2, further comprising:

the grid insulating layer covers the semiconductor layer, and the first grid electrode and the second grid electrode are positioned on the surface, far away from the semiconductor layer, of the grid insulating layer;

a dielectric layer covering the gate insulating layer, the first gate electrode and the second gate electrode;

the first electrode and the second electrode are arranged on the surface, far away from the gate insulating layer, of the dielectric layer, the first electrode is connected with the first doping area through a first through hole, and the second electrode is connected with the fourth doping area through a second through hole.

4. The transistor device of claim 1, further comprising:

the gate insulating layer covers the first active layer, and the first gate is positioned on the surface of the gate insulating layer far away from the first active layer;

a dielectric layer covering the gate insulating layer and the first gate electrode;

the connecting layer is arranged on the surface, far away from the gate insulating layer, of the dielectric layer and is connected with the fourth doping region through a connecting through hole; the second active layer is arranged on the surface, far away from the dielectric layer, of the connecting layer, and the third doped region, the second channel region and the fourth doped region are sequentially stacked along the direction far away from the connecting layer;

the first flat layer covers the connecting layer and the dielectric layer, and the second channel region and the fourth doped region protrude out of the first flat layer; the second grid electrode is arranged on the surface, far away from the connecting layer, of the first flat layer and is opposite to the second channel region;

a second planarization layer covering the first planarization layer, the second gate electrode, and the second active layer;

the first electrode and the second electrode are both arranged on the surface, far away from the first flat layer, of the second flat layer, the first electrode is connected with the first doping region through a first through hole, and the second electrode is connected with the fourth doping region through a second through hole.

5. The transistor device of any of claims 1-4, wherein the material of at least one of the first active layer and the second active layer comprises polysilicon.

6. A method of manufacturing a transistor device, comprising:

providing a substrate;

forming a thin film transistor and a tunneling transistor on the same side of the substrate; the thin film transistor comprises a first active layer and a first grid electrode, wherein the first active layer comprises a first channel region, a first doped region and a second doped region, and the first doped region and the second doped region are separated from two sides of the first channel region; the first grid electrode is opposite to the first channel region; the tunneling transistor comprises a second active layer and a second grid electrode, the second active layer comprises a second channel region, a third doped region and a fourth doped region, the third doped region and the fourth doped region are separated from two sides of the second channel region and are different in doping type, and the second doped region is connected with the third doped region and is consistent in doping type; the second grid electrode is opposite to the second channel region;

forming a first electrode connected with the first doped region;

and forming a second electrode connected with the fourth doped region.

7. The method of manufacturing according to claim 6, wherein forming the thin film transistor and the tunneling transistor comprises:

forming a semiconductor layer on one side of the substrate, wherein the semiconductor layer comprises a first region and a second region;

doping a part of the first region to obtain a first active layer, wherein the first active layer comprises a first channel region, a first doping region and a second doping region, and the first doping region and the second doping region are separated from two sides of the first channel region;

doping a part of the second region to obtain a second active layer, wherein the second active layer comprises a second channel region, a third doping region and a fourth doping region, the third doping region and the fourth doping region are separated from two sides of the second channel region and have different doping types, and the second doping region is connected with the third doping region and has the same doping type; and the second doped region and the third doped region are both located between the first channel region and the second channel region.

8. The method of manufacturing according to claim 7, wherein forming the thin film transistor and the tunneling transistor further comprises:

forming a gate insulating layer covering the semiconductor layer;

forming the first grid electrode and the second grid electrode on the surface of the grid insulating layer far away from the semiconductor layer;

forming a dielectric layer covering the first gate electrode, the second gate electrode and the gate insulating layer;

and forming a first electrode and a second electrode on the surface of the dielectric layer far away from the gate insulating layer, wherein the first electrode is connected with the first doped region through a first through hole, and the second electrode is connected with the fourth doped region through a second through hole.

9. The method of manufacturing according to claim 6, wherein forming the thin film transistor and the tunneling transistor comprises:

forming a first active layer on one side of the substrate, wherein the first active layer comprises a first channel region, a first doping region and a second doping region, the first doping region and the second doping region are separated from two sides of the first channel region, and the doping types of the first doping region and the second doping region are different;

forming a gate insulating layer covering the first active layer;

forming a first grid electrode on the surface of the grid insulating layer far away from the first active layer;

forming a dielectric layer covering the first gate electrode and the gate insulating layer;

forming a connecting layer on the surface of the dielectric layer far away from the gate insulating layer, wherein the connecting layer is connected with the second doping region through a connecting through hole;

forming a second active layer on the surface of the connecting layer far away from the dielectric layer, wherein the second active layer comprises a third doped region, a second channel region and a fourth doped region which are sequentially stacked along the direction far away from the connecting layer, the doping types of the third doped region and the fourth doped region are different, and the doping types of the third doped region and the second doped region are consistent;

forming a first flat layer covering the connection layer and the dielectric layer, wherein the second channel region and the fourth doped region protrude from the first flat layer;

forming a second grid electrode on the surface of the first flat layer far away from the connecting layer, wherein the second grid electrode is arranged opposite to the second channel region;

forming a second planarization layer covering the first planarization layer, the second gate electrode, and the second active layer;

and forming a first electrode and a second electrode on the surface of the second flat layer far away from the first flat layer, wherein the first electrode is connected with the first doping region through a first through hole, and the second electrode is connected with the fourth doping region through a second through hole.

10. The manufacturing method according to any one of claims 6 to 9, wherein a material of at least one of the first active layer and the second active layer includes polysilicon.

11. A driving backplane comprising the transistor device of any of claims 1-5.

12. A display panel comprising the driving backplane of claim 11.

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