Summary of the invention
A kind of system for being designed to provide display device, driving backboard, transistor device and transistor device of the disclosureMethod is made, leakage current can be reduced, guarantees display effect.
According to one aspect of the disclosure, a kind of transistor device is provided, the film including being set to a substrate the same side is brilliantBody pipe, tunneling transistor, first electrode and second electrode, in which:
The thin film transistor (TFT) include the first active layer and first grid, first active layer include the first channel region,First doped region and the second doped region, first doped region and the second doped region are separated in the two sides of first channel region；The first grid and the first channel region face are arranged；
The tunneling transistor include the second active layer and second grid, second active layer include the second channel region,Third doped region and the 4th doped region, the third doped region and the 4th doped region be separated in the two sides of second channel region andDoping type is different, and second doped region is connected with the third doped region and doping type is consistent；The second grid withThe second channel region face setting；
The first electrode is connect with first doped region；
The second electrode is connect with the 4th doped region.
In a kind of exemplary embodiment of the disclosure, first active layer and second active layer are to lead with halfThe different piece of body layer, second doped region and the third doped region are respectively positioned on first channel region and second ditchBetween road area.
In a kind of exemplary embodiment of the disclosure, the transistor device further include:
Gate insulation layer, covers the semiconductor layer, and the first grid and the second grid are located at the gate insulation layerSurface far from the semiconductor layer；
Dielectric layer covers the gate insulation layer, the first grid and the second grid；
The first electrode and the second electrode are set to surface of the dielectric layer far from the gate insulation layer, and instituteState first electrode and connect with first doped region by the first via hole, the second electrode pass through second via hole with it is describedThe connection of 4th doped region.
In a kind of exemplary embodiment of the disclosure, the transistor device further include:
Gate insulation layer, covers first active layer, and the first grid is located at the gate insulation layer far from described firstThe surface of active layer；
Dielectric layer covers the gate insulation layer and the first grid；
Articulamentum, the surface set on the dielectric layer far from the gate insulation layer, and pass through connection via hole and the described 4thDoped region connection；Second active layer be set to surface of the articulamentum far from the dielectric layer, and the third doped region,Second channel region and the 4th doped region are stacked gradually along the direction far from the articulamentum；
First flatness layer covers the articulamentum and the dielectric layer, second channel region and the 4th doped regionProtrude from first flatness layer；The second grid be set to the surface of first flatness layer far from the articulamentum, and withThe second channel region face setting；
Second flatness layer covers first flatness layer, the second grid and second active layer；
The first electrode and the second electrode are set to table of second flatness layer far from first flatness layerFace, and the first electrode connect by the first via hole with first doped region, the second electrode pass through the second via hole andThe 4th doped region connection.
In a kind of exemplary embodiment of the disclosure, at least one in first active layer and second active layerMaterial include polysilicon.
According to one aspect of the disclosure, a kind of manufacturing method of transistor device is provided, comprising:
One substrate is provided；
Thin film transistor (TFT) and tunneling transistor are formed in the same side of the substrate；The thin film transistor (TFT) has including firstActive layer and first grid, first active layer include the first channel region, the first doped region and the second doped region, and described first mixesMiscellaneous area and the second doped region are separated in the two sides of first channel region；The first grid is set with the first channel region faceIt sets；The tunneling transistor includes the second active layer and second grid, and second active layer is mixed including the second channel region, thirdMiscellaneous area and the 4th doped region, the third doped region and the 4th doped region are separated in the two sides of second channel region and doping classType is different, and second doped region is connected with the third doped region and doping type is consistent；The second grid and described theThe setting of two channel region faces；
Form the first electrode connecting with first doped region；
Form the second electrode connecting with the 4th doped region.
In a kind of exemplary embodiment of the disclosure, the thin film transistor (TFT) and the tunneling transistor are formed, comprising:
Semiconductor layer is formed in the one side of substrate, the semiconductor layer includes first area and second area；
The part of the first area is doped, to obtain the first active layer, first active layer includes firstChannel region, the first doped region and the second doped region, first doped region and the second doped region are separated in first channel regionTwo sides；
The part of the second area is doped, the second active layer is obtained, second active layer includes the second ditchRoad area, third doped region and the 4th doped region, the third doped region and the 4th doped region are separated in second channel regionTwo sides and doping type difference, second doped region is connected with the third doped region and doping type is consistent；And describedTwo doped regions and the third doped region are respectively positioned between first channel region and second channel region.
In a kind of exemplary embodiment of the disclosure, the thin film transistor (TFT) and the tunneling transistor are formed, is also wrappedIt includes:
Form the gate insulation layer for covering the semiconductor layer；
The first grid and the second grid are formed far from the surface of the semiconductor layer in the gate insulation layer；
Form the dielectric layer for covering the first grid, the second grid and the gate insulation layer；
Formation first electrode and second electrode on surface of the dielectric layer far from the gate insulation layer, first electricityPole is connect by the first via hole with first doped region, and the second electrode is connected by the second via hole and the 4th doped regionIt connects.
In a kind of exemplary embodiment of the disclosure, the thin film transistor (TFT) and the tunneling transistor are formed, comprising:
The first active layer is formed in the one side of substrate, first active layer includes the first channel region, the first doped regionWith the second doped region, first doped region and the second doped region are separated in the two sides of first channel region, and described firstDoped region and the second doped region doping type are different；
Form the gate insulation layer for covering first active layer；
First grid is formed far from the surface of first active layer in the gate insulation layer；
Form the dielectric layer for covering the first grid and the gate insulation layer；
The dielectric layer far from the gate insulation layer surface formed articulamentum, the articulamentum by connection via hole withThe second doped region connection；
The second active layer is formed far from the surface of the dielectric layer in the articulamentum, second active layer includes along remoteThird doped region, the second channel region and the 4th doped region that direction from the articulamentum stacks gradually, the third doped regionDifferent with the doping type of the 4th doped region, the third doped region is consistent with the doping type of second doped region；
Form the first flatness layer of the covering articulamentum and the dielectric layer, second channel region and the 4th doped regionProtrude from first flatness layer；
First flatness layer far from the articulamentum surface formed second grid, and the second grid with it is describedThe setting of second channel region face；
Form the second flatness layer for covering first flatness layer, the second grid and second active layer；
First electrode and second electrode are formed far from the surface of first flatness layer in second flatness layer, described theOne electrode is connect by the first via hole with first doped region, and the second electrode passes through the second via hole and the 4th dopingArea's connection.
In a kind of exemplary embodiment of the disclosure, at least one in first active layer and second active layerMaterial include polysilicon.
According to one aspect of the disclosure, a kind of driving backboard is provided, including transistors described in above-mentioned any onePart.
According to one aspect of the disclosure, a kind of display panel is provided, including driving backboard described in above-mentioned any one.
Display device, driving backboard, transistor device and its manufacturing method of the disclosure, due to the second of thin film transistor (TFT)Doped region is connected with the third doped region of tunneling transistor and doping type is consistent, and the first of first electrode and thin film transistor (TFT)4th doped region of doped region connection, second electrode and tunneling transistor connects, so as to by thin film transistor (TFT) and tunnelling crystalPipe is connected between the first electrode and the second electrode；It is disconnected when tunneling transistor does not work, between first electrode and second electrodeLine state makes thin film transistor (TFT) off state, so as to greatly reduce the leakage current of thin film transistor (TFT), to guarantee display effectFruit.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, notThe disclosure can be limited.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapesFormula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the disclosure willFully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Identical attached drawing in figureLabel indicates same or similar structure, thus the detailed description that will omit them.In addition, attached drawing is only the schematic of the disclosureDiagram, is not necessarily drawn to scale.
Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specificationThe relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in showThe direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" willAs the component in "lower".When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structuresOn, or refer to that certain structure is " direct " and be arranged in other structures, or refer to that certain structure is arranged by the way that another structure is " indirect " in other knotsOn structure.
Term "one", " one ", "the", " described " and "at least one" be to indicate that there are one or more elements/groupsAt part/etc.；Term " comprising " and " having " is to indicate the open meaning being included and refer in addition to listingElement/component part/also may be present except waiting other element/component part/etc.；Term " first ", " second ", " third " and" the 4th " only uses as label, is not the quantity limitation to its object.
Disclosure embodiment provides a kind of transistor device, can be used for the driving backboard of display panel, the display surfacePlate can be OLED display panel, and but not limited to this, can also be LCD display panel etc..
As shown in Figure 1-Figure 3, the transistor device of disclosure embodiment include thin film transistor (TFT) 1, tunneling transistor 2,First electrode 3 and second electrode 4, thin film transistor (TFT) 1 and tunneling transistor 2 are set to 100 the same side of a substrate, in which:
Thin film transistor (TFT) 1 includes the first active layer 11 and first grid 12, and the first active layer 11 includes the first channel region111, the first doped region 112 and the second doped region 113, the first doped region 112 and the second doped region 113 are separated in the first channel region111 two sides；First grid 12 and 111 face of the first channel region are arranged.
Tunneling transistor 2 includes the second active layer 21 and second grid 22, and the second active layer 21 includes the second channel region211, third doped region 212 and the 4th doped region 213, third doped region 212 and the 4th doped region 213 are separated in the second channel region211 two sides and doping type is different, the second doped region 113 is consistent with the connection of third doped region 212 and doping type；Second gatePole 22 and 211 face of the second channel region are arranged.
First electrode 3 is connect with the first doped region 112, and second electrode 4 is connect with the 4th doped region 213.
The transistor device of disclosure embodiment due to the second doped region 113 and the connection of third doped region 212 and adulteratesType is consistent, and first electrode 3 is connect with the first doped region 112, and second electrode 4 is connect with the 4th doped region 213, so as to incite somebody to actionThin film transistor (TFT) 1 and tunneling transistor 2 are connected between first electrode 3 and second electrode 4；When tunneling transistor 2 does not work,It is off state between first electrode 3 and second electrode 4, makes 1 off state of thin film transistor (TFT), so as to greatly reduce filmThe leakage current of transistor 1, to guarantee display effect.
Substrate 100 can be the materials rigid substrates such as glass, be also possible to the materials such as poly terephthalic acid class plastics (PET)Flexible substrate, herein not to its material can shape do particular determination.
Thin film transistor (TFT) 1 can be N-type TFT or P-type TFT, and the first channel region 111 can be N-type channelOr P-type channel, the doping type of the first doped region 112 and the second doped region 113 can be all n-type doping or p-type doping, specifically may be usedDepending on the type of thin film transistor (TFT) 1, particular determination is not done herein.Meanwhile first the material of active layer 11 include polysilicon materialMaterial, and formed by low temperature polysilicon process, so that thin film transistor (TFT) 1 can be low-temperature polysilicon film transistor.
First grid 12 can be set to the first side of the active layer 11 far from substrate 100, and set with 111 face of the first channel regionIt sets, i.e. orthographic projection of the first grid 12 on the first active layer 11 is at least partly overlapped with the first channel region 111.
Tunneling transistor 2 can be N-type tunneling transistor or p-type tunneling transistor, and the second channel region 211 can be N-type channelOr P-type channel；Third doped region 212 is different with the doping type of the 4th doped region 213, for example, third doped region 212 is N-typeDoping, the 4th doped region 213 are p-type doping；Alternatively, third doped region 212 is n-type doping, the 4th doped region 213 is mixed for p-typeIt is miscellaneous；Specifically particular determination can not be done herein depending on the type of tunneling transistor 2.Meanwhile second the material of active layer 21 includePolycrystalline silicon material, and formed by low temperature polysilicon process, so that tunneling transistor 2 can be low temperature polycrystalline silicon tunnelling film crystalPipe.P-type doping can be p-type heavy doping or p-type is lightly doped, and n-type doping can be N-type heavy doping or N-type is lightly doped.
Second grid 22 can be set to the second side of the active layer 21 far from substrate 100, and set with 211 face of the second channel regionIt sets, i.e. orthographic projection of the second grid 22 on the second active layer 21 is at least partly overlapped with the second channel region 211.
First electrode 3 and second electrode 4 are the conductive materials such as metal, and one of them is source electrode, another is drain electrode,Such as: the first electrode 3 connecting with the first doped region 112 of thin film transistor (TFT) 1 is source electrode, and second electrode 4 is drain electrode.
The first embodiment of disclosure transistor device
As shown in Figure 1, buffer layer 300 can be arranged on substrate 100, thin film transistor (TFT) 1 and tunneling transistor 2 can same layer setSet on surface of the buffer layer 300 far from substrate 100, the material of buffer layer 300 do not do herein it is special sex-limited, specifically:
As shown in Figure 1, the first active layer 11 and the second active layer 21 are contained in same semi-conductor layer 200, i.e., first is activeLayer 11 and the second active layer 21 are the different piece of the semiconductor layer 200, and semiconductor layer 200 is set to buffer layer 300 far from substrateOn 100 surface.Second doped region 113 and third doped region 212 be respectively positioned on the first channel region 111 and the second channel region 211 itBetween, and the second doped region 113 is consistent with the doping type of third doped region 212, for example, the second doped region 113 is adulterated with thirdArea 212 is p-type doping, and the second doped region 113 and third doped region 212 connect, so that thin film transistor (TFT) 1 and tunnelling is brilliantBody pipe 2 is together in series.Since the first active layer 11 and the second active layer 21 are contained in same semi-conductor layer 200, avoid being firstActive layer 11 and the second active layer 21 are respectively formed different semiconductor layers, so that technique be made to be simplified.
As shown in Figure 1, first grid 12 be set to side of the semiconductor layer 200 far from substrate 100, and with the first channel region111 faces, second grid 22 be set to side of the semiconductor layer 200 far from substrate 100, and with 211 face of the second channel region.
Further, as shown in Figure 1, the transistor device of present embodiment can also include gate insulation layer 5 and dielectric layer6, in which:
Gate insulation layer 5 can coat semiconductor layer 200, and the material of gate insulation layer 5 does not do particular determination herein, as long as insulation isIt can.
First grid 12 and second grid 22 are located at surface of the gate insulation layer 5 far from semiconductor layer 200, so as to pass through structureFigure technique is formed, and is conducive to simplify technique.111 face of first grid 12 and the first channel region, second grid 22 and the second ditch211 face of road area.
Dielectric layer 6 can cover gate insulation layer 5, first grid 12 and second grid 22, and material does not do particular determination herein,As long as insulating materials.Dielectric layer 6 is equipped with the first via hole and the second via hole through dielectric layer 6, the first via hole and firstThe orthographic projection on semiconductor layer 200 of 112 face of doped region, i.e. the first via hole is at least partly overlapped with the first doped region 112；Second213 face of via hole and the 4th doped region, i.e. the second via hole orthographic projection and the 4th doped region 213 at least portion on semiconductor layer 200Divide and is overlapped.
First electrode 3 and second electrode 4 are set to surface of the dielectric layer 6 far from gate insulation layer 5, and first electrode 3 passes throughFirst via hole is connect with the first doped region 112；Second electrode 4 is connect by second via hole with the 4th doped region 213.
In present embodiment, the second channel region 211 is N-type channel, and third doped region 212 can be p-type heavy doping, and the 4th mixesMiscellaneous area 213 can be n-type doping, and first electrode 3 is source electrode, and second electrode 4 is drain electrode.
It is of course also possible to above-mentioned buffer layer 300 is not provided with, as long as 2 same layer of thin film transistor (TFT) 1 and tunneling transistor can be madeThe same side of substrate 100 is set.
The second embodiment of disclosure transistor device
As shown in Fig. 2, thin film transistor (TFT) 1 and tunneling transistor 2 can be in direction of 100 1 lateral edge of substrate far from substrate 100Distribution, for example:
Buffer layer 300 can be set on substrate 100, and thin film transistor (TFT) 1 may be provided at buffer layer 300 far from substrate 100On surface, tunneling transistor 2 is located at side of the thin film transistor (TFT) 1 far from substrate 100, and the material of buffer layer 300 is not spy hereinIt is different sex-limited.It is of course also possible to be not provided with above-mentioned buffer layer 300.
As shown in Fig. 2, the first active layer 11 is set to 100 side of substrate, the specific structure of the first active layer 11 be can refer toThe first active layer 11 in first embodiment is stated, this will not be detailed here.Meanwhile transistor device may also include gate insulation layer 5,Dielectric layer 6, articulamentum 7, the first flatness layer 8 and the second flatness layer 9, in which:
Gate insulation layer 5 covers the first active layer 11, and the material of gate insulation layer 5 does not do particular determination herein, as long as insulation isIt can.
First grid 12 is set to surface of the gate insulation layer 5 far from substrate 100, and the first channel region with the first active layer 11The setting of 111 faces.
Dielectric layer 6 covers gate insulation layer 5 and first grid 12, i.e., covering surface of the gate insulation layer 5 far from substrate 100 not byThe region of first grid 12 and first grid 12.The material of dielectric layer 6 does not do particular determination herein, as long as insulating materials isIt can.Dielectric layer 6 can be equipped with the connection via hole through dielectric layer 6, connect the second doped region 113 of via hole and the first active layer 11 justRight, i.e. orthographic projection of the connection via hole on the first active layer 11 is at least partly overlapped with the second doped region 113.
Articulamentum 7 can be set to surface of the dielectric layer 6 far from gate insulation layer 5, and pass through connection via hole and the second doped region 113Connection.The material of articulamentum 7 can be metal etc., as long as conduction.Articulamentum 7 can be to the second doped region 113 far from the first ditchThe side in road area 111 extends, i.e., to extending on the outside of the first active layer 11, to avoid on the direction of vertical substrates 100 with filmTransistor 1 is overlapped.
As shown in Fig. 2, the second active layer 21 can be set to surface of the articulamentum 7 far from dielectric layer 6, and third doped region 212,Second channel region 211 and the 4th doped region 213 are cascading along the direction far from articulamentum 7, i.e., third doped region 212 is setIn surface of the articulamentum 7 far from dielectric layer 6, the second channel region 211 is set to the surface of 212 articulamentum 7 of third doped region, and the 4th mixesMiscellaneous area 213 is set to the second surface of the channel region 211 far from third doped region 212.
First flatness layer 8 covers articulamentum 7 and dielectric layer 6, but the first flatness layer 8 is located at the far from the surface of dielectric layer 6Two surfaces of the channel region 211 far from articulamentum 7 are close to the side of dielectric layer 6, so that the second channel region 211 and the 4th doped region213 protrude from the first flatness layer 8, and are uncovered.
Second grid 22 be set to the first surface of the flatness layer 8 far from articulamentum 7, and with 211 face interval of the second channel regionSetting, second grid 22 can be located at the second channel region 211 close to or far from the side of the first active layer 11.Meanwhile second grid22 within the scope of the orthographic projection on dielectric layer 6 is located at articulamentum 7.
Second flatness layer 9 covers the first flatness layer 8, second grid 22 and the second active layer 21, to realize planarization.TheThe material of two flatness layers 9 can be identical as the first flatness layer 8, can also be different, does not do particular determination herein.It should be noted thatThe part that second flatness layer 9 is located between second grid 22 and the second channel region 211 can be used as the gate insulation of tunneling transistor 2Layer.
Second flatness layer 9 can be equipped with the first via hole and the second via hole, and the first via hole can be flat through the second flatness layer 9, firstSmooth layer 8, dielectric layer 6 and gate insulation layer 5, and with 112 face of the first doped region, i.e. the first via hole just throwing on the first active layer 11Shadow is at least partly overlapped with the first doped region 112；Second via hole can run through the second flatness layer 9, and just with the 4th doped region 213Right, i.e. the second via hole orthographic projection on the second active layer 21 is at least partly overlapped with the 4th doped region 213.
First electrode 3 and second electrode 4 are set to surface of second flatness layer 9 far from the second flatness layer 9, and first electrode3 are connect by the first via hole with the first doped region 112, and second electrode 4 is connect by the second via hole with the 4th doped region 213.
In present embodiment, the second channel region 211 is N-type channel, and third doped region 212 can be p-type heavy doping, and the 4th mixesMiscellaneous area 213 can be n-type doping, and first electrode 3 is source electrode, and second electrode 4 is drain electrode.
In the third embodiment of disclosure transistor device, the first embodiment based on above-mentioned transistor deviceIn, as shown in figure 3, semiconductor layer 200 may also include third region, third region is located at second area and is adjacent to far from the firstth areaThe side in domain may be doped third region, and doping type is identical as the first doped region 112 and the second doped region 113, obtain5th doped region 214, the 5th doped region 214 belongs to tunneling transistor 2, and connects with the 4th doped region 213, and the second via hole can be with5th doped region, 214 face, second electrode 4 is connect by the second via hole with the 5th doped region 214, thus with the 4th doped region213 connections.
In the 4th embodiment of disclosure transistor device, tunneling transistor 2 can be located at thin film transistor (TFT) 1 and substrateBetween 100, for example, can make the first active layer 11, the second replacement mutually of active layer 21, second electrode 4 and second electrode 4 are replaced mutuallyIt changes.
In the other embodiment of disclosure transistor device, it is based on above-mentioned second embodiment, the second active layer 21Third doped region 212, the second channel region 211 and the 4th doped region 213 can be set to surface of the articulamentum 7 far from dielectric layer 6, andIt is no longer laminated along the direction far from articulamentum 7, other structures can be identical as above-mentioned second embodiment, and this will not be detailed here.
Disclosure embodiment provides a kind of manufacturing method of transistor device, which can be above-mentioned transistorTransistor device in any embodiment of device.As shown in figure 4, the manufacturing method includes:
Step S110, a substrate is provided；
Step S120, thin film transistor (TFT) and tunneling transistor are formed in the same side of the substrate；The thin film transistor (TFT)Including the first active layer and the first grid, first it is active include the first channel region, the first doped region and the second doped region, described firstDoped region and the second doped region are separated in the two sides of first channel region；The tunneling transistor includes the second active layer and theTwo grids, the second active layer include the second channel region, third doped region and the 4th doped region, and the third doped region and the 4th is mixedMiscellaneous area is separated in the two sides of second channel region and doping type is different, and second doped region and the third doped region connectIt connects and doping type is consistent；
Step S130, the first electrode connecting with first doped region is formed；
Step S140, the second electrode connecting with the 4th doped region is formed.
The beneficial effect of disclosure manufacturing method can refer to the beneficial effect of above-mentioned transistor device, and thin film transistor (TFT) andThe specific structure of tunneling transistor is described in detail in the embodiment of transistor device above, herein no longer in detailIt states.
The first embodiment of disclosure manufacturing method
As shown in figure 5, form the thin film transistor (TFT) and the tunneling transistor, i.e. step S110, including stepS1210- step S1230, in which:
Step S1210, semiconductor layer is formed in the one side of substrate, the semiconductor layer includes first area and the secondth areaDomain.
As shown in fig. 7, buffer layer 300 can be arranged on substrate 100, thin film transistor (TFT) 1 and tunneling transistor 2 can same layer setIt sets on surface of the buffer layer 300 far from substrate 100, the material of buffer layer 300 does not do special sex-limited herein.
Semiconductor layer 200 is formed in surface of the buffer layer 300 far from substrate 100, and the material of semiconductor layer 200 may includePolysilicon can be made up of low temperature polysilicon process.For example, amorphous silicon layer can be formed on substrate 100, pass through laser annealingTechnique handles amorphous silicon layer, obtains the semiconductor layer 200 of polycrystalline silicon material.First area and second area are adjacentTwo isolated areas.
Step S1220, the part of the first area is doped, to obtain the first active layer, the first active layer packetThe first channel region, the first doped region and the second doped region are included, first doped region and the second doped region are separated in described firstThe two sides of channel region.
As shown in Figure 10, the doping type of the first doped region 112 and the second doped region 113 can be all that n-type doping or p-type are mixedIt is miscellaneous, depending on the type of specific visual film transistor 1, particular determination is not done herein.For example, semiconductor layer can be covered by photoresist200, after overexposure, development, expose the region of the first doped region 112 and the second doped region 113 to be formed；Then, by fromSon injection or other modes by doping process to the region of the first doped region 112 to be formed and the second doped region 113 intoRow doping.Certainly, doping can also be performed in multiple times.
Step S1230, the part of the second area is doped, obtains the second active layer, the second active layer includesSecond channel region, third doped region and the 4th doped region, the third doped region and the 4th doped region are separated in second ditchThe two sides in road area and doping type is different, second doped region is connected with the third doped region and doping type is consistent；AndSecond doped region and the third doped region are respectively positioned between first channel region and second channel region.
As shown in Figure 8 and Figure 9, the doping type of third doped region 212 and the 4th doped region 213 can be n-type doping or p-typeDoping, but the doping type of third doped region 212 and the 4th doped region 213 is different, the type of specific visual tunneling transistor 2 andIt is fixed, particular determination is not done herein.For example, semiconductor layer 200 can be covered by photoresist layer, after overexposure, development, expose thirdIt one in doped region 212 or the 4th doped region 213, and is doped by ion implanting or other modes, then removes the photoresistLayer.Form the photoresist layer of covering semiconductor layer 200, through exposure and development after, expose third doped region 212 and the 4th doped region 213In another, and be doped by ion implanting or other modes, again removing photoresistance layer, thus to 212 He of third doped region4th doped region 213 is doped respectively, and doping type is different.For example, third doped region 212 is p-type doping, the 4th dopingArea 213 is n-type doping.
It should be noted that above-mentioned steps S1230 and step S1220 can be carried out before step S1220, it can also be in stepIt is carried out before after S1220.
Further, as shown in figure 5, formation thin film transistor (TFT) and tunneling transistor, i.e. step S110 may also include stepS1240- step S1270, in which:
Step S1240, the gate insulation layer for covering the semiconductor layer is formed.
Gate insulation layer 5 can coat semiconductor layer 200, and material does not do particular determination herein, as long as insulation.
Step S1250, the first grid and described is formed far from the surface of the semiconductor layer in the gate insulation layerSecond grid.
As shown in Figure 10, first grid 12 and second grid 22 are located at surface of the gate insulation layer 5 far from semiconductor layer 200,So as to be formed by patterning processes, be conducive to simplify technique.For example, can be in table of the gate insulation layer 5 far from semiconductor layer 200Face forms gate material layers, then forms first grid 12 and second grid 22, the specific steps of photoetching process by photoetching processThis will not be detailed here.111 face of first grid 12 and the first channel region, 211 face of second grid 22 and the second channel region.WhenSo, also first grid 12 and second grid 22 can be formed by other ways such as printings.As shown in Figure 10, above-mentioned stepS1220 can be carried out after step S1250.
Step S1260, the dielectric layer for covering the first grid, the second grid and the gate insulation layer is formed.
As shown in Figure 1, the material of dielectric layer 6 does not do particular determination herein, as long as insulating materials.Dielectric layer 6 is setThere are the first via hole and the second via hole through dielectric layer 6,112 face of the first via hole and the first doped region, i.e. the first via hole is halfOrthographic projection is at least partly overlapped with the first doped region 112 in conductor layer 200；213 face of second via hole and the 4th doped region, i.e.,The orthographic projection on semiconductor layer 200 of two via holes is at least partly overlapped with the 4th doped region 213.
Step S1270, in the formation first electrode and second electrode on surface of the dielectric layer far from the gate insulation layer,The first electrode connect by the first via hole with first doped region, and the second electrode passes through the second via hole and described theThe connection of four doped regions.
As shown in Figure 1, first electrode 3 and second electrode 4, and first electrode 3 can be formed simultaneously by a patterning processesIt is connect by the first via hole with the first doped region 112；Second electrode 4 is connect by second via hole with the 4th doped region 213.For example, electrode material layer can be formed far from the surface of gate insulation layer in dielectric layer 6, electrode material layer fills the first via hole and secondVia hole；First electrode 3 and second electrode 4 can be formed simultaneously by photoetching process.The specific steps of photoetching process are no longer detailed hereinIt states certainly, can also form first electrode 3 and second electrode 4 by other ways such as printings.
In present embodiment, the second channel region 211 is N-type channel, and third doped region 212 can be p-type heavy doping, and the 4th mixesMiscellaneous area 213 can be n-type doping, and first electrode 3 is source electrode, and second electrode 4 is drain electrode.
The second embodiment of disclosure manufacturing method
As shown in fig. 6, forming thin film transistor (TFT) and tunneling transistor, step S120, it may include step S1210- stepS1310, in which:
Step S1210, the first active layer is formed in the one side of substrate, the first active layer includes the first channel region, firstDoped region and the second doped region, first doped region and the second doped region are separated in the two sides of first channel region.
Buffer layer 300 can be set on substrate 100, and thin film transistor (TFT) 1 may be provided at buffer layer 300 far from substrate 100On surface, tunneling transistor 2 is located at side of the thin film transistor (TFT) far from substrate 100, and it is special that the material of buffer layer 300 is not done hereinIt is sex-limited.It is of course also possible to be not provided with above-mentioned buffer layer 300.
The material of first active layer 11 may include polysilicon, can be made up of low temperature polysilicon process.First active layer11 structure can refer to the second embodiment of above-mentioned transistor device, and this will not be detailed here.When forming the first active layer 11,It can be initially formed semiconductor material layer, then covered by the region that photoresist covers the first channel region 111 to be formed, to the first ditchThe two sides in road area 111 are doped simultaneously, while obtaining the first doped region 112 and the second doped region 113, doping type it is secondary notDo particular determination.
Step S1220, the gate insulation layer of the first active layer of covering is formed.
The material of gate insulation layer 5 does not do particular determination herein, as long as insulation.
Step S1230, first grid is formed far from the surface of the first active layer in the gate insulation layer.
Gate material layers can be formed far from the surface of substrate 100 in gate insulation layer 5, then the first grid is formed by photoetching processPole 12, and 111 face of the first channel region of first grid 12 and the first active layer 11 is arranged.Certainly, can also by printing etc. itsIts mode forms first grid 12.
Step S1240, the dielectric layer for covering the first grid and the gate insulation layer is formed.
As shown in figure 11, the material of dielectric layer 6 does not do particular determination herein, as long as insulating materials.Dielectric layer 6 canEquipped with the connection via hole for running through dielectric layer 6,113 face of the second doped region of via hole and the first active layer 11 is connected, that is, was connectedOrthographic projection of the hole on the first active layer 11 is at least partly overlapped with the second doped region 113.
Step S1250, articulamentum is formed far from the surface of the gate insulation layer in the dielectric layer, the articulamentum passes throughConnection via hole is connect with the 4th doped region.
As shown in figure 12, conductive layer, and the material of the conductive layer can be formed far from the surface of gate insulation layer 5 in dielectric layer 6It can be metal etc., and fill connection via hole, conductive layer can be patterned by photoetching process, obtain articulamentum 7, articulamentum7 are connect by connecting via hole with the second doped region 113.Certainly, articulamentum 7 can also be formed in alternative ways.
Articulamentum 7 can extend to the second doped region 113 far from the side of the first channel region 111, i.e., to the first active layer 11Outside extends, and is overlapped to avoid on the direction of vertical substrates 100 with thin film transistor (TFT) 1.
Step S1260, the second active layer, the second active layer packet are formed far from the surface of the dielectric layer in the articulamentumInclude third doped region, the second channel region and the 4th doped region stacked gradually along the direction far from the articulamentum, the thirdDoped region is different with the doping type of the 4th doped region, the doping type of the third doped region and second doped regionUnanimously.
As shown in figure 13, the material of the second active layer 21 may include polysilicon, can be made up of low temperature polysilicon process.The specific structure of second active layer 21 can refer to the second embodiment of above-mentioned transistor device, and this will not be detailed here.It is being formedWhen the second active layer 21, can by surface of the articulamentum 7 far from dielectric layer 6 by plasma enhanced chemical vapor deposition orOther way deposits three-layer semiconductor layer, and performs etching, and stacks gradually third doped region 212, the second channel region to be formed211 and the 4th doped region 213.According to plasma enhanced chemical vapor deposition, then the gas used may include phosphine and boronAlkane.
Step S1270, formed covering the articulamentum and the dielectric layer the first flatness layer, second channel region and4th doped region protrudes from first flatness layer.
First flatness layer 8 is located at the second surface of the channel region 211 far from articulamentum 7 close to Jie far from the surface of dielectric layer 6The side of electric layer 6 so that the second channel region 211 and the 4th doped region 213 protrude from the first flatness layer 8, and is uncovered.
Step S1280, second grid, and described second are formed far from the surface of the articulamentum in first flatness layerGrid and the second channel region face are arranged.
As shown in figure 14, gate metal layer can be formed far from the surface of articulamentum 7 in the first flatness layer 8, then passes through photoetchingTechnique patterns gate metal layer, to obtain second grid 22.Certainly, second gate can also be formed in alternative waysPole 22.Meanwhile second grid 22 and 211 face interval of the second channel region are arranged.Second grid 22 can be located at the second channel region 211Close to or far from the side of the first active layer 11.In addition, orthographic projection of the second grid 22 on dielectric layer 6 is located at articulamentum 7Within range.
Step S1290, form covering first flatness layer, the second grid and the second active layer second is flatLayer.
As shown in Fig. 2, the material of the second flatness layer 9 can be identical as the first flatness layer 8, it can also be different, be not spy hereinIt is different to limit.It should be noted that the part that the second flatness layer 9 is located between second grid 22 and the second channel region 211 can be used asThe gate insulation layer of tunneling transistor 2.
The first via hole and the second via hole can be opened up in the second flatness layer 9 by hole opening technology, the first via hole can run through secondFlatness layer 9, the first flatness layer 8, dielectric layer 6 and gate insulation layer 5, and with 112 face of the first doped region, i.e., the first via hole is firstOrthographic projection is at least partly overlapped with the first doped region 112 on active layer 11；Second via hole can run through the second flatness layer 9, and with theThe orthographic projection on the second active layer 21 of four doped regions, 213 face, i.e. the second via hole is at least partly overlapped with the 4th doped region 213.
Step S1310, first electrode and second is formed far from the surface of first flatness layer in second flatness layerElectrode, the first electrode connects by the first via hole with first doped region, the second electrode pass through the second via hole andThe 4th doped region connection.
As shown in Fig. 2, can be by a patterning processes in surface of second flatness layer 9 far from the first flatness layer 8 while shapeAt first electrode 3 and 4 first electrode 3 of second electrode and second electrode 4, and first electrode 3 passes through the first via hole and the first dopingArea 112 connects, and second electrode 4 is connect by the second via hole with the 4th doped region 213.For example, can be in the second flatness layer 9 far fromThe surface of one flatness layer 8 forms electrode material layer, and electrode material layer fills the first via hole and the second via hole；Photoetching process can be passed throughIt is formed simultaneously first electrode 3 and second electrode 4.This will not be detailed here for the specific steps of photoetching process certainly, can also pass through printingEtc. other ways form first electrode 3 and second electrode 4.
In present embodiment, the second channel region 211 is N-type channel, and third doped region 212 can be p-type heavy doping, and the 4th mixesMiscellaneous area 213 can be n-type doping, and first electrode 3 is source electrode, and second electrode 4 is drain electrode.
In the third embodiment of disclosure manufacturing method, the third embodiment party of above-mentioned transistor device can be used to formTransistor device in formula, details are not described herein for the detailed construction of transistor device, as shown in figure 3, the 5th doped region 214 can be withFirst doped region 112 and the second doped region 113 adulterate to be formed simultaneously.Second via hole can be with 214 face of the 5th doped region, the second electricityPole 4 is connect by the second via hole with the 5th doped region 214, to connect with the 4th doped region 213.
Disclosure embodiment provides a kind of driving backboard, the transistor device including above-mentioned any embodiment, the crystalline substanceThe detail and beneficial effect of body tube device can refer in the embodiment of above-mentioned transistor device, and details are not described herein.It shouldDrive the transistor device of backboard can be to be multiple, and array distribution, so that the pixel of drive array distribution shows image.
Disclosure embodiment also provides a kind of display panel, which can be with OLED display panel, LCD display surfacePlate etc. can be used for the electronic equipments such as mobile phone, TV, tablet computer, which may include above-mentioned driving backboard, certainly,Can also include
In addition, although describing each step of method in the disclosure in the accompanying drawings with particular order, this does not really wantThese steps must be executed in this particular order by asking or implying, or having to carry out step shown in whole could realizeDesired result.Additional or alternative, it is convenient to omit multiple steps are merged into a step and executed by certain steps, and/Or a step is decomposed into execution of multiple steps etc..
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosureIts embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes orPerson's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosureOr conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appendedClaim is pointed out.