CN109901784B

Movatterモバイル変換

Info

Publication number: CN109901784B
Application number: CN201711293129.6A
Authority: CN
Inventors: 林纬; 刘安城; 欧沥元; 陈思玮
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-12-08
Filing date: 2017-12-08
Publication date: 2022-03-29
Anticipated expiration: 2037-12-08
Also published as: CN109901784A

Abstract

一种数据存取方法、存储器控制电路单元以及存储器储存装置。此方法包括：使用第一读取电压读取第一实体程序化单元以取得第一数据；使用第二读取电压读取第一实体程序化单元以取得第二数据；将对应第一数据的第一状态参数以及对应第二数据的第二状态参数输入至数值运算引擎，并通过数值运算引擎决定用于读取第一实体程序化单元的第三读取电压。

A data access method, a memory control circuit unit, and a memory storage device. The method includes: using a first reading voltage to read a first physical programming unit to obtain first data; using a second reading voltage to read the first physical programming unit to obtain second data; The first state parameter and the second state parameter corresponding to the second data are input to the numerical operation engine, and the numerical operation engine determines the third read voltage for reading the first physical programming unit.

Description

Data access method, memory control circuit unit and memory storage device

Technical Field

The present invention relates to a data access method, a memory control circuit unit and a memory storage device, and more particularly, to a data access method using a numerical operation engine, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above. Particularly, with the rise of numerical operations (e.g., artificial intelligence, neural networks or deep learning networks), it is also one of the problems to be solved by those skilled in the art how to apply numerical operations to the rewritable nonvolatile memory module to improve the utilization efficiency of the rewritable nonvolatile memory module.

Disclosure of Invention

The invention provides a data access method, a memory control circuit unit and a memory storage device. The data access method can improve the access efficiency of the rewritable nonvolatile memory module through the numerical operation engine.

The invention provides a data access method, which is used for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The data access method comprises the following steps: reading a first physical programming unit in the plurality of physical programming units by using at least one first reading voltage in a plurality of reading voltages to obtain first data; reading the first physical programming unit by using at least one second reading voltage in the plurality of reading voltages to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to a numerical operation engine; determining, by the numerical operation engine, a third read voltage for reading the first physical programming unit from the plurality of read voltages according to the first state parameter and the second state parameter; and reading the first entity programming unit by using the third reading voltage to obtain third data.

In an embodiment of the present invention, the step of reading the first physical program cell of the plurality of physical program cells using the first read voltage of the plurality of read voltages to obtain the first data includes: performing a first decoding operation to correct errors in the first data according to first encoded data, and when uncorrectable errors exist in the first data, performing a step of reading the first physical programming unit using the second reading voltage of the plurality of reading voltages to obtain the second data. Wherein reading the first physical program cell using the second one of the plurality of read voltages to obtain the second data comprises: performing the first decoding operation to correct errors in the second data according to second encoded data, and when there are uncorrectable errors in the second data, performing the step of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to the numerical operation engine.

In an embodiment of the present invention, the third read voltage is an optimal read voltage for reading the first physical program cell.

In an embodiment of the present invention, the method further includes: performing the first decoding operation to correct errors in the third data from third encoded data; outputting the third data when there is no error in the third data; outputting the third data with corrected errors when errors in the third data are corrected; and determining that a failure occurs in reading the first physical program cell using the first decoding operation when there is an uncorrectable error in the third data.

In an embodiment of the invention, the first state parameter includes the first data, a total number ofbit values 1 in the first data, a total number ofbit values 0 in the first data, or a sum of first syndromes corresponding to the first data.

In an embodiment of the invention, the second state parameter includes the second data, a total number ofbit values 1 in the second data, a total number ofbit values 0 in the second data, or a sum of second syndromes corresponding to the second data.

In an embodiment of the present invention, the method further includes: when the rewritable nonvolatile memory module is just powered on, at least one operation parameter obtained through pre-training is loaded from the rewritable nonvolatile memory module to the numerical operation engine.

In an embodiment of the invention, the operation parameter includes a predefined weight or offset, wherein the step of determining, by the numerical operation engine, the third read voltage for reading the first physical program cell from the plurality of read voltages according to the first state parameter and the second state parameter includes: determining, by the numerical operation engine, the third read voltage according to the first state parameter, the second state parameter, and the predefined weight or the offset.

In an embodiment of the present invention, the method further includes: receiving a first write command from a host system; inputting a third state parameter corresponding to the first write instruction into the numerical operation engine; and determining the type of the first write data corresponding to the first write command according to the third state parameter by the numerical operation engine.

In an embodiment of the present invention, wherein the third status parameter includes a first logic address, a location parameter, or an instruction type corresponding to the first write data, wherein determining the type of the first write data corresponding to the first write instruction according to the third status parameter by the numerical operation engine comprises: and judging that the first written data is hot data or cold data according to the third state parameter by the numerical operation engine, wherein the frequency of accessing the hot data is higher than that of accessing the cold data.

The invention provides a memory control circuit unit which is used for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the memory control circuit unit comprises: the device comprises a host interface, a memory interface, a numerical operation engine and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface, the memory interface and the numerical operation engine. The memory management circuit is used for reading a first entity programming unit in the entity programming units by using at least one first reading voltage in a plurality of reading voltages so as to obtain first data. The memory management circuit is further configured to read the first physical programming unit using at least one second read voltage of the plurality of read voltages to obtain second data. The memory management circuit is further configured to input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to the numerical operation engine. The numerical operation engine is configured to determine a third read voltage for reading the first physical programming unit from the plurality of read voltages according to the first state parameter and the second state parameter. The memory management circuit is further configured to read the first physical programming unit using the third read voltage to obtain third data.

In an embodiment of the invention, in an operation of reading the first physical programming cell of the plurality of physical programming cells using the first reading voltage of the plurality of reading voltages to obtain the first data, the memory management circuit performs a first decoding operation to correct an error in the first data according to first encoded data, and when an uncorrectable error exists in the first data, performs an operation of reading the first physical programming cell using the second reading voltage of the plurality of reading voltages to obtain the second data. Wherein in an operation of reading the first physical programming unit using the second one of the plurality of reading voltages to obtain the second data, the memory management circuit performs the first decoding operation to correct errors in the second data according to second encoded data, and performs an operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to the numerical operation engine when there is an uncorrectable error in the second data.

In an embodiment of the invention, the third read voltage is an optimal read voltage for reading the first physical program cell.

In an embodiment of the invention, the memory management circuit performs the first decoding operation to correct errors in the third data according to third encoded data. The memory management circuit outputs the third data when there is no error in the third data. When an error in the third data is corrected, the memory management circuit outputs the third data of which the error is corrected. When the third data has an uncorrectable error, the memory management circuit determines that a failure occurs in reading the first physical program cell using the first decoding operation.

In an embodiment of the invention, when the rewritable nonvolatile memory module is just powered on, the memory management circuit loads at least one operation parameter obtained through pre-training from the rewritable nonvolatile memory module into the numerical operation engine.

In an embodiment of the present invention, the operation parameter includes a predefined weight or an offset, wherein the operation of the plurality of read voltages for reading the third read voltage of the first physical program cell is determined by the numerical operation engine according to the first state parameter and the second state parameter, and the third read voltage is determined by the numerical operation engine according to the first state parameter, the second state parameter and the predefined weight or the offset.

In an embodiment of the invention, the memory management circuit receives a first write command from the host system, the memory management circuit inputs a third status parameter corresponding to the first write command into the numerical operation engine, and the numerical operation engine determines a type of first write data corresponding to the first write command according to the third status parameter.

In an embodiment of the invention, the third status parameter includes a first logical address, a location parameter, or a type of instruction corresponding to the first write data, wherein in an operation in which the numerical operation engine determines a type of the first write data corresponding to the first write instruction according to the third status parameter, the numerical operation engine determines whether the first write data is hot data or cold data according to the third status parameter, wherein the hot data is accessed more frequently than the cold data.

The invention provides a memory storage device. The memory storage device comprises a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module and is provided with a numerical operation engine. The memory control circuit unit is used for reading a first entity programming unit in the entity programming units by using at least one first reading voltage in a plurality of reading voltages so as to obtain first data. The memory control circuit unit is further configured to read the first physical programming unit using at least one second read voltage of the plurality of read voltages to obtain second data. The memory control circuit unit is further configured to input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to the numerical operation engine, and determine a third read voltage for reading the first physical programming unit from the plurality of read voltages according to the first state parameter and the second state parameter by the numerical operation engine. The memory control circuit unit is further configured to read the first physical programming unit using the third read voltage to obtain third data.

In an embodiment of the invention, in an operation of reading the first physical programming cell of the plurality of physical programming cells using the first reading voltage of the plurality of reading voltages to obtain the first data, the memory control circuit unit performs a first decoding operation to correct an error in the first data according to first encoded data, and when an uncorrectable error exists in the first data, performs an operation of reading the first physical programming cell using the second reading voltage of the plurality of reading voltages to obtain the second data. Wherein in an operation of reading the first physical programming unit using the second one of the plurality of reading voltages to obtain the second data, the memory control circuit unit performs the first decoding operation to correct an error in the second data according to second encoded data, and performs an operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to the numerical operation engine when an uncorrectable error exists in the second data.

In an embodiment of the invention, the memory control circuit unit performs the first decoding operation to correct errors in the third data according to third encoded data. The memory control circuit unit outputs the third data when there is no error in the third data. When an error in the third data is corrected, the memory control circuit unit outputs the third data of which error has been corrected. When the third data has an uncorrectable error, the memory control circuit unit determines that a failure occurs in reading the first physical program unit using the first decoding operation.

In an embodiment of the invention, when the rewritable nonvolatile memory module is just powered on, the memory control circuit unit loads at least one operation parameter obtained through pre-training from the rewritable nonvolatile memory module into the numerical operation engine.

In an embodiment of the invention, the memory control circuit unit receives a first write command from the host system, inputs a third status parameter corresponding to the first write command into the numerical operation engine, and determines a type of first write data corresponding to the first write command according to the third status parameter.

In an embodiment of the invention, the third status parameter includes a first logic address, a location parameter, or a type of instruction corresponding to the first write data, wherein in an operation of determining a type of the first write data corresponding to the first write instruction according to the third status parameter by the numerical operation engine, the memory storage device determines whether the first write data is hot data or cold data according to the third status parameter by the numerical operation engine, wherein the hot data is accessed more frequently than the cold data.

Based on the above, the data access method of the present invention can determine the optimal Read voltage for reading a physical programming unit through the numerical operation engine when reading data from the rewritable non-volatile memory module, thereby reducing the time spent in a Retry-Read mechanism and improving the access efficiency of the rewritable non-volatile memory module. In addition, when the rewritable nonvolatile memory module is written, whether the written data is cold data or hot data can be judged through the numerical operation engine, and whether the written data can be compressed can also be judged through the numerical operation engine, so that the memory management circuit can select an optimal mode to write when the data is written.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

FIG. 5 is a schematic block diagram of a rewritable nonvolatile memory module according to an example embodiment.

FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment.

FIG. 7 is a graph illustrating a statistical distribution of gate voltages corresponding to write data stored in the memory cell array, according to an example embodiment.

FIG. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment.

FIG. 9 is a diagram illustrating reading data from a memory cell according to another example embodiment.

FIG. 10 is a diagram illustrating an example of a physically erased cell according to the present example embodiment.

FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 12 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

FIG. 13 is a diagram illustrating an example of a plurality of sets of physical program cells in a physically erased cell according to the example embodiment.

FIG. 14 is a diagram illustrating a set of read voltages for a re-read mechanism according to an exemplary embodiment of the invention.

FIG. 15 is a flowchart illustrating a data access method according to an example embodiment.

Description of the symbols:

10: a memory storage device;

11: a host system;

110: a system bus;

111: a processor;

112: a random access memory;

113: a read-only memory;

114: a data transmission interface;

12: input/output (I/O) devices;

20: a main board;

201: a carry-on disk;

202: a memory card;

203: a solid state disk;

204: a wireless memory storage device;

205: a global positioning system module;

206: a network interface card;

207: a wireless transmission device;

208: a keyboard;

209: a screen;

210: a horn;

32: an SD card;

33: a CF card;

34: an embedded storage device;

341: an embedded multimedia card;

342: an embedded multi-chip package storage device;

402: a connection interface unit;

404: a memory control circuit unit;

406: a rewritable non-volatile memory module;

2202: an array of memory cells;

2204: a word line control circuit;

2206: a bit line control circuit;

2208: a row decoder;

2210: a data input/output buffer;

2212: a control circuit;

502: a memory cell;

504: a bit line;

506: a word line;

508: a common source line;

512: a select gate drain transistor;

514: a select gate-source transistor;

LSB: a least significant bit;

CSB: a middle valid bit;

MSB: a most significant bit;

VA, VB, VC, VD, VE, VF, VG, VA _1, VB _1, VC _1, VD _1, VE _1, VF _1, VG _1, VA _2, VB _2, VC _2, VD _2, VE _2, VF _2, VG _2, VA _3, VB _3, VC _3, VD _3, VE _3, VF _3, VG _3, VA _ n, VB _ n, VC _ n, VD _ n, VE _ n, VF _ n, VG _ n: reading a voltage;

l _0 to L _ N: a lower entity programming unit;

m _0 to M _ N: a middle entity programming unit;

u _0 to U _ N: an upper entity programming unit;

1301. 1303, 1305, 1307, 1309, 1311: a set of entity programming cells;

702: a memory management circuit;

704: a host interface;

706: a memory interface;

708: an error checking and correcting circuit;

710: a buffer memory;

712: a power management circuit;

714: a numerical operation engine;

801(1) -801 (r): a location;

820: encoding data;

810(0) -810 (E): a physical programming unit;

RR _ 1-RR _ n: reading a voltage group;

s1501: reading a first physical programming unit in the plurality of physical programming units by using a first reading voltage in the plurality of reading voltages to obtain first data;

s1503: reading the first entity programming unit by using a second reading voltage in the plurality of reading voltages to obtain second data;

s1505: inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to the numerical operation engine;

s1507: determining a third read voltage for reading the first entity programming unit in the plurality of read voltages according to the first state parameter and the second state parameter by using a numerical operation engine;

s1509: and reading the first entity programming unit by using the third reading voltage to obtain third data.

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 1 and 2, thehost system 11 generally includes aprocessor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and adata transmission interface 114. Theprocessor 111, theRAM 112, theROM 113, and thedata transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, thehost system 11 is electrically connected to thememory storage device 10 through thedata transmission interface 114. For example,host system 11 can store data tomemory storage device 10 or read data frommemory storage device 10 viadata transfer interface 114. In addition, thehost system 11 is electrically connected to the I/O device 12 via asystem bus 110. For example, thehost system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via thesystem bus 110.

In the present exemplary embodiment, theprocessor 111, theram 112, therom 113 and thedata transmission interface 114 may be disposed on themotherboard 20 of thehost system 11. The number of data transfer interfaces 114 may be one or more. Themotherboard 20 can be electrically connected to thememory storage device 10 through thedata transmission interface 114 in a wired or wireless manner. Thememory storage device 10 can be, for example, apersonal disk 201, amemory card 202, a Solid State Drive (SSD) 203, or a wirelessmemory storage device 204. The wirelessmemory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) based memory storage device based on various wireless Communication technologies. In addition, themotherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS)module 205, anetwork interface card 206, awireless transmission device 207, akeyboard 208, ascreen 209, aspeaker 210, and the like through theSystem bus 110. For example, in an exemplary embodiment, themotherboard 20 may access the wirelessmemory storage device 204 via thewireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, thehost system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and thememory storage device 30 may be various non-volatile memory storage devices such as anSD card 32, a CF card 33, or an embeddedstorage device 34. The embeddedstorage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package storage devices (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

Referring to fig. 4, thememory storage device 10 includes aconnection interface unit 402, a memorycontrol circuit unit 404 and a rewritablenonvolatile memory module 406.

In the present exemplary embodiment,connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and theconnection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia storage Card (Embedded, Multimedia storage Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. Theconnection interface unit 402 may be packaged with the memorycontrol circuit unit 404 in one chip, or theconnection interface unit 402 may be disposed outside a chip including the memorycontrol circuit unit 404.

The memorycontrol circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritablenonvolatile memory module 406 according to commands of thehost system 11.

The rewritablenonvolatile memory module 406 is electrically connected to the memorycontrol circuit unit 404 and is used for storing data written by thehost system 11. The rewritablenonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

The memory cells in the rewritablenonvolatile memory module 406 are arranged in an array. The memory cell array is described below as a two-dimensional array. However, it should be noted that the following exemplary embodiment is only one example of the memory cell array, and in other exemplary embodiments, the arrangement of the memory cell array may be adjusted to meet practical requirements.

FIG. 5 is a schematic block diagram of a rewritable nonvolatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment.

Referring to fig. 5 and 6, the rewritablenonvolatile memory module 406 includes amemory cell array 2202, a wordline control circuit 2204, a bitline control circuit 2206, acolumn decoder 2208, a data input/output buffer 2210 and acontrol circuit 2212.

In the present exemplary embodiment, thememory cell array 2202 may include a plurality ofmemory cells 502 for storing data, a plurality of Select Gate Drain (SGD)transistors 512 and a plurality of Select Gate Source (SGS)transistors 514, and a plurality ofbit lines 504, a plurality ofword lines 506, and a common source line 508 (fig. 6) connecting the memory cells. Thememory cells 502 are arranged in an array (or in a stacked arrangement) at the intersections ofbit lines 504 and word lines 506. When a write command or a read command is received from thememory control circuit 404, thecontrol circuit 2212 controls the wordline control circuit 2204, the bitline control circuit 2206, thecolumn decoder 2208 and the data input/output buffer 2210 to write data into thememory cell array 2202 or read data from thememory cell array 2202, wherein the wordline control circuit 2204 controls voltages applied to the word lines 506, the bitline control circuit 2206 controls voltages applied to thebit lines 504, thecolumn decoder 2208 selects a corresponding bit line according to a row address in the command, and the data input/output buffer 2210 is used for temporarily storing the data.

The memory cells in the rewritablenonvolatile memory module 406 store bits (bits) by changing the threshold voltage. Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell ofmemory cell array 2202 has multiple storage states. And the storage state of the memory cell can be determined by reading the voltage, so as to obtain the bit stored in the memory cell.

Referring to fig. 7, taking the MLC NAND flash memory as an example, each memory cell has 4 storage states with different threshold voltages, and the storage states represent bits "11", "10", "00" and "01", respectively. In other words, each storage state includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). In the present exemplary embodiment, the 1 st bit from the left side in the storage states (i.e., "11", "10", "00", and "01") is the LSB, and the 2 nd bit from the left side is the MSB. Thus, in this exemplary embodiment, each memory cell can store 2 bits. It should be understood that the correspondence between the threshold voltages and the storage states shown in FIG. 7 is merely an example. In another exemplary embodiment of the present invention, the correspondence between the threshold voltage and the storage state may be arranged in the ranges of "11", "10", "01" and "00" or other arrangements as the threshold voltage is larger. In addition, in another exemplary embodiment, it is also possible to define that the 1 st bit from the left side is the MSB and the 2 nd bit from the left side is the LSB.

In an exemplary embodiment where a memory cell can store multiple bits (e.g., MLC or TLC NAND flash memory module), the physical program cells belonging to the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, in an MLC NAND flash memory module, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of the memory cell belongs to the upper physical programming unit. In an example embodiment, the lower physical program unit is also referred to as a fast page (fast page), and the upper physical program unit is also referred to as a slow page (slow page). In addition, in the TLC NAND flash memory module, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program unit, the middle Significant Bit (CSB) of the memory cell belongs to the middle physical program unit, and the Most Significant Bit (MSB) of the memory cell belongs to the upper physical program unit.

FIG. 8 is a diagram illustrating reading data from a memory cell, such as an MLC NAND type flash memory, according to an example embodiment.

Referring to FIG. 8, a read operation of the memory cells of thememory cell array 2202 is performed by applying read voltages VA-VC to the control gates to identify data stored in the memory cells by the conductive state of the memory cell channels. A verify bit (VA) for indicating whether the memory cell channel is turned on when the read voltage VA is applied; a verification bit (VC) for indicating whether the memory cell channel is turned on when the read voltage VC is applied; the Verify Bit (VB) is used to indicate whether the memory cell channel is turned on when the read voltage VB is applied. It is assumed that the verify bit is "1" indicating that the corresponding cell channel is turned on, and the verify bit is "0" indicating that the corresponding cell channel is not turned on. As shown in FIG. 8, the verification bits (VA) to (VC) can determine which storage state the memory cell is in, and then the stored bits can be obtained.

Referring to fig. 9, for an example of a TLC NAND type flash memory, each storage state includes a least Significant Bit LSB of a 1 st Bit from the left side, a middle Significant Bit (CSB) of a 2 nd Bit from the left side, and a most Significant Bit MSB of a 3 rd Bit from the left side. In this example, the memory cell has 8 storage states (i.e., "111", "110", "100", "101", "001", "000", "010", and "011") according to different threshold voltages. The bits stored in the memory cell can be identified by applying the read voltages VA-VG to the control gates.

It should be noted that the arrangement order of the 8 storage states in fig. 9 can be determined by the design of the manufacturer, but is not limited to the arrangement manner of the present example.

In addition, the memory cells of the rewritablenonvolatile memory module 406 form a plurality of physical programming units, and the physical programming units form a plurality of physical erasing units. Specifically, the memory cells on the same word line in FIG. 6 constitute one or more physical programming units. For example, if the rewritablenonvolatile memory module 406 is an MLC NAND flash memory module, the memory cells at the intersections of the same word line and multiple bit lines constitute 2 physical programming units, i.e., an upper physical programming unit and a lower physical programming unit. And an upper physical programming unit and a lower physical programming unit can be collectively referred to as a physical programming unit group. In particular, if the data bit to be read is in a lower physical program cell of a physical program cell group, the value of each bit in the lower physical program cell can be identified by the read voltage VA shown in fig. 8. If the data to be read is located in an upper physical programming cell of a physical programming cell group, the reading voltage VB and the reading voltage VC as shown in fig. 8 can be used to identify the value of each bit in the upper physical programming cell.

Alternatively, if the rewritablenonvolatile memory module 406 is a TLC NAND flash memory module, the memory cells at the intersections of the same word line and the bit lines constitute 3 physical programming units, i.e., an upper physical programming unit, a middle physical programming unit, and a lower physical programming unit. And an upper physical programming unit, a middle physical programming unit and a lower physical programming unit can be collectively referred to as a physical programming unit group. In particular, if the data bit to be read is in a lower physical program cell of a group of physical program cells, the value of each bit in the lower physical program cell can be identified by the read voltage VA in fig. 9. If the data to be read is located in one of the physical program cells of one of the physical program cell groups, the read voltage VB and the read voltage VC as shown in fig. 9 can be used to identify the value of each bit in the physical program cell. If the data bit to be read is in an upper physical programming cell of a physical programming cell group, the read voltage VD, the read voltage VE, the read voltage VF, and the read voltage VG shown in fig. 9 can be used to identify the value of each bit in the upper physical programming cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physical erase cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

Referring to FIG. 10, in the present exemplary embodiment, it is assumed that one entity erasing unit is composed of a plurality of entity programming unit groups, wherein each entity programming unit group includes a lower entity programming unit, a middle entity programming unit and an upper entity programming unit composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are considered as a physical programming cell group, and the other physical programming cells are classified into a plurality of physical programming cell groups according to the same manner.

Referring to FIG. 11, the memorycontrol circuit unit 404 includes amemory management circuit 702, ahost interface 704, amemory interface 706 and an error checking and correctingcircuit 708.

Thememory management circuit 702 is used to control the overall operation of the memorycontrol circuit unit 404. Specifically, thememory management circuit 702 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of thememory storage device 10. When the operation of thememory management circuit 702 or any circuit element included in the memorycontrol circuit unit 404 is described below, the operation of the memorycontrol circuit unit 404 is equivalently described.

In the exemplary embodiment, the control instructions of thememory management circuit 702 are implemented in firmware. For example, thememory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When thememory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of thememory management circuit 702 may also be stored in the form of program codes in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, thememory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when thememory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritablenonvolatile memory module 406 into the RAM of thememory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of thememory management circuit 702 may also be implemented in a hardware form. For example, thememory management circuit 702 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The cell management circuit is used for managing the memory cells or the group of the rewritablenonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritablenonvolatile memory module 406 to write data into the rewritablenonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritablenonvolatile memory module 406 to read data from the rewritablenonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritablenonvolatile memory module 406 so as to erase data from the rewritablenonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritablenonvolatile memory module 406 and data read from the rewritablenonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritablenonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, thememory management circuit 702 may issue other types of command sequences to the rewritablenonvolatile memory module 406 to instruct the corresponding operations to be performed.

Thehost interface 704 is electrically connected to thememory management circuit 702 and is used for receiving and recognizing commands and data transmitted by thehost system 11. That is, commands and data transmitted by thehost system 11 are transmitted to thememory management circuit 702 through thehost interface 704. In the exemplary embodiment,host interface 704 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and thehost interface 704 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

Thememory interface 706 is electrically connected to thememory management circuit 702 and is used for accessing the rewritablenonvolatile memory module 406. That is, the data to be written into the rewritablenonvolatile memory module 406 is converted into a format accepted by the rewritablenonvolatile memory module 406 through thememory interface 706. Specifically, if thememory management circuit 702 wants to access the rewritablenonvolatile memory module 406, thememory interface 706 transmits a corresponding instruction sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, thememory management circuit 702 and transferred to the rewritablenon-volatile memory module 406 via thememory interface 706. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification code, memory address, etc.

The error checking and correctingcircuit 708 is electrically connected to thememory management circuit 702 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when thememory management circuit 702 receives a write command from thehost system 11, the error checking and correctingcircuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and thememory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritablenonvolatile memory module 406. Thereafter, when thememory management circuit 702 reads data from the rewritablenonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correctingcircuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memorycontrol circuit unit 404 further includes abuffer memory 710, apower management circuit 712, and anumerical operation engine 714.

Thebuffer memory 710 is electrically connected to thememory management circuit 702 and is used for temporarily storing data and instructions from thehost system 11 or data from the rewritablenonvolatile memory module 406. Thepower management circuit 712 is electrically connected to thememory management circuit 702 and is used for controlling the power of thememory storage device 10.

In the present exemplary embodiment, thenumerical operation engine 714 implements a neural network (not shown) using a machine learning algorithm (or a deep learning algorithm) or other numerical operation algorithms in hardware in the memorycontrol circuit unit 404, for example. In addition, before the memorycontrol circuit unit 404 leaves the factory, the manufacturer of the memorycontrol circuit unit 404 may train the neural network in thenumerical operation engine 714 to obtain the weights and offsets (bias) required to be used by each layer (layer) in the neural network during operation. For example, after the neural network in thenumerical operation engine 714 is designed, a large amount of input data and a solution corresponding to each input data are required to be input into the neural network in thenumerical operation engine 714. The neural network in thenumerical operation engine 714 can adjust the weights and offsets of the layers in the neural network according to the input data and the solution corresponding to each input data.

For example, in one embodiment, the input data may be a piece of data read from a physical programming unit, a total number ofbit values 1 in the piece of data, a total number ofbit values 0 in the piece of data, or a sum of syndromes corresponding to the piece of data. In addition, the solution corresponding to the input data is, for example, an optimal read voltage for reading the physical program cell. However, in other embodiments, the input data may be a logical address corresponding to a write command, a sector count, or a command type of the write command, and the solution corresponding to the input data is, for example, that the write data of the write command is hot data or cold data. In yet another embodiment, the input data may also be write data corresponding to a write command, and the solution corresponding to the input data may be that the write data is compressible or incompressible.

When one of the input data (referred to as the first input data herein) is input to the neural network in thena 714 after the weights and offsets of the layers are adjusted to a certain degree, the output of the neural network is very close to the solution corresponding to the first input data. At this time, it may be said that the neural network in thenumerical operation engine 714 has been learned, or that the neural network in thenumerical operation engine 714 has converged.

It should be noted that the weights and offsets of the various layers in the neural network may be collectively referred to as "operation parameters", and the manufacturer may store the operation parameters in a system area (not shown) in the rewritablenonvolatile memory module 406 before the memorycontrol circuit unit 404 leaves the factory. Thereafter, when the rewritablenonvolatile memory module 406 is just powered on, thememory management circuit 702 can load the operation parameters (also referred to as predefined weights and offsets) obtained through pre-training (or learning) from the rewritablenonvolatile memory module 406 into thenumerical operation engine 714 to perform the operations required by thenumerical operation engine 714.

In addition, in the exemplary embodiment, the error checking and correctingcircuit 708 can perform single-frame (single-frame) coding on the data stored in the same physical program unit, or perform multi-frame (multi-frame) coding on the data stored in a plurality of physical program units. The single frame coding and the multi-frame coding may respectively use at least one of coding algorithms such as low density parity check code (LDPC), BCH code, convolutional code (convolutional code), turbo code, and the like. Alternatively, in an exemplary embodiment, the multi-frame coding may also use Reed-Solomon codes (RS codes) algorithms or exclusive OR (XOR) algorithms. In addition, in another exemplary embodiment, more coding algorithms not listed may also be employed, which is not described herein. Depending on the encoding algorithm employed, the ECC andcorrection circuit 708 encodes the data to be protected to generate corresponding ECC and/or ECC codes. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.

Referring to fig. 12, taking the data stored in the encoded entity programming units 810(0) to 810(E) as an example to generate the corresponding encodeddata 820, at least a portion of the data stored in each of the entity programming units 810(0) to 810(E) can be regarded as a frame. In multi-frame coding, data in the physical programming units 810(0) to 810(E) is coded according to the position of each bit (or byte). For example, bit b at position 801(1)₁₁、b₂₁、…、b_p1Will be encoded as bit b in the encodeddata 820_o1Bit b at position 801(2)₁₂、b₂₂、…、b_p2Will be encoded as bit b in the encoded data 820_o2(ii) a By analogy, bit b at position 801(r)_1r、b_2r、…、b_prWill be encoded as bit b in the encodeddata 820_or. Thereafter, the data read from the physical programming units 810(0) -810 (E) can be decoded according to the encodeddata 820 to attempt to correct errors that may exist in the read data.

In addition, in another exemplary embodiment of fig. 12, the data for generating the encodeddata 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the physical programming units 810(0) -810 (E). Take the data stored in the physical programming unit 810(0) as an example, wherein the redundant bits are, for example, encoded data generated by single frame encoding of the data bits stored in the physical programming unit 810 (0). In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810(0), the data read from the physical programming unit 810(0) can be decoded by using the redundant bits (e.g., the encoded data generated by the single frame coding) in the physical programming unit 810(0) to perform error detection and correction on the read data. However, when the decoding using the redundancy bits in the physical programming unit 810(0) fails (e.g., the number of bits error of the data stored in the decoded physical programming unit 810(0) is greater than a threshold), a Retry-Read mechanism may be used to select and attempt to Read the correct data from the physical programming unit 810(0) using other Read voltages. When the correct data cannot be Read from the physical programming units 810(0) by the Retry-Read mechanism, the encodeddata 820 and the data of the physical programming units 810(1) to 810(E) can be Read, and the decoding is performed according to the encodeddata 820 and the data of the physical programming units 810(1) to 810(E) to try to correct the errors in the data stored in the physical programming units 810 (0). That is, in the exemplary embodiment, when decoding using the encoded data generated by the single-frame encoding fails and reading using the re-Read (Retry-Read) mechanism fails, the encoded data generated by the multi-frame encoding is decoded instead.

In the present exemplary embodiment, thememory management circuit 702 configures a predetermined set of read voltages for the rewritablenon-volatile memory module 406. For example, in the case where the rewritablenon-volatile memory module 406 is an 8-level cell NAND type memory module, the predetermined read voltage set includes a plurality of voltages such as the read voltages VA to VG shown in FIG. 9. When reading the rewritablenonvolatile memory module 406, thememory management circuit 702 first reads the data stored in the rewritablenonvolatile memory module 406 using the read voltage of the preset read voltage set.

For example, FIG. 13 is a schematic diagram illustrating an example of a plurality of sets of physical program cells in a physically erased cell according to the present example embodiment.

Referring to fig. 13, when data stored in a physical program cell is to be read, thememory management circuit 702 first reads the data by using a predetermined set of read voltages (e.g., the read voltages VA to VG in fig. 9).

For example, if thememory management circuit 702 wants to read data from the lower physical programming cell L _0 (also referred to as the first physical programming cell) in the physicalprogramming cell group 1301, thememory management circuit 702 first reads data (hereinafter referred to as the first data) from the lower physical programming cell L _0 by using the read voltage VA (also referred to as the first read voltage) in the preset read voltage group. For example, thememory management circuit 702 uses the read voltage VA in the set of predetermined read voltages to identify the value of each bit in the physical program cell.

After the data reading is completed, thememory management circuit 702 can directly use another Read voltage to perform a re-Read (Retry-Read) mechanism to Read the data from the next physical programming cell L _ 0.

However, in another exemplary embodiment, the error checking and correctingcircuit 708 may be utilized to perform the error checking and correcting process according to the error checking and correcting code (i.e., the redundancy bits) corresponding to the read first data. Wherein the redundant bits (also referred to as first encoded data) are generated by single frame encoding. In the error checking and correcting process, thememory management circuit 702 performs a decoding operation (also referred to as a first decoding operation) corresponding to the single frame encoding to correct the error in the first data according to the first encoded data. If the first encoded data cannot completely correct the erroneous bit in the first data, thememory management circuit 702 determines that the data in the next physical programming cell L _0 cannot be correctly obtained. At this time, thememory management circuit 702 will use the re-Read (Retry-Read) mechanism to re-Read the data from the next physical programming unit L _ 0.

For example, FIG. 14 is a diagram illustrating a set of read voltages for a re-read mechanism according to an exemplary embodiment of the invention.

Referring to fig. 13 and 14, in the present example embodiment, thememory management circuit 702 pre-configures (or sets) the read voltage sets RR _1 to RR _ n for the re-read scheme. Each of the read voltage sets RR _1 through RR _ n includes a plurality of read voltages. For example, the read voltage set RR _1 can include a read voltage VA _1 for reading the lower physical program cell, a read voltage VB _1 and a read voltage VC _1 for reading the middle physical program cell, and a read voltage VD _1, a read voltage VE _1, a read voltage VF _1 and a read voltage VG _1 for reading the upper physical program cell. The read voltage set RR _2 may include a read voltage VA _2 for reading the lower physical program cell, a read voltage VB _2 and a read voltage VC _2 for reading the lower physical program cell, and a read voltage VD _2, a read voltage VE _2, a read voltage VF _2 and a read voltage VG _2 for reading the upper physical program cell. The read voltage set RR _3 may include a read voltage VA _3 for reading the lower physical program cell, a read voltage VB _3 and a read voltage VC _3 for reading the lower physical program cell, and a read voltage VD _3, a read voltage VE _3, a read voltage VF _3 and a read voltage VG _3 for reading the upper physical program cell. The read voltage set RR _ n may include a read voltage VA _ n for reading the lower physical program cell, a read voltage VB _ n and a read voltage VC _ n for reading the middle physical program cell, and a read voltage VD _ n, a read voltage VE _ n, a read voltage VF _ n and a read voltage VG _ n for reading the upper physical program cell. It should be noted that in other embodiments, thememory management circuit 702 may also pre-configure (or set) more or less read voltage sets for the re-read mechanism.

In the Retry-Read mechanism, thememory management circuit 702 sequentially selects the Read voltage sets from the Read voltage set RR _1 to the Read voltage set RR _ n, and reads data from the lower entity programming unit L _0 again according to the voltages in the selected Read voltage set. For example, thememory management circuit 702 selects the read voltage group RR _1 to perform the first re-read. Thememory management circuit 702 reads the lower physical programming unit L _0 according to the read voltage VA _1 (also referred to as a second read voltage) in RR _1 to obtain a data (also referred to as a second data). It should be noted that, when different reading voltages are used to read the same physical program cell (e.g., the lower physical program cell L _0), the number of error bits (or the probability of error occurrence) of the obtained data may be different.

In one embodiment, after reading the second data from the lower physical programming unit L _0 using the reading voltage VA _1, thememory management circuit 702 can select an optimal reading voltage (also referred to as a third reading voltage) for reading the lower physical programming unit L _0 through thenumerical operation engine 714. In detail, thememory management circuit 702 may input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to thenumerical operation engine 714. Thereafter, thenumerical operation engine 714 determines an optimal read voltage for reading the next physical program cell L _0 from the read voltage sets RR _ 1-RR _ n according to the first state parameter, the second state parameter, and the predefined weight and offset previously loaded into thenumerical operation engine 714. It is assumed that thevalue operation engine 714 can deduce an optimal read voltage for reading the lower physical programming unit L _0 as the read voltage VA _ n of the read voltage set RR _ n according to the first state parameter and the second state parameter.

It should be noted that the first status parameter may include the first data, the total number ofbit values 1 in the first data, the total number ofbit values 0 in the first data, or the sum of syndromes (also referred to as first syndromes) corresponding to the first data. The first syndrome is, for example, a plurality of syndromes generated by multiplying the read first data by a parity check matrix in a low density parity check code (LDPC) decoding process. Since the calculation method of the syndrome can be known from the prior art, it is not described herein.

Similarly, the second state parameter includes the second data, the total number ofbit values 1 in the second data, the total number ofbit values 0 in the second data, or the sum of syndromes (also referred to as second syndromes) corresponding to the second data. The second syndrome is, for example, a plurality of syndromes generated by multiplying the read second data by a parity check matrix in a low density parity check code (LDPC) decoding process. Since the calculation method of the syndrome can be known from the prior art, it is not described herein.

It should be noted that, in the present exemplary embodiment, the first status parameter and the second status parameter are the same kind. More specifically, when the first state parameter is the first data, the second state parameter is the second data; when the first state parameter is the total number ofbit values 1 in the first data, the second state parameter is the total number ofbit values 1 in the second data; when the first state parameter is the total number of the bit values of 0 in the first data, the second state parameter is the total number of the bit values of 0 in the second data; when the first state parameter is a sum of syndromes corresponding to the first data, the second state parameter is a sum of syndromes corresponding to the second data. However, the present invention is not limited thereto, and in other embodiments, the first status parameter and the second status parameter may be different in kind.

However, in another exemplary embodiment, the error checking and correctingcircuit 708 may be utilized to perform the error checking and correcting process according to the error checking and correcting code (i.e., the redundant bits, referred to herein as the second encoded data) corresponding to the read second data. Wherein the first encoded data is generated by single frame encoding. In the error checking and correcting process, thememory management circuit 702 performs a decoding operation (also referred to as a first decoding operation) corresponding to the single frame encoding to correct the error in the second data according to the second encoded data. Assuming that thememory management circuit 702 performs the first decoding operation but cannot completely correct the erroneous bits in the second data according to the second encoded data, thememory management circuit 702 performs the operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to thevalue operation engine 714 to deduce the optimum read voltage for reading the lower physical programming unit L _ 0.

In other words, in one embodiment, after thememory management circuit 702 obtains the first data by using the read voltage VA and obtains the second data by using the read voltage VA _1, thememory management circuit 702 can perform the operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data into thenumerical operation engine 714 to deduce the optimum read voltage for reading the lower physical programming unit L _ 0. In another embodiment, when both the first data and the second data have uncorrectable errors, thememory management circuit 702 performs an operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to thenumerical operation engine 714 to deduce an optimal read voltage for reading the lower physical programming unit L _ 0.

It is noted that, in the foregoing embodiment, the first read voltage is a read voltage in the preset voltage set (i.e., the read voltage VA) and the second read voltage is a read voltage in the read voltage set RR _1 (i.e., the read voltage VA _ 1). However, the present invention is not limited thereto, and in another embodiment, the first read voltage may be one of the read voltage sets RR _ 1-RR _ N (e.g., the read voltage VA _1) and the second read voltage may be another one of the read voltage sets RR _ 1-RR _ N (e.g., the read voltage VA _ 2). The source of the first read voltage and the source of the second read voltage are not limited in the present invention.

That is, in the conventional re-Read (Retry-Read) scheme, thememory management circuit 702 may need to sequentially try to use all of the Read voltage sets RR _1 to RR _ n to finally obtain the optimal Read voltage for reading the lower physical program cell L _0 (i.e., the Read voltage VA _ n of the Read voltage set RR _ n). However, the present invention of thenumerical operation engine 714 allows thememory management circuit 702 to quickly obtain the optimum read voltage for reading the lower entity program unit L _0 without trying all of the read voltage sets RR _ 1-RR _ n. It should be noted that the present invention is not limited to the number of re-reads, and in other embodiments, the first state parameter and the second state parameter (or other more state parameters) may be input to thevalue operation engine 714 for inference to obtain the optimal read voltage when performing more (or fewer) re-reads.

After thenumerical operation engine 714 obtains the optimal read voltage (e.g., the read voltage VA _ n) for reading the lower entity program unit L _0, thenumerical operation engine 714 may output the read voltage VA _ n to thememory management circuit 702. Thereafter, thememory management circuit 702 can read the next physical program cell L _0 to obtain a data (also referred to as a third data) by using thememory management circuit 702.

Thereafter, the error checking and correctingcircuit 708 performs an error checking and correcting process according to the error checking and correcting code (i.e., the redundant bits, referred to as the third encoded data). Wherein the third encoded data is generated by single frame encoding. In the error checking and correcting process, thememory management circuit 702 performs a decoding operation (also referred to as a first decoding operation) corresponding to the single frame encoding to correct the error in the third data according to the third encoded data.

When thememory management circuit 702 checks the third data according to the third encoded data and determines that there is no error in the third data, thememory management circuit 702 may output the read third data to thehost system 11. In addition, when thememory management circuit 702 can correct the error in the third data according to the third encoded data, thememory management circuit 702 can also output the error-corrected third data to thehost system 11. However, when there is an error in the third data that cannot be corrected by the third encoded data, thememory management circuit 702 determines that a failure occurs in reading the lower physical programming unit L _0 using the first decoding operation. In other words, thememory management circuit 702 determines that the correct data cannot be Read from the lower entity program unit L _0 through the Retry-Read mechanism. Thememory management circuit 702 determines that decoding of the encoded data generated using the single-frame encoding has failed. Then, thememory management circuit 702 decodes the encoded data generated by the multi-frame encoding instead.

As can be seen from the above, when reading data from the rewritablenonvolatile memory module 406, thenumerical operation engine 714 can be used to determine at least one optimal Read voltage for reading a physical program unit, thereby reducing the time spent in the re-Read (Retry-Read) mechanism and improving the access efficiency of the rewritablenonvolatile memory module 406.

It should be noted that although the above-mentioned exemplary embodiments use thevalue operation engine 714 to deduce the optimum read voltage for reading the next physical program cell, the invention is not limited thereto. In other embodiments, thenumerical operation engine 714 can also be used to derive the optimal read voltage for reading a middle or upper physical program cell. In addition, although the exemplary embodiments described above are described with reference to TLC NAND type flash memory modules, the present invention is not limited thereto. In other embodiments, the data access method of the present invention can also be applied to SLC NAND type flash memory modules or MLC NAND type flash memory modules.

In particular, in one embodiment, thecalculation engine 714 can also be used in the case where thehost system 11 issues a write command to thememory management circuit 702. In detail, when thememory management circuit 702 receives a write command (also referred to as a first write command) from thehost system 11, thememory management circuit 702 may input a status parameter (also referred to as a third status parameter) corresponding to the first write command to thenumerical operation engine 714. Thereafter, thearithmetic operation engine 714 can determine the type of the write data (also referred to as the first write data) corresponding to the first write command according to the third status parameter.

In detail, in one embodiment, the third status parameter includes a logical address (also referred to as a first logical address), a physical address, a sector count, or a command type of the first write command for writing the first write data. Thearithmetic engine 714 can determine whether the first write data is hot data or cold data according to one of the third state parameters. Wherein hot data is accessed more frequently than cold data. In one embodiment, thememory management circuit 702 can store the data identified as hot data in thebuffer memory 710 of the memorycontrol circuit unit 404 that is accessed more frequently (or more strongly) without temporarily storing the data identified as hot data in the rewritablenon-volatile memory module 406, for example. In another embodiment, however, thememory management circuit 702 can write the data identified as hot data to the rewritablenonvolatile memory module 406 using a single page programming mode, for example. The memory cells in the rewritablenonvolatile memory module 406 that are written using the single-page programming mode only store one bit of data. In addition, thememory management circuit 702 may, for example, directly (or immediately) store the data identified as cold data into the rewritablenon-volatile memory module 406, and delete the data identified as cold data temporarily stored in thebuffer memory 710. In one embodiment, thememory management circuit 702 can write the data identified as cold data to the rewritablenonvolatile memory module 406 directly using a multi-page programming mode, and the memory cells written using the multi-page programming mode store multiple bits of data.

In addition, in an embodiment, the third status parameter may also include the first write data. Thevalue operation engine 714 can determine whether the first write data is compressible or incompressible according to the first write data. It should be noted that, determining whether a piece of data is compressible or incompressible can be known in the prior art, and is not described herein again. When thedata calculation engine 714 determines that the first written data is compressible, thedata calculation engine 714 may determine a compression rate of the first written data and output the compression rate to thememory management circuit 702. Thereafter, thememory management circuit 702 may compress the first write data according to the compression rate output by thenumerical operation engine 714.

Referring to fig. 15, in step S1501, thememory management circuit 702 reads a first physical programming cell of the plurality of physical programming cells using a first reading voltage of the plurality of reading voltages to obtain first data. In step S1503, thememory management circuit 702 reads the first physical programming unit using a second read voltage of the plurality of read voltages to obtain second data. In step S1505, thememory management circuit 702 inputs the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to thenumerical operation engine 714. Next, in step S1507, thenumerical operation engine 714 determines an optimal read voltage for reading the first physical program cell among the plurality of read voltages according to the first state parameter and the second state parameter. Finally, in step S1509, thememory management circuit 702 reads the first physical program unit using the optimal read voltage to obtain third data.

In summary, the data access method of the present invention can determine the optimal Read voltage for reading a physical programming unit through the numerical operation engine when reading data from the rewritable non-volatile memory module, thereby reducing the time spent in the Retry-Read mechanism and improving the access efficiency of the rewritable non-volatile memory module. In addition, when the rewritable nonvolatile memory module is written, the numerical operation engine can be used for judging whether the written data is cold data or hot data or not, and the numerical operation engine can be used for judging whether the written data can be compressed or not, so that the memory management circuit can select an optimal mode to write when the data is written.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data access method is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the data access method comprises the following steps:

reading a first physical programming unit in the plurality of physical programming units by using at least one first reading voltage in a plurality of reading voltages to obtain first data;

reading the first physical programming unit by using at least one second reading voltage in the plurality of reading voltages to obtain second data;

inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to a numerical operation engine;

determining, by the numerical operation engine, a third read voltage for reading the first physical programming unit from the plurality of read voltages according to the first state parameter and the second state parameter; and

and reading the first entity programming unit by using the third reading voltage to obtain third data.

2. The data access method of claim 1, wherein reading the first physical program cell of the plurality of physical program cells using the first read voltage of the plurality of read voltages to obtain the first data comprises:

performing a first decoding operation to correct errors in the first data according to first encoded data, and when uncorrectable errors exist in the first data, performing a step of reading the first physical programming unit using the second reading voltage of the plurality of reading voltages to obtain the second data,

wherein reading the first physical program cell using the second one of the plurality of read voltages to obtain the second data comprises:

performing the first decoding operation to correct errors in the second data according to second encoded data, and when there are uncorrectable errors in the second data, performing the step of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to the numerical operation engine.

3. The data access method of claim 1, wherein the third read voltage is an optimal read voltage for reading the first physical program cell.

4. The data access method of claim 2, further comprising:

performing the first decoding operation to correct errors in the third data from third encoded data;

outputting the third data when there is no error in the third data;

outputting the third data with corrected errors when errors in the third data are corrected; and

when the third data has an uncorrectable error, determining that a failure occurs in reading the first physical program cell using the first decoding operation.

5. The data access method of claim 1, wherein the first state parameter comprises the first data, a total number of bit values of 1 in the first data, a total number of bit values of 0 in the first data, or a sum of first syndromes corresponding to the first data.

6. The data access method of claim 1, wherein the second state parameter comprises a sum of the second data, a total number of bit values of 1 in the second data, a total number of bit values of 0 in the second data, or a second syndrome corresponding to the second data.

7. The data access method of claim 1, further comprising:

when the rewritable nonvolatile memory module is just powered on, at least one operation parameter obtained through pre-training is loaded from the rewritable nonvolatile memory module to the numerical operation engine.

8. The data access method of claim 7, wherein the operation parameter comprises a predefined weight or offset, wherein determining, by the numerical operation engine, the third read voltage for reading the first physical program cell from the plurality of read voltages according to the first state parameter and the second state parameter comprises:

determining, by the numerical operation engine, the third read voltage according to the first state parameter, the second state parameter, and the predefined weight or the offset.

9. The data access method of claim 1, further comprising:

receiving a first write command from a host system;

inputting a third state parameter corresponding to the first write instruction into the numerical operation engine; and

determining, by the numerical operation engine, a type of first write data corresponding to the first write command according to the third state parameter.

10. The data access method of claim 9, wherein the third status parameter comprises a first logical address, a location parameter, or an instruction type corresponding to the first write data, wherein determining, by the numerical operation engine, a type of the first write data corresponding to the first write instruction according to the third status parameter comprises:

and judging that the first written data is hot data or cold data according to the third state parameter by the numerical operation engine, wherein the frequency of accessing the hot data is higher than that of accessing the cold data.

11. A memory control circuit unit is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, the memory control circuit unit comprises:

a host interface for electrically connecting to a host system;

a memory interface for electrically connecting to the rewritable nonvolatile memory module;

a numerical operation engine; and

a memory management circuit electrically connected to the host interface, the memory interface and the numerical operation engine,

wherein the memory management circuit is configured to read a first physical program cell of the plurality of physical program cells using at least a first read voltage of a plurality of read voltages to obtain first data,

wherein the memory management circuit is further configured to read the first physical programming unit using at least a second read voltage of the plurality of read voltages to obtain second data,

wherein the memory management circuit is further configured to input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to the numerical operation engine,

the numerical operation engine is configured to determine a third read voltage for reading the first physical program cell among the plurality of read voltages according to the first state parameter and the second state parameter,

the memory management circuit is further configured to read the first physical programming unit using the third read voltage to obtain third data.

12. The memory control circuit unit of claim 11, wherein in the operation of reading the first physical program cell of the plurality of physical program cells using the first read voltage of the plurality of read voltages to obtain the first data,

the memory management circuit performs a first decoding operation to correct errors in the first data according to first encoded data, and performs an operation of reading the first physical programming unit using the second reading voltage of the plurality of reading voltages to obtain the second data when uncorrectable errors exist in the first data,

wherein in an operation of reading the first physical program cell using the second one of the plurality of read voltages to obtain the second data,

the memory management circuit performs the first decoding operation to correct errors in the second data according to second encoded data, and performs an operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to the numerical operation engine when an uncorrectable error exists in the second data.

13. The memory control circuit unit of claim 11, wherein the third read voltage is an optimal read voltage for reading the first physical program cell.

14. The memory control circuit cell of claim 12, wherein

The memory management circuit performs the first decoding operation to correct an error in the third data according to third encoded data,

the memory management circuit outputs the third data when there is no error in the third data,

when an error in the third data is corrected, the memory management circuit outputs the third data with the error corrected, an

When the third data has an uncorrectable error, the memory management circuit determines that a failure occurs in reading the first physical program cell using the first decoding operation.

15. The memory control circuit unit of claim 11, wherein the first state parameter comprises the first data, a total number of bit values of 1 in the first data, a total number of bit values of 0 in the first data, or a sum of first syndromes corresponding to the first data.

16. The memory control circuit unit of claim 11, wherein the second state parameter comprises the second data, a total number of bit values of 1 in the second data, a total number of bit values of 0 in the second data, or a sum of second syndromes corresponding to the second data.

17. The memory control circuit cell of claim 11, wherein

When the rewritable nonvolatile memory module is just powered on, the memory management circuit loads at least one operation parameter obtained through pre-training from the rewritable nonvolatile memory module into the numerical operation engine.

18. The memory control circuit unit of claim 17, wherein the operation parameter comprises a predefined weight or offset, wherein the numerical operation engine determines an operation of the plurality of read voltages for reading the third read voltage of the first physical program cell according to the first state parameter and the second state parameter,

the numerical operation engine determines the third read voltage according to the first state parameter, the second state parameter, and the predefined weight or the offset.

19. The memory control circuit cell of claim 11, wherein

The memory management circuitry receives a first write command from the host system,

the memory management circuit inputs a third state parameter corresponding to the first write command into the numerical operation engine, an

And the numerical operation engine determines the type of first write data corresponding to the first write command according to the third state parameter.

20. The memory control circuit unit of claim 19, wherein the third state parameter comprises a first logical address, a location parameter, or an instruction type corresponding to the first write data, wherein in operation of the numerical operation engine determining the type of the first write data corresponding to the first write instruction based on the third state parameter,

and the numerical operation engine judges that the first written data is hot data or cold data according to the third state parameter, wherein the frequency of accessing the hot data is higher than that of accessing the cold data.

21. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module and having a numerical operation engine,

wherein the memory control circuit unit is configured to read a first physical programming unit of the plurality of physical programming units using at least one first read voltage of a plurality of read voltages to obtain first data,

wherein the memory control circuit unit is further configured to read the first physical programming unit using at least one second read voltage of the plurality of read voltages to obtain second data,

wherein the memory control circuit unit is further configured to input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data to the numerical operation engine, and determine a third read voltage for reading the first physical programming unit among the plurality of read voltages according to the first state parameter and the second state parameter by the numerical operation engine,

the memory control circuit unit is further configured to read the first physical programming unit using the third read voltage to obtain third data.

22. The memory storage device of claim 21, wherein in the operation of reading the first physical program cell of the plurality of physical program cells using the first read voltage of the plurality of read voltages to obtain the first data,

the memory control circuit unit performs a first decoding operation to correct errors in the first data according to first encoded data, and performs an operation of reading the first physical programming unit using the second read voltage among the plurality of read voltages to obtain the second data when there is an uncorrectable error in the first data,

the memory control circuit unit performs the first decoding operation to correct errors in the second data according to second encoded data, and performs an operation of inputting the first state parameter corresponding to the first data and the second state parameter corresponding to the second data to the numerical operation engine when there is an uncorrectable error in the second data.

23. The memory storage device of claim 21, wherein the third read voltage is an optimal read voltage for reading the first physical program cell.

24. The memory storage device of claim 22, wherein

The memory control circuit unit performs the first decoding operation to correct an error in the third data according to third encoded data,

the memory control circuit unit outputs the third data when there is no error in the third data,

when an error in the third data is corrected, the memory control circuit unit outputs the third data corrected for errors, an

When the third data has an uncorrectable error, the memory control circuit unit determines that a failure occurs in reading the first physical program unit using the first decoding operation.

25. The memory storage device of claim 21, wherein the first state parameter comprises a sum of the first data, a total number of bit values of 1 in the first data, a total number of bit values of 0 in the first data, or a first syndrome corresponding to the first data.

26. The memory storage device of claim 21, wherein the second state parameter comprises a sum of the second data, a total number of bit values in the second data being 1, a total number of bit values in the second data being 0, or a second syndrome corresponding to the second data.

27. The memory storage device of claim 21, wherein

When the rewritable nonvolatile memory module is just powered on, the memory control circuit unit loads at least one operation parameter obtained through pre-training from the rewritable nonvolatile memory module into the numerical operation engine.

28. The memory storage device of claim 27, wherein the operation parameter comprises a predefined weight or offset, wherein the numerical operation engine determines an operation of the plurality of read voltages for reading the third read voltage of the first physical program cell according to the first state parameter and the second state parameter,

29. The memory storage device of claim 21, wherein

The memory control circuitry unit receives a first write command from the host system,

the memory control circuit unit inputs a third state parameter corresponding to the first write command into the numerical operation engine, and determines the type of first write data corresponding to the first write command according to the third state parameter through the numerical operation engine.

30. The memory storage device of claim 29, wherein the third state parameter comprises a first logical address, a location parameter, or an instruction type corresponding to the first write data, wherein in an operation of determining a type of the first write data corresponding to the first write instruction by the numerical operation engine according to the third state parameter,

the memory storage device judges whether the first write data is hot data or cold data according to the third state parameter through the numerical operation engine, wherein the frequency of accessing the hot data is higher than the frequency of accessing the cold data.