This application claims be filed in entitled " the ADVANCED INTEGRATED CIRCUIT on November 30th, 2017STRUCTURE FABRICATION(Advanced Integrated Circuits structure manufacture) " U.S. Provisional Application No. 62/593,149 equity,Its entire content is incorporated by reference into whereby herein.
Specific embodiment
Describe advanced integrated circuit structure manufacture.In the following description, such as specific integrated and material group is illustratedNumerous details of organization method etc, in order to provide the thorough understanding to embodiment of the disclosure.For those skilled in the artFor member it will be apparent that, can embodiment of the disclosure without these specific details.At itIn the case of him, it is not described in the well-known characteristic of such as IC design layout etc, in order to avoid unnecessarily make the disclosureEmbodiment it is hard to understand.In addition, it is to be appreciated that, various embodiments shown in the accompanying drawings are illustrative expressions, and differentIt is fixed drawn to scale.
Described in detail below is only embodiment that is illustrative and being not intended to limit this theme or such reality in itselfApply the application and use of example.As used in this article, word " exemplary " means " being used as example, example or illustration ".HereinBe described as illustrative any implementation be not necessarily to be construed as being achieved in that compared to other it is preferred or advantageous.ThisOutside, it is not intended to present in the technical field by front, background technique, summary of the invention or specific embodiment below anyThe theoretical constraint expressed or implied.
This specification includes the reference to " one embodiment " or " embodiment ".The phrase " in one embodiment " or "In embodiment " appearance be not necessarily referring to the same embodiment.It can be combined in any suitable manner according to the disclosure specificFeature, structure or characteristic.
Term.Following paragraphs provide for the term occurred in the disclosure (including appended claims) definition orContext:
" comprising ": the term is open.As used in appended claims, which is not excluded for additional structure or behaviourMake.
" being configured to ": it is that " being configured to " executes one or more that various unit or assemblies, which can be described or claimed protection,A task.In such context, " being configured to " is used for by indicating that the unit or assembly includes executing during operationThe structure of that one or more task implies structure.As such, even if not operating currently in the unit or assembly (for example, not havingHave unlatching or inactive) when, specified unit or assembly can also be said to be to be configured to execute the task.It illustrates singleMember or circuit or component " being configured to " are intended to not quote 35 for the unit or assembly with executing one or more task-awaresU.S.C. the sixth item of § 112.
" first ", " second " etc.: as used in this article, these terms are used as the mark for the noun after themLabel, and do not imply that it is any kind of sequence (for example, spatially, it is temporal, in logic etc.).
" coupling " --- reference element or node is described below or feature is " coupled " together.As used in this article,Unless expressly stated otherwise, it otherwise " couples " and means that an element or node or feature are coupled, directly or indirectly, to another elementOr node or feature (or directly or indirectly communicating), and not necessarily mechanically.
Additionally, it is also possible to which the purpose only for reference uses certain terms in the following description, and the term is thereforeIt is not intended to be restrictive.It is joined for example, the term of such as "upper", "lower", " top " and " lower section " etc refers toThe direction in attached drawing examined.The term in such as " front ", " rear ", " back ", " side ", " outside ", " inside " etc describesOrientation or position or both of each section of component in consistent but arbitrary referential, by reference to the component in description discussionText and associated attached drawing illustrate the referential.Such term may include the word referred to specifically above, itsThe word of derivative and similar meaning.
" inhibition " --- as used in this article, inhibit for describing that effect is made to reduce or minimize.When component or featureWhen being described as inhibition movement, movement or condition, the result or consequence or future state can be entirely prevented.Additionally, " suppressionSystem " can also refer to reduce or mitigate consequence, performance or the effect that may occur originally.Therefore, when component, elements or features quiltReferred to as suppression result or when state, does not need to entirely prevent or eliminate the result or state.
Embodiment described herein can be related to front-end process (FEOL) semiconductor processes and structure.FEOL is integrated electricityThe first part of road (IC) manufacture, wherein to each device (for example, transistor, capacitor, resistance in semiconductor substrate or layerDevice etc.) it is patterned.FEOL generally covers any process until the deposition of (but not including) metal interconnecting layer.LastIt is as a result usually the wafer (for example, not having any conducting wire) with isolated transistor after FEOL operation.
Embodiment described herein can be related to back-end process (BEOL) semiconductor processes and structure.BOEL is IC manufactureSecond part, wherein making each device (for example, brilliant using the wiring (for example, one or more metalization layer) on waferBody pipe, capacitor, resistor etc.) interconnection.BEOL includes contact portion, insulating layer (dielectric), metal level and arrives for chipEncapsulate the junction of connection.In the part BEOL of fabrication stage, contact portion (pad), interconnecting lead, through-hole and electricity are formedDielectric structure.For modern IC processes, it can be added in BEOL and be more than 10 metal layers.
Embodiment as described below can be applicable to FEOL processing and structure, BEOL processing and structure or FEOL andBoth BEOL processing and structure.Particularly, although FEOL processing scene, which can be used, carrys out illustrating exemplary processing scheme, thisThe method of sample can also be applicable to BEOL processing.Equally, although BEOL processing scene, which can be used, carrys out illustrating exemplary processingScheme, but such method can also be applicable to FEOL processing.
Pitch dividing processing may be implemented and patterning regimes enable to realize embodiment described herein, orIt may include a part of pitch dividing processing and patterning regimes as embodiment described herein.Pitch segmentation patterningTypically refer to pitch bisection, pitch quartering etc..Pitch splitting scheme can be applicable to FEOL processing, BEOL processing orBoth person FEOL(device) and BEOL(metallization) processing.According to one or more embodiments described herein, realize firstOptical lithography in predefined pitch to print unidirectional line (for example, strictly one-directional or main unidirectional).Then pitch point is realizedProcessing is cut as the technology for increasing line density.
In embodiment, the term " cell structure " for fin, grid line, metal wire, ILD line or hard mask line is at thisIn text for refer to tight knot away from cell structure.In one suchembodiment, tight knot is away from not directly by selectedPhotoetching is realized.For example, it can be initially formed the pattern based on selected photoetching, but can be by using spacer portion mask patternChange to halve pitch, as known in the art.Further, the second wheel spacer portion mask patterning can be passed throughCome quartering mesomere away from.Therefore, grid-like patterns described herein can have is opened with substantially uniform pitch intervalAnd metal wire, ILD line or hard mask line with substantially uniform width.For example, in some embodiments, pitch variationWill be within 10% and change width will be within 10%, and in some embodiments, pitch variation will be 5% withInterior and change width will be within 5%.It can be divided by pitch halving method or pitch quartering process or other pitchesMethod manufactures pattern.In embodiment, grid be not necessarily single-unit away from.
In the first embodiment, pitch may be implemented to halve so that the line density of manufactured cell structure doubles.Figure1A instantiate the layer of hard mask material formed on interlayer dielectric (ILD) layer after deposition, but before patterningBeginning structure viewgraph of cross-section.Figure 1B, which is instantiated through pitch bisection, patterns Figure 1A's after the hard mask layerThe viewgraph of cross-section of structure.
With reference to Figure 1A, starting structure 100 has the layer of hard mask material being formed on interlayer dielectric (ILD) layer 102104.Patterned mask 106 is deposited in layer of hard mask material 104.Patterned mask 106 has along its featureThe side wall of (line), the spacer portion 108 formed in layer of hard mask material 104.
With reference to Figure 1B, hard mask material layer 104 is come with pitch halving method.Specifically, removal is through scheming firstThe mask 106 of case.The pattern of obtained spacer portion 108 has the pitch or feature of double density or mask 106Half.The pattern of spacer portion 108 is transferred to layer of hard mask material 104 for example, by etching process, it is patterned to be formedHard mask 110, as in Figure 1B describe as.In one suchembodiment, patterned hard mask 110 is formedThere is the grid pattern with unidirectional line.The grid pattern of patterned hard mask 110 can be tight knot away from cell structure.For example, tight knot can not be realized directly by selected photoetching technique away from possibly.Further, although being not shown,Can by second wheel spacer portion mask patterning come quartering mesomere away from.Therefore, the patterned hard mask 110 of Figure 1BGrid-like patterns can have with constant pitch be spaced apart and relative to each other with constant width hard mask line.Institute is realExisting size can be more much smaller than the critical size of used photoetching technique.
Therefore, for front-end process (FEOL) or back-end process (BEOL) or two kinds of Integrated Solutions, light can be usedIt carves with etching process and patterns blanket film, the photoetching and etching process can be related to such as double figure based on spacer portionCase (SBDP) or pitch bisection or four times of patternings (SBQP) or pitch quarterings based on spacer portion.To be understoodIt is that other pitch split plot designs also may be implemented.Under any circumstance, in embodiment, such as 193nm immersion can be passed throughThe selected photoetching process of photoetching (193i) etc is laid out to manufacture lattice-shaped.It may be implemented during lattice-shaped is laid out by pitch segmentationLine density increases to n times.The lattice-shaped of pitch segmentation using 193i photoetching plus " n " again is laid out to be formed and can name as 193iThe segmentation of+P/n pitch.In one suchembodiment, the immersion scaling of 193nm, which can be extended, has cost effect for utilizingThe pitch segmentation of rate carries out many generations.
In the manufacture of integrated circuit device, as device size persistently reduces, such as tri-gate transistor etc it is moreGridistor becomes popular.Generally tri-gate transistor is manufactured on bulk Si substrate or silicon on insulated substrate.?Under some cases, compatibility of the bulk Si substrate due to its lower cost and with existing high production bulk Si substrate infrastructureBut it is preferred.
However, scaling multi-gated transistor not has no achievement.With the ruler of the basic building block of these microelectronic circuitsVery little Jiang Dis and the absolute quantity with the basic building block manufactured in a given area increase, to for manufacturing these structuresThe constraint for building the semiconductor technology of block, which has become, to be difficult to bear.
According to one or more other embodiments of the present disclosure, pitch quartering process is realized to be used for patterned semiconductor layer with shapeAt semiconductor fin.In one or more embodiments, fusion fin pitch quartering process is realized.
Fig. 2A is according to an embodiment of the present disclosure for manufacturing the signal of the pitch quartering process 200 of semiconductor finFigure.Fig. 2 B instantiates the cross section view of the semiconductor fin according to an embodiment of the present disclosure manufactured using pitch quartering processFigure.
With reference to Fig. 2A, at operation (a), photoresist layer (PR) is patterned to form photoresist feature 202.It can be used such asThe standard lithographic processing techniques of 193 immersion lithographies etc patterns photoresist feature 202.At operation (b), photoresist spy is usedSign 202 carrys out patterned material layer, such as insulation or dielectric hardmask, to form the first pillar (BB1) feature 204.ThenThe side wall of adjacent first pillar feature 204 forms the first spacer portion (SP1) feature 206.At operation (c), the first pillar is removedFeature 204 is only to leave the first spacer portion feature 206.It, can be thin before removing the first pillar feature 204 or during this periodChange the first spacer portion feature 206 to form the first spacer portion feature 206' being thinned, as described in Fig. 2A.It can beRemoval BB1(feature 204) before (as depicted) or execute the thinning after this, this depends on special for BB2Required required interval is determined with size for levying (208, be described below).At operation (d), the first spacer portion is usedFeature 206 or the first spacer portion feature 206' being thinned carry out patterned material layer, such as insulation or dielectric hardmask, withForm the second pillar (BB2) feature 208.Then the side wall for abutting the second pillar feature 208 forms the second spacer portion (SP2) feature210.At operation (e), the second pillar feature 208 is removed only to leave the second spacer portion feature 210.Then it can be used and stayedUnder the second spacer portion feature 210 carry out patterned semiconductor layer, with provide relative to initial patterned photoresist feature 202Multiple semiconductor fins of size with the pitch quartering.As an example, using the second spacer portion feature 210 with reference to Fig. 2 BMultiple semiconductor fins 250 are formed as the mask for patterning (for example, dry method or plasma etching patterning), such asThe silicon fin formed by blocky silicon layer.In the example of Fig. 2 B, the multiple semiconductor fin 250 has substantially identical alwaysPitch and interval.
It is to be appreciated that the interval between initial patterned photoresist feature can modify so that pitch quartering processStructure results change.In this example, Fig. 3 A is according to an embodiment of the present disclosure for manufacturing the fusion of semiconductor finThe schematic diagram of fin pitch quartering process 300.Fig. 3 B instantiates according to an embodiment of the present disclosure using fusion fin pitch fourThe viewgraph of cross-section of the semiconductor fin of equisection method manufacture.
With reference to Fig. 3 A, at operation (a), photoresist layer (PR) is patterned to form photoresist feature 302.It can be used such asThe standard photolithography process technology of 193 immersion lithographies etc but generate uniform pitch pattern at double may finally interfereThe interval (for example, referred to as sub- design rule interval) of required design rule patterns photoresist feature 302.At operation (b),Carry out patterned material layer using photoresist feature 302, such as insulation or dielectric hardmask, it is special to form the first pillar (BB1)Sign 304.Then the side wall for abutting the first pillar feature 304 forms the first spacer portion (SP1) feature 306.However, with example in Fig. 2AThe scheme shown is compared, as closer photoresist feature 302 as a result, some in adjacent the first spacer portion feature 306 areMerge spacer portion feature.At operation (c), the first pillar feature 304 is removed only to leave the first spacer portion feature 306.It is goingIt, can be with some to be formed through thin in the first spacer portion of thinning feature 306 except before the first pillar feature 304 or after thisThe the first spacer portion feature 306' changed, as described in Fig. 3 A.At operation (d), 306 He of the first spacer portion feature is usedThe first spacer portion feature 306' being thinned carrys out patterned material layer, such as insulation or dielectric hardmask, to form secondPillar (BB2) feature 308.Then the side wall for abutting the second pillar feature 308 forms the second spacer portion (SP2) feature 310.SoAnd in the position that BB2 feature 308 is fusion feature, such as at the central BB2 feature 308 of Fig. 3 A, the second interval is not formedPortion.At operation (e), the second pillar feature 308 is removed only to leave the second spacer portion feature 310.Then it can be used and stayedUnder the second spacer portion feature 310 carry out patterned semiconductor layer, with provide relative to initial patterned photoresist feature 302Multiple semiconductor fins of size with the pitch quartering.
As an example, with reference to Fig. 3 B, use the second spacer portion feature 310 as pattern (for example, dry method or wait fromSub- etch patterning) mask form multiple semiconductor fins 350, the silicon fin such as formed by blocky silicon layer.However,In the example of Fig. 3 B, the modified pitch of the multiple semiconductor fin 350 and interval.Such fusion fin may be implementedSpacer portion patterning process is substantially to eliminate presence of the fin in certain positions of the pattern of multiple fins.Therefore, certainThe first spacer portion feature 306 is merged in position allows its based on two the first pillar feature 304(to generally produce eight fins, such asAs being described in association with Fig. 2A and 2B) manufacture six or four fins.In one example, fin has phase in plateThan the pitch by generating fin with regular pitches and then to cut pitch that unwanted fin will usually allow closer,But latter method still may be implemented according to embodiment described herein.
In the exemplary embodiment, with reference to the integrated circuit structure of Fig. 3 B, a semiconductor fin 352 more than first have alongThe longest dimension of first direction (y, into the page).Adjacent each semiconductor fin more than first in a semiconductor fin 352Piece 353 is spaced each other the first quantity (S11) in the second direction (x) orthogonal with first direction y.A semiconductor fin more than second354 have the longest dimension of y along a first direction.Adjacent each semiconductor fin more than second in a semiconductor fin 354355 are spaced each other the first quantity (S1) in second direction.It is belonging respectively to a more than 352 and second half of semiconductor fin more than firstThe hithermost semiconductor fin 356 and 357 of conductor fin 354 is spaced each other the second quantity (S2) in second direction x.In realityIt applies in example, the second quantity S2 is greater than the first quantity S1 but is less than two times of the first quantity S1.In another embodiment, the second numberMeasure two times that S2 is greater than the first quantity S1.
In one embodiment, a semiconductor fin 354 of a semiconductor fin more than 352 and second more than first includes silicon.?In one embodiment, a semiconductor fin 354 of a semiconductor fin more than 352 and second more than first connects with following monocrystalline silicon substrateIt is continuous.In one embodiment, each semiconductor in a semiconductor fin 354 of a semiconductor fin more than 352 and second more than firstFin has along second direction x from each in a semiconductor fin 354 of semiconductor fin more than 352 and second a more than firstThe side wall of the top-to-bottom of semiconductor fin being tapered outward.In one embodiment, a semiconductor fin more than first352 have lucky five semiconductor fins, and a semiconductor fin 354 more than second has lucky five semiconductor fins.
In a further exemplary embodiment, with reference to Fig. 3 A and 3B, the method for manufacturing integrated circuit structure includes forming firstBB1 on the left of primary pillar feature 304() and the second primary pillar feature 304(on the right side of BB1).Adjacent first primary pillar is specialBB1 on the left of sign 304() and the second primary pillar feature 304(on the right side of BB1) side wall form primary spacer portion structure 306.BB1 on the left of the primary pillar feature 304(of fusion first) and the second primary pillar feature 304(on the right side of BB1) between primarySpacer portion structure 306.The primary pillar feature (BB1 in left side) of removal first and the second primary pillar feature (BB1 on right side), andFirst, second, third and fourth grade pillar feature 308 is provided.Fusion second and third secondary pillar feature are (for example, centerThe secondary pillar feature 308 of a pair).The side wall of adjacent first, second, third and fourth grade pillar feature 308 forms secondarySpacer portion structure 310.Then first, second, third and fourth grade pillar feature 308 is removed.Then, by semiconductor material figureCase has secondary spacer portion structure 310, to form semiconductor fin 350 in a semiconductor material.
In one embodiment, by the BB1 on the left of the first primary corbeling 304() and the second primary corbeling 304(BB1 on right side) is patterned with the sub- design rule interval between the first primary corbeling and the second primary corbeling.?In one embodiment, semiconductor material includes silicon.In one embodiment, each semiconductor fin in semiconductor fin 350Top-to-bottom with each semiconductor fin in the slave semiconductor fin 350 along second direction x gradually becomes outwardThin side wall.In one embodiment, semiconductor fin 350 and following monocrystalline silicon substrate are continuous.In one embodiment, willIt includes forming first with the longest dimension of y along a first direction that semiconductor material, which is patterned with secondary spacer portion structure 310,Multiple semiconductor fins 352, wherein adjacent each semiconductor fin more than first in a semiconductor fin 352 with first partyThe first quantity S1 is spaced each other in the second direction x orthogonal to y.A semiconductor fin 354 is formed along first more than secondDirection y has longest dimension, wherein adjacent each semiconductor fin more than second in a semiconductor fin 354 is in second directionThe first quantity S1 is spaced each other in x.It is belonging respectively to a semiconductor fin 354 of a semiconductor fin more than 352 and second more than firstHithermost semiconductor fin 356 and 357 is spaced each other the second quantity S2 in second direction x.In embodiment, the second quantityS2 is greater than the first quantity S1.In one suchembodiment, twice of the second quantity S2 less than the first quantity S1.It is another thisIn the embodiment of sample, the second quantity S2 is greater than two times of the first quantity S1 but is less than its three times.In embodiment, more than firstSemiconductor fin 352 has lucky five semiconductor fins, and a semiconductor fin 254 more than second has lucky five and half to leadBody fin, as described in Fig. 3 B.
In another aspect, it is to be appreciated that, fin of the fin removal as the alternative to fusion fin method is being executedIn piece dressing process, (removal) fin can be modified during hard mask pattern or by physically removing finPiece.As the example of latter method, Fig. 4 A-4C is the side according to an embodiment of the present disclosure for indicating to manufacture multiple semiconductor finsThe viewgraph of cross-section of various operations in method.
With reference to Fig. 4 A, patterned hard mask layer is formed on the semiconductor layer 404 of such as bulk-shaped monocrystal silicon layer etc402.With reference to Fig. 4 B, fin 406 is then formed in semiconductor layer 404 for example, by dry method or plasma etch processes.With reference toFig. 4 C removes selected fin 406 using such as mask and etching process.In the example shown, one in fin 406 is removedIt is a, and remaining fin root 408 can be left, as described in Fig. 4 C.It, will in such " fin finishing extreme trace " methodHard mask 402 is patterned as a whole to provide cell structure in the case where not removing or modifying each feature.UntilIt has manufactured fin and has just modified fin group later.
In another aspect, it can be realized between semiconductor fin and be properly termed as the more of shallow trench isolation (STI) structureLayer trench isolation region.In embodiment, multilayer sti structure is formed between the silicon fin being formed in bulk Si substrate to limitDetermine the sub- fin regions of silicon fin.
Can be using bulk silicon for fin or transistor based on three grids close it is desired.However, there are following GusConsider: the region (sub- fin) below effective silicon fin part (for example, grid-controlled region or HSi) of device is weakened or notIt is controlled by grid.As such, if source electrode or drain region are at HSi point or lower than HSi points, it would be possible that the sub- fin can be passed throughPanel region and there are leakage paths.It may is that in this way: should be controlled in sub- fin regions for device operation appropriateLeakage path.
The method to solve the above problems, which has been directed to use, wherein carries out heavy doping (example to the sub- fin regionsSuch as, compare 2E18/cm3It is much bigger) trap implant procedure, this has cut off the leakage of sub- fin it can also cause largely mixing in finIt is miscellaneous.Addition halogen implantation material further increases fin doping, so that the end of line fin is doped with high level (for example, bigIn about 1E18/cm3).
Another method is related to adulterating provided doping by sub- fin, without the doping of phase same level to be transferred toThe part HSi of fin.Process can be related to for example the three sub- fins of grid doping glass to selecting by way of external diffusionProperty it is entrained in the sub- fin regions of three grids or FinFET transistor that manufacture on blocky Silicon Wafer.For example, selectively mixingThe sub- fin regions of miscellaneous three grid or FinFET transistor can alleviate sub- fin leakage and fin doping is kept low simultaneously.It willSolid state doping source (for example, p-type and n-type doping oxide, nitride or carbide) is incorporated into transistor process flow ---It is after being recessed from fin sidewall --- trap doping is transferred in sub- fin regions and keeps relatively undoped simultaneouslyFin body.
Therefore, process program may include the solid source doped layer that is deposited on fin after fin etch (for example, mixingBoron oxide compound) use.Later after trench fill and polishing, doped layer is made to be recessed together with trench fill material, with limitSurely it is used for the fin height (HSi) of device.The operation eliminates doped layer from the fin sidewall higher than HSi.Therefore, only alongThere are doped layers for fin sidewall in sub- fin regions, which ensure that the accurate control that doping is launched.It is driving into after formula annealing,It is highly doped to be limited to sub- fin regions, so that (which form the channel regions of transistor in the adjacent fin regions higher than HSiDomain) in fast transition to low-doped.In general, realizing Pyrex (BSG) for the doping of NMOS fin, and it is directed to PMOS finPhosphorosilicate glass (PSG) or arsenic silica glass (AsSG) layer is realized in piece doping.In one example, such p-type solid state doping material resourceIt is the bsg layer with the boron concentration about in the range of 0.1-10 mass percent.In another example, such N-typeSolid state doping material resource be respectively provided with the phosphorus or arsenic concentration about in the range of 0.1-10 mass percent PSG layer orAsSG layers.It can include silicon nitride capping layer on doped layer, and then can include dioxy on the silicon nitride capping layerSiClx or silica-filled material.
According to another embodiment of the present disclosure, relatively thin fin as following (is less than about for example, havingThe fin of 20 nanometers of width) for the leakage of sub- fin it is sufficiently low: abutted directly against in the fin fin formed it is undoped orThe silica or silicon dioxide film of light dope form nitrogen on undoped or light dope the silica or silicon dioxide filmSiClx layer, and include silica or silica-filled material on the silicon nitride capping layer.It is to be appreciated that sub- fin areaThe doping of such as halogen doping etc in domain can also be realized with such structure.
Fig. 5 A instantiates a pair of of the semiconductor fin according to an embodiment of the present disclosure separated by three layers of groove isolation constructionViewgraph of cross-section.
With reference to Fig. 5 A, integrated circuit structure includes fin 502, such as silicon fin.Fin 502 has lower fin portion (sonFin) 502A and upper fin portion 502B(HSi).First insulating layer 504 is directly in the lower fin portion 502A's of fin 502On side wall.Second insulating layer 506 is directly in the first insulating layer directly on the side wall of the lower fin portion 502A of fin 502On 504.To direct neighbor, the second insulating layer 506 is directly in for dielectric filler material 508 and 506 side of second insulating layerDirectly on the first insulating layer 504 on the side wall of the lower fin portion 502A of fin 502.
In embodiment, the first insulating layer 504 is the undoped insulating layer for including silicon and oxygen, such as silica or dioxySiClx insulating layer.In embodiment, the first insulating layer 504 includes silicon and oxygen, and is not had containing than every cube of 1E15 atomOther atomic species of centimetre bigger atomic concentration.In embodiment, the first insulating layer 504 has the model at 0.5-2 nanometersThickness in enclosing.
In embodiment, second insulating layer 506 includes silicon and nitrogen, and such as stoichiometry is Si3N4Silicon nitride dielectric layer,The silicon nitride dielectric layer of the silicon nitride dielectric layer of Silicon-rich or poor silicon.In embodiment, second insulating layer 506 has and receives in 2-5Thickness in the range of rice.
In embodiment, dielectric filler material 508 includes silicon and oxygen, such as silica or silicon dioxide insulating layer.?In embodiment, the final upper fin portion 502B on the top of the upper fin portion 502B of fin 502 and with fin 502Side wall laterally be adjacent to form gate electrode.
It is to be appreciated that during processing, may corrode or consume the upper fin portion of semiconductor fin.Moreover, finBetween groove isolation construction may also become to be etched into nonplanar pattern, or may be formed with nonplanarPattern in manufacture.As an example, Fig. 5 B instantiate according to another embodiment of the present disclosure by another three layers of groove isolation constructionThe viewgraph of cross-section of another pair semiconductor fin separated.
With reference to Fig. 5 B, integrated circuit structure includes the first fin 552, such as silicon fin.First fin 552 has lower finShoulder at part 552A and upper fin portion 552B and region between lower fin portion 552A and upper fin portion 552BShape feature 554.Second fin 562 of such as second silicon fin etc have lower fin portion 562A and upper fin portion 562B withAnd the shoulder feature 564 at the region between lower fin portion 562A and upper fin portion 562B.First insulating layer 574 is directlyOn the side wall of the lower fin portion 552A of the first fin 552 and directly the lower fin portion 562A's of the second fin 562On side wall.First insulating layer 574 has first end 574A substantially coplanar with the shoulder feature 554 of the first fin 552, andAnd first insulating layer 574 further have the second end 574B substantially coplanar with the shoulder feature 564 of the second fin 562.Second insulating layer 576 is directly on the first insulating layer 574, and first insulating layer 574 is directly in the lower fin of the first fin 552On the side wall of part 552A and directly on the side wall of the lower fin portion 562A of the second fin 562.
578 side of dielectric filler material is to second insulating layer 576 is abutted directly against, and the second insulating layer 576 is directlyOn one insulating layer 574, first insulating layer 574 directly on the side wall of the lower fin portion 552A of the first fin 552 andDirectly on the side wall of the lower fin portion 562A of the second fin 562.In embodiment, dielectric filler material 578 has upperSurface 578A, wherein a part of the upper surface 578A of dielectric filler material 578 is lower than the shoulder feature of the first fin 552At least one of 554 and be lower than the second fin 562 at least one of shoulder feature 564, such as that described in Fig. 5 BSample.
In embodiment, the first insulating layer 574 is the undoped insulating layer for including silicon and oxygen, such as silica or dioxySiClx insulating layer.In embodiment, the first insulating layer 574 includes silicon and oxygen, and is not had containing than every cube of 1E15 atomOther atomic species of centimetre bigger atomic concentration.In embodiment, the first insulating layer 574 has the model at 0.5-2 nanometersThickness in enclosing.
In embodiment, second insulating layer 576 includes silicon and nitrogen, and such as stoichiometry is Si3N4Silicon nitride dielectric layer,The silicon nitride dielectric layer of the silicon nitride dielectric layer of Silicon-rich or poor silicon.In embodiment, second insulating layer 576 has and receives in 2-5Thickness in the range of rice.
In embodiment, dielectric filler material 578 includes silicon and oxygen, such as silica or silicon dioxide insulating layer.?In embodiment, the final upper fin portion on the top of the upper fin portion 552B of the first fin 552 and with the first fin 552The side wall of point 552B be laterally adjacent to and on the top of the upper fin portion 562B of the second fin 562 and with the second finThe side wall of the upper fin portion 562B of piece 562 laterally is adjacent to form gate electrode.The gate electrode further the first fin 552 withOn dielectric filler material 578 between second fin 562.
Fig. 6 A-6D instantiates the cross of the various operations in three layers of groove isolation construction of manufacture according to an embodiment of the present disclosureSection view.
With reference to Fig. 6 A, the method for manufacturing integrated circuit structure includes forming fin 602, such as silicon fin.Directly in finThe first insulating layer 604 is formed on 602, and first insulating layer 604 and fin 602 are conformal, as described in Fig. 6 B.?In embodiment, the first insulating layer 604 includes silicon and oxygen, and does not have and contain the atom bigger than 1E15 atoms per cubic centimeterOther atomic species of concentration.
With reference to Fig. 6 C, directly on the first insulating layer 604 formed second insulating layer 606, and the second insulating layer 606 withFirst insulating layer 604 is conformal.In embodiment, second insulating layer 606 includes silicon and nitrogen.The shape directly in second insulating layer 606At dielectric filler material 608, as described in Fig. 6 D.
In embodiment, this method, which further relates to, makes dielectric filler material 608, the first insulating layer 604 and secondThe recess of insulating layer 606 is to provide the upper fin portion 602A(with exposure for example, the upper fin portion of such as Fig. 5 A and 5B502B, 552B or 562B) fin 602.Obtained structure can be as contacted Fig. 5 A or 5B description.In a realityIt applies in example, is related to dielectric filler material 608, the first insulating layer 604 and the recess of second insulating layer 606 using wet etchingProcess.In another embodiment, it is related to dielectric filler material 608, the first insulating layer 604 and the recess of second insulating layer 606To using plasma etching or dry etch process.
In embodiment, the first insulating layer 604 is formed using chemical vapor deposition processes.In embodiment, using changeVapor deposition processes are learned to form second insulating layer 606.In embodiment, electric Jie is formed using spin coating (spin-on) processMatter packing material 608.In one suchembodiment, dielectric filler material 608 is spin-on material and is for example being recessedSteam treatment is exposed to before or after etching process, to provide the curing materials for including silicon and oxygen.In embodiment, finallyLaterally it is adjacent to be formed on the top of the upper fin portion of fin 602 and with the side wall of the upper fin portion of fin 602Gate electrode.
In another aspect, can retain on certain trench isolation regions gate lateral wall spacer portion material be used as withThe protection that trench isolation region corrodes is fought during processing operation afterwards.For example, Fig. 7 A-7E instantiates the implementation according to the disclosureThe angled three-dimensional cross-section view of various operations in the method for the manufacture integrated circuit structure of example.
With reference to Fig. 7 A, the method for manufacturing integrated circuit structure includes forming fin 702, such as silicon fin.Fin 702 hasLower fin portion 702A and upper fin portion 702B.The side wall for abutting directly against the lower fin portion 702A of fin 702 forms insulationStructure 704.Gate structure 706 is formed on upper fin portion 702B and on insulation system 704.In embodiment,Gate structure is reserved location or dummy gate electrode structure comprising sacrificial gate dielectric layer 706A, sacrifices grid 706B and hardMask 706C.With the upper fin portion 702B of fin 702 conformally, with gate structure 706 conformally and with insulation system 704It is conformally formed dielectric substance 708.
With reference to Fig. 7 B, hard mask material 710 is formed on dielectric substance 708.In embodiment, hard mask material710 be the hard mask material based on carbon formed using spin coating process.
With reference to Fig. 7 C, make the recess of hard mask material 710 to form the hard mask material 712 of recess and exposure dielectric materialA part conformal and conformal with gate structure 706 with the upper fin portion 702B of fin 702 of material 708.The hard mask of recessA part conformal with insulation system 704 of 712 covering dielectric material 708 of material.In embodiment, using wet etching mistakeJourney come make hard mask material 710 be recessed.In another embodiment, come using ash etching, dry etching or plasma etch processesHard mask material 710 is set to be recessed.
With reference to Fig. 7 D, etched in a manner of heterogeneous dielectric substance 708 with along the side wall of gate structure 706, along finThe partial sidewall of the upper fin portion 702B of piece 702 and patterned dielectric substance is formed on insulation system 704714(such as dielectric spacer portion 714A).
With reference to Fig. 7 E, the hard mask material 712 of recess is removed from the structure of Fig. 7 D.In embodiment, gate structure 706It is dummy gate electrode structure, and subsequent processing includes with permanent gate-dielectric and gate electrode stack come replacement gate structure706.In embodiment, further processing includes that embedded source electrode or drain junction are formed on the opposite side of gate structure 706Structure, as described below in more detail.
Referring again to Fig. 7 E, in embodiment, integrated circuit structure 700 includes first fin of such as first silicon fin etcPiece (the 702 of left side), first fin have lower fin portion 702A and upper fin portion 702B.Integrated circuit structure is furtherThe second fin (the 702 of right side) including such as second silicon fin etc, second fin have lower fin portion 702A and upperFin portion 702B.Insulation system 704 abuts directly against the side wall of the lower fin portion 702A of the first fin and abuts directly againstThe side wall of the lower fin portion 702A of two fins.Gate electrode 706 the upper fin portion 702B of the first fin (the 702 of left side) itIt is upper, on the upper fin portion 702B of the second fin (the 702 of right side) and the first part of insulation system 704 704 itOn.First dielectric spacer portion 714A along the upper fin portion 702B of the first fin (the 702 of left side) side wall, and secondDielectric spacer portion 702C along the upper fin portion 702B of the second fin (the 702 of right side) side wall.Second dielectric intervalPortion 714C is between the first fin (the 702 of left side) and the second fin (the 702 of right side) in the second part of insulation system 704It is continuous with the first dielectric spacer portion 714B on 704B.
In embodiment, the first and second dielectric spacer portion 714B and 714C include silicon and nitrogen, and such as stoichiometry isSi3N4Silicon nitride material, the silicon nitride material of Silicon-rich or the silicon nitride material of poor silicon.
In embodiment, integrated circuit structure 700 further comprises the embedded source electrode on opposite sides in gate electrode 706Or drain electrode structure, the embedded source electrode or drain electrode structure have the upper fin portion 702B along the first and second fins 702Bottom surface of the side wall below the top surface of the first and second dielectric spacer portion 714B and 714C, and the source electrode or leakagePole structure has along the side wall of the upper fin portion 702B of the first and second fins 702 in the first and second dielectric spacer portionsTop surface above the top surface of 714B and 714C, as connection Fig. 9 B description as follows.In embodiment, insulation system704 include the first insulating layer, directly second insulating layer on the first insulating layer and directly laterally over the second dielectricDielectric filler material, such as also connection Fig. 9 B description below.
Fig. 8 A-8F instantiates the various behaviour in the method according to an embodiment of the present disclosure for manufacture integrated circuit structureThe viewgraph of cross-section slightly projected that the a-a' axis along Fig. 7 E made intercepts.
With reference to Fig. 8 A, the method for manufacturing integrated circuit structure includes forming fin 702, such as silicon fin.Fin 702 hasLower fin portion (can't see in Fig. 8 A) and upper fin portion 702B.Abut directly against the side of the lower fin portion 702A of fin 702Wall forms insulation system 704.A pair of of gate structure is formed on upper fin portion 702B and on insulation system 704706.It is to be appreciated that the visual angle shown in Fig. 8 A-8F slightly projects, to show in front of upper fin portion 702BThe insulation system of (except the page) and the part of gate structure 706, wherein on this fin portion slightly into the page.In realityIt applies in example, gate structure 706 is reserved location or dummy gate electrode structure comprising sacrificial gate dielectric layer 706A, sacrificial gatePole 706B and hard mask 706C.
With reference to Fig. 8 B, correspond to the process operation of connection Fig. 7 A description, it is conformal with the upper fin portion 702B of fin 702Ground conformally and with the expose portion of insulation system 704 is conformally formed dielectric substance 708 with gate structure 706.
With reference to Fig. 8 C, corresponds to the process operation of connection Fig. 7 B description, form hard mask on dielectric substance 708Material 710.In embodiment, hard mask material 710 is the hard mask material based on carbon formed using spin coating process.
With reference to Fig. 8 D, corresponds to the process operation of connection Fig. 7 C description, make the recess of hard mask material 710 to form recessHard mask material 712 and exposure dielectric substance 708 conformal with the upper fin portion 702B of fin 702 and with grid knotThe conformal a part of structure 706.One conformal with insulation system 704 of 712 covering dielectric material 708 of hard mask material of recessPart.In embodiment, hard mask material 710 is made to be recessed using wet etch process.In another embodiment, it is lost using ashIt carves, dry etching or plasma etch processes make the hard mask material 710 be recessed.
With reference to Fig. 8 E, corresponds to the process operation of connection Fig. 7 D description, dielectric substance 708 is etched in a manner of heterogeneousUsing along gate structure 706 side wall (as part 714A), along the partial sidewall of the upper fin portion 702B of fin 702 withAnd patterned dielectric substance 714 is formed on insulation system 704.
With reference to Fig. 8 F, correspond to the process operation of connection Fig. 7 E description, removal recess covers firmly from the structure of Fig. 8 EMold materials 712.In embodiment, gate structure 706 is dummy gate electrode structure, and subsequent processing includes with permanent gridDielectric and gate electrode stack carry out replacement gate structure 706.In embodiment, further processing is included in gate structure 706Opposite side on form embedded source electrode or drain electrode structure, as described below in more detail.
Referring again to Fig. 8 F, in embodiment, integrated circuit structure 700 includes the fin 702 of such as silicon fin etc, shouldFin 702 has lower fin portion (invisible in Fig. 8 F) and upper fin portion 702B.Insulation system 704 abuts directly against finThe side wall of 702 lower fin portion.First gate electrode (the 706 of left side) is on upper fin portion 702B and in insulation systemOn 704 first part 704A.Second gate electrode (the 706 of right side) is on upper fin portion 702B and in insulation systemOn 704 second part 704A'.First dielectric spacer portion (714A on 706 right side in left side) is along first grid electricityThe side wall of pole (the 706 of left side), and the second dielectric spacer portion (714A in 706 left side on right side) is along second gate electricityThe side wall of pole (the 706 of right side), the second dielectric spacer portion is in first gate electrode (the 706 of left side) and the second gate electrode (right side706) between it is continuous with the first dielectric spacer portion on the Part III 704A'' of insulation system 704.
Fig. 9 A instantiates according to an embodiment of the present disclosure for including permanent gate stack and epitaxial source or drain electrodeThe viewgraph of cross-section slightly projected that the a-a' axis along Fig. 7 E of the integrated circuit structure in region intercepts.Fig. 9 B is instantiated according to thisDisclosed embodiment for the integrated circuit structure including epitaxial source or drain region and multilayer groove isolation constructionThe viewgraph of cross-section intercepted along the b-b' axis of Fig. 7 E.
With reference to Fig. 9 A and 9B, in embodiment, integrated circuit structure includes in the on opposite sides embedded of gate electrode 706Source electrode or drain electrode structure 910.Embedded source electrode or drain electrode structure 910 have the upper fin portion along the first and second fins 702Divide bottom surface 910A of the side wall of 702B below the top surface 990 of the first and second dielectric spacer portion 714B and 714C.It is embeddingEntering formula source electrode or drain electrode structure 910 has along the side wall of the upper fin portion 702B of the first and second fins 702 in the first HeTop surface 910B above the top surface of second dielectric spacer portion 714B and 714C.
In embodiment, gate stack 706 is permanent gate stack 920.In one suchembodiment, permanentlyGate stack 920 includes that gate dielectric layer 922, the first grid layer 924 of such as work function grid layer etc and grid are filled outMaterial 926 is filled, as described in Fig. 9 A.In one embodiment, wherein permanent gate structure 920 is in insulation systemOn 704, permanent gate structure 920, the polysilicon segment 930 of the remnants are formed on remaining polysilicon segment 930It can be the residue for being related to sacrificing the replacement gate process of polygate electrodes.
In embodiment, insulation system 704 include the first insulating layer 902, directly on the first insulating layer 902 second absolutelyEdge layer 904 and the directly laterally dielectric filler material 906 in second insulating layer 904.In one embodiment, first absolutelyEdge layer 902 is the undoped insulating layer for including silicon and oxygen.In one embodiment, second insulating layer 904 includes silicon and nitrogen.?In one embodiment, dielectric filler material 906 includes silicon and oxygen.
In another aspect, the embedded source electrode of extension or drain region be implemented as semiconductor fin source electrode orDrain electrode structure.As an example, Figure 10 instantiates the integrated of the interception according to an embodiment of the present disclosure at source electrode or drain locationsThe viewgraph of cross-section of circuit structure.
With reference to Figure 10, integrated circuit structure 1000 includes P-type device, such as P type metal oxide semiconductor (PMOS) devicePart.Integrated circuit structure 1000 further includes N-type device, such as N-type metal-oxide semiconductor (MOS) (NMOS) device.
The PMOS device of Figure 10 includes more than first a semiconductor fins 1002, the silicon such as formed by bulk Si substrate 1001Fin.At source electrode or drain locations, the top of fin 1002 has been had been removed, and has grown identical or different semiconductor materialMaterial is to form source electrode or drain electrode structure 1004.It is to be appreciated that source electrode or drain electrode structure 1004 are on the either side of gate electrodeThe viewgraph of cross-section of interception will appear to it is identical, for example, they will seem substantially identical in drain side in source side.?In embodiment, as depicted, source electrode or drain electrode structure 1004 with the part below the upper surface of insulation system 1006 and are somebody's turn to doPart above upper surface.In embodiment, as depicted, source electrode or drain electrode structure 1004 are strong facetings.ImplementingIn example, electrically conducting contact 1008 is formed on source electrode or drain electrode structure 1004.However, in one suchembodiment, sourceThe strong faceting and relatively wide growth of pole or drain electrode structure 1004 inhibit electrically conducting contact 1008 at least to some extentGood covering.
The NMOS device of Figure 10 includes more than second a semiconductor fins 1052, the silicon such as formed by bulk Si substrate 1001Fin.At source electrode or drain locations, the top of fin 1052 has been had been removed, and has grown identical or different semiconductor materialMaterial is to form source electrode or drain electrode structure 1054.It is to be appreciated that source electrode or drain electrode structure 1054 are on the either side of gate electrodeThe viewgraph of cross-section of interception will appear to it is identical, for example, they will seem substantially identical in drain side in source side.?In embodiment, as depicted, source electrode or drain electrode structure 1054 with the part below the upper surface of insulation system 1006 and are somebody's turn to doPart above upper surface.In embodiment, as depicted, source electrode or drain electrode structure 1054 are relative to source electrode or drain electrode structure1004 be weak faceting.In embodiment, electrically conducting contact 1058 is formed on source electrode or drain electrode structure 1054.At oneIn such embodiment, the relatively weak facet of (as compared with source electrode or drain electrode structure 1004) source electrode or drain electrode structure 1054Change and obtained relatively narrow growth enhances the good covering carried out by electrically conducting contact 1058.
Contact area of the shape of the source electrode or drain electrode structure that can change PMOS device to improve be superimposed contact portion.ExampleSuch as, Figure 11 instantiates the cross of another integrated circuit structure according to an embodiment of the present disclosure intercepted at source electrode or drain locationsSection view.
With reference to Figure 11, integrated circuit structure 1100 includes P-type semiconductor (for example, PMOS) device.The PMOS device includesFirst fin 1102, such as silicon fin.The first epitaxial source or drain electrode structure 1104 are embedded in the first fin 1102.At oneIn embodiment, although not describing, the first epitaxial source or drain electrode structure 1104 are (can be formed on fin 1102On the upper fin portion of such as channel portion etc) first side position of first gate electrode, and in such first grid electricitySecond side opposite with the first side of pole, which is in the first fin 1102, is embedded in the second epitaxial source or drain electrode structure.In embodimentIn, the first epitaxial source or drain electrode structure 1104 and the second epitaxial source or drain electrode structure include silicon and germanium, and have profile1105.In one embodiment, which is matchstick shape profile, as described in Figure 11.First conductive electrode 1108On the first epitaxial source or drain electrode structure 1104.
Referring again to Figure 11, in embodiment, integrated circuit structure 1100 further includes N-type semiconductor (for example, NMOS) devicePart.The NMOS device includes the second fin 1152, such as silicon fin.Third epitaxial source or leakage are embedded in the second fin 1152Pole structure 1154.In one embodiment, although not describing, third epitaxial source or drain electrode structure 1154 are (can be withIt is formed on the upper fin portion of such as channel portion etc of fin 1152) first side position of the second gate electrode, andAnd fourth epitaxial source electrode is embedded in the second fin 1152 at second side opposite with the first side of such second gate electrodeOr drain electrode structure.In embodiment, third epitaxial source or drain electrode structure 1154 and fourth epitaxial source electrode or drain electrode structure includeSilicon, and have basic with the profile 1105 of the first epitaxial source or drain electrode structure 1104 and the second epitaxial source or drain electrode structureUpper identical profile.Second conductive electrode 1158 is on third epitaxial source or drain electrode structure 1154.
In embodiment, the first epitaxial source or drain electrode structure 1104 are weak facetings.In embodiment, the first extensionSource electrode or drain electrode structure 1104 with about 50 nanometers height and there is the width in 30-35 nanometers of range.OneIn a such embodiment, third epitaxial source or drain electrode structure 1154 with about 50 nanometers height and in 30-Width in 35 nanometers of range.
In embodiment, the first epitaxial source or drain electrode structure 1104 are classified: the first epitaxial source orAbout 20% germanium concentration at the bottom 1104A of drain electrode structure 1104 is to the top of the first epitaxial source or drain electrode structure 1104About 45% germanium concentration at 1104B.In embodiment, the first epitaxial source or drain electrode structure 1104 are doped with boron atom.?In one such embodiment, third epitaxial source or drain electrode structure 1154 are doped with phosphorus atoms or arsenic atom.
Figure 12 A-12D instantiates the various operations according to an embodiment of the present disclosure indicated in manufacture integrated circuit structure simultaneouslyAnd the viewgraph of cross-section intercepted at source electrode or drain locations.
With reference to Figure 12 A, the method for manufacturing integrated circuit structure includes forming fin, the silicon such as formed by silicon substrate 1201Fin.Fin 1202 has lower fin portion 1202A and upper fin portion 1202B.In embodiment, although not describing,Fin 1202 upper fin portion 1202B into forming gate electrode on the part at the position in the page.Such gridElectrode has first side opposite with second side, and source electrode or drain locations are limited in the first and second sides.For example,For the purpose of illustration, at one of each side of gate electrode place in the interception of one of source electrode or drain locations place for Figure 12 A-12D'sThe cross-section location of view.
With reference to Figure 12 B, make source electrode or the drain locations recess of fin 1202 to form the fin portion 1206 of recess.FinThe source electrode or drain locations of 1202 recess can be at the side of gate electrode and be at second side of gate electrode.With reference toBoth Figure 12 A and 12B, in embodiment, along the side wall of a part for example at the side of gate structure of fin 1202Form dielectric spacer portion 1204.In one suchembodiment, it is related to the recess of fin 1202 in dielectric spacer portionFin 1202 is set to be recessed below 1204 top surface 1204A.
With reference to Figure 12 C, such as epitaxial source or drain electrode structure 1208 are formed on the fin 1206 of recess, and therefore shouldEpitaxial source or drain electrode structure 1208 can be formed at the side of gate electrode.In one suchembodiment, it is being recessedFin 1206 on the second part at second side of such gate electrode form the second epitaxial source or drain electrode structure.?In embodiment, epitaxial source or drain electrode structure 1208 include silicon and germanium, and have matchstick shape profile, as described in Figure 12 CAs.In embodiment, including dielectric spacer portion 1204, and it is the side along epitaxial source or drain electrode structure 1208The lower part 1208A of wall, as depicted.
With reference to Figure 12 D, conductive electrode 1210 is formed on epitaxial source or drain electrode structure 1208.In embodiment, conductiveElectrode 1210 includes electrically conductive barrier 1210A and conductive filling material 1210B.In one embodiment, conductive electrode 1210 is abided byThe profile of epitaxial source or drain electrode structure 1208 is followed, as depicted.In other embodiments, epitaxial source or drain junctionThe top of structure 1208 is etched during the manufacture of conductive electrode 1210.
In another aspect, fin finishing isolation (FTI) and single gate spacer for segregate fin are described.BenefitWith the non-planar transistor of the fin from substrate surface semiconductor material outstanding use the two sides around the fin, three sides orThe even gate electrode (that is, bigrid, three grids, nano-wire transistor) of all sides.Then source electrode and drain electrode region is usually in gridThe regrowth part of fin is formed in fin or is formed on the either side of electrode.In order to by the first non-planar crystalline substanceThe source electrode of body pipe or drain region are isolated with the source electrode of the second adjacent non-planar transistor or drain region, can be twoGap or interval are formed between a adjacent fin.Such external series gap generally requires certain mask etching.Once being isolated, soGate stack is just patterned on each fin afterwards, be usually again using certain mask etching (for example, line etching orOpening etching, this depends on specific embodiment).
One about above-mentioned fin isolation technology is potentially prone to: grid will not with the end SeIf-alignment of fin, andAnd gate stack pattern and semiconductor fin pattern are aligned being superimposed dependent on the two patterns.As such, photoetching is superimposed toleranceIt is added in the size determination of semiconductor fin and external series gap, wherein fin needs between having biggish length and being isolatedGap is greater than the size that they will have originally for given transistor function level.It is true to reduce such excessively sizeFixed device architectures and manufacturing technology thus provide the highly advantageous improvement in terms of transistor density.
It is potentially prone to about above-described the another of fin isolation technology: for desired by improvement carrier mobilitySemiconductor fin in stress may be left during manufacture useless transistor from wherein excessive fin surfaceIt is lost in channel region, so that fin tension be allowed to loosen.Maintain the device architectures and system of the expectation fin stress of higher levelThe technology of making thus provides the favourable improvement of non-planar transistor aspect of performance.
In accordance with an embodiment of the present disclosure, there is described herein penetrate grid fin isolation architecture and technology.Illustrated byIn exemplary embodiment, the non-planar transistor in such as microelectronic component of integrated circuit (IC) etc is with SeIf-alignment to crystalline substanceThe mode of the gate electrode of body pipe and be isolated from each other.Although embodiment of the disclosure is applicable to using non-planar transistor almostAny IC, but exemplary IC includes but is not limited to: microprocessor core, RFIC including the part logic and memory (SRAM)(e.g., including the wireless IC of digital baseband and analog front-end module) and Power IC.
In embodiment, using area of isolation that the both ends of adjacent semiconductor fin are electrically isolated from one, utilize only onePattern mask grade to position the area of isolation relative to gate electrode.In embodiment, had using single mask to be formedFixed knot away from multiple sacrifice reserved location items, the first subset of reserved location item defines position or the size of area of isolation,And the second subset of reserved location item defines position or the size of gate electrode.In certain embodiments, reserved location item is removedThe first subset and carry out the isolation cutting in the semiconductor fin into the opening as obtained from the removal of the first subset, and it is finalThe second subset of reserved location item is substituted with non-sacrificial gate electrode stack.Due to using the reserved place for gate electrode substitutionThe subset set forms area of isolation, therefore this method and obtained framework be referred to herein as " penetrating grid " isolation.ThisThe one or more of described in the text, which penetrates gate isolation, for example can make it possible to realize higher transistor density and more Gao ShuiFlat advantageous transistor channel stress.
In the case where limiting isolation after placing or limiting gate electrode, biggish transistor density may be implemented, this isBecause can about gate electrode ideally live (on-pitch) to carry out fin isolation size determining and place so that gate electrode andThe integral multiple of area of isolation both minimal characteristic pitch of single mask grade.Have in semiconductor fin and is placed in finIn the other embodiment of the lattice mismatch of substrate thereon, maintained by limiting isolation after placing or limiting gate electrodeBigger tension degree.For such embodiment, other features of the transistor formed before limiting fin tips are (such asGate electrode and added source electrode or drain material) facilitate after carrying out the isolation cutting into fin mechanically to maintain finPiece tension.
In order to provide further context, transistor scaling can benefit from the intensive filling of the unit in chip.MeshBefore, the adjacent unit of most counting unit is separated by two or more dummy gate electrodes, the dummy gate electrode has hiddenBury fin.The unit is isolated by etching fin under the two or more dummy gate electrode, the fin is by oneUnit is connected to another.If the number for separating the dummy gate electrode of adjacent unit can be reduced to one from two or moreA, then scaling can bring benefits significantly.As explained above, a solution requires two or more illusory gridPole.The fin being etched in during fin pattern below the two or more dummy gate electrodes.About such methodIt is potentially prone to the space that can be used for unit on dummy gate electrode consumption chip.In embodiment, method described hereinIt makes it possible for only single dummy gate electrode and separates neighbouring unit.
In embodiment, fin finishing partition method is implemented as the patterning regimes of SeIf-alignment.Herein, list is etchedFin under a grid.Therefore, neighbouring unit can be separated by single dummy gate electrode.The advantages of such method, canTo include saving space on chip and allowing more to calculate power for given area.This method can also allow for oneFin finishing is executed at fixed sub- fin pitch.
Figure 13 A and 13B instantiate it is according to an embodiment of the present disclosure indicate to have be used to form and be locally isolated the more of structureThe plan view of various operations in the patterning method of the fin of gate spacer.
With reference to Figure 13 A, multiple fins 1302 with 1304 length along a first direction are shown.Show along withThe grid 1306 of the orthogonal second direction 1308 of first direction 1304, has interval 1307 in-between, and the grid 1306 limitsThe position for ultimately forming multiple grid lines is determined.
With reference to Figure 13 B, a part of (for example, removing by etching process) the multiple fin 1302 is cut to leaveWherein with the fin 1310 of notch 1312.Therefore the isolation structure finally formed in notch 1312 has greater than single gateThe size of line, for example, there are three the sizes of grid line 1306 for tool.Therefore, it will at least partly formed in notch 1312The gate structure finally formed along the position of grid line 1306 is formed on isolation structure.Therefore, notch 1312 is relatively wideFin notch.
Figure 14 A-14D, which instantiates expression according to another embodiment of the present disclosure and has, to be used to form and is locally isolated structureThe plan view of various operations in the patterning method of the fin of single gate spacer.
With reference to Figure 14 A, the method for manufacturing integrated circuit structure includes forming multiple fins 1402, the multiple fin 1402In each fin have along a first direction 1404 longest dimension.Multiple gate structures 1406 are in the multiple fin 1402On, each gate structure in gate structure 1406 has along the second direction 1408 orthogonal with first direction 1404 mostLong size.In embodiment, gate structure 1406 is sacrifice grid line or dummy gate electrode line for example made of polysilicon.OneIn a embodiment, multiple fins 1402 are silicon fins, and continuous with a part of following silicon substrate.
With reference to Figure 14 B, dielectric substance is formed between the adjacent gate structure 1406 in multiple gate structures 1406Structure 1410.
With reference to Figure 14 C, one a part 1412 in multiple gate structures 1406 is removed with the multiple fins 1402 of exposureEach of fin a part 1414.In embodiment, one a part in multiple gate structures 1406 is removed1412 are related to using the broader photoetching of width 1418 than one part 1412 in multiple gate structures 1406Window 1416.
With reference to Figure 14 D, the part 1414 of each of multiple fins 1402 fin being exposed is removed to form notchRegion 1420.In embodiment, each of multiple fins 1402 fin is removed using dry method or plasma etch processesThe part 1414 being exposed.In embodiment, the part of each of multiple fins 1402 fin being exposed is removed1414 are related to being etched to depth more smaller than the height of multiple fins 1402.In one suchembodiment, the depth ratioThe depth of source electrode or drain region in the multiple fin 1402 is bigger.In embodiment, the depth is than multiple fins 1402Live part depth it is deeper, to provide isolative interval.In embodiment, each of multiple fins 1402 fin is removedThe part 1414 being exposed without etching or substantially not etching the source electrode or drain region (such as extension of multiple fins 1402Source electrode or drain region).In one suchembodiment, being exposed for each of multiple fins 1402 fins is removedPart 1414 without lateral etch or the substantially not source electrode of the multiple fins 1402 of lateral etch or drain region (such as extension sourcePole or drain region).
In embodiment, finally for example in the position for being removed part 1414 of each of multiple fins 1402 finIt is middle that incision tract 1420 is filled with insulating layer.Exemplary insulated layer or " polymerization notch " or " plug " structure are described below.SoAnd in other embodiments, incision tract 1420 only partially is filled with insulating layer, is then formed in the insulating layer conductiveStructure.The conductive structure may be used as local interlinkage.In embodiment, with insulating layer or with accommodate local interlinkage structure it is exhaustedEdge layer passes through incision tract 1420 before filling incision tract 1420, can adulterating nitride layer by solid source and implant the dopants intoOr it is transmitted in the part of one or more fins being shown partially cut.
Figure 15 instantiates the viewgraph of cross-section of the integrated circuit structure according to an embodiment of the present disclosure with fin, describedFin has the multi-gate interval for being locally isolated.
With reference to Figure 15, silicon fin 1502 has the first fin portion 1504 of lateral adjacent second fin portion 1506.It is logicalCross relatively wide notch 1508(and such as contact Figure 13 A and 13B description) by the first fin portion 1504 and the second fin portion1506 separate, which has width X.Dielectric filler material is formed in the relatively wide notch 15081510, and the first fin portion 1504 and the second fin portion 1506 are electrically isolated by dielectric filler material 1510.Multiple gridPolar curve 1512 is on silicon fin 1502, wherein each of described grid line can include gate-dielectric and gate electrodeStack 1514, dielectric covers 1516 and sidewall spacers portion 1518.Two grid lines (two grid lines 1512 in left side) occupyRelatively wide notch 1508, and as such, by actually two dummy gate electrodes or invalid grid by the first fin portion1504 separate with the second fin portion 1506.
In contrast, each fin portion can be separated by single gate distance.As an example, Figure 16 A instantiates rootAccording to the viewgraph of cross-section of the integrated circuit structure with fin of another embodiment of the present disclosure, the fin has for partSingle gate spacer of isolation.
With reference to Figure 16 A, silicon fin 1602 has the first fin portion 1604 of lateral adjacent second fin portion 1606.It is logicalCross relatively narrow notch 1608(and such as contact Figure 14 A-14D description) by the first fin portion 1604 and the second fin portion1606 separate, which has width Y, and wherein Y is less than the X of Figure 15.In the relatively narrow notch 1608Dielectric filler material 1610 is formed, and dielectric filler material 1610 is by the first fin portion 1604 and the second fin portion1606 are electrically isolated.Multiple grid lines 1612 are on silicon fin 1602, wherein each of described grid line can includeGate-dielectric and gate electrode stack 1614, dielectric covers 1616 and sidewall spacers portion 1618.Dielectric filler material 1610Occupy position occupied by previous single gate line, and as such, by single " plug-in type (plugged) " grid line by theOne fin portion 1604 is separated with the second fin portion 1606.In one embodiment, remaining spacer portion material 1620 retainsOn the side wall of the position for the gate line portion being removed, as depicted.It is to be appreciated that can be by by relatively early, (there are three invalid grid lines for tool for two or even more invalid grid lines made of broader fin cutting processRegion 1622) by other regions of fin 1602 be isolated from each other, as described below.
Referring again to Figure 16 A, integrated circuit structure 1600 includes fin 1602, such as silicon fin.Fin 1602 has edgeThe longest dimension of first direction 1650.Isolation structure 1610 is along a first direction 1650 by the first top 1604 of fin 1602It is separated with the second top 1606 of fin 1602.Isolation structure 1610 has along a first direction 1650 center 1611.
For first grid structure 1612A on the first top 1604 of fin 1602, first grid structure 1612A has edgeThe second direction 1652(orthogonal with first direction 1650 for example, into the page) longest dimension.By along first partyThe center 1613A of first grid structure 1612A is spaced apart by the pitch to 1650 with the center 1611 of isolation structure 1610.SecondOn the first top 1604 of fin, second grid structure 1612B has along second direction 1652 gate structure 1612BLongest dimension.By along a first direction 1650 pitch by the center 1613B of second grid structure 1612B and first grid knotThe center 1613A of structure 1612A is spaced apart.Third gate structure 1612C is on the second top 1606 of fin 1602, third gridPole structure 1612C has the longest dimension along second direction 1652.By along a first direction 1650 pitch by third gridThe center 1613C of pole structure 1612C is spaced apart with the center 1611 of isolation structure 1610.In embodiment, isolation structure 1610With substantially with the top of first grid structure 1612A, with the top of second grid structure 1612B and with third grid knotThe coplanar top in the top of structure 1612C, as depicted.
In embodiment, in first grid structure 1612A, second grid structure 1612B and third gate structure 1612CEach on the side wall of high k gate dielectric layer 1662 and between the side walls include gate electrode 1660, such asAs being illustrated for exemplary third gate structure 1612C.In one suchembodiment, first grid structure 1612A,Each of second grid structure 1612B and third gate structure 1612C further comprise on gate electrode 1660 andInsulating cover 1616 on the side wall of high k gate dielectric layer 1662.
In embodiment, integrated circuit structure 1600 is between first grid structure 1612A and isolation structure 1610 in finIt further comprise the first epitaxial semiconductor region 1664A on first top 1604 of piece 1602.Second epitaxial semiconductor region1664B is on the first top 1604 between first grid structure 1612A and second grid structure 1612B in fin 1602.Third epitaxial semiconductor region 1664C between third gate structure 1612C and isolation structure 1610 in fin 1602 theOn two tops 1606.In one embodiment, first, second, and third epitaxial semiconductor region 1664A, 1664B and 1664C packetInclude silicon and germanium.In another embodiment, first, second, and third epitaxial semiconductor region 1664A, 1664B and 1664C includesSilicon.
In embodiment, isolation structure 1610 is on the first top 1604 of fin 1602 and the second of fin 1602Stress is induced on top 1606.In one embodiment, stress is compression.In another embodiment, stress is tensile stress.?In other embodiments, isolation structure 1610 is the insulating layer being partially filled with, and then forms conductive structure wherein.The conductive structureIt may be used as local interlinkage.In embodiment, isolation is being formed with insulating layer or with the insulating layer for accommodating local interlinkage structureBefore structure 1610, by solid source adulterate nitride layer implant the dopants into or be transmitted to one or more of fins by partIn the part of cutting.
In another aspect, it is to be appreciated that, can be in the localized positions of fin notch or in the wider of fin notchEffective gate electrode is replaced to form the isolation structure of such as above-mentioned isolation structure 1610 etc at position.Additionally, fin notchThe depth of such local location or broad position can be formed the depth changed relative to each other in fin.FirstIn example, Figure 16 B, which instantiates according to an embodiment of the present disclosure show, can form at which fin isolation structure to replaceThe viewgraph of cross-section of the position of gate electrode.
With reference to Figure 16 B, the fin 1680 of such as silicon fin etc is formed on 1682 top of substrate and can connect therewithIt is continuous.Fin 1680 has fin tips or wide fin notch 1684, for example, it, which can be, such as modifies extreme trace method in above-mentioned finIn formed in fin pattern.Fin 1680 also has partial cut-out 1686, wherein for example modifying isolation method using finThe a part for removing fin 1680 is substituted with dielectric plug as described above in fin finishing isolation methodDummy gate electrode.Effective gate electrode 1688 is formed on fin, and for illustrative purposes, effective gate electrode 1688 is illustrated asSlightly in 1680 front of fin, and fin 1680 is in the background, and wherein dotted line is indicated from the region that front view is capped.It can beDielectric plug 1690 is formed at fin tips or wide fin notch 1684 to replace using effective grid at these locations.ThisOutside or alternatively, dielectric plug 1692 can be formed at partial cut-out 1686 to replace using effective grid at these locationsPole.It is to be appreciated that also being shown at the position of fin 1680 between effective gate electrode 1688 and plug 1690 or 1692Epitaxial source or drain region 1694.Additionally, in embodiment, the rough surface of the fin tips at partial cut-out 1686Degree is more rougher than the fin tips at the position of wider notch, as described in Figure 16 B.
Figure 17 A-17C instantiates the fin according to an embodiment of the present disclosure for using fin finishing isolation method manufacture and cutsThe various depth possibilities of mouth.
With reference to Figure 17 A, the semiconductor fin 1700 of such as silicon fin etc is formed on following 1702 top of substrate simultaneouslyAnd it can be continuous therewith.Fin 1700 has such as time fin as defined by height of the insulation system 1704 relative to fin 1700Part 1700A and upper fin portion 1700B.Fin 1700 is separated into the first fin portion by local fin isolation cut 1706A1710 and second fin portion 1712.In the example of Figure 17 A, as along shown in a-a' axis, local fin isolation cut 1706ADepth be fin 1700 arrive substrate 1702 entire depth.
With reference to Figure 17 B, in the second example, as along shown in a-a' axis, the depth ratio of local fin isolation cut 1706BThe entire depth of fin 1700 to substrate 1702 is deeper.Also that is, notch 1706B is extended in following substrate 1702.
With reference to Figure 17 C, in third example, as along shown in a-a' axis, the depth ratio of local fin isolation cut 1706CThe entire depth of fin 1700 is smaller, but deeper than the upper surface of isolation structure 1704.Referring again to Figure 17 C, show the 4thIn example, as along shown in a-a' axis, the depth of local fin isolation cut 1706D is smaller than the entire depth of fin 1700, andAnd it is in the level about coplanar with the upper surface of isolation structure 1704.
Figure 18 instantiates the local location comparison according to an embodiment of the present disclosure shown for the fin notch in finThe plan view of the possibility option of the depth of more width position and the cross section taken in correspondence view intercepted along a-a' axis.
With reference to Figure 18, first and second semiconductor fins 1800 and 1802 of such as silicon fin etc have in insulation systemThe upper fin portion 1800B and 1802B that 1804 tops extend.Both fins 1800 and 1802 all have fin tips or wide finNotch 1806, for example, what it was formed when can be such as in above-mentioned fin finishing extreme trace method in fin pattern.Fin 1800Also all there is partial cut-out 1808 with both 1802, wherein for example using fin finishing isolation method removal fin 1800 or 1802A part substitutes dummy gate electrode with dielectric plug as described above in fin finishing isolation method.In realityIt applies in example, the surface roughness of the end of the fin 1800 and 1802 at partial cut-out 1808 is than the fin at 1806 positionPiece end is rougher, as described in Figure 18.
With reference to the viewgraph of cross-section of Figure 18, lower fin portion 1800A can be seen below the height of insulation system 1804And 1802A.Also in the viewgraph of cross-section it is seen that before forming insulation system 1804 when fin modifies extreme trace processThe nubbin 1810 for the fin being removed, as described above.Although illustrated as substrate is projected above, stillNubbin 1810 also may be at the level of substrate or into substrate, such as pass through additional exemplary wide notch depth 1820It is discribed.It is to be appreciated that the wide notch 1806 for fin 1800 and 1802 also may be at for notch depth 1820The level of description depicts its example.Partial cut-out 1808, which can have, corresponds to showing for Figure 17 A-17C depth describedExample property depth, as depicted.
Collective reference Figure 16 A, 16B, 17A-17C and 18, in accordance with an embodiment of the present disclosure, integrated circuit structure include comprisingThe fin of silicon, the fin have top and side wall, and wherein the top has longest dimension along a first direction.First isolation junctionStructure along a first direction separates the first end of the first end of the first part of fin and the second part of fin.First everyThere is width along a first direction from structure.The first end of the first part of fin has surface roughness.Gate structureThe laterally adjacent gate electrode of the side wall in a region including the first part on the top of fin and with fin.GridStructure has a width along a first direction, and by pitch along a first direction by the center of gate structure with first everyCenter from structure is spaced apart.Second isolation structure is on the second end of the first part of fin, second end and theOne end is opposite.Second isolation structure has width along a first direction, and the second end tool of the first part of finThere is surface roughness more smaller than the surface roughness of the first end of the first part of fin.Pass through section along a first directionAway from the center of the second isolation structure is spaced apart with the center of gate structure.
In one embodiment, the first end of the first part of fin has crenation pattern, as described in Figure 16 BLike that.In one embodiment, the first epitaxial semiconductor region is in fin between gate structure and the first isolation structureIn first part.Second epitaxial semiconductor region is in the first part of fin between gate structure and the second isolation structureOn.In one embodiment, the first and second epitaxial semiconductor regions have along the second direction orthogonal with first directionWidth, along second direction width than the fin below gate structure first part the width along second direction moreWidth, for example, as connection Figure 11 and 12D describe extension feature, with than in the visual angle shown in Figure 11 and 12D at itUpper their fin portion wider width of growth.In one embodiment, gate structure further comprises in gate electrode and finThe high-pound dielectric layer of side wall between the first part of piece and along gate electrode.
Collective reference Figure 16 A, 16B, 17A-17C and 18, according to another embodiment of the present disclosure, integrated circuit structure includesFin comprising silicon, the fin have top and side wall, and wherein the top has the longest dimension along a direction.First everyThe first end of the first end of the first part of fin and the second part of fin is separated along the direction from structure.FinFirst part first end have certain depth.Gate structure includes first on the top of fin and with finThe laterally adjacent gate electrode of the side wall in a partial region.Second isolation structure is in the second end of the first part of finOn, second end is opposite with first end.The second end of the first part of fin has the with the first part of finThe different depth of the depth of one end.
In one embodiment, the depth of the second end of the first part of fin is less than the first of the first part of finThe depth of end.In one embodiment, the depth of the second end of the first part of fin is greater than the first part of finThe depth of first end.In one embodiment, the first isolation structure has the width along the direction, and gate structure hasThere is the width along the direction.Second isolation structure has the width along the direction.In one embodiment, by along thisThe center of gate structure is spaced apart by the pitch in direction with the center of the first isolation structure, and passes through the pitch along the directionThe center of second isolation structure is spaced apart with the center of gate structure.
Collective reference Figure 16 A, 16B, 17A-17C and 18, according to another embodiment of the present disclosure, integrated circuit structure includesThe first fin comprising silicon, first fin have top and side wall, and wherein the top has the longest ruler along certain orientationIt is very little, and discontinuities (discontinuity) along the direction by the first end of the first part of the first fin and the finThe first end of second part separate.The first part of first fin has the second end opposite with first end, andThe first end of the first part of the fin has certain depth.Integrated circuit structure further includes the second fin comprising silicon, shouldSecond fin has top and side wall, and wherein the top has the longest dimension along the direction.Integrated circuit structure further includesRemaining or remaining fin portion between first fin and the second fin.Remaining fin portion has top and side wall, wherein shouldTop has the longest dimension along the direction, and the depth of the first end of the first part of the top and the fin is notCoplanar.
In one embodiment, the depth of the first end of the first part of fin is lower than remaining or remaining fin portionTop.In one embodiment, the second end of the first part of fin has and the first end of the first part of finThe coplanar depth of depth.In one embodiment, the second end of the first part of fin has the first part lower than finFirst end depth depth.In one embodiment, the second end of the first part of fin has higher than finThe depth of the depth of the first end of first part.In one embodiment, the depth of the first end of the first part of finHigher than the top of remaining or remaining fin portion.In one embodiment, the second end of the first part of fin has and finThe coplanar depth of the depth of the first end of the first part of piece.In one embodiment, the second end of the first part of finHold the depth with the depth of first end of the first part lower than fin.In one embodiment, the first part of finSecond end have higher than fin first part first end depth depth.In one embodiment, finThe second end of first part has the depth coplanar with the top of remaining fin portion.In one embodiment, the of finThe second end of a part has the depth at the top lower than remaining fin portion.In one embodiment, first of finThe second end divided has the depth at the top for being higher than remaining fin portion.
In another aspect, the dielectric plug formed in part or the position of wide fin notch can be customized as finPiece or fin portion provide specific stress.In such an embodiment, the dielectric plug is properly termed as fin tipsStress riser.
One or more embodiments are related to manufacturing the semiconductor devices based on fin.It can be filled via from polymerization plugThe channel stress that journey induces carries out the performance improvement for such devices.Embodiment may include in polymerization plug filling processThe middle mechanical stress induced using material properties in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) channel.AsAs a result, the stress induced can promote the mobility and driving current of transistor.In addition, plug filling side described hereinMethod can permit eliminate deposition during any gap or gap formed.
In order to provide context, the unique material attribute that the plug filling of fin is adjoined in manipulation can induce answering in channelPower.Channel is modulated by tuning composition, deposition and the post-treatment condition of plug packing material according to one or more embodimentsIn stress so that both NMOS and PMOS transistor all be benefited.In addition, compared to such as epitaxial source or drain electrode etc itsFor his common stress source technology, such plug can reside at deeper inside in fin substrate.Plug filling realizes thisThe property of the effect of sample also eliminates the gap or gap during deposition, and certain Defect Modes during alleviating the processFormula.
In order to provide further context, there is no deliberate stress engineering now for grid (polymerization) plug.It is unfortunate, from traditional stress riser stress enhancing tend to device pitch contraction and reduce, it is described tradition stress riser such asIt is epitaxial source or drain electrode, illusory polymerization grid removal, stress liner etc..One or more of to solve the above-mentioned problems,According to one or more other embodiments of the present disclosure, additional stress riser is incorporated into transistor arrangement.Utilize such processAnother possible benefit can be a cancellation using may be common in the case where other chemical gas-phase deposition methods plug inGap or gap.
Figure 19 A and 19B instantiate the selection fin according to an embodiment of the present disclosure at the fin tips with wide notchVarious operations in the method (for example, a part as fin as described above finishing extreme trace process) of end stress source positionViewgraph of cross-section.
With reference to Figure 19 A, the fin 1900 of such as silicon fin etc is formed on 1902 top of substrate and can connect therewithIt is continuous.Fin 1900 has fin tips or wide fin notch 1904, for example, it, which can be, such as modifies extreme trace method in above-mentioned finIn formed in fin pattern.Effective gate electrode position 1906 and dummy gate electrode position are formed on fin 19001908, and for illustrative purposes, effective gate electrode position 1906 and dummy gate electrode position 1908 are shown as slightly existing1900 front of fin, and fin 1900 is in the background, wherein dotted line is indicated from the region that front view is capped.It is to be appreciated thatEpitaxial source or drain region 1910 are also shown at the position between gate location 1906 and 1908 of fin 1900.It additionally, include inter-level dielectric material 1912 at the position between gate location 1906 and 1908 of fin 1900.
With reference to Figure 19 B, grid reserved location structure or dummy gate electrode position 1908 are removed, thus exposure fin tips or widthFin notch 1904.The removal produces opening 1920, may finally form dielectric plug, such as fin end in the openingHold stress riser dielectric plug.
Figure 20 A and 20B instantiate the selection fin according to an embodiment of the present disclosure at the fin tips with partial cut-outVarious behaviour in the method (for example, a part as fin as described above finishing isolation processes) of piece end stress source positionThe viewgraph of cross-section of work.
With reference to Figure 20 A, the fin 2000 of such as silicon fin etc is formed on 2002 top of substrate and can connect therewithIt is continuous.Fin 2000 has partial cut-out 2004, wherein a part of fin 2000 is for example removed using fin finishing isolation method,Dummy gate electrode is removed as described above in the fin finishing isolation method and fin is etched in local location.In finEffective gate electrode position 2006 and dummy gate electrode position 2008 are formed on 2000, and for illustrative purposes, effective gridElectrode position 2006 and dummy gate electrode position 2008 are shown as slightly in 2000 front of fin, and fin 2000 is in backgroundIn, wherein dotted line is indicated from the region that front view is capped.It is to be appreciated that being also located at gate location 2006 in fin 2000With 2008 between position at show epitaxial source or drain region 2010.Additionally, it is located at grid position in fin 2000Setting includes inter-level dielectric material 2012 at the position between 2006 and 2008.
With reference to Figure 20 B, grid reserved location structure or dummy gate electrode position 2008 are removed, so that there is part to cut for exposureThe fin tips of mouth 2004.The removal produces opening 2020, may finally form dielectric plug, such as fin in the openingPiece end stress riser dielectric plug.
Figure 21 A-21M, which instantiates manufacture according to an embodiment of the present disclosure, has differentiation fin tips dielectric plugThe viewgraph of cross-section of various operations in the method for integrated circuit structure.
With reference to Figure 21 A, initial structure 2100 includes NMOS area and PMOS area.The NMOS area packet of initial structure 2100The first fin 2102 for including such as first silicon fin etc is formed on 2104 top of substrate and can connect with substrate 2104It is continuous.First fin 2102 has fin tips 2106, and fin tips 2106 can be formed by part or wide fin notch.FirstFirst effective gate electrode position 2108 and the first dummy gate electrode position 2110 are formed on fin 2102, and for illustrationPurpose, first effective gate electrode position 2108 and the first dummy gate electrode position 2110 are shown as slightly in the first fin 2102Front, and the first fin 2102 is in the background, wherein dotted line is indicated from the region that front view is capped.Also in the first fin 2102The position between gate location 2108 and 2110 at show extension N-type source or drain region 2112, such as extensionSilicon source or drain electrode structure.Additionally, it is wrapped at the position between gate location 2108 and 2110 of the first fin 2102Include inter-level dielectric material 2114.
The PMOS area of initial structure 2100 includes second fin 2122 of such as second silicon fin etc, is formed onAnd it can be continuous with substrate 2104 above substrate 2104.Second fin 2122 has fin tips 2126, fin tips 2106It can be formed by part or wide fin notch.Second effective gate electrode position 2128 and second is formed on the second fin 2122Dummy gate electrode position 2130, and for illustrative purposes, second effective gate electrode position 2128 and the second dummy gate electrodePosition 2130 is shown as slightly in the front of the second fin 2122, and the second fin 2122 is in the background, wherein dotted line indicate fromThe capped region of front view.Also shown at the position between gate location 2128 and 2130 of the second fin 2122Epitaxial p type source electrode or drain region 2132, such as epitaxial silicon germanium source or drain electrode structure.Additionally, in the second fin 2122It include inter-level dielectric material 2134 at position between gate location 2128 and 2130.
With reference to Figure 21 B, the first and second dummy gate electrodes at position 2110 and 2130 are removed respectively.As soon as it is removed,Expose the fin tips 2106 of the first fin 2102 and the fin tips 2126 of the second fin 2122.The removal also generates respectivelyOpening 2116 and 2136 may finally form dielectric plug, such as fin tips stress riser dielectrics in the openingPlug.
With reference to Figure 21 C, material liners 2140 are conformally formed with the structure of Figure 21 B.In embodiment, the material liners packetSilicon and nitrogen are included, such as silicon nitride material pads.
With reference to Figure 21 D, protectiveness canopy 2142, such as metal nitride layer are formed in the structure of Figure 21 C.
With reference to Figure 21 E, hard mask material 2144 is formed on the structure of Figure 21 D, such as based on the hard mask material of carbon.Mask or mask stack 2146 are formed on hard mask material 2144.
Part and protection with reference to Figure 21 F, from the hard mask material 2144 removed in the structure of Figure 21 E in PMOS areaThe part of property canopy 2142.Also mask or mask stack 2146 are removed.
With reference to Figure 21 G, the second material liners 2148 are conformally formed with the structure of Figure 21 F.In embodiment, the second materialLiner includes silicon and nitrogen, such as the second silicon nitride material liner.In embodiment, the second material liners 2148 have different answerPower state is to adjust the stress in the plug being exposed.
With reference to Figure 21 H, the second hard mask material 2150 is formed on the structure of Figure 21 G, such as second based on the hard of carbonMask material, and second hard mask material 2150 is then made to be recessed in the opening 2136 of the PMOS area of the structure.
With reference to Figure 21 I, the second material liners 2148 are etched to remove the second material from NMOS area from the structure of Figure 21 HPad 2148 and to make the second material liners 2148 be recessed in the PMOS area of the structure.
With reference to Figure 21 J, hard mask material 2144 is removed from the structure of Figure 21 I, protectiveness canopy 2142 and second is covered firmlyMold materials 2150.Compared with opening 2136, which is respectively that opening 2116 leaves two different interstitital textures.
With reference to Figure 21 K, formed in the opening 2116 and 2136 of the structure of Figure 21 J insulation filling material 2152 and to its intoRow planarizing (planarize).In embodiment, insulation filling material 2152 is flowable oxide material, such as flowableSilica or earth silicon material.
With reference to Figure 21 L, make the recess of insulation filling material 2152 to be formed in the opening 2116 and 2136 of the structure of Figure 21 KThe insulation filling material 2154 of recess.In embodiment, it is held as a part of dishing process or after the dishing processRow steam oxidation process, to solidify the insulation filling material 2154 of recess.In one suchembodiment, the insulation of recess is filled outThe contraction of material 2154 is filled, to induce the tensile stress on fin 2102 and 2122.However, existing in PMOS area than the area NOMSRelatively less tensile stress inducing materials in domain.
With reference to Figure 21 M, third material liners 2156 are on the structure of Figure 21 L.In embodiment, third material liners2156 include silicon and nitrogen, and such as third silicon nitride material pads.In embodiment, third material liners 2156 prevent the exhausted of recessEdge packing material 2154 is etched during subsequent source electrode or drain contact etch.
Figure 22 A-22D instantiates the example of PMOS fin tips stress riser dielectric plug according to an embodiment of the present disclosureThe viewgraph of cross-section of property structure.
With reference to Figure 22 A, the opening 2136 in the PMOS area of structure 2100 includes the material along the side wall of opening 2136Liner 2140.The lower part of second material liners 2148 and material liners 2140 is conformal, but relative to the upper of material liners 2140Portion is recess.The insulation filling material 2154 of recess has and the second material liners in the second material liners 2148The coplanar upper surface in 2148 upper surface.Third material liners 2156 are filled out in the top of material liners 2140, and in insulationIt fills on the upper surface of material 2154 and on the upper surface of the second material liners 2148.Third material liners 2156 have gap2157, for example, the product as the deposition process for being used to form third material liners 2156.
With reference to Figure 22 B, the opening 2136 in the PMOS area of structure 2100 includes the material along the side wall of opening 2136Liner 2140.The lower part of second material liners 2148 and material liners 2140 is conformal, but relative to the upper of material liners 2140Portion is recess.The insulation filling material 2154 of recess has and the second material liners in the second material liners 2148The coplanar upper surface in 2148 upper surface.Third material liners 2156 are filled out in the top of material liners 2140, and in insulationIt fills on the upper surface of material 2154 and on the upper surface of the second material liners 2148.Third material liners 2156 do not have seamGap.
With reference to Figure 22 C, the opening 2136 in the PMOS area of structure 2100 includes the material along the side wall of opening 2136Liner 2140.The lower part of second material liners 2148 and material liners 2140 is conformal, but relative to the upper of material liners 2140Portion is recess.The insulation filling material 2154 of recess has and is higher than in the second material liners 2148 and on itThe upper surface of the upper surface of second material liners 2148.Third material liners 2156 in the top of material liners 2140, andOn the upper surface of insulation filling material 2154.Third material liners 2156 are shown as not having gap, but in other realitiesIt applies in example, third material liners 2156 have gap.
With reference to Figure 22 D, the opening 2136 in the PMOS area of structure 2100 includes the material along the side wall of opening 2136Liner 2140.The lower part of second material liners 2148 and material liners 2140 is conformal, but relative to the upper of material liners 2140Portion is recess.The insulation filling material 2154 of recess has recess in the second material in the second material liners 2148The upper surface upper surface below of liner 2148.Third material liners 2156 are in the top of material liners 2140, and exhaustedOn the upper surface of edge packing material 2154 and on the upper surface of the second material liners 2148.Third material liners 2156 are shownOut for without gap, but in other embodiments, third material liners 2156 have gap.
Collective reference Figure 19 A, 19B, 20A, 20B, 21A-21M and 22A-22D integrate electricity in accordance with an embodiment of the present disclosureLine structure includes the fin of such as silicon etc, which has top and side wall.The top has the longest ruler along a directionIt is very little.First isolation structure is on the first end of the fin.Gate structure includes on the top of fin and and finThe laterally adjacent gate electrode of the side wall in one region of piece.Gate structure is spaced apart with the first isolation structure along the direction.TheFor two isolation structures on the second end of the fin, second end is opposite with first end.Along the direction by second everyIt is spaced apart from structure with gate structure.Both first isolation structure and the second isolation structure all include the first dielectric substance (exampleSuch as, material liners 2140), laterally around the recess different from first dielectric substance the second dielectric substance (for example,Second material liners 2148).Second dielectric substance of recess is laterally around different from the first and second dielectric substances theAt least part of three dielectric substances (for example, insulation filling material 2154 of recess).
In one embodiment, both the first isolation structure and the second isolation structure all further comprise by the first dielectricLateral circular the 4th dielectric substance (for example, third material liners 2156) in the top of material, the 4th dielectric substance isOn the upper surface of three dielectric substances.In one suchembodiment, the 4th dielectric substance is further in the second dielectricOn the upper surface of material.In another such embodiment, the 4th dielectric substance has the center gap of near vertical.AnotherIn embodiment as one, the 4th dielectric substance does not have gap.
In one embodiment, third dielectric substance has the upper table coplanar with the upper surface of the second dielectric substanceFace.In one embodiment, third dielectric substance has the upper surface of the upper surface lower than the second dielectric substance.At oneIn embodiment, third dielectric substance has the upper surface of the upper surface higher than the second dielectric substance, and third dielectricMaterial is further on the upper surface of the second dielectric substance.In one embodiment, the first and second isolation structures induceCompression on fin.In one suchembodiment, gate electrode is p-type gate electrode.
In one embodiment, the first isolation structure has the width along the direction, and gate structure has along the partyTo width, and the second isolation structure have along the direction width.In one suchembodiment, by along thisThe center of gate structure is spaced apart by the pitch in direction with the center of the first isolation structure, and passes through the section along the directionAway from the center of the second isolation structure is spaced apart with the center of gate structure.In one embodiment, the first and second isolation junctionBoth structures are in the respective grooves all in interlevel dielectric layer.
In one suchembodiment, the first source electrode or drain region be in gate structure and the first isolation structure itBetween.Second source electrode or drain region are between gate structure and the second isolation structure.In one suchembodiment, firstIt is embedded source electrode or the drain region for including silicon and germanium with the second source electrode or drain region.In one suchembodiment,Gate structure further comprises the high-pound dielectric layer of the side wall between gate electrode and fin and along gate electrode.
In another aspect, in semiconductor structure or in a framework being formed on common substrate, Ge Ge electricityThe depth of dielectric plug can change.As an example, Figure 23 A instantiate according to another embodiment of the present disclosure have fin endStress is held to induce the viewgraph of cross-section of another semiconductor structure of feature.Connect with reference to Figure 23 A, including shallow dielectric plug 2308AWith a pair of deep dielectric plug 2308B and 2308C.In one suchembodiment, as depicted, shallow dielectric plug2308A, which is in, is approximately equal to the depth of depth of the semiconductor fin 2302 in substrate 2304, and this is to deep dielectric plug2308B and 2308C is in the depth lower than depth of the semiconductor fin 2302 in substrate 2304.
Referring again to Figure 23 A, such arrangement may be implemented to modify answering on isolation (FTI) device in fin in the trenchPower amplification, the groove are etched deeper into substrate 2304 in order to provide the isolation between adjacent fin 2302.It may be implementedSuch method is with the density of the transistor of increased core on piece.In embodiment, answering of inducing on transistor is filled in by plugStress effect is extended in FTI transistor, because stress biography both occurs for the substrate or trap below fin and transistorIt passs.
In another aspect, in semiconductor structure or in the framework being formed on common substrate, it is included in electricityThe width or quantity of tensile stress induced oxidation nitride layer in dielectric plug can change, this is for example PMOS device depending on the devicePart or NMOS device.As an example, Figure 23 B instantiate according to another embodiment of the present disclosure have fin tips stress lureSend out the viewgraph of cross-section of another semiconductor structure of feature.With reference to Figure 23 B, in certain embodiments, NMOS device include thanThe relatively more tensile stress induced oxidation nitride layer 2350 of corresponding PMOS device.
Referring again to Figure 23 B, in embodiment, realizes and progress differentiation is filled to induce in NMOS and PMOS to plugStress appropriate.For example, NMOS plug 2308D and 2308E ratio PMOS plug 2308F and 2308G are big with more volume and moreThe tensile stress induced oxidation nitride layer 2350 of width.Plug can be filled and be patterned to be induced in NMOS and PMOS deviceDifferent stress.It is, for example, possible to use lithographic patternings (to be situated between for example, widening for the electricity of PMOS device to open PMOS deviceMatter plug trenches), at this point it is possible to execute different the fill options so that the plug in NMOS comparison PMOS device fills differenceChange.In the exemplary embodiment, the volume for reducing the flowable oxide in the plug in PMOS device, which can reduce, to be inducedTensile stress.In one suchembodiment, compression can be for example due to being applied to source electrode and drain electrode region for compressionAnd it is dominant.In other embodiments, the use of different plugs liner or different packing materials provides tunable answerPower control.
As described above, it is to be appreciated that, polymerization plug stress effect can make NMOS transistor (for example, channel tensile stress)It is all benefited with both PMOS transistors (for example, channel compression).In accordance with an embodiment of the present disclosure, semiconductor fin is uniaxiallyIt is applied the semiconductor fin of stress.It can use tensile stress or be uniaxially applied partly leading for stress to this using compressionBody fin uniaxially applies stress.For example, Figure 24 A, which is instantiated, has single shaft according to one or more other embodiments of the present disclosureTo the angled view of the fin of tensile stress, and Figure 24 B is instantiated according to one or more other embodiments of the present disclosure with singleThe angled view of the fin of axial compression stress.
With reference to Figure 24 A, semiconductor fin 2400, which has, is deployed in discrete channel region (C) therein.In semiconductor finSource region (S) and drain region (D) is disposed in the either side of channel region (C) in piece 2400.Point of semiconductor fin 2400Vertical channel region has (to be directed toward away from each other and towards the arrow of end 2402 and 2404 along the direction of uniaxially tensile stressHead) from source region (S) to the direction of current flow of drain region (D).
With reference to Figure 24 B, semiconductor fin 2450, which has, is deployed in discrete channel region (C) therein.In semiconductor finSource region (S) and drain region (D) is disposed in the either side of channel region (C) in piece 2450.Point of semiconductor fin 2450Vertical channel region has the direction (arrow that direction is pointed out each other and from end 2452 and 2454 along uniaxially compressionHead) from source region (S) to the direction of current flow of drain region (D).It is thereby achieved that embodiment described herein withTransistor mobility and driving current are improved, to allow faster execution circuit and chip.
In another aspect, (FTI) local fin is isolated with production fin finishing in production grid line notch (polymerization notch)May exist relationship between the position of piece notch.In embodiment, the part FTI fin only is made in the position of production polymerization notchPiece notch.However, in one suchembodiment, not necessarily production FTI is cut at each position of production polymerization notchMouthful.
Figure 25 A and 25B, which instantiate expression patterning according to an embodiment of the present disclosure, to be had for cutting in selected grid lineThe plan view for the various operations being locally isolated in the method for the fin of single gate spacer of structure is formed in mouth position.
With reference to Figure 25 A, the method for manufacturing integrated circuit structure includes forming multiple fins 2502, the multiple fin 2502In each fin have along a first direction 2504 longest dimension.Multiple gate structures 2506 are in the multiple fin 2502On, each gate structure in gate structure 2506 has along the second direction 2508 orthogonal with first direction 2504 mostLong size.In embodiment, gate structure 2506 is the sacrifice grid line or dummy gate electrode line for example manufactured by polysilicon.OneIn a embodiment, the multiple fin 2502 is silicon fin, and continuous with a part of following silicon substrate.
Referring again to Figure 25 A, dielectric is formed between the adjacent gate structure in the multiple gate structure 2506Material structure 2510.Two parts 2512 and 2513 in the multiple gate structure 2506 are removed with the multiple fin of exposureThe part of each of piece 2502 fin.In embodiment, two 2512 Hes of part in gate structure 2506 are removed2513 are related to the broader photoetching window of width using each of part 2512 and 2513 than gate structure 2506.It goesExcept the part of each of the multiple fin 2502 at position 2512 being exposed is to form incision tract 2520.In realityIt applies in example, being exposed for each of the multiple fin 2502 fin is removed using dry method or plasma etch processesPart.However, the part being exposed of each of the multiple fin 2502 at position 2513 is masked from removal.In embodiment, region 2512/2520 indicates polymerization both notch and the part FTI fin notch.However, position 2513 only indicatesIt polymerize notch.
With reference to Figure 25 B, polymerization notch and the part FTI fin are filled with the insulation system 2530 of such as dielectric plug etcThe position 2512/2520 of piece notch and the position 2513 for polymerizeing notch.Exemplary insulated structure is described below or " polymerization is cutMouthful " or " plug " structure.
Figure 26 A-26C instantiates the cross section of the various possibilities according to an embodiment of the present disclosure for dielectric plugView, the dielectric plug for Figure 25 B structure various regions polymerization notch and the part FTI fin incision site withAnd only it polymerize incision site.
With reference to Figure 26 A, the portion of the dielectric plug 2530 at position 2513 is shown along the a-a' axis of the structure of Figure 25 BDivide the viewgraph of cross-section of 2600A.The part 2600A of dielectric plug 2530 be shown as on not cutting fin 2502 andBetween dielectric material structure 2510.
With reference to Figure 26 B, the portion of the dielectric plug 2530 at position 2512 is shown along the b-b' axis of the structure of Figure 25 BDivide the viewgraph of cross-section of 2600B.The part 2600B of dielectric plug 2530 is shown as on having cut fin position 2520 simultaneouslyAnd between dielectric material structure 2510.
With reference to Figure 26 C, the portion of the dielectric plug 2530 at position 2512 is shown along the c-c' axis of the structure of Figure 25 BDivide the viewgraph of cross-section of 2600C.The part 2600C of dielectric plug 2530 is shown as the trench isolations between fin 2502In structure 2602 and between dielectric material structure 2510.In embodiment, described above is its example, trench isolations knotsStructure 2602 includes the first insulating layer 2602A, second insulating layer 2602B and the insulation filling material on second insulating layer 2602B2602C。
Collective reference 25A, 25B and 26A-26C manufacture the method packet of integrated circuit structure in accordance with an embodiment of the present disclosureIt includes to form multiple fins, each fin in the multiple fin is along a first direction.It is formed on the multiple fin moreA gate structure, each gate structure in gate structure is along the second direction orthogonal with first direction.In the multiple gridDielectric material structure is formed between adjacent gate structure in the structure of pole.Remove first in the multiple gate structureA part of gate structure is with the first part of each of the multiple fin of exposure fin.Remove the multiple grid knotA part of second gate structure in structure is with the second part of each of the multiple fin of exposure fin.Removal instituteThe first part of each of multiple fins fin being exposed is stated, but does not remove each of the multiple fin finThe second part of piece being exposed.The first insulation knot is formed in the position for the first part of the multiple fin being removedStructure.The second insulation system is formed in the position for being removed part of second gate structure in the multiple gate structure.
In one embodiment, the part for removing first in the multiple gate structure and second gate structure relates toAnd to using than each of the part of first and second gate structure in the multiple gate structureThe broader photoetching window of width.In one embodiment, to be exposed of each of the multiple fin fin is removedA part is related to being etched to depth more smaller than the height of the multiple fin.In one suchembodiment, the depthDepth than source electrode or drain region in the multiple fin is bigger.In one embodiment, the multiple fin includes silicon,And it is continuous with a part of silicon substrate.
Collective reference Figure 16 A, 25A, 25B and 26A-26C, according to another embodiment of the present disclosure, integrated circuit structure packetThe fin comprising silicon is included, which has longest dimension along a first direction.Isolation structure be in the fin top itOn, the isolation structure has center along a first direction.First grid structure is on the top of fin, first gridStructure has the longest dimension along the second direction orthogonal with first direction.By pitch along a first direction by the first gridThe center of pole structure is spaced apart with the center of isolation structure.Second grid structure is on the top of fin, second grid knotStructure has the longest dimension along second direction.By the pitch along a first direction by the center of second grid structure and theThe center of one gate structure is spaced apart.Third gate structure be on the top of fin with the first and second gate structures everyOpposite from the side of structure, third gate structure has the longest dimension along second direction.Pass through the section along a first directionAway from the center of third gate structure is spaced apart with the center of isolation structure.
In one embodiment, each of first grid structure, second grid structure and third gate structure be allIncluding the gate electrode on the side wall of high k gate dielectric layer between the side wall.In one suchembodiment, firstEach of gate structure, second grid structure and third gate structure all further comprise on gate electrode and in heightInsulating cover on the side wall of k gate dielectric layer.
In one embodiment, the first epitaxial semiconductor region is in fin between first grid structure and isolation structureTop on.Second epitaxial semiconductor region is on the top between first grid structure and second grid structure in fin.Third epitaxial semiconductor region is on the top between third gate structure and isolation structure in fin.It is real as oneIt applies in example, the first, second, and third epitaxial semiconductor region includes silicon and germanium.In another such embodiment, first, secondIt include silicon with third epitaxial semiconductor region.
Collective reference Figure 16 A, 25A, 25B and 26A-26C, according to another embodiment of the present disclosure, integrated circuit structure packetShallow trench isolation (STI) structure between a pair of of semiconductor fin is included, which has longest ruler along a first directionIt is very little.Isolation structure is on the sti structure, and the isolation structure has center along a first direction.First grid structureOn the sti structure, first grid structure has the longest dimension along the second direction orthogonal with first direction.Pass through edgeThe pitch of first direction the center of first grid structure is spaced apart with the center of isolation structure.Second grid structure is in shouldOn sti structure, second grid structure has the longest dimension along second direction.By pitch along a first direction by secondThe center of gate structure is spaced apart with the center of first grid structure.Third gate structure be on the sti structure with first andThe side of the isolation structure of second grid structure is opposite, and third gate structure has the longest dimension along second direction.Pass through edgeThe pitch of first direction the center of third gate structure is spaced apart with the center of isolation structure.
In one embodiment, each of first grid structure, second grid structure and third gate structure be allIncluding the gate electrode on the side wall of high k gate dielectric layer between the side wall.In one suchembodiment, firstEach of gate structure, second grid structure and third gate structure all further comprise on gate electrode and in heightInsulating cover on the side wall of k gate dielectric layer.In one embodiment, this is a pair of of silicon fin to semiconductor fin.
In another aspect, either polymerization notch still only polymerize notch together with the fin notch of the part FTI, for filling outThe insulation system or dielectric plug for filling cutting position can extend laterally between the corresponding dielectric for having cut grid lineEvery in portion, or even extend beyond the corresponding dielectric spacer portion for having cut grid line.
In the first example that wherein trench contact portion shape is not influenced by polymerization notch dielectric plug, Figure 27 AShown the integrated circuit structure according to an embodiment of the present disclosure with grid line notch plan view and corresponding cross sectionView, the grid line notch have the dielectric plug in the dielectric spacer portion for extending to grid line.
With reference to Figure 27 A, integrated circuit structure 2700A includes the first silicon with 2703 longest dimension along a first directionFin 2702.Second silicon fin 2704 has along a first direction 2703 longest dimension.Insulating material 2706 is in firstBetween silicon fin 2702 and the second silicon fin 2704.Grid line 2708 is along second direction 2709 on the first silicon fin 2702And on the second silicon fin 2704, second direction 2709 is orthogonal with first direction 2703.Grid line 2708 has the first side2708A and second side 2708B, and there is first end 2708C and second end 2708D.Grid line 2708, which has, to insulateDiscontinuities 2710 on body material 2706 between the first end 2708C of grid line 2708 and second end 2708D.Pass throughDielectric plug 2712 fills discontinuities 2710.
Trench contact portion 2714 is at the first side 2708A of grid line 2708 along second direction 2709 in the first silicon finOn 2702 and on the second silicon fin 2704.Trench contact portion 2714 is in the position laterally adjacent with dielectric plug 2712It is continuous for setting 2715 and being on insulating material 2706.Dielectric spacer portion 2716 is on lateral in trench contact portion 2714Between the first side 2708A of grid line 2708.Dielectric spacer portion 2716 along grid line 2708 the first side 2708A and electricityDielectric plug 2712 is continuous.Dielectric spacer portion 2716 has the width (W2) laterally adjacent with dielectric plug 2712,The width width (W1) more laterally adjacent than with the first side 2708A of grid line 2708 is thinner.
In one embodiment, second groove contact portion 2718 is at second side 2708B of grid line 2708 along secondDirection 2709 is on the first silicon fin 2702 and on the second silicon fin 2704.Second groove contact portion 2718 with electricityIt is continuous that the laterally adjacent position 2719 of dielectric plug 2712, which is on insulating material 2706,.Implement as oneIn example, the second dielectric spacer portion 2720 is on lateral in second side of second groove contact portion 2718 and grid line 2708Between 2708B.Second dielectric spacer portion 2720 is to connect along second side 2708B and dielectric plug 2712 of grid line 2708Continuous.Second dielectric spacer portion has the width laterally adjacent with dielectric plug 2712, the width ratio and grid line 2708Second side 2708B it is laterally adjacent width it is thinner.
In one embodiment, grid line 2708 includes high k gate dielectric layer 2722, gate electrode 2724 and dielectric capLayer 2726.In one embodiment, dielectric plug 2712 includes material identical with dielectric spacer portion 2714, but with electricityDielectric distance portion 2714 is discrete.In one embodiment, dielectric plug 2712 includes different from dielectric spacer portion 2714Material.
In the second example that wherein trench contact portion shape is influenced by polymerization notch dielectric plug, Figure 27 BThe plan view and corresponding cross of the integrated circuit structure with grid line notch according to another embodiment of the present disclosure are shownSection view, the grid line notch have the dielectric plug for the dielectric spacer portion for extending beyond grid line.
With reference to Figure 27 B, integrated circuit structure 2700B includes the first silicon with 2753 longest dimension along a first directionFin 2752.Second silicon fin 2754 has along a first direction 2753 longest dimension.Insulating material 2756 is in firstBetween silicon fin 2752 and the second silicon fin 2754.Grid line 2758 is along second direction 2759 on the first silicon fin 2752And on the second silicon fin 2754, second direction 2759 is orthogonal with first direction 2753.Grid line 2758 has the first side2758A and second side 2758B, and there is first end 2758C and second end 2758D.Grid line 2758, which has, to insulateDiscontinuities 2760 on body material 2756 between the first end 2758C of grid line 2758 and second end 2758D.Pass throughDielectric plug 2762 fills discontinuities 2760.
Trench contact portion 2764 is at the first side 2758A of grid line 2758 along second direction 2759 in the first silicon finOn 2752 and on the second silicon fin 2754.Trench contact portion 2764 is in the position laterally adjacent with dielectric plug 2762It is continuous for setting 2765 and being on insulating material 2756.Dielectric spacer portion 2766 is on lateral in trench contact portion 2764Between the first side 2758A of grid line 2758.Dielectric spacer portion 2766 along grid line 2758 the first side 2758A, butIt is not along dielectric plug 2762, to obtain discontinuous dielectric spacer portion 2766.Trench contact portion 2764 have withThe laterally adjacent width of dielectric plug 2762 (W1), the width width more laterally adjacent than with dielectric spacer portion 2766 (W2)It is thinner.
In one embodiment, second groove contact portion 2768 is at second side 2758B of grid line 2758 along secondDirection 2759 is on the first silicon fin 2752 and on the second silicon fin 2754.Second groove contact portion 2768 with electricityIt is continuous that the laterally adjacent position 2769 of dielectric plug 2762, which is on insulating material 2756,.Implement as oneIn example, the second dielectric spacer portion 2770 is on lateral in second side of second groove contact portion 2768 and grid line 2758Between 2758B.Second dielectric spacer portion 2770 along grid line 2758 second side 2758B, but not along dielectric insertPlug 2762, to obtain discontinuous dielectric spacer portion 2770.Second groove contact portion 2768 has and dielectric plug2762 laterally adjacent width, the width width more laterally adjacent than with the second dielectric spacer portion 2770 are thinner.
In one embodiment, grid line 2758 includes high k gate dielectric layer 2772, gate electrode 2774 and dielectric capLayer 2776.In one embodiment, dielectric plug 2762 includes material identical with dielectric spacer portion 2764, but with electricityDielectric distance portion 2764 is discrete.In one embodiment, dielectric plug 2762 includes different from dielectric spacer portion 2764Material.
In the third being wherein tapered at the top of plug to plug bottom for polymerizeing the dielectric plug of incision siteIn example, Figure 28 A-28F instantiate according to another embodiment of the present disclosure manufacture have with dielectric plug gridThe viewgraph of cross-section of various operations in the method for the integrated circuit structure of line notch, the dielectric plug, which has, to be extended beyondLower part in the top of the dielectric spacer portion of grid line and the dielectric spacer portion for extending to grid line.
With reference to Figure 28 A, formed on structure 2804, on the groove isolation construction such as between semiconductor fin moreA grid line 2802.In one embodiment, each of grid line 2802 is all sacrifice or dummy gate electrode line, such as withDummy gate electrode 2806 and dielectric cap 2808.It later can (such as the dielectric that is described below be inserted in replacement gate processAfter plug is formed) in substitution is such sacrifices or the part of dummy gate electrode line.Dielectric spacer portion 2810 is along grid line 2802Side wall.The dielectric substance 2812 of such as interlevel dielectric layer etc is between grid line 2802.Formed mask 2814 and withPhotolithographicallpatterned is patterned to expose one a part in grid line 2802.
With reference to Figure 28 B, in the case where mask 2814 is in place, central grid line 2802 is removed using etching process.ThenRemove mask 2814.In embodiment, etching process has corroded the dielectric spacer portion 2810 for the grid line 2802 being removedPart, to form the dielectric spacer portion 2816 of reduction.Additionally, it has been corroded in etching process and has been masked 2814 exposuresThe top of dielectric substance 2812, to form the dielectric material portion 2818 being etched.In certain embodiments, such asThe remaining dummy gate electrode material 2820 of remaining polysilicon etc retains in the structure, the system as incomplete etching processProduct.
With reference to Figure 28 C, hard mask 2822 is formed on the structure of Figure 28 B.Hard mask 2822 can be with the structure of Figure 28 BTop it is conformal and particularly conformal with the dielectric material portion 2818 that is etched.
With reference to Figure 28 D, such as remaining dummy gate electrode material 2820 is removed using etching process, which can beIt is chemically similar to the etching process for removing the central grid line in grid line 2802.In embodiment, remaining in removalDummy gate electrode material 2820 during, hard mask 2822 protects the dielectric material portion 2818 being etched from further invadingErosion.
With reference to Figure 28 E, hard mask 2822 is removed.In one embodiment, or there is no to being etchedDielectric material portion 2818 it is further erosion in the case where remove hard mask 2822.
With reference to Figure 28 F, dielectric plug 2830 is formed in the opening of the structure of Figure 28 E.Dielectric plug 2830 it is upperPortion is on the dielectric material portion 2818 being etched, for example, being effectively more than primary leading portion 2810.Dielectric plug2830 lower part is adjacent with reduced dielectric spacer portion 2816, for example, effectively entering in primary leading portion 2810 stillNo more than primary leading portion 2810.As a result, dielectric plug 2830 has the wheel being tapered as described in Figure 28 FIt is wide.It is to be appreciated that dielectric plug 2830 can be by above with respect to other polymerization notch or FTI plug or fin tips stressThe material of Source Description and process manufacture.
In another aspect, the part of reserved location gate structure or dummy gate electrode structure can be retained in permanent gridOn trench isolation region below the structure of pole, as the erosion-resistant protection of trench isolation region during replacement gate process.For example, Figure 29 A-29C is instantiated at the part of the bottom according to an embodiment of the present disclosure in permanent gate stack with residualThe plan view and corresponding viewgraph of cross-section of the integrated circuit structure of remaining dummy gate electrode material.
With reference to Figure 29 A-29C, integrated circuit structure includes from the fin 2902 outstanding of semiconductor substrate 2904, such as silicon finPiece.Fin 2902 has lower fin portion 2902B and upper fin portion 2902A.Upper fin portion 2902A has top 2902CWith side wall 2902D.Isolation structure 2906 is around lower fin portion 2902B.Isolation structure 2906 includes having top surface 2907Insulating materials 2906C.Semiconductor material 2908 is in a part of the top surface 2907 of insulating materials 2906C.Semiconductor materialMaterial 2908 is separated with fin 2902.
Gate dielectric layer 2910 is on the top 2902C of upper fin portion 2902A and laterally abuts upper finThe side wall 2902D of part 2902A.Gate dielectric layer 2910 is more in the institute of the top surface 2907 of insulating materials 2906CIt states on the semiconductor material 2908 on part.The additional gate dielectric layer between two parties of such as oxidized portion of fin 2902 etc2911 can be between gate dielectric layer 2910 and the top 2902C of upper fin portion 2902A, and laterally abuts upper finThe side wall 2902D of part 2902A.Gate electrode 2912 is in the gate-dielectric on the top 2902C of upper fin portion 2902AAbut on layer 2910 and laterally the side wall 2902D for going up fin portion 2902A.Gate electrode 2912 is more in insulating materialsOn the gate dielectric layer 2910 on semiconductor material 2908 on the part of the top surface 2907 of 2906C.First sourceFirst side of the adjacent gate electrode 2912 in pole or drain region 2916, and the adjacent gate electrode of the second source electrode or drain region 29182912 second side, second side are opposite with the first side.In embodiment, described above is its example, isolation structure 2906 includesFirst insulating layer 2906A, second insulating layer 2906B and insulating materials 2906C.
In one embodiment, the semiconductor material on the part of the top surface 2907 of insulating materials 2906C2908 are or including polysilicon.In one embodiment, the top surface 2907 of insulating materials 2906C have pit, and byDescribe, and semiconductor material 2908 is in the pit.In one embodiment, isolation structure 2906 includes along insulation materialExpect the second insulating materials (2906A or both 2906B or 2906A/2906B) of the bottom and side wall of 2906C.As oneIn embodiment, the side wall along insulating materials 2906C of the second insulating materials (2906A or both 2906B or 2906A/2906B)Part there is top surface above the highest face temperature of insulating materials 2906C, as depicted.In one embodimentIn, the top surface of the second insulating materials (2906A or both 2906B or 2906A/2906B) is higher than semiconductor material 2908 mostHigh surface is coplanar with the highest face temperature.
In one embodiment, the semiconductor material on the part of the top surface 2907 of insulating materials 2906C2908 are not extended past gate dielectric layer 2910.Also that is, from the viewpoint of plan view, the position of semiconductor material 2908It is limited to the region covered by gate stack 2912/2910.In one embodiment, the first dielectric spacer portion 2920 alongFirst side of gate electrode 2912.Second dielectric spacer portion 2922 along gate electrode 2912 second side.It is real as oneIt applies in example, gate dielectric layer 2910 is further along the first dielectric spacer portion 2920 and the second dielectric spacer portion 2922Side wall extends, as described in Figure 29 B.
In one embodiment, gate electrode 2912 includes conformal electrically conductive layers 2912A(for example, work-function layer).One thisIn the embodiment of sample, work-function layer 2912A includes titanium and nitrogen.In another embodiment, work-function layer 2912A includes titanium, aluminium, carbonAnd nitrogen.In one embodiment, gate electrode 2912 further comprises the conductive fill metal layer on work-function layer 2912A2912B.In one suchembodiment, conductive fill metal layer 2912B includes tungsten.In certain embodiments, conduction is filled outFill metal layer 2912B include 95 or more thick atom percentage tungsten and 0.1 to 2 atomic percent fluorine.In one embodiment,Insulating cover 2924 is on gate electrode 2912 and can extend on gate dielectric layer 2910, such as that described in Figure 29 BSample.
Figure 30 A-30D instantiates manufacture according to another embodiment of the present disclosure in the portion of the bottom of permanent gate stackThe viewgraph of cross-section of various operations in the method for the integrated circuit structure with remaining dummy gate electrode material respectively.The visual angleA part of a-a' axis along the structure of Figure 29 C is shown.
With reference to Figure 30 A, the method for manufacturing integrated circuit structure includes forming fin 3000 from semiconductor substrate 3002.Fin3000 have lower fin portion 3000A and upper fin portion 3000B.Upper fin portion 3000B has top 3000C and side wall3000D.Isolation structure 3004 is around lower fin portion 3000A.Isolation structure 3004 includes the insulation material with top surface 3005Expect 3004C.Reserved location gate electrode 3006 is on the top 3000C of upper fin portion 3000B and laterally abuts upper finThe side wall 3000D of piece part 3000B.Reserved location gate electrode 3006 includes semiconductor material.
Although not describing (show its position in Figure 29 C) from the visual angle of Figure 30 A, reserved place can be abuttedThe first side for setting gate electrode 3006 forms the first source electrode or drain region, and can abut the of reserved location gate electrode 3006Two sides form the second source electrode or drain region, second side are opposite with the first side.It additionally, can be along reserved location gate electrode3006 side wall forms gate-dielectric spacer portion, and can laterally abut reserved location gate electrode 3006 and form interlayer electricity JieMatter (ILD) layer.
In one embodiment, reserved location gate electrode 3006 is or including polysilicon.In one embodiment, it is isolatedThe top surface 3005 of the insulating materials 3004C of structure 3004 has pit, as depicted.Reserved location gate electrode 3006A part in the pit.In one embodiment, isolation structure 3004 include the second insulating materials (3004A or 3004B,Or both 3004A and 3004B), along the bottom and side wall of insulating materials 3004C, as depicted.In this way at oneEmbodiment in, the second insulating materials (3004A or 3004B or both 3004A and 3004B) along insulating materials 3004C'sThe part of side wall has the top surface above at least part of the top surface 3005 of insulating materials 3004C.Implement at oneIn example, the top surface of the second insulating materials (3004A or 3004B or both 3004A and 3004B) is higher than reserved location gate electrodeThe minimum surface of 3006 a part.
With reference to Figure 30 B, on the top 3000C and side wall 3000D of upper fin portion 3000B, for example along Figure 30 A'sDirection 3008 etches reserved location gate electrode 3006.The etching process is properly termed as replacement gate process.In embodiment, it etchesOr replacement gate process is incomplete, and leaves the insulation material positioned at isolation structure 3004 of reserved location gate electrode 3006Expect the part 3012 at least part of the top surface 3005 of 3004C.
With reference to both Figure 30 A and 30B, in embodiment, the upper fin formed before forming reserved location gate electrode 3006The oxidized portion 3010 of piece part 3000B is retained during etching process, as depicted.However, in another implementationIn example, reserved location gate dielectric layer is formed before forming reserved location gate electrode 3006, and in etching reserved locationReserved location gate dielectric layer is removed after gate electrode.
With reference to Figure 30 C, abuts on the top 3000C of upper fin portion 3000B and laterally and go up fin portion 3000BSide wall 3000D formed gate dielectric layer 3014.In one embodiment, the top 3000C of upper fin portion 3000B itOn upper fin portion 3000B oxidized portion 3010 on and laterally the side wall 3000D of adjacent upper fin portion 3000B is formedGate dielectric layer 3014, as depicted.In another embodiment, it is eliminated after etching reserved location gate electrodeIn the case where the oxidized portion 3010 of upper fin portion 3000B, directly exist on the top 3000C of upper fin portion 3000BAbut on upper fin portion 3000B and laterally the side wall 3000D formation gate dielectric layer 3014 for going up fin portion 3000B.In any case, in embodiment, further in the insulation material positioned at isolation structure 3004 of reserved location gate electrode 3006Expect to form gate dielectric layer 3014 on the part 3012 on the part of the top surface 3005 of 3004C.
With reference to Figure 30 D, on the gate dielectric layer 3014 on the top 3000C of upper fin portion 3000B andThe side wall 3000D of lateral adjacent upper fin portion 3000B forms permanent gate electrode 3016.Permanent gate electrode 3016 is furtherOn part 3012 on the part of the top surface 3005 positioned at insulating materials 3004C in reserved location gate electrode 3006On gate dielectric layer 3014.
In one embodiment, forming permanent gate electrode 3016 includes forming work-function layer 3016A.As oneIn embodiment, work-function layer 3016A includes titanium and nitrogen.In another such embodiment, work-function layer 3016A include titanium, aluminium,Carbon and nitrogen.In one embodiment, forming permanent gate electrode 3016 further comprises forming conductive fill metal layer 3016B,It is formed on work-function layer 3016A.In one suchembodiment, forming conductive fill metal layer 3016B includes makingWith utilization tungsten hexafluoride (WF6) atomic layer deposition (ALD) of precursor forms the film comprising tungsten.In embodiment, permanentInsulated gate electrode cap rock 3018 is formed on gate electrode 3016.
In another aspect, some embodiments of the present disclosure include that the nothing in the gate dielectric structure for gate electrode is fixedShape high-k layer.It in other embodiments, include the high k of partly or completely holocrystalline in the gate dielectric structure for gate electrodeLayer.Wherein including in partly or completely one embodiment of the high-k layer of holocrystalline, which is ferroelectricity (FE) gridPole dielectric medium structure.Wherein including in partly or completely another embodiment of the high-k layer of holocrystalline, which isAntiferroelectric (AFE) gate dielectric structure.
In embodiment, there is described herein for increasing device ditch by using ferroelectricity or antiferroelectric gate oxideCharge in road and the method for improving subthreshold value behavior.Ferroelectricity and antiferroelectric gate oxide can increase for high currentChannel charge, and can also realize more precipitous connection behavior.
In order to provide context, ferroelectricity and antiferroelectric (FE or AFE) material based on hafnium or zirconium (Hf or Zr) are usually than allSuch as the ferroelectric material much thinner of lead zirconate titanate (PZT) etc, and as such, can be compatible with the logic technology of height scaling.FEOr there are two the performances that feature can improve logic transistor for AFE material: (1) in the channel realized by FE or AFE polarizationHigher charge, and (2) are attributed to the more precipitous connection behavior of sharp FE or AFE transformation.Such attribute can pass through increasingHigh current simultaneously reduces subthreshold swing (SS) Lai Gaijin transistor performance.
Figure 31 A instantiates the semiconductor according to an embodiment of the present disclosure with ferroelectricity or antiferroelectric gate dielectric structureThe viewgraph of cross-section of device.
With reference to Figure 31 A, integrated circuit structure 3100 includes gate structure 3102 above substrate 3104.In one embodimentIn, gate structure 3102 is above and over the semiconductor channel structure 3106 for including the monocrystal material of such as monocrystalline silicon etc.Gate structure 3102 includes gate-dielectric on semiconductor channel structure 3106 and on gate dielectric structureGate electrode.Gate-dielectric includes ferroelectricity or antiferroelectric polycrystalline material layer 3102A.Gate electrode has in ferroelectricity or antiferroelectric moreConductive layer 3102B on brilliant material layer 3102A.Conductive layer 3102B includes metal and can be barrier layer, work-function layer or mouldPlate layer, the crystallization of FE or AFE layers of enhancing.One or more grid filled layer 3102C are above conductive layer 3102B.SourcePolar region domain 3108 and drain region 3110 are on the opposite side of gate structure 3102.Source electrode or drain contact 3112 are in positionIt is electrically connected to source region 3108 and drain region 3110 at 3149, and passes through interlevel dielectric layer 3114 or gate-dielectricIn spacer portion 3116 one or two and be spaced apart with gate structure 3102.In the example of Figure 31 A, 3108 He of source regionDrain region 3110 is the region of substrate 3104.In embodiment, source electrode or drain contact 3112 include barrier layer 3112A andConductive trench fill material 3112B.In one embodiment, ferroelectricity or antiferroelectric polycrystalline material layer 3102A are along between dielectricExtend every portion 3116, as described in Figure 31 A.
In embodiment, and when applicable throughout the disclosure, ferroelectricity or antiferroelectric polycrystalline material layer 3102A are ferroelectricitiesPolycrystalline material layer.In one embodiment, ferroelectric polycrystalline material layer is the oxide for including Zr and Hf, and wherein Zr:Hf ratio is 50:50 or Zr is bigger.Ferroelectric effect can increase with the increase of orthorhombic system crystallinity.In one embodiment, ferroelectricity is moreBrilliant material layer has at least 80% orthorhombic system crystallinity.
In embodiment, and when applicable throughout the disclosure, ferroelectricity or antiferroelectric polycrystalline material layer 3102A are anti-ironElectric polycrystalline material layer.In one embodiment, antiferroelectric polycrystalline material layer is the oxide for including Zr and Hf, wherein Zr:Hf ratioIt is that 80:20 or Zr are bigger, and even as high as 100% Zr, i.e. ZrO2.In one embodiment, antiferroelectric polycrystalline material layerWith at least 80% tetragonal crystal system crystallinity.
In embodiment, and when applicable throughout the disclosure, the gate-dielectric of gate stack 3102 is further wrappedThe amorphous dielectric layer 3103 between ferroelectricity or antiferroelectric polycrystalline material layer 3102A and semiconductor channel structure 3106 is included,Such as primary silicon oxide layer, high-k dielectrics (HfOx, Al2O3Deng) or oxide and high K combination.In embodiment, andWhen applicable throughout the disclosure, ferroelectricity or antiferroelectric polycrystalline material layer 3102A have the thickness in 1 nanometer to 8 nanometers of rangeDegree.In embodiment, and when applicable throughout the disclosure, ferroelectricity or antiferroelectric polycrystalline material layer 3102A, which have, about to existGrain size in the range of 20 or more nanometers.
In embodiment, ferroelectricity or antiferroelectric polycrystalline material layer 3102A for example deposited by atomic layer deposition (ALD)Later, the layer including metal is formed in ferroelectricity or antiferroelectric polycrystalline material layer 3102A (for example, layer 3102B, such as 5-10 receiveThe titanium nitride or tantalum nitride or tungsten of rice).Then annealing is executed.In one embodiment, execute annealing up to 1 millisecond -30 minutesRange in duration.In one embodiment, annealing is executed with temperature in 500-1100 degrees Celsius of range.
Figure 31 B instantiates according to another embodiment of the present disclosure another with ferroelectricity or antiferroelectric gate dielectric structureThe viewgraph of cross-section of semiconductor device.
With reference to Figure 31 B, integrated circuit structure 3150 includes gate structure 3152 above substrate 3154.In one embodimentIn, gate structure 3152 is above and over the semiconductor channel structure 3156 for including the monocrystal material of such as monocrystalline silicon etc.Gate structure 3152 includes gate-dielectric on semiconductor channel structure 3156 and on gate dielectric structureGate electrode.Gate-dielectric includes ferroelectricity or antiferroelectric polycrystalline material layer 3152A, and may further include amorphousCompound layer 3153.Gate electrode has the conductive layer 3152B in ferroelectricity or antiferroelectric polycrystalline material layer 3152A.Conductive layer 3152BIncluding metal, and it can be barrier layer or work-function layer.One or more grid filled layer 3152C are on conductive layer 3152BOr top.The source region 3158 of the protrusion in such as region of semiconductor material different from semiconductor channel structure 3156 etcDrain region 3160 with protrusion is on the opposite side of gate structure 3152.Source electrode or drain contact 3162 are at position 3199It is electrically connected to source region 3158 and drain region 3160, and passes through interlevel dielectric layer 3164 or gate-dielectric spacer portionIn 3166 one or two and be spaced apart with gate structure 3152.In embodiment, source electrode or drain contact 3162 includeBarrier layer 3162A and conductive trench fill material 3162B.In one embodiment, ferroelectricity or antiferroelectric polycrystalline material layer 3152AExtend along dielectric spacer portion 3166, as described in Figure 31 B.
Figure 32 A instantiates the flat of multiple grid lines on a pair of of semiconductor fin according to another embodiment of the present disclosureFace view.
With reference to Figure 32 A, multiple effective grid lines 3204 are formed on multiple semiconductor fins 3200.Dummy gate electrode line3206 in the end of multiple semiconductor fins 3200.Interval 3208 between grid line 3204/3206 is that trench contact portion canTo be located at its position for sentencing the electrically conducting contact provided to source electrode or drain region, the source electrode or drain region such as source electrodeOr drain region 3251,3252,3253 and 3254.In embodiment, it the pattern of multiple grid lines 3204/3206 or multiple partly leadsThe pattern of body fin 3200 is described as cell structure.In one embodiment, grid-like patterns include with constant pitch intervalOpen and have the patterns of multiple semiconductor fins 3200 of constant width perhaps multiple grid lines 3204/3206 or the two.
Figure 32 B instantiates the viewgraph of cross-section that the a-a' axis according to an embodiment of the present disclosure along Figure 32 A intercepts.
With reference to Figure 32 B, multiple effective grid lines 3264, the semiconductor fin are formed on semiconductor fin 32623262 are formed on 3260 top of substrate.Dummy gate electrode line 3266 is in the end of semiconductor fin 3262.Dielectric layer 3270Outside dummy gate electrode line 3266.Trench contact portion material 3297 is between effective grid line 3264 and in dummy gate electrodeBetween line 3266 and effectively grid line 3264.Embedded source electrode or drain electrode structure 3268 are in semiconductor fin 3262, are havingIt imitates between grid line 3264 and between dummy gate electrode line 3266 and effectively grid line 3264.
Effective grid line 3264 includes gate dielectric structure 3272, work function gate electrode part 3274 and filling gate electrodePart 3276 and gate electrode capping layer 3278.Effective grid line 3264 and dummy gate electrode line are lining in dielectric spacer portion 32803266 side wall.In embodiment, gate dielectric structure 3272 includes ferroelectricity or antiferroelectric polycrystalline material layer 3298.At oneIn embodiment, gate dielectric structure 3272 further comprises amorphous oxide layer 3299.
In another aspect, the device with same conduction type --- such as N-type or p-type --- can have for sameThe gate electrode stack of the differentiation of one conduction type.However, for comparison purposes, the device with same conduction type can be withWith the differentiation voltage threshold (VT) based on modulation doping.
Figure 33 A instantiates a pair according to an embodiment of the present disclosure with the differentiation voltage threshold based on modulation dopingThe viewgraph of cross-section of NMOS device and a pair of of PMOS device with the differentiation voltage threshold based on modulation doping.
With reference to Figure 33 A, the first NMOS device 3302 is on semiconductor active region 3300, such as in silicon fin or substrateOn adjacent second NMOS device 3304.Both first NMOS device 3302 and the second NMOS device 3304 all include that grid electricity is situated betweenThe first gate electrode conductive layer 3308 and gate electrode conductive fill 3310 of matter layer 3306, such as work-function layer etc.In embodimentIn, the material having the same of first gate electrode conductive layer 3308 and phase of the first NMOS device 3302 and the second NMOS device 3304Same thickness, and as such, work function having the same.However, the first NMOS device 3302 has than the second NMOS device3304 lower VT.In one suchembodiment, the first NMOS device 3302 is known as " standard VT " device, and secondNMOS device 3304 is known as " high VT " device.In embodiment, by the first NMOS device 3302 and the second NMOS deviceDifferentiation VT is realized using modulation or the doping of differentiation implantation material at 3304 region 3312.
Referring again to Figure 33 A, the first PMOS device 3322 on semiconductor active region 3320, such as in silicon fin orAdjacent second PMOS device 3324 on substrate.Both first PMOS device 3322 and the second PMOS device 3324 all include gridThe first gate electrode conductive layer 3328 and gate electrode conductive fill 3330 of dielectric layer 3326, such as work-function layer etc.In realityIt applies in example, the material having the same of first gate electrode conductive layer 3328 of the first PMOS device 3322 and the second PMOS device 3324With identical thickness, and as such, work function having the same.However, the first PMOS device 3322 has than the 2nd PMOS deviceThe higher VT of part 3324.In one suchembodiment, the first PMOS device 3322 is known as " standard VT " device, and secondPMOS device 3324 is known as " low VT " device.In embodiment, by the first PMOS device 3322 and the second PMOS deviceDifferentiation VT is realized using modulation or the doping of differentiation implantation material at 3324 region 3332.
Compared with Figure 33 A, Figure 33 B instantiates having based on differentiation gate electrode knot according to another embodiment of the present disclosureA pair of of NMOS device of the differentiation voltage threshold of structure and with the differentiation voltage threshold based on differentiation gate electrode structureA pair of of PMOS device viewgraph of cross-section.
With reference to Figure 33 B, the first NMOS device 3352 is on semiconductor active region 3350, such as in silicon fin or substrateOn adjacent second NMOS device 3354.Both first NMOS device 3352 and the second NMOS device 3354 all include that grid electricity is situated betweenMatter layer 3356.However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stack.Particularly, the first NMOS device 3352 includes the first gate electrode conductive layer 3358 and gate electrode of such as first work-function layer etcConductive fill 3360.The second gate electrode conducting layer 3359 of second NMOS device 3354 including such as second work-function layer etc,First gate electrode conductive layer 3358 and gate electrode conductive fill 3360.First NMOS device 3352 has than the second NMOS device3354 lower VT.In one suchembodiment, the first NMOS device 3352 is known as " standard VT " device, and secondNMOS device 3354 is known as " high VT " device.In embodiment, by using differentiation grid for same conduction type deviceIt stacks to realize differentiation VT.
Referring again to Figure 33 B, the first PMOS device 3372 on semiconductor active region 3370, such as in silicon fin orAdjacent second PMOS device 3374 on substrate.Both first PMOS device 3372 and the second PMOS device 3374 all include gridDielectric layer 3376.However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrodeIt stacks.Particularly, the first PMOS device 3372 includes the gate electrode conductive layer with first thickness of such as work-function layer etc3378A and gate electrode conductive fill 3380.Second PMOS device 3374 includes the gate electrode conductive layer 3378B with second thicknessWith gate electrode conductive fill 3380.In one embodiment, gate electrode conductive layer 3378A and gate electrode conductive layer 3378B haveIdentical composition, but thickness (of the thickness (second thickness) of gate electrode conductive layer 3378B than gate electrode conductive layer 3378AOne thickness) it is bigger.First PMOS device 3372 has than the higher VT of the second PMOS device 3374.In such embodimentIn, the first PMOS device 3372 is known as " standard VT " device, and the second PMOS device 3374 is known as " low VT " device.ImplementingIn example, by realizing differentiation VT using differentiation gate stack for same conduction type device.
Referring again to Figure 33 B, in accordance with an embodiment of the present disclosure, integrated circuit structure includes fin (for example, silicon fin, allAs 3350).It is to be appreciated that the fin have top (as shown in the figure) and side wall (into the page neutralization leave the page itOutside).Gate dielectric layer 3356 is on the top of fin and laterally abuts the side wall of fin.The N-type grid of device 3354Electrode is on the gate dielectric layer 3356 on the top of fin and laterally abuts the side wall of fin.N-type gate electrodeIncluding the p-type metal layer 3359 on gate dielectric layer 3356 and the N-type metal layer 3358 on p-type metal layer 3359.Such asIt will be appreciated that, the first N-type source or drain region can abut the first side (for example, into the page in) of gate electrode, andSecond N-type source or drain region can abut second side (for example, leaving except the page) of gate electrode, second side and the first sideRelatively.
In one embodiment, p-type metal layer 3359 includes titanium and nitrogen, and N-type metal layer 3358 includes titanium, aluminium, carbonAnd nitrogen.In one embodiment, p-type metal layer 3359 has the thickness in 2-12 angstroms of range, and in specific embodimentIn, p-type metal layer 3359 has the thickness in 2-4 angstroms of range.In one embodiment, N-type gate electrode further comprisesConductive fill metal layer 3360 on N-type metal layer 3358.In one suchembodiment, conductive fill metal layer 3360Including tungsten.In certain embodiments, conductive fill metal layer 3360 includes the tungsten and 0.1 to 2 of 95 or more thick atom percentageThe fluorine of atomic percent.
Referring again to Figure 33 B, according to another embodiment of the present disclosure, integrated circuit structure includes having voltage threshold (VT)The first N-type device 3352, the first N-type device 3352 has first grid dielectric layer 3356 and in first grid dielectric layerThe first N-type metal layer 3358 on 3356.Also included is the second N-type device 3354 with voltage threshold (VT), the second N-typeDevice 3354 have second grid dielectric layer 3356, the p-type metal layer 3359 on second grid dielectric layer 3356 andThe second N-type metal layer 3358 on p-type metal layer 3359.
In one embodiment, wherein the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352.At oneIn embodiment, the first N-type metal layer 3358 and the composition having the same of the second N-type metal layer 3358.In one embodiment,One N-type metal layer 3358 and the thickness having the same of the second N-type metal layer 3358.In one embodiment, wherein N-type metal layer3358 include titanium, aluminium, carbon and nitrogen, and p-type metal layer 3359 includes titanium and nitrogen.
Referring again to Figure 33 B, in accordance with an embodiment of the present disclosure, integrated circuit structure includes the with voltage threshold (VT)One P-type device 3372, the first P-type device 3372 have first grid dielectric layer 3376 and in first grid dielectric layers 3376On the first p-type metal layer 3378A.First p-type metal layer 3378A has a thickness.It further include the second P-type device 3374, andAnd it is with voltage threshold (VT).Second P-type device 3374 has second grid dielectric layer 3376 and is situated between in second grid electricityThe second p-type metal layer 3378B on matter layer 3376.Second p-type metal layer 3378B has thicker than the first p-type metal layer 3378ASpend bigger thickness.
In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372.Implement at oneIn example, the first p-type metal layer 3378A and the second p-type metal layer 3378B composition having the same.In one embodiment, firstBoth p-type metal layer 3378A and the second p-type metal layer 3378B include titanium and nitrogen.In one embodiment, the first p-type metalThe work function saturation thickness of material of the thickness less than the first p-type metal layer 3378A of layer 3378A.In one embodiment, althoughDo not describe, but the second p-type metal layer 3378B includes the first metal in the second metal film (for example, from first deposition)Film (for example, from second deposition), and a gap is between the first metal film and the second metal film.
Referring again to Figure 33 B, according to another embodiment of the present disclosure, integrated circuit structure includes the first N-type device 3352,First N-type device 3352 has first grid dielectric layer 3356 and the first N-type gold on first grid dielectric layer 3356Belong to layer 3358.Second N-type device 3354 has second grid dielectric layer 3356, the on second grid dielectric layer 3356One p-type metal layer 3359 and the second N-type metal layer 3358 on the first p-type metal layer 3359.First P-type device 3372 toolThere are third gate dielectric layer 3376 and the second P-type grid electrode layer 3378A on third gate dielectric layer 3376.Second p-typeMetal layer 3378A has a thickness.Second P-type device 3374 has the 4th gate dielectric layer 3376 and is situated between in the 4th grid electricityThird P-type grid electrode layer 3378B on matter layer 3376.Third p-type metal layer 3378B has thicker than the second p-type metal layer 3378ASpend bigger thickness.
In one embodiment, the first N-type device 3352 has voltage threshold (VT), and the second N-type device 3354 has electricityIt presses threshold value (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352.In one embodiment, firstP-type device 3372 has voltage threshold (VT), and the second P-type device 3374 has voltage threshold (VT), and the second P-type device3374 VT is lower than the VT of the first P-type device 3372.In one embodiment, third p-type metal layer 3378B is included in the second gold medalBelong to the first metal film on film and the gap between the first metal film and the second metal film.
It is to be appreciated that can include for the more of same conduction type in same structure, such as on same tube coreIn two kinds of VT device.In the first example, Figure 34 A instantiates according to an embodiment of the present disclosure with based on differentiationGate electrode structure and one group of three NMOS device of the differentiation voltage threshold based on modulation doping and have be based on differentiationThe viewgraph of cross-section of one group of three PMOS device of gate electrode structure and the differentiation voltage threshold based on modulation doping.
With reference to Figure 34 A, the first NMOS device 3402 is on semiconductor active region 3400, such as in silicon fin or substrateOn adjacent second NMOS device 3404 and third NMOS device 3403.First NMOS device 3402, the second NMOS device 3404It include gate dielectric layer 3406 with third NMOS device 3403.First NMOS device 3402 and third NMOS device 3403 haveThe same or similar gate electrode stack in structure.However, the second NMOS device 3404 have with the first NMOS device 3402 andThe structurally different gate electrode stack of third NMOS device 3403.Particularly, the first NMOS device 3402 and the 3rd NMOS devicePart 3403 includes the first gate electrode conductive layer 3408 and gate electrode conductive fill 3410 of such as first work-function layer etc.SecondNMOS device 3404 includes the second gate electrode conducting layer 3409, first gate electrode conductive layer of such as second work-function layer etc3408 and gate electrode conductive fill 3410.First NMOS device 3402 has than the lower VT of the second NMOS device 3404.OneIn a such embodiment, the first NMOS device 3402 is known as " standard VT " device, and the second NMOS device 3404 is known as " heightVT " device.In embodiment, by realizing differentiation VT using differentiation gate stack for same conduction type device.In embodiment, third NMOS device 3403 has different from the VT of the first NMOS device 3402 and the second NMOS device 3404VT, even if the gate electrode structure of third NMOS device 3403 is identical as the gate electrode structure of the first NMOS device 3402.At oneIn embodiment, the VT of third NMOS device 3403 is between the first NMOS device 3402 and the VT of the second NMOS device 3404.?In embodiment, by realizing the using modulation or the doping of differentiation implantation material at the region of third NMOS device 3,403 3412Differentiation VT between three NMOS devices 3403 and the first NMOS device 3402.In one suchembodiment, third N-type devicePart 3403 has the channel region containing the concentration of dopant different from the concentration of dopant of channel region of the first N-type device 3402Domain.
Referring again to Figure 34 A, the first PMOS device 3422 on semiconductor active region 3420, such as in silicon fin orAdjacent second PMOS device 3424 and third PMOS device 3423 on substrate.First PMOS device 3422, the second PMOS device3424 and third PMOS device 3423 include gate dielectric layer 3426.First PMOS device 3422 and third PMOS device 3423With gate electrode stack the same or similar in structure.However, the second PMOS device 3424 has and the first PMOS device3422 and the structurally different gate electrode stack of third PMOS device 3423.Particularly, the first PMOS device 3422 and thirdPMOS device 3423 includes the gate electrode conductive layer 3428A and gate electrode with first thickness of such as work-function layer etc conductiveFilling 3430.Second PMOS device 3424 includes the gate electrode conductive layer 3428B and gate electrode conductive fill with second thickness3430.In one embodiment, gate electrode conductive layer 3428A and gate electrode conductive layer 3428B composition having the same, but gridThickness (first thickness) of the thickness (second thickness) of electrode conducting layer 3428B than gate electrode conductive layer 3428A is bigger.ImplementingIn example, the first PMOS device 3422 has than the higher VT of the second PMOS device 3424.In one suchembodiment, firstPMOS device 3422 is known as " standard VT " device, and the second PMOS device 3424 is known as " low VT " device.In embodiment, lead toIt crosses and realizes differentiation VT using differentiation gate stack for same conduction type device.In embodiment, the 3rd PMOS devicePart 3423 has the VT different from the VT of the first PMOS device 3422 and the second PMOS device 3424, even if third PMOS device3423 gate electrode structure is identical as the gate electrode structure of the first PMOS device 3422.In one embodiment, the 3rd PMOS deviceThe VT of part 3423 is between the first PMOS device 3422 and the VT of the second PMOS device 3424.In embodiment, by thirdThird PMOS device 3423 and the are realized using modulation or the doping of differentiation implantation material at the region 3432 of PMOS device 3423Differentiation VT between one PMOS device 3422.In one suchembodiment, third P-type device 3423 has containing with theThe channel region of the different concentration of dopant of the concentration of dopant of the channel region of one P-type device 3422.
In the second example, Figure 34 B instantiates having based on differentiation gate electrode according to another embodiment of the present disclosureStructure and one group of three NMOS device of the differentiation voltage threshold based on modulation doping and have be based on differentiation gate electrodeThe viewgraph of cross-section of structure and one group of three PMOS device of the differentiation voltage threshold based on modulation doping.
With reference to Figure 34 B, the first NMOS device 3452 is on semiconductor active region 3450, such as in silicon fin or substrateOn adjacent second NMOS device 3454 and third NMOS device 3453.First NMOS device 3452, the second NMOS device 3454It include gate dielectric layer 3456 with third NMOS device 3453.Second NMOS device 3454 and third NMOS device 3453 haveThe same or similar gate electrode stack in structure.However, the first NMOS device 3452 have with the second NMOS device 3454 andThe structurally different gate electrode stack of third NMOS device 3453.Particularly, the first NMOS device 3452 includes such as firstThe first gate electrode conductive layer 3458 and gate electrode conductive fill 3460 of work-function layer etc.Second NMOS device 3454 and thirdNMOS device 3453 includes the second gate electrode conducting layer 3459, first gate electrode conductive layer of such as second work-function layer etc3458 and gate electrode conductive fill 3460.First NMOS device 3452 has than the lower VT of the second NMOS device 3454.OneIn a such embodiment, the first NMOS device 3452 is known as " standard VT " device, and the second NMOS device 3454 is known as " heightVT " device.In embodiment, by realizing differentiation VT using differentiation gate stack for same conduction type device.In embodiment, third NMOS device 3453 has different from the VT of the first NMOS device 3452 and the second NMOS device 3454VT, even if the gate electrode structure of third NMOS device 3453 is identical as the gate electrode structure of the second NMOS device 3454.At oneIn embodiment, the VT of third NMOS device 3453 is between the first NMOS device 3452 and the VT of the second NMOS device 3454.?In embodiment, by realizing the using modulation or the doping of differentiation implantation material at the region of third NMOS device 3,453 3462Differentiation VT between three NMOS devices 3453 and the second NMOS device 3454.In one suchembodiment, third N-type devicePart 3453 has the channel region containing the concentration of dopant different from the concentration of dopant of channel region of the second N-type device 3454Domain.
Referring again to Figure 34 B, the first PMOS device 3472 on semiconductor active region 3470, such as in silicon fin orAdjacent second PMOS device 3474 and third PMOS device 3473 on substrate.First PMOS device 3472, the second PMOS device3474 and third PMOS device 3473 include gate dielectric layer 3476.Second PMOS device 3474 and third PMOS device 3473With gate electrode stack the same or similar in structure.However, the first PMOS device 3472 has and the second PMOS device3474 and the structurally different gate electrode stack of third PMOS device 3473.Particularly, the first PMOS device 3472 includes allSuch as the gate electrode conductive layer 3478A and gate electrode conductive fill 3480 with first thickness of work-function layer etc.2nd PMOSDevice 3474 and third PMOS device 3473 include the gate electrode conductive layer 3478B and gate electrode conductive fill with second thickness3480.In one embodiment, gate electrode conductive layer 3478A and gate electrode conductive layer 3478B composition having the same, but gridThickness (first thickness) of the thickness (second thickness) of electrode conducting layer 3478B than gate electrode conductive layer 3478A is bigger.ImplementingIn example, the first PMOS device 3472 has than the higher VT of the second PMOS device 3474.In one suchembodiment, firstPMOS device 3472 is known as " standard VT " device, and the second PMOS device 3474 is known as " low VT " device.In embodiment, lead toIt crosses and realizes differentiation VT using differentiation gate stack for same conduction type device.In embodiment, the 3rd PMOS devicePart 3473 has the VT different from the VT of the first PMOS device 3472 and the second PMOS device 3474, even if third PMOS device3473 gate electrode structure is identical as the gate electrode structure of the second PMOS device 3474.In one embodiment, the 3rd PMOS deviceThe VT of part 3473 is between the first PMOS device 3472 and the VT of the second PMOS device 3474.In embodiment, by thirdThird PMOS device 3473 and the are realized using modulation or the doping of differentiation implantation material at the region 3482 of PMOS device 3473Differentiation VT between one PMOS device 3472.In one suchembodiment, third P-type device 3473 has containing with theThe channel region of the different concentration of dopant of the concentration of dopant of the channel region of two P-type devices 3474.
Figure 35 A-35D, which instantiates manufacture according to another embodiment of the present disclosure, to be had based on differentiation gate electrode structureThe viewgraph of cross-section of various operations in the method for the NMOS device of differentiation voltage threshold.
With reference to Figure 35 A, wherein region " standard VT NMOS " (STD VT NMOS) and " high VT NMOS " region (HIGH VTNMOS it) is shown as the bifurcated on common substrate, the method for manufacturing integrated circuit structure is included in the first semiconductor fin 3502On and on the second semiconductor fin 3504, such as on the first and second silicon fins form gate dielectric layer3506.It is formed on gate dielectric layer 3506 on the first semiconductor fin 3502 and on the second semiconductor fin 3504P-type metal layer 3508.
With reference to Figure 35 B, p-type metal layer 3508 is removed from the gate dielectric layer 3506 on the first semiconductor fin 3502A part, but a part 3509 of p-type metal layer 3508 be retained in the grid electricity on the second semiconductor fin 3504 JieOn matter layer 3506.
With reference to Figure 35 C, on the gate dielectric layer 3506 on the first semiconductor fin 3502 and in the second semiconductorN-type metal layer 3510 is formed on the part 3509 of the p-type metal layer on gate dielectric layer 3506 on fin 3504.In realityIt applies in example, subsequent processing includes the first N-type device for being formed on the first semiconductor fin 3502 and having voltage threshold (VT),And the second N-type device with voltage threshold (VT) is formed on the second semiconductor fin 3504, wherein the second N-type deviceVT be higher than the first N-type device VT.
With reference to Figure 35 D, in embodiment, conductive fill metal layer 3512 is formed on N-type metal layer 3510.One thisIn the embodiment of sample, forming conductive fill metal layer 3512 includes using to utilize tungsten hexafluoride (WF6) precursor atomic layer deposition(ALD) film comprising tungsten is formed.
Figure 36 A-36D, which instantiates manufacture according to another embodiment of the present disclosure, to be had based on differentiation gate electrode structureThe viewgraph of cross-section of various operations in the method for the PMOS device of differentiation voltage threshold.
With reference to Figure 36 A, wherein region " standard VT PMOS " (STD VT PMOS) and " low VT PMOS " region (LOW VTPMOS it) is shown as the bifurcated on common substrate, the method for manufacturing integrated circuit structure is included in the first semiconductor fin 3602On and on the second semiconductor fin 3604, such as on the first and second silicon fins form gate dielectric layer3606.It is formed on gate dielectric layer 3606 on the first semiconductor fin 3602 and on the second semiconductor fin 3604First p-type metal layer 3608.
With reference to Figure 36 B, the first p-type metal layer is removed from the gate dielectric layer 3606 on the first semiconductor fin 36023608 a part, but a part 3609 of the first p-type metal layer 3608 is retained on the second semiconductor fin 3604On gate dielectric layer 3606.
With reference to Figure 36 C, on the gate dielectric layer 3606 on the first semiconductor fin 3602 and in the second semiconductorThe second p-type metal layer is formed on the part 3609 of the first p-type metal layer on gate dielectric layer 3606 on fin 36043610.In embodiment, subsequent processing includes the formed on the first semiconductor fin 3602 with voltage threshold (VT)One P-type device, and second P-type device with voltage threshold (VT) is formed on the second semiconductor fin 3604, whereinThe VT of second P-type device is lower than the VT of the first P-type device.
In one embodiment, the first p-type metal layer 3608 and the composition having the same of the second p-type metal layer 3610.?In one embodiment, the first p-type metal layer 3608 and the thickness having the same of the second p-type metal layer 3610.In one embodimentIn, the first p-type metal layer 3608 and the thickness having the same of the second p-type metal layer 3610 and identical composition.Implement at oneIn example, gap 3611 is between the first p-type metal layer 3608 and the second p-type metal layer 3610, as depicted.
With reference to Figure 36 D, in embodiment, conductive fill metal layer 3612 is formed on p-type metal layer 3610.At oneIn such embodiment, forming conductive fill metal layer 3612 includes using to utilize tungsten hexafluoride (WF6) precursor atomic layer deposition(ALD) is accumulated to form the film comprising tungsten.In one embodiment, in p-type metal before forming conductive fill metal layer 3612N-type metal layer 3614 is formed on layer 3610, as depicted.In one suchembodiment, N-type metal layer 3614 isThe product of double-metal grid alternate process scheme.
In another aspect, the metal gates for complementary metal oxide semiconductor (CMOS) semiconductor devices are describedStructure.In this example, Figure 37 instantiates the cross section view of the integrated circuit structure according to an embodiment of the present disclosure with P/N knotFigure.
With reference to Figure 37, integrated circuit structure 3700 includes the semiconductor substrate with N well region 3704 and p-well region 37083702, the N well region 3704 has from wherein the first semiconductor fin 3706 outstanding, and the p-well region 3708 hasHave from wherein the second semiconductor fin 3710 outstanding.First semiconductor fin 3706 and the second semiconductor fin 3710 are spacedIt opens.N well region 3704 is directly adjacent with p-well region 3708 in semiconductor substrate 3702.Groove isolation construction 3712 is partly being ledOn structure base board 3702, between the first semiconductor fin 3706 and 3710 outside of the second semiconductor fin and its.First semiconductorFin 3706 and the second semiconductor fin 3710 extend above groove isolation construction 3712.
Gate dielectric layer 3714 is in the first semiconductor fin 3706 and the second semiconductor fin 3710 and in grooveOn isolation structure 3712.Gate dielectric layer 3714 connects between the first semiconductor fin 3706 and the second semiconductor fin 3710It is continuous.Conductive layer 3716 is located on the first semiconductor fin 3706 still the not grid on the second semiconductor fin 3710On dielectric layer 3714.In one embodiment, conductive layer 3716 includes titanium, nitrogen and oxygen.P-type metal gate layers 3718 are located atOn the first semiconductor fin 3706 but not on the conductive layer 3716 on the second semiconductor fin 3710.P-type goldBelong to groove isolation construction 3712 of the grid layer 3718 also between the first semiconductor fin 3706 and the second semiconductor fin 3710A part on but and it is not all on.N-shaped metal gate layers 3720 on the second semiconductor fin 3710, in the first semiconductorOn groove isolation construction 3712 between fin 3706 and the second semiconductor fin 3710 and in p-type metal gate layersOn 3718.
In one embodiment, interlayer dielectric (ILD) layer 3722 is in the first semiconductor fin 3706 and the second half and leads3712 top of groove isolation construction on the outside of body fin 3710.ILD layer 3722 has opening 3724,3724 exposure the of openingSemiconductor fin 3706 and the second semiconductor fin 3710.In one suchembodiment, further along opening 3724Side wall 3726 form conductive layer 3716, p-type metal gate layers 3718 and N-shaped metal gate layers 3720, as depicted.In certain embodiments, conductive layer 3716 has top surface 3717 along the side wall 3726 of opening 3724, along openingThe top surface 3719 of the p-type gate metal layer 3718 of 3724 side wall 3726 and the top surface of N-shaped metal gate layers 37203721 lower sections, as depicted.
In one embodiment, p-type metal gate layers 3718 include titanium and nitrogen.In one embodiment, N-shaped metal gatesLayer 3720 includes titanium and aluminium.In one embodiment, conductive fill metal layer 3730 is on N-shaped metal gate layers 3720, such asDepicted in.In one suchembodiment, conductive fill metal layer 3730 includes tungsten.In certain embodiments,Conductive fill metal layer 3730 include 95 or more thick atom percentage tungsten and 0.1 to 2 atomic percent fluorine.Implement at oneIn example, gate dielectric layer 3714 has the layer including hafnium and oxygen.In one embodiment, thermal oxide layer or chemical oxideLayer 3732 is between the first semiconductor fin 3706 and the top of the second semiconductor fin 3710, as depicted.OneIn a embodiment, semiconductor substrate 3702 is blocky silicon semiconductor substrate.
Now only with reference to the right-hand side of Figure 37, in accordance with an embodiment of the present disclosure, integrated circuit structure includes semiconductor substrate3702, semiconductor substrate 3702 includes with the N well region 3704 from wherein semiconductor fin 3706 outstanding.Trench isolations knotStructure 3712 is around semiconductor fin 3706 on semiconductor substrate 3702.Semiconductor fin 3706 is in groove isolation construction3712 tops extend.Gate dielectric layer 3714 is on semiconductor fin 3706.Conductive layer 3716 is in semiconductor fin 3706On gate dielectric layer 3714 on.In one embodiment, conductive layer 3716 includes titanium, nitrogen and oxygen.P-type metal gatesLayer 3718 is on the conductive layer 3716 on semiconductor fin 3706.
In one embodiment, interlayer dielectric (ILD) layer 3722 is above groove isolation construction 3712.ILD layer hasOpening, opening exposure semiconductor fin 3706.Conductive layer 3716 and p-type metal gate are formed further along the side wall of the openingPole layer 3718.In one suchembodiment, conductive layer 3716 has top surface along the side wall of opening, along openingSide wall p-type metal gate layers 3718 top surface below.In one embodiment, p-type metal gate layers 3718 are in conductionOn layer 3716.In one embodiment, p-type metal gate layers 3718 include titanium and nitrogen.In one embodiment, conductive fill goldBelong to layer 3730 on p-type metal gate layers 3718.In one suchembodiment, conductive fill metal layer 3730 includesTungsten.In specific such embodiment, conductive fill metal layer 3730 is by 95 or the tungsten and 0.1 to 2 of more thick atom percentageThe fluorine of atomic percent forms.In one embodiment, gate dielectric layer 3714 includes the layer with hafnium and oxygen.
Figure 38 A-38H is instantiated according to an embodiment of the present disclosure to be made using double-metal grid replacement gate process flowMake the viewgraph of cross-section of the various operations in the method for integrated circuit structure.
With reference to showing NMOS(N type) region and PMOS(P type) region Figure 38 A, the method for manufacturing integrated circuit structureIt is included in 3800 top of substrate and forms interlayer dielectric above the first semiconductor fin 3804 and the second semiconductor fin 3806(ILD) layer 3802.Opening 3808,3808 the first semiconductor fins 3804 of exposure of opening and the second half are formed in ILD layer 3802Conductor fin 3806.In one embodiment, by removing initially in the first semiconductor fin 3804 and the second semiconductor finAppropriate position grid reserved location or dummy gate electrode structure on 3806 form opening 3808.
In opening 3808 and on the first semiconductor fin 3804 and the second semiconductor fin 3806 and in ditchRecess isolating structure 3812 is formed in a part between the first semiconductor fin 3804 and the second semiconductor fin 3806Gate dielectric layer 3810.In one embodiment, in the thermal oxide or chemistry of such as silica or silicon dioxide layer etcForm gate dielectric layer 3810 on oxide skin(coating) 3811, the thermal oxide or chemical oxide layer 3811 are led the first halfIt is formed on body fin 3804 and the second semiconductor fin 3806, as depicted.In another embodiment, directlyGate dielectric layer 3810 is formed on semiconductor fin 3804 and the second semiconductor fin 3806.
In the gate dielectric layer 3810 being formed on the first semiconductor fin 3804 and the second semiconductor fin 3806On formed conductive layer 3814.In one embodiment, conductive layer 3814 includes titanium, nitrogen and oxygen.It is being formed in the first semiconductorP-type metal gate layers are formed on fin 3804 and on the conductive layer 3814 that is formed on the second semiconductor fin 38063816。
With reference to Figure 38 B, dielectric etch stop layer 3818 is formed in p-type metal gate layers 3816.In one embodimentIn, dielectric etch stop layer 3818 includes the first silicon oxide layer (for example, SiO2), the alumina layer on the first silicon oxide layer(for example, Al2O3) and the second silicon oxide layer on alumina layer (for example, SiO2).
With reference to Figure 38 C, mask 3820 is formed on the structure of Figure 38 B.Mask 3820 covers PMOS area and exposureNMOS area.
With reference to Figure 38 D, figure is carried out to dielectric etch stop layer 3818, p-type metal gate layers 3816 and conductive layer 3814Case is to provide on the first semiconductor fin 3804 but not on the second semiconductor fin 3806 in patternedConductive layer 3815 on patterned dielectric etch stop layer 3819, patterned p-type metal gate layers 3817.In embodiment, conductive layer 3814 protects the second semiconductor fin 3806 during patterning.
With reference to Figure 38 E, mask 3820 is removed from the structure of Figure 38 D.With reference to Figure 38 F, warp is removed from the structure of Figure 38 EPatterned dielectric etch stop layer 3819.
With reference to Figure 38 G, the first semiconductor is on the second semiconductor fin 3806, in groove isolation construction 3812On part between fin 3804 and the second semiconductor fin 3806 and patterned p-type metal gate layers 3817 itUpper formation N-shaped metal gate layers 3822.In embodiment, the side wall 3824 further along opening 3808 is formed patternedConductive layer 3815, patterned p-type metal gate layers 3817 and N-shaped metal gate layers 3822.In such embodimentIn, patterned conductive layer 3815 has top surface along the side wall 3824 of opening 3808, in the side along opening 3808Below the top surface of the patterned p-type gate metal layer 3817 of wall 3824 and the top surface of N-shaped metal gate layers 3822.
With reference to Figure 38 H, conductive fill metal layer 3826 is formed on N-shaped metal gate layers 3822.In one embodimentIn, by using utilization tungsten hexafluoride (WF6) atomic layer deposition (ALD) of precursor forms conduction and fill out to deposit the film comprising tungstenFill metal layer 3826.
In another aspect, the dual silicide for complementary metal oxide semiconductor (CMOS) semiconductor devices is describedStructure.As exemplary process flow, Figure 39 A-39H instantiates expression manufacture according to an embodiment of the present disclosure based on double silicationThe viewgraph of cross-section of various operations in the method for the integrated circuit of object.
With reference to Figure 39 A, wherein NMOS area and PMOS area are shown as the bifurcated on common substrate, manufacture integrated circuitThe method of structure includes the formation first grid structure 3902 on first fin 3904 of such as first silicon fin etc, canTo include dielectric sidewall spacers portion 3903.Second grid is formed on second fin 3954 of such as second silicon fin etcStructure 3952 may include dielectric sidewall spacers portion 3953.On the first fin 3904 with first grid structure 3902It is adjacent to and is adjacent to form insulating materials 3906 with second grid structure 3952 on the second fin 3954.In a realityIt applies in example, insulating materials 3906 is expendable material, and is used as the mask during dual silicide.
With reference to Figure 39 B, insulating materials 3906 is removed on the first fin 3904 but not on the second fin 3954First part, with the first source electrode of exposure first fin 3904 adjacent with first grid structure 3902 or drain region 3908With the second source electrode or drain region 3910.In embodiment, the first source electrode or drain region 3908 and the second source electrode or drain regionDomain 3910 is the epitaxial region formed in the depressed section of the first fin 3904, as depicted.As oneIn embodiment, the first source electrode or drain region 3908 and the second source electrode or drain region 3910 include silicon and germanium.
With reference to Figure 39 C, in the first source electrode of the first fin 3904 or drain region 3908 and the second source electrode or drain regionThe first metal silicide layer 3912 is formed on 3910.In one embodiment, the first metal silication is formed by following stepsNitride layer 3912: deposition includes the layer of nickel and platinum, the layer for including nickel and platinum is annealed and removed in the structure of Figure 39 BThe unreacted part of layer including nickel and platinum.
Insulation material is removed on the second fin 3954 after forming the first metal silicide layer 3912 with reference to Figure 39 DThe second part of material 3906 is with the third source electrode of exposure second fin 3954 adjacent with second grid structure 3952 or drain regionDomain 3958 and the 4th source electrode or drain region 3960.In embodiment, in the second fin 3954, such as in the second silicon finThird source electrode or drain region 3958 and the 4th source electrode or drain region 3960 are formed, as depicted.However anotherIn embodiment, third source electrode or drain region 3958 and the 4th source electrode or drain region 3960 are the recess in the second fin 3954The epitaxial region formed in part.In one suchembodiment, third source electrode or drain region 3958 and the 4th source electrode orDrain region 3960 includes silicon.
With reference to Figure 39 E, in the structure of Figure 39 D, i.e. in the first source electrode or drain region 3908, the second source electrode or drain regionThe first metal layer 3914 is formed on domain 3910, third source electrode or drain region 3958 and the 4th source electrode or drain region 3960.SoThe second gold medal is formed on the third source electrode of the second fin 3954 or drain region 3958 and the 4th source electrode or drain region 3960 afterwardsBelong to silicide layer 3962.Such as the second metal silicide layer 3962 is formed from the first metal layer 3914 using annealing process.?In embodiment, the second metal silicide layer 3962 is upper different from the first metal silicide layer 3912 in composition.In one embodimentIn, the first metal layer 3914 is or including titanium layer.In one embodiment, the first metal layer 3914 is formed conformal metalLayer, for example, it is conformal with the open channel of Figure 39 D, as depicted.
With reference to Figure 39 F, in embodiment, make the recess of the first metal layer 3914 with the first source electrode or drain region 3908,It is each in second source electrode or drain region 3910, third source electrode or drain region 3958 and the 4th source electrode or drain region 3960A top forms U-shaped metal layer 3916.
With reference to Figure 39 G, in embodiment, second metal layer is formed on the U-shaped metal layer 3916 of the structure of Figure 39 F3918.In embodiment, second metal layer 3918 is upper different from U-shaped metal layer 3916 in composition.
With reference to Figure 39 H, in embodiment, third metal layer is formed in the second metal layer 3918 of the structure of Figure 39 G3920.In embodiment, third metal layer 3920 has composition identical with U-shaped metal layer 3916.
Referring again to Figure 39 H, in accordance with an embodiment of the present disclosure, integrated circuit structure 3900 includes the p-type above substrateSemiconductor devices (PMOS).The P-type semiconductor device includes the first fin 3904, such as the first silicon fin.It is to be appreciated that theOne fin has top (being shown as 3904A) and side wall (for example, the neutralization into the page is left except the page).First grid electricityPole 3902 includes the first grid on the top 3904A of the first fin 3904 and laterally abutting the side wall of the first fin 3904Dielectric layer, and including on the first grid dielectric layer on the top 3904A of the first fin 3904 and lateral adjacentConnect the first gate electrode of the side wall of the first fin 3904.First gate electrode 3902 have the first side 3902A and with the first side 3902AOpposite second side 3902B.
First and second semiconductor source electrodes or drain region 3908 and 3910 abut the first of first gate electrode 3902 respectivelySide 3902A and second side 3902B.First and second groove interface constructions 3930 and 3932 are respectively in the first and second semiconductor sourcesOn pole or drain region 3908 and 3910, the first side 3902A and second side 3902B of adjacent first gate electrode 3902.FirstMetal silicide layer 3912 is respectively directly in the first and second groove interface constructions 3930 and 3932 and the first and second semiconductorsBetween source electrode or drain region 3908 and 3910.
Integrated circuit structure 3900 includes the N-type semiconductor device (NMOS) above substrate.The N-type semiconductor device packetInclude the second fin 3954, such as the second silicon fin.It is to be appreciated that the second fin has top (being shown as 3954A) and sideWall (for example, the neutralization into the page is left except the page).Second gate electrode 3952 includes at the top of the second fin 3954The second grid dielectric layer of the side wall of the second fin 3954 on 3954A and is laterally abutted, and is included in the second finOn second grid dielectric layer on 3954 top 3954A and laterally abut the second gate of the side wall of the second fin 3954Electrode.Second gate electrode 3952 has the first side 3952A and second side 3952B opposite with the first side 3952A.
Third and fourth semiconductor source electrode or drain region 3958 and 3960 abut the first of the second gate electrode 3952 respectivelySide 3952A and second side 3952B.Third and fourth groove interface construction 3970 and 3972 is respectively in the third and fourth semiconductor sourceOn pole or drain region 3958 and 3960, the first side 3952A and second side 3952B of adjacent second gate electrode 3952.SecondMetal silicide layer 3962 is respectively directly in the third and fourth groove interface construction 3970 and 3972 and the third and fourth semiconductorBetween source electrode or drain region 3958 and 3960.In embodiment, the first metal silicide layer 3912 includes being not included in theAt least one of two metal silicide layers 3962 metal species.
In one embodiment, the second metal silicide layer 3962 includes titanium and silicon.First metal silicide layer 3912 packetInclude nickel, platinum and silicon.In one embodiment, the first metal silicide layer 3912 further comprises germanium.In one embodiment,One metal silicide layer 3912 further comprises titanium, for example, such as then forming the second metallic silicon with the first metal layer 3914It is incorporated into during compound layer 3962 in first metal silicide layer 3912.In one suchembodiment, further by moving backFiery process modifies the silicide layer formed on pmos source or drain region, and the annealing process is used in the source NMOSSilicide regions are formed on pole or drain region.This can obtain having whole metal silicides on pmos source or drain regionPercentage fractional silicide layer.However, in other embodiments, not changed by annealing process or not passed through generallyAnnealing process changes such silicide layer formed on pmos source or drain region, and the annealing process is used forSilicide regions are formed on NMOS source or drain region.
In one embodiment, the first and second semiconductor source electrodes or drain region 3908 and 3910 be include silicon and germaniumFirst and second embedded semiconductor source electrodes or drain region.In one suchembodiment, the third and fourth semiconductor sourcePole or drain region 3958 and 3960 are the third and fourth embedded semiconductor source electrode or the drain region for including silicon.In another realityIt applies in example, the third and fourth semiconductor source electrode or drain region 3958 and 3960 are formed in fin 3954, rather than embeddedEpitaxial region.
In embodiment, the first, second, third and fourth groove interface construction 3930,3932,3970 and 3972 is allIncluding U-shaped metal layer 3916 and on entire U-shaped metal layer 3916 and the T shape metal layer 3918 of top.In one embodimentIn, U-shaped metal layer 3916 includes titanium, and T shape metal layer 3918 includes cobalt.In one embodiment, first, second, thirdIt all further comprise the third on T shape metal layer 3918 with the 4th groove interface construction 3930,3932,3970 and 3972Metal layer 3920.In one embodiment, third metal layer 3920 and the composition having the same of U-shaped metal layer 3916.SpecificIn embodiment, third metal layer 3920 and U-shaped metal layer include titanium, and T shape metal layer 3918 includes cobalt.
In another aspect, the groove interface construction for example for source electrode or drain region is described.In this example, scheme40A instantiates the transversal of the integrated circuit structure with the trench contact portion for NMOS device according to an embodiment of the present disclosureFace view.Figure 40 B instantiates the integrated of the trench contact portion having for PMOS device according to another embodiment of the present disclosureThe viewgraph of cross-section of circuit structure.
With reference to Figure 40 A, integrated circuit structure 4000 includes fin 4002, such as silicon fin.Gate dielectric layer 4004 existsOn fin 4002.Gate electrode 4006 is on gate dielectric layer 4004.In embodiment, gate electrode 4006 includes conformal leadsElectric layer 4008 and conductive fill 4010.In embodiment, dielectric cap 4012 is situated between on gate electrode 4006 and in grid electricityOn matter layer 4004.Gate electrode has the first side 4006A and second side 4006B opposite with the first side 4006A.Dielectric intervalPortion 4013 along gate electrode 4006 side wall.In one embodiment, gate dielectric layer 4004 is more between dielectricEvery first in portion 4013 between the first side 4006A of gate electrode 4006, and in dielectric spacer portion 4013Between second and second side 4006B of gate electrode 4006, as depicted.In embodiment, although not describing,The thin oxide layer of such as hot or chemical oxygen SiClx or silicon dioxide layer etc fin 4002 and gate dielectric layer 4004 itBetween.
First and second semiconductor source electrodes or drain region 4014 and 4016 abut the first side of gate electrode 4006 respectively4006A and second side 4006B.In one embodiment, the first and second semiconductor source electrodes or drain region 4014 and 4016 existIn fin 4002, as depicted.However, in another embodiment, the first and second semiconductor source electrodes or drain region4014 and 4016 be the embedded epitaxial region formed in the recess of fin 4002.
First and second groove interface constructions 4018 and 4020 are respectively in the first and second semiconductor source electrodes or drain regionOn 4014 and 4016, the first side 4006A and second side 4006B of adjacent gate electrode 4006.First and second trench contact knotsBoth structures 4018 and 4020 all includes U-shaped metal layer 4022 and on entire U-shaped metal layer 4022 and the T shape metal layer of top4024.In one embodiment, U-shaped metal layer 4022 and T shape metal layer 4024 are upper different in composition.As oneIn embodiment, U-shaped metal layer 4022 includes titanium, and T shape metal layer 4024 includes cobalt.In one embodiment, first andBoth two groove interface constructions 4018 and 4020 all further comprise the third metal layer 4026 on T shape metal layer 4024.?In one such embodiment, third metal layer 4026 and the composition having the same of U-shaped metal layer 4022.In specific embodimentIn, third metal layer 4026 and U-shaped metal layer 4022 include titanium, and T shape metal layer 4024 includes cobalt.
First groove contact through hole 4028 is electrically connected to first groove contact portion 4018.In certain embodiments, firstTrench contact through-hole 4028 is on the third metal layer 4026 of first groove contact portion 4018 and is coupled to the third metal layer4026.First groove contact through hole 4028 further connects on one a part in dielectric spacer portion 4013 and therewithTouching, and on a part of dielectric cap 4012 and contact.Second groove contact through hole 4030 is electrically connected to secondTrench contact portion 4020.In certain embodiments, second groove contact through hole 4030 in second groove contact portion 4020On three metal layers 4026 and it is coupled to the third metal layer 4026.Second groove contact through hole 4030 is further between dielectricOn another a part in portion 4013 and contact, and on another part of dielectric cap 4012 and withContact.
In embodiment, metal silicide layer 4032 is respectively directly in the first and second groove interface constructions 4018 and 4020Between the first and second semiconductor source electrodes or drain region 4014 and 4016.In one embodiment, metal silicide layer4032 include titanium and silicon.In specific such embodiment, 4014 He of the first and second semiconductor source electrodes or drain region4016 be the first and second N-type semiconductor source electrodes or drain region.
With reference to Figure 40 B, integrated circuit structure 4050 includes fin 4052, such as silicon fin.Gate dielectric layer 4054 existsOn fin 4052.Gate electrode 4056 is on gate dielectric layer 4054.In embodiment, gate electrode 4056 includes conformal leadsElectric layer 4058 and conductive fill 4060.In embodiment, insulating cover 4062 is on gate electrode 4056 and in gate-dielectricOn layer 4054.Gate electrode has the first side 4056A and second side 4056B opposite with the first side 4056A.Dielectric spacer portion4063 along gate electrode 4056 side wall.In one embodiment, gate dielectric layer 4054 is more in dielectric intervalFirst in portion 4063 is between the first side 4056A of gate electrode 4056, and the in dielectric spacer portion 4063Between two and second side 4056B of gate electrode 4056, as depicted.In embodiment, all although not describingIf the thin oxide layer of heat or chemical oxygen SiClx or silicon dioxide layer etc is between fin 4052 and gate dielectric layer 4054.
First and second semiconductor source electrodes or drain region 4064 and 4066 abut the first side of gate electrode 4056 respectively4056A and second side 4056B.In one embodiment, the first and second semiconductor source electrodes or drain region 4064 and 4066 areThe embedded epitaxial region formed in the recess 4065 and 4067 of fin 4052 respectively, as depicted.However, anotherIn one embodiment, the first and second semiconductor source electrodes or drain region 4064 and 4066 are in fin 4052.
First and second groove interface constructions 4068 and 4070 are respectively in the first and second semiconductor source electrodes or drain regionOn 4064 and 4066, the first side 4056A and second side 4056B of adjacent gate electrode 4056.First and second trench contact knotsBoth structures 4068 and 4070 all includes U-shaped metal layer 4072 and on entire U-shaped metal layer 4072 and the T shape metal layer of top4074.In one embodiment, U-shaped metal layer 4072 and T shape metal layer 4074 are upper different in composition.As oneIn embodiment, U-shaped metal layer 4072 includes titanium, and T shape metal layer 4074 includes cobalt.In one embodiment, first andBoth two groove interface constructions 4068 and 4070 all further comprise the third metal layer 4076 on T shape metal layer 4074.?In one such embodiment, third metal layer 4076 and the composition having the same of U-shaped metal layer 4072.In specific embodimentIn, third metal layer 4076 and U-shaped metal layer 4072 include titanium, and T shape metal layer 4074 includes cobalt.
First groove contact through hole 4078 is electrically connected to first groove contact portion 4068.In certain embodiments, firstTrench contact through-hole 4078 is on the third metal layer 4076 of first groove contact portion 4068 and is coupled to the third metal layer4076.First groove contact through hole 4078 further connects on one a part in dielectric spacer portion 4063 and therewithTouching, and on a part of dielectric cap 4062 and contact.Second groove contact through hole 4080 is electrically connected to secondTrench contact portion 4070.In certain embodiments, second groove contact through hole 4080 in second groove contact portion 4070On three metal layers 4076 and it is coupled to the third metal layer 4076.Second groove contact through hole 4080 is further between dielectricOn another a part in portion 4063 and contact, and on another part of dielectric cap 4062 and withContact.
In embodiment, metal silicide layer 4082 is respectively directly in the first and second groove interface constructions 4068 and 4070Between the first and second semiconductor source electrodes or drain region 4064 and 4066.In one embodiment, metal silicide layer4082 include nickel, platinum and silicon.In specific such embodiment, 4064 He of the first and second semiconductor source electrodes or drain region4066 be the first and second P-type semiconductor source electrodes or drain region.In one embodiment, metal silicide layer 4082 is furtherIncluding germanium.In one embodiment, metal silicide layer 4082 further comprises titanium.
One or more embodiment described herein is related to being vapor-deposited using metallochemistry for circulating type (wrap-Around) semiconductor interface contact portion.Embodiment can be applied to or including one of the following or multiple: chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), electrically conducting contact manufacture or film.
Specific embodiment may include the low temperature using contact portion metal (for example, being lower than 500 degrees Celsius, or in 400-In 500 degrees Celsius of range) chemical vapor deposition come manufacture titanium or similar metal-containing layer with provide conformal source electrode or drain electrode connectContact portion.Realize that such conformal source electrode or drain contact can improve three-dimensional (3D) transistor complementary metal oxide semiconductor(CMOS) performance.
In order to provide context, sputtering can be used by metal deposit to semiconductor contact layer.Sputtering is a kind of sight(line of sight) process, and the manufacture of 3D transistor may be poorly suited for.Known sputtering solution have withPoor or incomplete metal semiconductor junction on the angled device contact surface of the incidence of deposition.
According to one or more other embodiments of the present disclosure, realize low temperature chemical vapor deposition process for manufacturing contact portion goldBelong to, to provide the conformability in three dimensions and maximize metal semiconductor junction contact area.Obtained biggish contact surfaceProduct can reduce the resistance of the knot.Embodiment may include the deposition on the semiconductor surface with uneven pattern,The pattern in middle region refers to surface shape and feature itself, and uneven pattern includes uneven surface shape and featureOr the part of surface shape and feature, i.e., not completely flat surface shape and feature.
Embodiment described herein may include manufacture circulating type contact structures.In one suchembodiment, it retouchesIt has stated through chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or plasma enhanced atomic layerDeposit and conformally deposit to the use of the pure metal on transistor source-drain contact.It is such conformal heavy to can be usedProduct is to increase the usable area in metal-semiconductor contact portion and reduce resistance, to improve the performance of transistor device.ImplementingIn example, the relatively low temperature of deposition causes the per unit area of knot to minimize resistance.
It is related to the Integrated Solution of metal-containing layer deposition process as described in this article it is to be appreciated that can be used to makeMake various integrated circuit structures.In accordance with an embodiment of the present disclosure, a kind of method manufacturing integrated circuit structure is included inSubstrate is provided in chemical vapor deposition (CVD) room with the source RF, the substrate has feature on it.This method further includesMake titanium tetrachloride (TiCl4) and hydrogen (H2) react to form titanium (Ti) layer in the feature of the substrate.
In embodiment, which has the total atom composition including 98% or more titanium and the chlorine of 0.5-2%.It is replacingIn embodiment, the high-purity of zinc (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) or vanadium (V) is manufactured using similar procedure containing metalLayer.In embodiment, there are relatively small film thickness changes, such as in embodiment, and all coverings are both greater than 50%, andIt is nominally 70% or bigger (that is, thickness change is 30% or smaller).In embodiment, thickness is in silicon (Si) or SiGe (SiGe)On it is moderately thicker than other surfaces because Si or SiGe react during deposition and quickly absorb Ti.In embodimentIn, film constitutes Cl(or Cl less than 1% including about 0.5%) it is used as impurity, and there is no other impurity observed.?In embodiment, which makes it possible to realize the metal covering on non-line-of-sight surface, the non-line-of-sight surface such as byThe surface that sputtering sedimentation sight is hidden.May be implemented embodiment described herein with by reduce be driven through source electrode andThe non-essential resistance of the electric current of drain contact drives to improve transistor device.
In accordance with an embodiment of the present disclosure, the substrate is characterized in exposing source electrode or the leakage of semiconductor source electrode or drain electrode structurePole contact trench.Titanium layer (or other high-purity metal-containing layers) is the conductive contact for the semiconductor source electrode or drain electrode structureLayer.Contact below Figure 41 A, 41B, 42,43A-43C and 44 exemplary embodiment of such embodiment described.
Figure 41 A instantiates partly the leading with electrically conducting contact according to an embodiment of the present disclosure on source electrode or drain regionThe viewgraph of cross-section of body device.
With reference to Figure 41 A, semiconductor structure 4100 includes gate structure 4102 above substrate 4104.Gate structure 4102 wrapsInclude gate dielectric layer 4102A, work-function layer 4102B and grid filling 4102C.Source region 4108 and drain region 4110 existOn the opposite side of gate structure 4102.Source electrode or drain contact 4112 are electrically connected to source region 4108 and drain region4110, and pass through one or two and the gate structure in interlevel dielectric layer 4114 or gate-dielectric spacer portion 41164102 are spaced apart.Source region 4108 and drain region 4110 are the regions of substrate 4104.
In embodiment, source electrode or drain contact 4112 include all high-purity metal-containing layers as described above4112A and conductive trench fill material 4112B.In one embodiment, high-purity metal-containing layer 4112A have including 98% orThe total atom of more titaniums is constituted.In one suchembodiment, the total atom of high-purity metal-containing layer 4112A is constituted into oneStep includes the chlorine of 0.5-2%.In embodiment, high-purity metal-containing layer 4112A has 30% or smaller thickness change.ImplementingIn example, conductive trench fill material 4112B is made of conductive metal, conductive metal such as, but not limited to Cu, Al, W or its alloy.
Figure 41 B, which is instantiated on the source electrode according to an embodiment of the present disclosure in protrusion or drain region, has electrically conducting contactAnother semiconductor devices viewgraph of cross-section.
With reference to Figure 41 B, semiconductor structure 4150 includes gate structure 4152 above substrate 4154.Gate structure 4152 wrapsInclude gate dielectric layer 4152A, work-function layer 4152B and grid filling 4152C.Source region 4158 and drain region 4160 existOn the opposite side of gate structure 4152.Source electrode or drain contact 4162 are electrically connected to source region 4158 and drain region4160, and pass through one or two and the gate structure in interlevel dielectric layer 4164 or gate-dielectric spacer portion 41664152 are spaced apart.Source region 4158 and drain region 4160 are the extensions formed in the region of substrate 4154 etched awayOr embedded material region.As depicted, in embodiment, source region 4158 and drain region 4160 are the source electrodes of protrusionThe drain region and.In specific such embodiment, the source electrode and drain electrode region of protrusion is silicon source and the drain region of protrusionDomain or the SiGe source electrode and drain electrode region of protrusion.
In embodiment, source electrode or drain contact 4162 include all high-purity metal-containing layers as described above4162A and conductive trench fill material 4162B.In one embodiment, high-purity metal-containing layer 4162A have including 98% orThe total atom of more titaniums is constituted.In one suchembodiment, the total atom of high-purity metal-containing layer 4162A is constituted into oneStep includes the chlorine of 0.5-2%.In embodiment, high-purity metal-containing layer 4162A has 30% or smaller thickness change.ImplementingIn example, conductive trench fill material 4162B is made of conductive metal, conductive metal such as, but not limited to Cu, Al, W or its alloy.
Therefore, in embodiment, collective reference Figure 41 A and 41B, integrated circuit structure include the feature (source with surfacePole or drain contact groove exposure semiconductor source electrode or drain electrode structure).High-purity metal-containing layer 4112A or 4162A is in the source electrodeOr on the surface of drain contact groove.It is to be appreciated that contact portion forming process may relate to consumption source electrode or drain regionThe silicon being exposed or germanium or germanium material.Such consumption can make degraded device performance.In contrast, according to the disclosureEmbodiment, do not corrode or consume or do not corrode substantially or consume the semiconductor in source electrode or drain contact beneath trenchesThe surface (4149 or 4199) of source electrode (4108 or 4158) or (the 4110 or 4160) structure that drains.In such embodimentIn, low temperature depositing by high-purity containing metal contact layer is not consumed there is this or is not corroded.
Figure 42 instantiates the plane view of multiple grid lines on a pair of of semiconductor fin according to an embodiment of the present disclosureFigure.
With reference to Figure 42, multiple effective grid lines 4204 are formed on multiple semiconductor fins 4200.Dummy gate electrode line4206 in the end of multiple semiconductor fins 4200.Interval 4208 between grid line 4204/4206 is that trench contact portion canTo be formed to the position of the electrically conducting contact of source electrode or drain region, the source electrode or drain region such as source electrode or drain electrodeRegion 4251,4252,4253 and 4254.
Figure 43 A-43C instantiates various in the method according to an embodiment of the present disclosure for manufacture integrated circuit structureThe viewgraph of cross-section that the a-a ' axis along Figure 42 of operation intercepts.
With reference to Figure 43 A, multiple effective grid lines 4304, the semiconductor fin are formed on semiconductor fin 43023262 are formed on 4300 top of substrate.Dummy gate electrode line 4306 is in the end of semiconductor fin 4302.Dielectric layer 4310Between effective grid line 4304, between dummy gate electrode line 4306 and effectively grid line 4304 and in dummy gate electrodeOutside line 4306.Embedded source electrode or drain electrode structure 4308 are in semiconductor fin 4302, between effective grid line 4304And between dummy gate electrode line 4306 and effectively grid line 4304.Effective grid line 4304 include gate dielectric layer 4312,Work function gate electrode part 4314 and filling gate electrode part 4316 and gate electrode capping layer 4318.Dielectric spacer portion 4320Inside it is lining in the side wall of effective grid line 4304 and dummy gate electrode line 4306.
With reference to Figure 43 B, remove dielectric layer 4310 between effective grid line 4304 and in dummy gate electrode line 4306With the part between effective grid line 4304, in the position to form trench contact portion at which provide opening 4330.It goesExcept dielectric layer 4310 between effective grid line 4304 and between dummy gate electrode line 4306 and effectively grid line 4304Part may result in and corrode embedded source electrode or drain electrode structure 4308 to provide the embedded source electrode being etched or drain junctionStructure 4332 can have shape of a saddle pattern, as described in Figure 43 B.
With reference to Figure 43 C, between effective grid line 4304 and dummy gate electrode line 4306 and effective grid line 4304 itBetween opening 4330 in formed trench contact portion 4334.Each of trench contact portion 4334 can include contacting containing metalLayer 4336 and conductive filling material 4338.
Figure 44 instantiates what the b-b ' axis along Figure 42 according to an embodiment of the present disclosure for integrated circuit structure interceptedViewgraph of cross-section.
With reference to Figure 44, fin 4402 is depicted in 4404 top of substrate.The lower part of fin 4402 is by trench isolation4404 are surrounded.The top for having eliminated fin 4402 enables to grow embedded source electrode and drain electrode structure 4406.In electricityTrench contact portion 4408 is formed in the opening of dielectric layer 4410, which exposes embedded source electrode and drain electrode structure 4406.DitchSlot contact portion includes containing metal contact layer 4412 and conductive filling material 4414.It is to be appreciated that being connect according to embodiment containing metalContact layer 4412 extends to the top in trench contact portion 4408, as described in Figure 44.However in another embodiment, containing goldBelong to the top that contact layer 4412 is not extend to trench contact portion 4408, but it is slightly concave in trench contact portion 4408, for example,Similar to the description containing metal contact layer 4336 in Figure 43 C.
Therefore, collective reference Figure 42,43A-43C and 44, in accordance with an embodiment of the present disclosure, a kind of integrated circuit structure includesSemiconductor fin (4200,4302,4402) above substrate (4300,4400).Semiconductor fin (4200,4302,4402)With top and side wall.Gate electrode (4204,4304) on the top of semiconductor fin (4200,4302,4402) and withThe side wall of a part of semiconductor fin (4200,4302,4402) is adjacent.Gate electrode (4204,4304) defines semiconductor finChannel region in piece (4200,4302,4402).First semiconductor source electrode or drain electrode structure (4251,4332,4406) are in gridThe first side position of electrode (4204,4304) at the first end of channel region, the first semiconductor source electrode or drain electrode structure (4251,4332,4406) there is uneven pattern.Second semiconductor source electrode or drain electrode structure (4252,4332,4406) are in gate electrodeAt the second side of (4204,4304) at the second end of channel region, the second end is opposite with first end, and second side and theSide is opposite.Second semiconductor source electrode or drain electrode structure (4252,4332,4406) have uneven pattern.Material is contacted containing metalExpect (4336,4412) directly on the first semiconductor source electrode or drain electrode structure (4251,4332,4406) and directly the second halfOn conductor source electrode or drain electrode structure (4252,4332,4406).Containing metallic contact material (4336,4412) and the first semiconductor sourceThe uneven pattern of pole or drain electrode structure (4251,4332,4406) is conformal, and with the second semiconductor source electrode or drain electrode structureThe uneven pattern of (4252,4332,4406) is conformal.
In embodiment, there are the single metal species including 95% or more containing metallic contact material (4336,4412)Total atom is constituted.In one suchembodiment, have containing metallic contact material (4336,4412) including 98% or moreThe total atom of titanium is constituted.In specific such embodiment, the total atom containing metallic contact material (4336,4412) constitute intoOne step includes the chlorine of 0.5-2%.In embodiment, have containing metallic contact material (4336,4412) along the first semiconductor source electrodeOr drain electrode structure (4251,4332,4406) uneven pattern and along the second semiconductor source electrode or drain electrode structure (4252,4332,30% or less thickness change of uneven pattern 4406).
In embodiment, the uneven pattern and second of the first semiconductor source electrode or drain electrode structure (4251,4332,4406)Both uneven patterns of semiconductor source electrode or drain electrode structure (4252,4332,4406) all include protrusion center portion and compared withLow lateral parts, for example, as described in Figure 44.In embodiment, the first semiconductor source electrode or drain electrode structureThe injustice of the uneven pattern of (4251,4332,4406) and the second semiconductor source electrode or drain electrode structure (4252,4332,4406)Both smooth patterns all include shape of a saddle part, for example, as described in Figure 43 C.
In embodiment, the first semiconductor source electrode or drain electrode structure (4251,4332,4406) and the second semiconductor source electrode orBoth drain electrode structures (4252,4332,4406) all include silicon.In embodiment, the first semiconductor source electrode or drain electrode structureBoth (4251,4332,4406) and the second semiconductor source electrode or drain electrode structure (4252,4332,4406) all further comprise germanium,For example, in the form of SiGe.
In embodiment, direct being connect containing metal on the first semiconductor source electrode or drain electrode structure (4251,4332,4406)Material (4336,4412) are touched further along the side wall of the groove in dielectric layer (4320,4410) in the first semiconductor source electrodeOr on drain electrode structure (4251,4332,4406), the groove exposure the first semiconductor source electrode or drain electrode structure (4251,4332,4406) a part.In one suchembodiment, containing metallic contact material (4336) along the thickness of the side wall of the grooveAbove from the first semiconductor source electrode or drain electrode structure (4336A from 4332) to the first semiconductor source electrode or drain electrode structure (4332)Position (4336B) it is thinning, its example is instantiated in Figure 43 C.In embodiment, conductive filling material (4338,4414) existsContaining on metallic contact material (4336,4412) in groove, as described in Figure 43 C and 44.
In embodiment, integrated circuit structure further comprise have top and side wall the second semiconductor fin (for example,The upper fin 4200 of Figure 42,4302,4402).Gate electrode (4204,4304) is further on the top of the second semiconductor finAnd adjacent with the side wall of a part of the second semiconductor fin, gate electrode limits the channel region in the second semiconductor fin.Third semiconductor source electrode or drain electrode structure (4253,4332,4406) are the first side positions in gate electrode (4204,4304) secondAt the first end of the channel region of semiconductor fin, third semiconductor source electrode or drain electrode structure have uneven pattern.4th halfConductor source electrode or drain electrode structure (4254,4332,4406) are to be in the second semiconductor in second side of gate electrode (4204,4304)At the second end of the channel region of fin, the second end is opposite with first end, the 4th semiconductor source electrode or drain electrode structure (4254,4332,4406) there is uneven pattern.(4336,4412) containing metallic contact material are directly in third semiconductor source electrode or drain electrodeIn structure (4253,4332,4406) and directly on the 4th semiconductor source electrode or drain electrode structure (4254,4332,4406), containThe uneven pattern of metallic contact material (4336,4412) and third semiconductor source electrode or drain electrode structure (4253,4332,4406)It is conformal and conformal with the uneven pattern of the 4th semiconductor source electrode or drain electrode structure (4254,4332,4406).In embodimentIn, containing metallic contact material (4336,4412) the first semiconductor source electrode or drain electrode structure (4251,4332, left side 4406)And third semiconductor source electrode or drain electrode structure (4253,4332, right side 4406) between be continuous, and in the second semiconductorIt is continuous between source electrode or drain electrode structure (4252) and the 4th semiconductor source electrode or drain electrode structure (4254).
In another aspect, hard mask material is for saving and (inhibiting to corrode), and can be retained in conductive trench contactOn dielectric substance in the groove line position that portion is interrupted at which (such as in contact plunger position).For example, Figure 45 A andIt includes the integrated of the trench contact plug with hard mask material on it that 45B, which is illustrated respectively according to an embodiment of the present disclosure,The plan view of circuit structure and corresponding viewgraph of cross-section.
With reference to Figure 45 A and 45B, in embodiment, integrated circuit structure 4500 includes fin 4502A, such as silicon fin.It is moreA gate structure 4506 is on fin 4502A.Each gate structure in gate structure 4506 is along orthogonal with fin 4502ADirection 4508, and there is a pair of of dielectric sidewall spacers portion 4510.Groove interface construction 4512 on fin 4502A simultaneouslyAnd directly between the dielectric sidewall spacers portion 4510 of first couple of gate structure 4506A/4506B in gate structure 4506.Second pair gate structure 4506B/ of the contact plunger 4514B on fin 4502A and directly in gate structure 4506Between the dielectric sidewall spacers portion 4510 of 4506C.Contact plunger 4514B includes lower dielectric substance 4516 and upper hard mask materialMaterial 4518.
In embodiment, the lower dielectric substance 4516 of contact plunger 4516B include silicon and oxygen, such as such as silica orEarth silicon material.The upper hard mask material 4518 of contact plunger 4516B includes silicon and nitrogen, such as such as silicon nitride, Silicon-rich nitrogenCompound or poor nitride material.
In embodiment, groove interface construction 4512 includes that the electricity on lower conductive structure 4520 and lower conductive structure 4520 is situated betweenMatter lid 4522.In one embodiment, the dielectric cap 4522 of groove interface construction 4512 has upper with contact plunger 4514BThe coplanar upper surface in the upper surface of hard mask material 4518, as depicted.
In embodiment, each gate structure in multiple gate structures 4506 includes on gate dielectric layer 4526Gate electrode 4524.Dielectric cap 4528 is on gate electrode 4524.In one embodiment, each in multiple gate structures 4506The dielectric cap 4528 of gate structure has the upper table coplanar with the upper surface of upper hard mask material 4518 of contact plunger 4514BFace, as depicted.In embodiment, although not describing, such as hot or chemical oxygen SiClx or silicon dioxide layer itThe thin oxide layer of class is between fin 4502A and gate dielectric layer 4526.
Referring again to Figure 45 A and 45B, in embodiment, integrated circuit structure 4500 includes multiple fins 4502, such as moreA silicon fin.Each fin in multiple fins 4502 along a first direction 4504.Multiple gate structures 4506 are in multiple finsOn 4502.Each gate structure in multiple gate structures 4506 is along the second direction orthogonal with first direction 45044508.Each gate structure in multiple gate structures 4506 has a pair of of dielectric sidewall spacers portion 4510.Trench contact knotStructure 4512 is on the first fin 4502A in multiple fins 4502 and a pair of of grid knot directly in gate structure 4506Between the dielectric sidewall spacers portion 4510 of structure.Contact plunger 4514A is on the second fin 4502B in multiple fins 4502And directly between the dielectric sidewall spacers portion 4510 of a pair of of gate structure in gate structure 4506.It is inserted similar to contactThe viewgraph of cross-section of 4514B is filled in, contact plunger 4514A includes lower dielectric substance 4516 and upper hard mask material 4518.
In embodiment, the lower dielectric substance 4516 of contact plunger 4516A include silicon and oxygen, such as such as silica orEarth silicon material.The upper hard mask material 4518 of contact plunger 4516A includes silicon and nitrogen, such as such as silicon nitride, Silicon-rich nitrogenCompound or poor nitride material.
In embodiment, groove interface construction 4512 includes that the electricity on lower conductive structure 4520 and lower conductive structure 4520 is situated betweenMatter lid 4522.In one embodiment, the dielectric cap 4522 of groove interface construction 4512 have with contact plunger 4514A orThe coplanar upper surface in the upper surface of the upper hard mask material 4518 of 4514B, as depicted.
In embodiment, each gate structure in multiple gate structures 4506 includes on gate dielectric layer 4526Gate electrode 4524.Dielectric cap 4528 is on gate electrode 4524.In one embodiment, each in multiple gate structures 4506The dielectric cap 4528 of gate structure has total with the upper surface of the upper hard mask material 4518 of contact plunger 4514A or 4514BThe upper surface in face, as depicted.In embodiment, although not describing, such as hot or chemical oxygen SiClx or dioxyThe thin oxide layer of SiClx layer etc is between fin 4502A and gate dielectric layer 4526.
One or more other embodiments of the present disclosure are related to a kind of contact process of grid alignment.Such process may be implementedTo form contact structures for semiconductor structure manufacture (such as IC manufacturing).In embodiment, by hookupCase is formed as being aligned with existing gate pattern.In contrast, other methods generally involve additional photoetching process, wherein combiningPhotolithography contact pattern is closely registrated to existing gate pattern by the etching of selective exposure portion.For example, another process may includeTo the patterning of polymerization (grid) grid, wherein discretely patterned contact portion and contact plunger.
According to one or more embodiments described herein, a kind of contact portion forming method be related to being formed substantially withThe contact patterns of existing gate pattern perfection alignment and eliminate the photoetching with extreme closely registration budget (budget) simultaneouslyThe use of operation.In one suchembodiment, this method makes it possible for the wet etching of substantially high selectivity(for example, compared to dry etching or plasma etching) Lai Shengcheng contact openings.In embodiment, by utilizing existing grid figureCase combination contact plunger lithography operations form contact patterns.In one suchembodiment, this method makes it possible to eliminateTo the needs such as the script used in other methods to generate the conclusive lithography operations of contact patterns.In embodimentIn, discretely patterned trench does not contact grid, but trench contact grid is formed between polymerization (grid) line.For example,In one such embodiment, trench contact grid are formed after grid patterning but before grid cuttingLattice.
It includes manufacture on it with hard mask material that Figure 46 A-46D, which instantiates expression according to an embodiment of the present disclosure,The viewgraph of cross-section of various operations in the method for the integrated circuit structure of trench contact plug.
With reference to Figure 46 A, the method for manufacturing integrated circuit structure includes forming multiple fins, each in the multiple finFin 4602 is along a first direction 4604.Each fin 4602 in the multiple fin may include diffusion zone 4606.Multiple gate structures 4608 are formed on multiple fins.Each gate structure in multiple gate structures 4508 is along with firstThe orthogonal second direction 4610(in direction 4604 is for example, the neutralization that direction 4610 enters the page is left except the page).At first pairExpendable material structure 4612 is formed between gate structure 4608.Contact plunger is formed between second pair of gate structure 46084614.Contact plunger includes lower dielectric substance 4616.Hard mask material 4618 is on lower dielectric substance 4616.
In embodiment, gate structure 4608 includes sacrificing gate stack or dummy gate electrode stacking and dielectric spacer portion4609.It sacrifices gate stack or dummy gate electrode is stacked and can be made of polysilicon or nitridation silicon column or certain other expendable material,It is properly termed as grid void material.
With reference to Figure 46 B, from the structure of Figure 46 A removal expendable material structure 4612 between first pair of gate structure 4608Form opening 4620.
With reference to Figure 46 C, groove interface construction 4622 is formed in the opening 4620 between first pair of gate structure 4608.It is attachedAdd ground, in embodiment, as a part for forming groove interface construction 4622, the hard mask 4618 of Figure 46 A and 46B are carried outPlanarizing.The contact plunger 4614 ' being finally completed includes lower dielectric substance 4616 and is formed from hard mask material 4618 upperHard mask material 4624.
In embodiment, the lower dielectric substance 4616 of each of contact plunger 4614 ' includes silicon and oxygen, and is connectThe upper hard mask material 4624 for touching each of plug 4614 ' includes silicon and nitrogen.In embodiment, groove interface construction 4622Each of include lower conductive structure 4626 and lower conductive structure 4626 on dielectric cap 4628.In one embodiment,The dielectric cap 4628 of groove interface construction 4622 has total with the upper surface of the upper hard mask material 4624 of contact plunger 4614 'The upper surface in face.
With reference to Figure 46 D, the sacrifice gate stack or illusory grid of replacement gate structure 4608 in replacement gate process regimesPole stacks.In such scheme, the dummy gate electrode material of removal such as polysilicon or silicon nitride column material etc, and with permanentlyProperty gate material substitutes them.In one suchembodiment, permanent gate-dielectric is also formed in this processLayer, such as with from earlier handle implemented it is opposite.
Therefore, permanent gate structure 4630 includes permanent gate dielectric layer 4632 and permanent gate electrode layer or heapFolded 4634.Additionally, in embodiment, the top section of permanent gate structure 4630 such as by etching process is removed,And the part is substituted with dielectric cap 4636.In embodiment, each gate structure in permanent gate structure 4630Dielectric cap 4636 has the upper surface coplanar with the upper surface of upper hard mask material 4624 of contact plunger 4614 '.
Referring again to Figure 46 A-46D, in embodiment, replacement gate mistake is executed after forming groove interface construction 4622Journey, as depicted.However according to other embodiments, replacement gate mistake is executed before forming groove interface construction 4622Journey.
In another aspect, contact portion (COAG) structure and the process on effective grid are described.One of the disclosure orMultiple embodiments are related to one or more grid on the live part with the gate electrode for being deployed in semiconductor structure or deviceThe semiconductor structure or device of pole contact structures (for example, as gate contact through-hole).One or more other embodiments of the present disclosureBeing related to manufacture has the one or more gate contacts formed on the live part of semiconductor structure or the gate electrode of deviceThe method of the semiconductor structure or device of structure.Method described herein can be used by making it possible in effective gate regionsRealize that gate contact is formed to reduce standard cell area on domain.In one or more embodiments, it is produced for connecingThe gate contacting structure for touching gate electrode is self-aligned through-hole structure.
In wherein space and layout constraint with compared with former generation space and layout constraint in the technology of semi-coast, Ke YitongThe contact portion of a part for being made to the gate electrode being deployed on area of isolation is crossed to be fabricated onto the contact portion of gate structure.MakeFor example, Figure 47 A instantiates the flat of the semiconductor devices with the gate contact being deployed on the inactive portion of gate electrodeFace view.
With reference to Figure 47 A, semiconductor structure or device 4700A include being deployed in substrate 4702 and in area of isolation 4706Interior diffusion or active region 4704.On diffusion or active region 4704 and on a part of area of isolation 4706Dispose one or more grid lines (also referred to as polymerization line), such as grid line 4708A, 4708B and 4708C.In semiconductor structureOr source electrode or drain contact (also referred to as trench contact portion) are disposed on the source electrode and drain electrode region of device 4700A, such as connectContact portion 4710A and 4710B.Trench contact through-hole 4712A and 4712B are provided respectively to connecing for trench contact portion 4710A and 4710BTouching.Isolated gate contact 4714 provides the contact of grid line 4708B with the gate contact through-hole 4716 of superposition.With sourcePole or drain trenches contact portion 4710A or 4710B are compared, and from the viewpoint of plan view, gate contact 4714 is disposedWithout on diffusion or active region 4704 on area of isolation 4706.In addition, in source electrode or drain trenches contact portionGate contact 4714 is neither disposed between 4710A and 4710B nor disposes gate contact through-hole 4716.
Figure 47 B instantiates the nonplanar semiconductor device with the gate contact being deployed on the inactive portion of gate electrodeThe viewgraph of cross-section of part.With reference to Figure 47 B, semiconductor structure or device 4700B(are for example, the device 4700A's of Figure 47 A is non-planarVersion) include formed from substrate 4702 and the non-planar diffusion in area of isolation 4706 or active region 4704C(Such as, fin structure).The top of a part on non-planar diffusion or active region 4704B and in area of isolation 4706Affix one's name to grid line 4708B.As shown, grid line 4708B includes gate electrode 4750 and the grid with dielectric covers 4754 togetherDielectric layer 4752.The gate contact through-hole 4716 of gate contact 4714 and superposition is also seen from the visual angle, and be superimposedMetal interconnection 4760 is all deployed in interlayer dielectric stacking or layer 4770.Also see from the visual angle of Figure 47 B, gridPole contact portion 4714 is deployed on area of isolation 4706 but not on non-planar diffusion or active region 4704B.
Referring again to Figure 47 A and 47B, the arrangement of semiconductor structure or device 4700A and 4700B respectively area of isolation itOn placed gate contact.Such arrangement wastes arrangement space.However, placing gate contact on active regionAsk that extreme closely registration budget or grid size will have to increase connects grid to provide enough spacesContact portion is landed.In addition, from saying in history, because drilling other grid materials (for example, polysilicon) and contacting following active areaThe risk in domain and avoid contacting grid on diffusion zone.One or more embodiment described herein is used for by providingManufacture contact structures feasible method and obtained structure and solve the above problem, contact structures contact in diffusion orThe part of the gate electrode formed on active region.
As an example, Figure 48 A instantiate it is according to an embodiment of the present disclosure have be deployed in gate electrode live part itOn gate contact through-hole semiconductor devices plan view.With reference to Figure 48 A, semiconductor structure or device 4800A include portionAffix one's name to the diffusion in substrate 4802 and in area of isolation 4806 or active region 4804.Diffusion or active region 4804 itIt is upper and one or more grid lines are disposed on a part of area of isolation 4806, such as grid line 4808A, 4808B and4808C.Source electrode or drain trenches contact portion are disposed on the source electrode and drain electrode region of semiconductor structure or device 4800A, it is allSuch as trench contact portion 4810A and 4810B.Trench contact through-hole 4812A and 4812B be provided respectively to trench contact portion 4810A andThe contact of 4810B.The gate contact through-hole 4816 of separate gate contact layer between two parties does not provide connecing to grid line 4808BTouching.Compared with Figure 47 A, from the viewpoint of plan view, gate contact 4816 is deployed in diffusion or active region 4804On and between source electrode or drain contact 4810A and 4810B.
Figure 48 B, which is instantiated, according to an embodiment of the present disclosure there is the grid for being deployed on the live part of gate electrode to connectTouch the viewgraph of cross-section of the non-planar semiconductor device of through-hole.With reference to Figure 48 B, semiconductor structure or device 4800B(are for example, figureThe non-planar version of the device 4800A of 48A) it include non-planar expansion formed from substrate 4802 and in area of isolation 4806It dissipates or active region 4804B(is for example, fin structure).On non-planar diffusion or active region 4804B and in isolated areaGrid line 4808B is disposed on a part in domain 4806.As indicated, grid line 4808B includes gate electrode 4850 and and dielectricThe gate dielectric layer 4852 of cap rock 4854 together.Gate contact through-hole 4816, and the metal of superposition are also seen from the visual angleInterconnection 4860, the two are all deployed in interlayer dielectric stacking or layer 4870.Also see that grid connects from the visual angle of Figure 48 BTouching through-hole 4816 is deployed on non-planar diffusion or active region 4804B.
Therefore, referring again to Figure 48 A and 48B, in embodiment, trench contact through-hole 4812A, 4812B and gate contactThrough-hole 4816 is formed within the same layer and substantially coplanar.Compared with Figure 47 A and 47B, the contact to grid line will in additionIncluding additional gate contact layer, for example, its trend can be vertical with corresponding grid line.However, in connection Figure 48 A and 48B description(one or more) structure in, the manufacture of structure 4800A and 4800B make it possible to respectively will be directly from metal interconnecting layerContact portion lands in effective grid part without being short-circuited to adjacent source electrode or drain region.In embodiment, suchIt is arranged through to eliminate and be provided in circuit layout with forming the needs in reliable contacts portion to extending transistor gate in isolationBiggish area reduce.As used everywhere, in embodiment, grid line or knot are referred to the reference of the live part of gridThe part of structure being deployed on the effective or diffusion zone of following substrate (from the point of view of plane angle).In embodimentIn, being deployed on the area of isolation of following substrate of grid line or structure is referred to the reference of the inactive portion of gridThe part of (from the point of view of plane angle).
In embodiment, semiconductor structure or device 4800 are nonplanar devices, such as, but not limited to fin FET or three gridPole device.In such embodiments, corresponding semiconducting channel region is made of three-dimensional body and is formed on the three-dimensionalIn main body.In one suchembodiment, the gate electrode stack of grid line 4808A-4808C surrounds the three-dimensional body at leastTop surface and a pair of sidewalls.In another embodiment, at least channel region is made discrete three-dimensional body, such as in gridIn complete wound device.In one suchembodiment, the gate electrode stack of grid line 4808A-4808C is respectively entirely around ditchRoad region.
More generally, one or more embodiments are related to for directly making gate contact logical on effective transistor gateThe method that hole is landed and the structure formed by directly making gate contact through-hole land on effective transistor gate.It is suchMethod can eliminate in isolation extend grid line with the needs for contacting purpose.Such method can also eliminate toIn the needs from grid line or isolated gate contact (GCN) layer of structure guidance signal.In embodiment, features described above is eliminatedIt is accomplished by the following way: making to contact metal recess in trench contact portion (TCN) and be introduced in the process flow attachedThe dielectric substance (for example, TILA) added.The additional dielectric material is as trench contact dielectric covers,It has and is aligned the gate dielectric material being aligned in contact process (GAP) processing scheme for trench contact in gridThe different etching characteristic of cap rock (for example, GILA).
As exemplary fabrication scheme, Figure 49 A-49D, which instantiates expression manufacture according to an embodiment of the present disclosure, has portionAffix one's name to the cross section view of the various operations in the method for the semiconductor structure of the gate contacting structure on the live part of gridFigure.
With reference to Figure 49 A, semiconductor structure 4900 is provided after trench contact portion (TCN) is formed.It is to be appreciated that structure4900 specific arrangements are only used for illustrating purpose, and various possible layouts can benefit from public affairs described hereinOpen the embodiment of content.Semiconductor structure 4900 includes one or more gate stack structures, is such as deployed in substrate 4902The gate stack structure 4908A-4908E of top.Gate stack structure may include gate dielectric layer and gate electrode.Groove connectsContact portion --- such as to the contact portion of the diffusion zone of substrate 4902, such as trench contact portion 4910A-4910C --- is also wrappedIt includes in structure 4900, and is spaced apart by dielectric spacer portion 4920 with gate stack structure 4908A-4908E.InsulationCap rock 4922 can be deployed in gate stack structure 4908A-4908E(for example, GILA) on, as also described in Figure 49 ALike that.As also described in Figure 49 A, the contact by inter-level dielectric material manufacture in such as region 4923 etc prevents regionOr " contact plunger " can be included therein in the region that prevent contact from being formed.
In embodiment, structure 4900 is provided and is related to being formed the hookup being substantially aligned with existing gate pattern perfectionCase and the use for eliminating the lithography operations with extreme closely registration budget simultaneously.In one suchembodiment, the partyMethod makes it possible for wet etching (for example, compared to the dry etching or plasma etching) next life of substantially high selectivityAt contact openings.In embodiment, by forming contact patterns using existing gate pattern combination contact plunger lithography operations.In one suchembodiment, this method makes it possible to eliminate to as contacted to generate originally used in other methodsThe needs of the conclusive lithography operations of pattern.In embodiment, discretely patterned trench does not contact grid, but is polymerizeingTrench contact grid is formed between (grid) line.For example, in one suchembodiment, after grid patterning butIt is to form trench contact grid before grid cutting.
Furthermore, it is possible to manufacture gate stack structure 4908A-4908E by replacement gate process.In such schemeIn, can remove the dummy gate electrode material of such as polysilicon or silicon nitride column material etc, and with permanent gate material comeSubstitute them.In one suchembodiment, permanent gate dielectric layer is also formed in this process, such as and from relatively earlyProcessing implemented it is opposite.In embodiment, dummy gate electrode is removed by dry etching or wet etch process.In a realityIt applies in example, dummy gate electrode is made of polysilicon or amorphous silicon, and is using including SF6Dry etch process removal.In another embodiment, dummy gate electrode is made of polysilicon or amorphous silicon, and is using including aqueous NH4OH or hydroxideThe wet etch process removal of tetramethylammonium.In one embodiment, dummy gate electrode is made of silicon nitride, and is to utilize to includeThe wet etching removal of water-bearing phosphate.
In embodiment, one or more method described herein is it is essentially contemplated that dummy gate electrode and replacement gate mistakeJourney combination virtual connection contact portion realizes structure 4900 with substitution contact portion process.In one suchembodiment, in replacement gateSubstitution contact portion process is executed after process to allow at least part to permanent gate stack to carry out high annealing.ExampleSuch as, in specific such embodiment, for example, after forming gate dielectric layer greater than about 600 degrees Celsius at a temperature ofAnnealing is executed at least part of permanent gate structure.Annealing is executed before forming permanent contact portion.
With reference to Figure 49 B, the trench contact portion 4910A-4910C of structure 4900 is set to be recessed in spacer portion 4920 recessed to provideSunken trench contact portion 4911A-4911C has the height of the top surface lower than spacer portion 4920 and insulating cap 4922.SoInsulating cap 4924(is formed on the trench contact portion 4911A-4911C of recess afterwards for example, TILA).According to the implementation of the disclosureExample, the insulating cap 4924 on the trench contact portion 4911A-4911C of recess be by have in gate stack structureWhat the material of the different etching characteristic of insulating cap 4922 on 4908A-4908E was constituted.It will be seen such as in post-treatment operationsIt arrives, can use such difference and come selectively from another in one in 4922/4924 etching 4922/4924.
It can be by making trench contact for the process of spacer portion 4920 and the selectivity of the material of insulating cap 4922Portion 4910A-4910C recess.For example, in one embodiment, passing through such as wet etch process or dry etch process etcEtching process come make trench contact portion 4910A-4910C be recessed.It can be by being suitable for trench contact portion 4910A-4910C'sThe upper that is exposed provides the process of conformal and sealing layer to form insulating cap 4924.For example, in one embodiment,Insulating cap 4924 is formed as to the conforma layer above total by chemical vapor deposition (CVD) process.Then for exampleThe conforma layer is planarized by chemically mechanical polishing (CMP), with only in trench contact portion 4910A-4910C and againNewly 4924 material of insulating cap is provided above exposed spacer portion 4920 and insulating cap 4922.
About the suitable material composition for insulating cap 4922/4924, in one embodiment, this is to 4922/4924In one be made of silica and another is made of silicon nitride.In another embodiment, this is to one in 4922/4924It is made of silica and another is made of carbon dope silicon nitride.In another embodiment, this is to one in 4922/4924 by oxygenSiClx is constituted and another is made of silicon carbide.In another embodiment, this is made of one in 4922/4924 silicon nitrideAnd another is made of carbon dope silicon nitride.In another embodiment, this is made of one in 4922/4924 silicon nitride and anotherOne is made of silicon carbide.In another embodiment, this is made of and another one in 4922/4924 carbon dope silicon nitrideIt is made of silicon carbide.
With reference to Figure 49 C, forms interlayer dielectric (ILD) 4930 and hard mask 4932 is stacked and patterned to them,To provide for example in patterned metal (0) groove 4934 of the superstructure of Figure 49 B.
The interlayer dielectric (ILD) 4930 can consist of such materials: the material is suitable for being electrically isolated finally at itThe metallicity of middle formation and maintain simultaneously front-end and back-end handle between steady structure.In addition, in embodiment, ILD4930 composition is selected to and selectively consistent, the following Federation of Literary and Art Circles for the patterned through hole etching of trench contact dielectric coversIt is as Figure 49 D is more fully described.In one embodiment, ILD 4930 is by single or several silicon oxide layers or listA or several carbon-doped oxide (CDO) material layers are constituted.However in other embodiments, ILD 4930 has the double-deck composition,Wherein top section is made of the material different from the bottom part below ILD 4930.Hard mask layer 4932 can be by being suitable forThe material for serving as subsequent sacrificial layer is constituted.For example, in one embodiment, hard mask layer 4932 generally consist of carbon, for example,Organic polymer layers as crosslinking.In other embodiments, use silicon nitride or carbon dope silicon nitride as hard mask 4932.It canTo be patterned by photoetching and etching process to interlayer dielectric (ILD) 4930 and the stacking of hard mask 4932.
With reference to Figure 49 D, via openings 4936(is formed in interlayer dielectric (ILD) 4930 for example, VCT), from metal(0) groove 4934 extends to one or more of trench contact portion 4911A-4911C of recess.For example, in Figure 49 D, shapeAt via openings with the trench contact portion 4911A and 4911C of exposure recess.Forming via openings 4936 includes that etching interlayer electricity is situated betweenThe corresponding portion of matter (ILD) 4930 and corresponding insulating cap 4924.In one suchembodiment, to interlayer dielectric(ILD) 4930 patterned during exposure insulating cap 4922 a part (for example, exposure insulating cap 4922 in grid pilePart on stack structure 4908B and 4908E).In this embodiment, etching insulating cap 4924 is to form to insulating capThe via openings 4936 of selectivity (that is, indistinctively etching or influence insulating cap 4922) for 4922.
In one embodiment, eventually by not etching insulating cap 4922(that is, gate insulator cap rock) etching processVia openings pattern is transferred to insulating cap 4924(that is, trench contact portion insulating cap).Insulating cap 4924(TILA)It can be made of any or a combination thereof in following, comprising: silica, silicon nitride, silicon carbide, carbon dope silicon nitride, carbon dope oxygenSiClx, amorphous silicon, various metal oxides and silicate, including zirconium oxide, hafnium oxide, lanthana or combinations thereof.It can makeThe layer is deposited with any in following technology, and the technology includes CVD, ALD, PECVD, PVD, HDP, assist type CVD, lowWarm CVD.Corresponding dry plasma etch is developed as chemically and physically sputter the combination of mechanism.It can be used simultaneousPolymer deposits are selective to control material removal rate, etching outline and film.Dry etching is usually with including NF3、CHF3、C4F8, HBr and O2Admixture of gas usually with the pressure and 50-1000 watts of plasma in the range of 30-100 millitorrIt biases to generate.Dry etching can be designed significantly to lose 4922(GILA) to realize in cap rock 4924(TILA) and between layerCarve selectivity, with minimize be used to form transistor source-drain regions contact portion 4924(TILA) dry etchingThe 4922(GILA of period) loss.
Referring again to Figure 49 D, it is to be appreciated that, similar method may be implemented to manufacture eventually by not etching insulating coverLayer 4924(that is, gate insulator cap rock) etching process be transferred to insulating cap 4922(that is, trench contact portion insulating cap)Via openings pattern.
For the concept of contact portion (COAG) technology on the effective grid of further illustration, Figure 50 is instantiated according to the disclosureThe plan view of integrated circuit structure in the trench contact portion with the insulating cap including superposition of embodiment and correspondingViewgraph of cross-section.
With reference to Figure 50, integrated circuit structure 5000 includes on the semiconductor substrate or fin 5002 of such as silicon fin etcThe grid line 5004 of side.Grid line 5004 includes gate stack 5005(e.g., including gate dielectric layer or stacking and at thisGate dielectric layer or the stacked on gate electrode of heap) and gate insulator cap rock 5006 on gate stack 5005.Between dielectricEvery portion 5008 along the side wall of gate stack 5005, and in embodiment, along the side wall of gate insulator cap rock 5006, such as instituteAs description.
The side wall of the adjacent grid line 5004 in trench contact portion 5010, wherein dielectric spacer portion 5008 grid line 5004 withBetween trench contact portion 5010.Each trench contact portion in trench contact portion 5010 includes conductive contact structure 5011 and is leadingTrench contact portion insulating cap 5012 on electric contact structure 5011.
Referring again to Fig. 50, gate contact through-hole 5014, and grid are formed in the opening of gate insulator cap rock 5006Contact through hole 5014 is in electrical contact gate stack 5005.In embodiment, gate contact through-hole 5014 is in semiconductor substrate or finGate stack 5005 on 5002 and is laterally in electrical contact at the position between trench contact portion 5010, as depicted thatSample.In one suchembodiment, the trench contact portion insulating cap 5012 on conductive contact structure 5011 prevents from passing throughThe grid of gate contact through-hole 5014 is to source short or grid to drain short circuit.
Referring again to Fig. 50, trench contact through-hole 5016 is formed in the opening of trench contact portion insulating cap 5012, andAnd trench contact through-hole 5016 is in electrical contact corresponding conductive contact structure 5011.In embodiment, trench contact through-hole 5016 existsPhase is in electrical contact on semiconductor substrate or fin 5002 and laterally at the position of the gate stack 5005 of adjacent grid line 5004The conductive contact structure 5011 answered, as depicted.In one suchembodiment, the grid on gate stack 5005Insulating cap 5006 prevents short-circuit to gate short or drain-to-gate by the source electrode of trench contact through-hole 5016.
It is to be appreciated that the different structure that can be manufactured between insulated gate electrode cap rock and insulated trench contact portion cap rock is closedSystem.As an example, Figure 51 A-51F instantiates the viewgraph of cross-section of various integrated circuit structures according to an embodiment of the present disclosure,The integrated circuit structure respectively has the trench contact portion of the insulating cap including superposition and has the insulation including superpositionThe gate stack of cap rock.
With reference to Figure 51 A, 51B and 51C, integrated circuit structure 5100A, 5100B and 5100C respectively include fin 5102, allSuch as silicon fin.Although depicted as viewgraph of cross-section, but it is to be appreciated that, fin 5102 have top 5102A and side wall (intoThe neutralization for entering the page at shown visual angle is left except the page at shown visual angle).First and second gate dielectric layers, 5104 He5106 on the top 5102A of fin 5102 and laterally abut the side wall of fin 5102.First and second gate electrodes 5108With 5110 respectively on the first and second gate dielectric layers 5104 and 5106,5104 He of the first and second gate dielectric layers5106 on the top 5102A of fin 5102 and laterally abut the side wall of fin 5102.First and second gate electrodes 5108It respectively include that such as work function sets the conformal electrically conductive layers 5109A of layer etc and above conformal electrically conductive layers 5109A with 5110Conductive filling material 5109B.Both first and second gate electrodes 5108 and 5110 all have the first side 5112 and with the first side5112 opposite second side 5114.First and second gate electrodes 5108 and 5110 also all have insulating cover 5116, the insulating cover5116 have top surface 5118.
First side 5112 of the adjacent first gate electrode 5108 of the first dielectric spacer portion 5120.Second dielectric spacer portionSecond side 5114 of 5122 adjacent second gate electrodes 5110.Adjacent first and second electricity of semiconductor source electrode or drain region 5124 is situated betweenMatter spacer portion 5120 and 5122.Groove interface construction 5126 is on semiconductor source electrode or drain region 5124, adjacent first andSecond dielectric spacer portion 5120 and 5122.
Groove interface construction 5126 includes the insulating cover 5128 on conductive structure 5130.Groove interface construction 5126 it is exhaustedEdge lid 5128 has substantially coplanar with the top surface 5118 of insulating cover 5116 of the first and second gate electrodes 5108 and 5110Top surface 5129.In embodiment, the insulating cover 5128 of groove interface construction 5126 extends laterally to the first and second dielectricsIn recess 5132 in spacer portion 5120 and 5122.In such embodiments, the insulating cover 5128 of groove interface construction 5126It is suspended from the conductive structure 5130 of groove interface construction 5126.However in other embodiments, groove interface construction 5126Insulating cover 5128 does not extend laterally in the recess 5132 in the first and second dielectric spacer portions 5120 and 5122, and thereforeIt is not suspended from the conductive structure 5130 of groove interface construction 5126.
It is to be appreciated that the conductive structure 5130 of groove interface construction 5126 can not be rectangle, in Figure 51 A-51CAs description.For example, the conductive structure 5130 of groove interface construction 5126 can have the projection being similar in Figure 51 ACross-sectional geometry shown in the conductive structure 5130A of middle illustration or cross-sectional geometry identical with the geometry.
In embodiment, the insulating cover 5128 of groove interface construction 5126 have with the first and second gate electrodes 5108 andThe different composition of the composition of 5110 insulating cover 5116.In one suchembodiment, the insulation of groove interface construction 5126Lid 5128 includes carbide material, such as carbofrax material.The insulating cover 5116 of first and second gate electrodes 5108 and 5110 wrapsInclude nitride material, such as silicon nitride material.
In embodiment, both insulating covers 5116 of the first and second gate electrodes 5108 and 5110 all have in trench contactBottom surface 5117A below the bottom surface 5128A of the insulating cover 5128 of structure 5126, as described in Figure 51 A.AnotherIn embodiment, both insulating covers of the first and second gate electrodes 5108 and 5,110 5116 all have substantially with groove interface constructionThe bottom surface 5128B of 5126 insulating cover 5128 coplanar bottom surface 5117B, as described in Figure 51 B.In another implementationIn example, both insulating covers 5116 of the first and second gate electrodes 5108 and 5110 all have the insulation in groove interface construction 5126Bottom surface 5117C above the bottom surface 5128C of lid 5128, as described in Figure 51 C.
In embodiment, the conductive structure 5130 of groove interface construction 5128 includes U-shaped metal layer 5134, in entire U-shapedOn metal layer 5134 and the T shape metal layer 5136 of top and the third metal layer 5138 on T shape metal layer 5136.GrooveThe insulating cover 5128 of contact structures 5126 is on third metal layer 5138.In one suchembodiment, third metal layer5138 and U-shaped metal layer 5134 include titanium, and T shape metal layer 5136 include cobalt.In specific such embodiment, T shapeMetal layer 5136 further comprises carbon.
In embodiment, metal silicide layer 5140 directly the conductive structure 5130 of groove interface construction 5126 with partly leadBetween body source electrode or drain region 5124.In one suchembodiment, metal silicide layer 5140 includes titanium and silicon.In spyIn fixed such embodiment, semiconductor source electrode or drain region 5124 are N-type semiconductor source electrode or drain region.In another realityIt applies in example, metal silicide layer 5140 includes nickel, platinum and silicon.In specific such embodiment, semiconductor source electrode or drain electrodeRegion 5124 is P-type semiconductor source electrode or drain region.In another specific such embodiment, metal silicide layer is into oneStep includes germanium.
In embodiment, with reference to Figure 51 D, first grid electricity of the conductive through hole 5150 on the top 5102A of fin 5102In a part of pole 5108 and it is electrically connected to the part.Conductive through hole 5150 is in the insulating cover 5116 of first gate electrode 5108In opening 5152 in.In one suchembodiment, conductive through hole 5150 is in the insulating cover of groove interface construction 5126The conductive structure 5130 of groove interface construction 5126 is still not electrically connected in 5128 a part.In specific such implementationIn example, conductive through hole 5150 is in the part 5154 of the insulating cover 5128 of groove interface construction 5126 being etched.
In embodiment, with reference to Figure 51 E, conductive through hole 5160 is in a part of groove interface construction 5126 and is electrically connectedIt is connected to the part.Conductive through hole is in the opening 5162 of the insulating cover 5128 of groove interface construction 5126.As oneIn embodiment, conductive through hole 5160 is in a part of the insulating cover 5116 of the first and second gate electrodes 5108 and 5110 stillIt is not electrically connected to the first and second gate electrodes 5108 and 5110.In specific such embodiment, conductive through hole 5160 is inIn the part 5164 of the insulating cover 5116 of first and second gate electrodes 5108 and 5110 being etched.
1E referring again to Fig. 5, in embodiment, conductive through hole 5160 are with identical with the conductive through hole 5150 of Figure 51 DSecond conductive through hole of structure.In one suchembodiment, such second conductive through hole 5160 and conductive through hole 5150Isolation.In another such embodiment, such second conductive through hole 5160 merges short to form electricity with conductive through hole 5150Road contact portion 5170, as described in Figure 51 F.
Method and structure described herein, which can enable to be formed, can not be manufactured or be difficult to using other methods to makeThe other structures or device made.In the first example, Figure 52 A instantiate according to another embodiment of the present disclosure have be deployed inThe plan view of another semiconductor devices of gate contact through-hole on the live part of grid.With reference to Figure 52 A, semiconductor junctionStructure or device 5200 include the multiple gate structure 5208A-5208C to cross one another with multiple trench contact portion 5210A and 5210B(these features are deployed in above the active region of substrate, and substrate is not shown).The shape on the live part of gate structure 5208BAt gate contact through-hole 5280.Gate contact through-hole 5280 is further deployed on the live part of gate structure 5208C, fromAnd coupled gates structure 5208B and 5208C.It is to be appreciated that can by using trench contact portion isolation cap (for example,TILA) it is isolated trench contact portion 5210B between two parties with contact portion 5280.The contact configuration of Figure 52 A, which can provide, to be easier toAdjacent grid line is banded in the method in a layout without making to tie up the metalization layer that route passes through top, therefore energyEnough realize smaller cellar area or less complicated cabling scenario or the two.
In the second example, Figure 52 B instantiates having and couple a pair of of trench contact according to another embodiment of the present disclosureThe plan view of another semiconductor devices of the trench contact through-hole in portion.With reference to Figure 52 B, semiconductor structure or device 5250 includeIt is disposed with multiple these features of gate structure 5258A-5258C(that multiple trench contact portion 5260A and 5260B cross one anotherAbove the active region of substrate, substrate is not shown).Trench contact through-hole 5290 is formed on trench contact portion 5260A.GrooveContact through hole 5290 is further deployed on trench contact portion 5260B, thus Coupled Furrow contact portion 5260A and 5260B.It wantsUnderstand, can be made by using gate isolation cap rock (for example, passing through GILA process) gate structure 5258B between two parties withTrench contact through-hole 5290 is isolated.The contact configuration of Figure 52 B, which can provide, to be easier to adjacent trench contact portion being banded in oneWithout making to tie up route across the method for the metalization layer on top in a layout, thus can be realized smaller cellar area orThe less complicated cabling scenario of person or the two.
Several deposition operations can be used to manufacture the insulating cap for gate electrode, and as a result, insulating capIt may include the product of more deposition process.As an example, Figure 53 A-53E instantiates expression according to an embodiment of the present disclosureManufacture the cross section of the various operations in the method with the integrated circuit structure of gate stack of the insulating cap containing superpositionView.
With reference to Figure 53 A, initial structure 5300 includes the gate stack 5304 above substrate or fin 5302.Gate stack5304 include gate dielectric layer 5306, conformal electrically conductive layers 5308 and conductive filling material 5310.In embodiment, grid electricity is situated betweenMatter layer 5306 be using atomic layer deposition (ALD) process formed high k gate dielectric layer, and conformal electrically conductive layers be usingThe work-function layer that ALD process is formed.In one suchembodiment, such as hot or chemical silica or silicon oxide layer etcHeat or chemical oxide layer 5312 between substrate or fin 5302 and gate dielectric layer 5306.Such as silicon nitride spacer portionEtc the adjacent gate stack 5304 of dielectric spacer portion 5314 side wall.Dielectric gate stacks 5304 and dielectric spacer portion5314 are accommodated in interlayer dielectric (ILD) layer 5316.In embodiment, at using replacement gate and replacement gate dielectricReason scheme forms gate stack 5304.Mask 5318 is patterned above gate stack 5304 and ILD layer 5316, withThe opening 5320 of exposure gate stack 5304 is provided.
With reference to Figure 53 B, using one or more selective etch processes, to make include gate dielectric layer 5306, conformal is ledThe gate stack 5304 of electric layer 5308 and conductive filling material 5310 is recessed relative to dielectric spacer portion 5314 and layer 5316.SoMask 5318 is removed afterwards.The recess provides chamber 5322 above the gate stack 5324 of recess.
In another embodiment that do not describe, make conformal electrically conductive layers 5308 and conductive filling material 5310 relative to dielectricSpacer portion 5314 and layer 5316 are recessed, but gate dielectric layer 5306 is not made to be recessed or be allowed to only minimally be recessed.It wantsUnderstand, in other embodiments, is used for the depression treatment using the mask-free method based on high etch-selectivity.
With reference to Figure 53 C, the first deposition process in more deposition process for manufacturing gate insulator cap rock is executed.Use thisFirst deposition process forms first insulating layer 5326 conformal with the structure of Figure 53 B.In embodiment, the first insulating layer 5326Including silicon and nitrogen, for example, the first insulating layer 5326 is silicon nitride (Si3N4) layer, the silicon nitride layer of Silicon-rich, poor silicon silicon nitride layerOr the silicon nitride layer of carbon dope.In embodiment, the first insulating layer 5326 is only partially filled out above the gate stack of recess 5324Chamber 5322 is filled, as depicted.
With reference to Figure 53 D, the first insulating layer 5326 is subjected to etch back process, such as anisotropic etch process, to provide insulationThe first part 5328 of cap rock.The first part 5328 of insulating cap only partially fills above the gate stack of recess 5324Chamber 5322.
With reference to Figure 53 E, additional alternate deposition process and etch back process are executed, until the gate stack 5324 in recessUntil top insulated gate polar cap structure 5330 is filled with chamber 5322.In cross-sectional analysis, gap 5332 it is clear that andIt can indicate the number of the alternate deposition process and etch back process for insulated gate polar cap structure 5330.Shown in Figure 53 EExample in, the presence instruction of three groups of gaps 5332A, 5332B and 5332C are used for four alternatings of insulated gate polar cap structure 5330Deposition process and etch back process.In embodiment, the material of the insulated gate polar cap structure 5330 separated by gap 53325330A, 5330B, 5330C all have identical or substantially the same composition with 5330D.
Such as throughout described herein, substrate can wherein can migrated by being able to bear manufacturing process and chargeSemiconductor material is constituted.In embodiment, substrate described herein is the crystalline substance by forming active region doped with carrierThe bulk substrate that body silicon, silicon/germanium or germanium layer are constituted, described carrier such as, but not limited to phosphorus, arsenic, boron or combinations thereof.At oneIn embodiment, the concentration of the silicon atom in such bulk substrate is greater than 97%.In another embodiment, bulk substrate byThe epitaxial layer grown on different crystal substrate tops is constituted, for example, outside the silicon grown on the bulk silicon monocrystal substrate top of boron-dopingProlong layer.Bulk substrate can be alternatively made of one group of III-V material.In embodiment, bulk substrate is by III-V material structureAt the III-V material such as, but not limited to gallium nitride, gallium phosphide, GaAs, indium phosphide, indium antimonide, InGaAsP, arsenicGallium aluminium, InGaP or combinations thereof.In one embodiment, bulk substrate is made of III-V material, and charge-carrier dopant objectForeign atom is the atom of such as, but not limited to carbon, silicon, germanium, oxygen, sulphur, selenium or tellurium.
Such as throughout described herein, the area of isolation of such as shallow plough groove isolation area or sub- fin area of isolation etc canWith by be suitable for make the part of permanent gate structure be finally electrically isolated or facilitate with following bulk substrate its be isolated or fitIt is constituted in the material for being isolated in the active region (such as isolation fin active region) formed in following bulk substrate.For example,In one embodiment, area of isolation is made of one or more dielectric material layers, and the dielectric substance is such as but unlimitedIn silica, silicon oxynitride, silicon nitride, carbon dope silicon nitride or combinations thereof.
Such as throughout described herein, grid line or gate structure can be by including gate dielectric layer and gate electrode layerGate electrode stack is constituted.In embodiment, the gate electrode in gate electrode stack is made of metal gates, and gate dielectric layerIt is made of hafnium.For example, in one embodiment, gate dielectric layer is made of following material, such as, but not limited to aoxidizeHafnium, nitrogen oxidation hafnium, hafnium suicide, lanthana, zirconium oxide, zirconium silicide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanates, yttrium oxide,Aluminium oxide, lead oxide scandium tantalum, lead zinc niobate or combinations thereof.In addition, a part of gate dielectric layer may include by topThe native oxide layer that several layers of semiconductor substrates are formed.In embodiment, gate dielectric layer by top high k part and underPortion is constituted, and lower part is made of the oxide of semiconductor material.In one embodiment, gate dielectric layer by top section oxygenThe silica or silicon oxynitride for changing hafnium and bottom part are constituted.In some embodiments, a part of gate-dielectric is" U-shaped " structure comprising be arranged essentially parallel to the bottom part and the two of the top surface for being substantially perpendicular to substrate of substrate surfaceA sidewall sections.
In one embodiment, gate electrode is made of metal layer, the metal layer such as, but not limited to metal nitride, goldBelong to carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminium, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide.In certain embodiments, gate electrode is by the packing material structure of the NOT function function sets formed above metal work function setting layerAt.Gate electrode layer may include p-type workfunction metal or N-type workfunction metal, this, which depends on the transistor, should be PMOS stillNMOS transistor.In some embodiments, gate electrode layer may include the stacking of two or more metal layers, one of themOr multiple metal layers are workfunction layers and at least one metal layer is conductive filler layer.It, can be with for PMOS transistorMetal for gate electrode includes but is not limited to ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxide, such as ru oxide.P-type goldBelonging to layer will make it possible to be formed the PMOS gate electrode with the work function between about 4.9 eV and about 5.2 eV.For NMOS crystalline substanceBody pipe, the metal that can be used for gate electrode includes but is not limited to the alloy and these gold of hafnium, zirconium, titanium, tantalum, aluminium, these metalsThe carbide of category, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminium carbide.N-type metal layer will make it possible to be formedNMOS gate electrode with the work function between about 3.9 eV and about 4.2 eV.In some embodiments, gate electrode can be withIncluding " U-shaped " structure comprising be arranged essentially parallel to the bottom part of substrate surface and be substantially perpendicular to the top surface of substrateTwo side walls part.In another embodiment, it can be simply flat for forming at least one of metal layer of gate electrodeSurface layer is arranged essentially parallel to the top surface of substrate and does not include the sidewall sections for being substantially perpendicular to the top surface of substrate.In the other embodiment of the disclosure, gate electrode may include the combination of the non-U-shaped structure of U-shaped structure and plane.For example,Gate electrode may include the one or more U-shaped metal layers being formed on the top of the layer of non-U-shaped of one or more planes.
Such as throughout described herein, spacer portion associated with grid line or gate electrode stack can be by being suitable for finally makingPermanent gate structure is electrically isolated with adjacent electrically conducting contact (such as self-aligning contact portion) or facilitates its material being isolatedMaterial is constituted.For example, in one embodiment, spacer portion is made of dielectric substance, the dielectric substance is such as, but not limited toSilica, silicon oxynitride, silicon nitride or carbon dope silicon nitride.
In embodiment, method described herein can be related to being formed and particularly well be aligned with existing gate patternContact patterns and eliminate the uses of the lithography operations with extreme closely registration budget simultaneously.In such embodimentIn, this method makes it possible for the wet etching of substantially high selectivity (for example, losing compared to dry etching or plasmaCarve) Lai Shengcheng contact openings.In embodiment, by being connect using existing gate pattern combination contact plunger lithography operations to be formedTouch pattern.In one suchembodiment, this method make it possible to eliminate to as used in other methods script toGenerate the needs of the conclusive lithography operations of contact patterns.In embodiment, discretely patterned trench does not contact grid, andIt is the formation trench contact grid between polymerization (grid) line.For example, in one suchembodiment, in grid patternAfter changing but trench contact grid is formed before grid cutting.
Furthermore, it is possible to manufacture gate stack structure by replacement gate process.In such scheme, it can remove allSuch as the dummy gate electrode material of polysilicon or silicon nitride column material etc, and substituted with permanent gate material.One thisIn the embodiment of sample, also form permanent gate dielectric layer in this process, as with from handling implemented phase earlierInstead.In embodiment, dummy gate electrode is removed by dry etching or wet etch process.In one embodiment, dummy gate electrodeIt is made of polysilicon or amorphous silicon, and is using including SF6Use dry etch process removal.In another implementationIn example, dummy gate electrode is made of polysilicon or amorphous silicon, and is using using including aqueous NH4OH or tetramethylammonium hydroxideWet etch process removal.In one embodiment, dummy gate electrode is made of silicon nitride, and is using including aqueous phosphorusThe wet etching removal of acid.
In embodiment, one or more method described herein is it is essentially contemplated that dummy gate electrode and replacement gate mistakeJourney combination virtual connection contact portion realizes structure with substitution contact portion process.In one suchembodiment, in replacement gate processExecute substitution contact portion process later to allow at least part to permanent gate stack to carry out high annealing.For example,In specific such embodiment, for example, after forming gate dielectric layer greater than about 600 degrees Celsius at a temperature of to foreverAt least part of long property gate structure executes annealing.Annealing is executed before forming permanent contact portion.
In some embodiments, gate contact is placed on area of isolation by the arrangement of semiconductor structure or deviceGrid line or gate stack part on.However, such arrangement may be considered as ineffectually having used arrangement space.?In another embodiment, the contact structures of the part for the gate electrode that there is semiconductor devices contact to be formed on live part.OneAs for, be on the live part of grid and form gate contacting structure in layer identical with trench contact through-holeBefore (such as through-hole) (such as in addition to this), one or more other embodiments of the present disclosure include the ditch being aligned first using gridSlot contact process.Such process may be implemented formed groove interface construction with for semiconductor structure manufacture (such asIC manufacturing).In embodiment, trench contact pattern is formed as being aligned with existing gate pattern.In contrast, otherMethod generally involves additional photoetching process, is closely registrated photolithography contact pattern wherein etching in conjunction with selective exposure portionTo existing gate pattern.For example, another process may include the patterning to polymerization (grid) grid, wherein separating patternContact characteristic.
It is to be appreciated that and the non-required all aspects for practicing procedures described above can just fall into embodiment of the disclosureSpirit and scope.For example, in one embodiment, completely without being to manufacture grid on the live part of gate stackDummy gate electrode is formed before contact portion.Above-described gate stack can actually when being initially formed as permanent gridIt stacks.Further, it is possible to use process described herein manufactures one or more semiconductor devices.The semiconductor devices canTo be transistor or similar device.For example, in embodiment, the semiconductor devices is the metal oxygen for logic or memoryCompound semiconductor (MOS) transistor or bipolar transistor.In addition, in embodiment, the semiconductor devices has three-dimensionalFramework, such as three gated devices, independent access type dual-gated device or FIN-FET.One or more embodiments can forManufacturing semiconductor devices are particularly useful under 10 nanometers of (10 nm) technology nodes, sub-10 nano (10 nm) technology node.
The additional or intermediary operation manufactured for FEOL layers or structure may include standard micro manufacturing process, such as lightCarve, etching, film deposition, planarizing (such as chemically mechanical polishing (CMP)), diffusion, metering, using sacrificial layer, use etchingStop-layer uses planarizing stop-layer or any other movement associated with micromodule manufacture.In addition to be understoodIt is that the process operation for the description of aforementioned process process can be practiced in the order to replace, does not need to execute each behaviourMake, can perhaps execute additional process operation or the two is carried out.
It is to be appreciated that in above example FEOL embodiment, in embodiment, directly by 10 nanometers or Asia 10 is receivedThe processing of meter Jie Dian is realized into fabrication scheme, and obtained structure is as technology humanized power.In other embodiments, may be usedFEOL is driven to consider with process demand by 10 nanometers of BEOL or sub-10 nano.For example, for FEOL layers and the material of deviceMaterial selection and layout may need to be adapted to BEOL processing.In one suchembodiment, material selection and grid pile superimposedStructure is selected to be adapted to the high desnity metal of BEOL layer, such as passes through BEOL layer to reduce being formed in FEOL layersHigh desnity metal and the edge capacitance in the transistor arrangement that is coupled together.
Back-end process (BEOL) layer of integrated circuit is typically included in the conductive microelectronic structure referred in the art as through-holeStructure, by above through-hole metal wire or other interconnection be electrically connected to metal wire below through-hole or other interconnection.It can pass throughPhotoetching process forms through-hole.Typically, can on dielectric layer spin coating photoresist layer, can make photoresist layer pass through through schemingThe mask of case and be exposed to patterned actinic radiation, and then can make the layer being exposed development so as in photoresist layerMiddle formation opening.Next, can be etched in the dielectric layer by using the opening of this in photoresist layer as etching maskOpening for through-hole.The opening is properly termed as via openings.Finally, one or more metals or other conductive materials can be usedTo fill via openings to form through-hole.
The size of through-hole and interval are gradually reduced, and at least for certain form of integrated circuit (for example, advanced micro-Processor, chipset component, graphic chips etc.) for, it is expected that the size of through-hole will continue to be gradually reduced with future is spaced in.WhenPhotoetching process in this way is with extremely small pitch come when patterning to extremely small through-hole, there are several challenges.OneA such challenge is the superposition between the superposition between through-hole and the interconnection of superposition and through-hole and following landing interconnection,In general need to be controlled into the high tolerance of approximate a quarter through-hole pitch.Since the scale of through-hole pitch is with the timePassage and it is smaller and smaller, therefore the superposition tolerance is intended to the even greater rate can be able to catch up with than lithographic equipment with itScale.
Another such challenge is that the critical size of via openings is generally intended to the resolution ratio than photolithography scannerAbility quickly scales.In the presence of the contraction technology of the critical size for shrinking via openings.However, shrinkage be intended to byThe limitation of minimum vias pitch, and by contraction process enough optical proximity effects amendment (OPC) neutral point, without showingLand compromise line width roughness (LWR) or critical size inhomogeneities (CDU) or both ability limitation.As anotherChallenge is that the characteristic --- LWR or CDU or both --- of photoresist generally requires the critical size with via openingsReduce and improve, to maintain the identical percent of total of critical size budget.
Above-mentioned factor also consider back-end process (BEOL) metal interconnection structure metal wire between non-conductive space orPlacement and the scaling for interrupting (referred to as " plug ", " dielectric plug " or " metal wire end ") are related.Therefore, for manufacturing goldBelong to and needs to improve in the field of the back segment metallization manufacturing technology of line, metal throuth hole and dielectric plug.
In another aspect, realize pitch quartering process with mutual to form BEOL for patterned trench in the dielectric layerLink structure.In accordance with an embodiment of the present disclosure, divide using pitch for manufacturing metal wire in BEOL fabrication scheme.Embodiment canEnable to realize the continuously zooming of the pitch of the metal layer of the resolution capabilities beyond prior art lithographic equipment.
Figure 54 is according to an embodiment of the present disclosure for manufacturing the pitch quartering process of the groove for interconnection structure5400 schematic diagram.
With reference to Figure 54, at operation (a), pillar feature 5402 is formed using direct photoetching.For example, can be to photoresist layerOr it stacks and is patterned, and transfer the pattern onto hard mask material to ultimately form pillar feature 5402.It can be used allAs the standard of 193 immersion lithographies etc lithographic processing techniques come pattern be used to form pillar feature 5402 photoresist layer orIt stacks.Then the side wall for abutting pillar feature 5402 forms the first spacer portion feature 5404.
At operation (b), pillar feature 5402 is removed only to leave the first spacer portion feature 5404.When at this stage, theOne spacer portion feature 5404 is effectively half pitch masks, for example, indicating that pitch halves process.First spacer portion feature 5404It is used directly for pitch quartering process, or can first be transferred to the pattern of the first spacer portion feature 5404 new hardIn mask material, wherein depicting latter method.
At operation (c), the pattern of the first spacer portion feature 5404 is transferred in new hard mask material to formOne spacer portion feature 5404 '.Then the side wall for abutting the first spacer portion feature 5404 ' forms the second spacer portion feature 5406.
At operation (d), the first spacer portion feature 5404 ' is removed only to leave the second spacer portion feature 5406.In the rankDuan Shi, the second spacer portion feature 5406 is effectively a quarter pitch masks, for example, indicating pitch quartering process.
At operation (e), the second spacer portion feature 5406 is used as mask and carrys out the pattern in dielectric or hard mask layerChange multiple grooves 5408.The groove may finally be filled with conductive material to lead to be formed in the metalization layer of integrated circuitIt is electrically interconnected.Groove 5408 with label " B " corresponds to pillar feature 5402.Groove 5408 with label " S " corresponds to theOne spacer portion feature 5404 or 5404 '.Groove 5408 with label " C " corresponds to the complementary region between pillar feature 54025407。
It is to be appreciated that since each groove in the groove 5408 of Figure 54 has the pillar feature corresponding to Figure 545402, one patterning beginning in the first spacer portion feature 5404 or 5404 ' or complementary region 5407, therefore these are specialThe width of sign and/or the difference in pitch can be revealed as in the finally formed conductive interconnection in the metalization layer of integrated circuitPitch quartering process product.As an example, Figure 55 A instantiates the use pitch quartering according to an embodiment of the present disclosureThe viewgraph of cross-section of the metalization layer of scheme manufacture.
With reference to Figure 55 A, integrated circuit structure 5500 includes interlayer dielectric (ILD) layer 5504 above substrate 5502.Multiple conductive interconnection lines 5506 are in ILD layer 5504, and by the part of ILD layer 5504 by the multiple conductive interconnection lineEach conductive interconnection line in 5506 be separated from each other.Each conductive interconnection line packet in the multiple conductive interconnection line 5506Include electrically conductive barrier 5508 and conductive filling material 5510.
With reference to both Figure 54 and 55A, conductive interconnection line 5506B is formed in the trench from pillar feature 5402Pattern.Conductive interconnection line 5506S is formed with the pattern from the first spacer portion feature 5404 or 5404 ' in the trench.It leadsElectrical interconnection line 5506C is formed with the pattern from the complementary region 5407 between pillar feature 5402 in the trench.
5A referring again to Fig. 5, in embodiment, the multiple conductive interconnection line 5506 include the with a width (W1)One interconnection line 5506B.Second interconnection line 5506S close together first interconnection line 5506B, the second interconnection line 5506S have and theThe different width (W2) of the width (W1) of one interconnection line 5506B.The close together second interconnection line 5506S of third interconnection line 5506C,Third interconnection line 5506C has a width (W3).4th interconnection line (second 5506S) close together third interconnection line 5506C,4th interconnection line has with the width (W2) of the second interconnection line 5506S identical width (W2).5th interconnection line (second5506B) close together 4th interconnection line (second 5506S), the 5th interconnection line (second 5506B) have and the first interconnection lineThe identical width (W1) of the width (W1) of 5506B.
In embodiment, the width (W3) of third interconnection line 5506C is different from the width (W1) of the first interconnection line 5506B.In one suchembodiment, the width (W3) of third interconnection line 5506C is different from the width of the second interconnection line 5506S(W2).In another such embodiment, the width (W3) of third interconnection line 5506C and the width of the second interconnection line 5506S(W2) identical.In another embodiment, the width (W1) of the width (W3) of third interconnection line 5506C and the first interconnection line 5506BIt is identical.
In embodiment, the pitch (P1) between the first interconnection line 5506B and third interconnection line 5506C and the second interconnection linePitch (P2) between 5506S and the 4th interconnection line (second 5506S) is identical.In another embodiment, the first interconnection linePitch (P1) and the second interconnection line 5506S and the 4th interconnection line (second between 5506B and third interconnection line 5506CPitch (P2) between 5506S) is different.
5A referring again to Fig. 5, in another embodiment, the multiple conductive interconnection line 5506 include having a width (W1)The first interconnection line 5506B.Second interconnection line 5506S close together first interconnection line 5506B, the second interconnection line 5506S haveOne width (W2).Third interconnection line 5506C close together second interconnection line 5506S, third interconnection line 5506C have with first mutuallyThe different width (W3) of the width (W1) of line 5506B.4th interconnection line (second 5506S) close together third interconnection line5506C, the 4th interconnection line have with the width (W2) of the second interconnection line 5506S identical width (W2).5th interconnection line (secondA 5506B) close together 4th interconnection line (second 5506S), the 5th interconnection line (second 5506B) has and the first interconnectionThe identical width (W1) of the width (W1) of line 5506B.
In embodiment, the width (W2) of the second interconnection line 5506S is different from the width (W1) of the first interconnection line 5506B.In one suchembodiment, the width (W3) of third interconnection line 5506C is different from the width of the second interconnection line 5506S(W2).In another such embodiment, the width (W3) of third interconnection line 5506C and the width of the second interconnection line 5506S(W2) identical.
In embodiment, the width (W2) of the second interconnection line 5506S is identical as width (W1) of the first interconnection line 5506B.In embodiment, the pitch (P1) between the first interconnection line 5506B and third interconnection line 5506C and the second interconnection line 5506S andPitch (P2) between 4th interconnection line (second 5506S) is identical.In embodiment, the first interconnection line 5506B and third are mutualPitch between pitch (P1) and the second interconnection line 5506S between line 5506C and the 4th interconnection line (second 5506S)(P2) different.
Figure 55 B instantiates according to an embodiment of the present disclosure in the metallization layer manufactured using pitch quartering schemeUse the viewgraph of cross-section of the metalization layer of the second-class offshoot program manufacture of pitch.
With reference to Figure 55 B, integrated circuit structure 5550 includes the first interlayer dielectric (ILD) layer above substrate 55525554.A conductive interconnection line 5556 more than first is in the first ILD layer 5554, and will by the part of the first ILD layer 5554Each conductive interconnection line more than first in a conductive interconnection line 5556 be separated from each other.In the multiple conductive interconnection line 5556Each conductive interconnection line include electrically conductive barrier 5558 and conductive filling material 5560.Integrated circuit structure 5550 further wrapsInclude the second interlayer dielectric (ILD) layer 5574 above substrate 5552.A conductive interconnection line 5576 more than second is in the 2nd ILDIn layer 5574, and by the part of the second ILD layer 5574 by each conductive interconnection in more than second a conductive interconnection lines 5576Line be separated from each other.Each conductive interconnection line in the multiple conductive interconnection line 5576 includes electrically conductive barrier 5578 and leadsElectric packing material 5580.
In accordance with an embodiment of the present disclosure, 5B referring again to Fig. 5, a kind of method manufacturing integrated circuit structure are included in substrate5552 tops form more than first a conductive interconnection lines 5556 in the first interlayer dielectric (ILD) layer 5554, and more than firstConductive interconnection line 5556 is spaced apart by the first interlayer dielectric (ILD) layer 5554.Use the pitch quartering mistake based on spacer portionJourney (for example, method of operation (a)-(e) description of connection Figure 54) forms a conductive interconnection line 5556 more than first.First5554 top of ILD layer forms more than second a conductive interconnection lines 5576, and a conductive interconnection more than second in the second ILD layer 5574Line 5576 is spaced apart by the second ILD layer 5574.Process is halved (for example, the behaviour of connection Figure 54 using the pitch based on spacer portionMake the method for (a) and (b) description) form a conductive interconnection line 5576 more than second.
In embodiment, a conductive interconnection line 5556 more than first have between the close adjacent line less than 40 nanometersPitch (P1).A conductive interconnection line 5576 more than second has 44 nanometers or bigger of the pitch between close adjacent line(P2).In embodiment, it is to be based on that the pitch quartering process based on spacer portion and the pitch based on spacer portion, which halve process,Immersion 193nm photoetching process.
In embodiment, each conductive interconnection line more than first in a conductive interconnection line 5554 is served as a contrast including the first conductive barrierPad 5558 and the first conductive filling material 5560.Each conductive interconnection line more than second in a conductive interconnection line 5556 includes secondConductive barrier liner 5578 and the second conductive filling material 5580.In one suchembodiment, the first conductive filling material5560 is upper different from the second conductive filling material 5580 in composition.In another embodiment, the first conductive filling material 5560 existsIt is identical as the second conductive filling material 5580 in composition.
Although not describing, in embodiment, this method further comprises above the second ILD layer 5574 in thirdThe multiple conductive interconnection lines of third are formed in ILD layer, and the multiple conductive interconnection lines of third are spaced apart by third ILD layer.Do not makeThe multiple conductive interconnection lines of third are formed in the case where being divided with pitch.
Although not describing, in embodiment, this method further comprises forming more than second a conductive interconnection linesBefore 5576, the multiple conductive interconnection lines of third are formed in third ILD layer above the first ILD layer 5554, and third is multipleConductive interconnection line is spaced apart by third ILD layer.Using forming the multiple conductions of third based on the pitch quartering process of spacer portionInterconnection line.In one suchembodiment, after forming more than second a conductive interconnection lines 5576, in the second ILD layer 5574Top forms more than the 4th a conductive interconnection lines in the 4th ILD layer, and a conductive interconnection line more than the 4th is by the 4th ILD layer intervalIt opens.A conductive interconnection line more than the 4th is formed using process is halved based on the pitch of spacer portion.In embodiment, such sideMethod further comprises forming more than the 5th a conductive interconnection lines in the 5th ILD layer above the 4th ILD layer, and more than the 5th is ledElectrical interconnection line is spaced apart by the 5th ILD layer, forms more than the 5th conduction mutually using process is halved based on the pitch of spacer portionLine.Then more than the 6th a conductive interconnection lines are formed in the 6th ILD layer above the 5th ILD layer, and more than the 6th conductiveInterconnection line is spaced apart by the 6th ILD layer, forms a conductive interconnection more than the 6th using process is halved based on the pitch of spacer portionLine.Then more than the 7th a conductive interconnection lines are formed in the 7th ILD layer above the 6th ILD layer, and more than the 7th conductive mutualLine is spaced apart by the 7th ILD layer.More than the 7th a conductive interconnection lines are formed under the case where dividing without using pitch.
In another aspect, metal wire is formed between each metalization layer and is varied.Such arrangement is properly termed as differentMatter metalization layer.In embodiment, the conductive filling material for relatively large interconnection line is used copper as, and is made using cobaltFor the conductive filling material for relatively small interconnection line.Lesser line with cobalt as packing material can provide reductionElectromigration and maintain low-resistivity simultaneously.Copper is replaced to can solve about scaling copper wire for lesser interconnection line using cobaltThe problem of, wherein electrically conductive barrier consumes larger amount of interconnection volume and copper is reduced, this substantially hampers normally mutual with copperThe associated advantage of line.
In the first example, Figure 56 A instantiates according to an embodiment of the present disclosure in a kind of utilization metal wire compositionMetallization layer the metalization layer constituted using different metal wire integrated circuit structure viewgraph of cross-section.
With reference to Figure 56 A, integrated circuit structure 5600 is included in 5602 top of substrate in the first interlayer dielectric (ILD) layerMore than first a conductive interconnection lines 5606 being spaced apart in 5604 and by the first interlayer dielectric (ILD) layer 5554.Conductive interconnectionA 5606A in line is shown as the through-hole 5607 for having following.Each conduction more than first in a conductive interconnection line 5606Interconnection line includes the first conductive barrier materials 5608 of the side wall and bottom along the first conductive filling material 5610.
A conductive interconnection line 5616 more than second is above the first ILD layer 5604 in the second ILD layer 5614 and by secondILD layer 5614 is spaced apart.A 5616A in conductive interconnection line is shown as the through-hole 5617 for having following.More than second is ledEach conductive interconnection line in electrical interconnection line 5616 include along the second conductive filling material 5620 side wall and bottom secondConductive barrier materials 5618.Second conductive filling material 5620 is upper different from the first conductive filling material 5610 in composition.
In embodiment, the second conductive filling material 5620 mainly includes copper, and the first conductive filling material 5610 is mainIt to include cobalt.In one suchembodiment, the first conductive barrier materials 5608 are constituting upper and the second conductive barrier materials5618 is different.In another such embodiment, the first conductive barrier materials 5608 are constituting upper and the second conductive barrier materials5618 is identical.
In embodiment, the first conductive filling material 5610 includes the copper with the first concentration of dopant impurities atom,And the second conductive filling material 5620 includes the copper with the second concentration of dopant impurities atom.Dopant impurities atomSecond concentration is less than the first concentration of dopant impurities atom.In one suchembodiment, dopant impurities atom is selected fromGroup including aluminium (Al) and manganese (Mn).In embodiment, the first conductive barrier materials 5610 and the second conductive barrier materials5620 compositions having the same.In embodiment, the first conductive barrier materials 5610 and the second conductive barrier materials 5620 haveDifferent compositions.
6A referring again to Fig. 5, the second ILD layer 5614 are on etching stopping layer 5622.Conductive through hole 5617 is in secondIn ILD layer 5614 and in the opening in etching stopping layer 5622.In embodiment, 5604 He of the first and second ILD layers5614 include silicon, carbon and oxygen, and etching stopping layer 5622 includes silicon and nitrogen.In embodiment, a conductive interconnection line more than firstEach conductive interconnection line in 5606 has the first width (W1), and each conduction more than second in a conductive interconnection line 5616Interconnection line has the second width (W2) greater than the first width (W1).
In the second example, Figure 56 B instantiate it is according to an embodiment of the present disclosure have be coupled to using a kind of metal wireThe viewgraph of cross-section of the integrated circuit structure for the metalization layer of the metalization layer of composition constituted using different metal wire.
With reference to Figure 56 B, integrated circuit structure 5650 is included in 5652 top of substrate in the first interlayer dielectric (ILD) layerMore than first a conductive interconnection lines 5656 being spaced apart in 5654 and by the first interlayer dielectric (ILD) layer 5654.Conductive interconnectionA 5656A in line is shown as the through-hole 5657 for having following.Each conduction more than first in a conductive interconnection line 5656Interconnection line includes the first conductive barrier materials 5658 of the side wall and bottom along the first conductive filling material 5660.
A conductive interconnection line 5666 more than second on the first ILD layer 5654 in the second ILD layer 5664 and by secondILD layer 5664 is spaced apart.A 5666A in conductive interconnection line is shown as the through-hole 5667 for having following.More than second is ledEach conductive interconnection line in electrical interconnection line 5666 include along the second conductive filling material 5670 side wall and bottom secondConductive barrier materials 5668.Second conductive filling material 5670 is upper different from the first conductive filling material 5660 in composition.
In embodiment, conductive through hole 5657 is in the independent conductive interconnection in more than first a conductive interconnection lines 5656On line 5656B and it is electrically coupled to conductive interconnection line 5656B, thus by independent one in more than second a conductive interconnection lines 5666A conductive interconnection line 5666A is electrically coupled to the independent conductive interconnection line 5656B more than first in a conductive interconnection line 5656.?In embodiment, each conductive interconnection line more than first in a conductive interconnection line 5656 along a first direction 5698(for example, into pageThe neutralization in face is left except the page), and each conductive interconnection line more than second in a conductive interconnection line 5666 is along with firstThe orthogonal second direction 5699 in direction 5698, as depicted.In embodiment, conductive through hole 5667 includes along secondThe side wall of conductive filling material 5670 and the second conductive barrier materials 5668 of bottom, as depicted.
In embodiment, the second ILD layer 5664 is on the etching stopping layer 5672 on the first ILD layer 5654.Conduction is logicalHole 5667 is in the second ILD layer 5664 and in the opening in etching stopping layer 5672.In embodiment, first and secondILD layer 5654 and 5664 includes silicon, carbon and oxygen, and etching stopping layer 5672 includes silicon and nitrogen.In embodiment, more than firstEach conductive interconnection line in conductive interconnection line 5656 has the first width (W1), and more than second in a conductive interconnection line 5666Each conductive interconnection line have greater than the first width (W1) the second width (W2).
In embodiment, the second conductive filling material 5670 mainly includes copper, and the first conductive filling material 5660 is mainIt to include cobalt.In one suchembodiment, the first conductive barrier materials 5658 are constituting upper and the second conductive barrier materials5668 is different.In another such embodiment, the first conductive barrier materials 5658 are constituting upper and the second conductive barrier materials5668 is identical.
In embodiment, the first conductive filling material 5660 includes the copper with the first concentration of dopant impurities atom,And the second conductive filling material 5670 includes the copper with the second concentration of dopant impurities atom.Dopant impurities atomSecond concentration is less than the first concentration of dopant impurities atom.In one suchembodiment, dopant impurities atom is selected fromGroup including aluminium (Al) and manganese (Mn).In embodiment, the first conductive barrier materials 5660 and the second conductive barrier materials5670 compositions having the same.In embodiment, the first conductive barrier materials 5660 and the second conductive barrier materials 5670 haveDifferent compositions.
Figure 57 A-57C instantiates the tool of the structure according to an embodiment of the present disclosure for being suitable for contacting Figure 56 A and 56B descriptionThere is the viewgraph of cross-section of each interconnection line of various blocker pads and conductive capping structure arrangement.
With reference to Figure 57 A, the interconnection line 5700 in dielectric layer 5701 includes conductive barrier materials 5702 and conductive fillMaterial 5704.Conductive barrier materials 5702 include outer layer 5706 and close conductive fill material far from conductive filling material 5704The internal layer 5708 of material 5704.In embodiment, conductive filling material includes cobalt, and outer layer 5706 includes titanium and nitrogen, and internal layer5708 include tungsten, nitrogen and carbon.In one suchembodiment, outer layer 5706 has about 2 nanometers of thickness, and internal layer5708 have about 0.5 nanometer of thickness.In another embodiment, conductive filling material includes cobalt, and outer layer 5706 includes tantalum, andAnd internal layer 5708 includes ruthenium.In one suchembodiment, outer layer 5706 further comprises nitrogen.
With reference to Figure 57 B, the interconnection line 5720 in dielectric layer 5721 includes conductive barrier materials 5722 and conductive fillMaterial 5724.Conductive cap layer 5730 is on the top of conductive filling material 5724.In one suchembodiment, conductive cap layer5730 further on the top of conductive barrier materials 5722, as depicted.In another embodiment, conductive cap layer5730 on the top of conductive barrier materials 5722.In embodiment, conductive cap layer 5730 includes mainly cobalt, and conduction is filled outFilling material 5724 mainly includes copper.
With reference to Figure 57 C, the interconnection line 5740 in dielectric layer 5741 includes conductive barrier materials 5742 and conductive fillMaterial 5744.Conductive barrier materials 5742 include outer layer 5746 and close conductive fill material far from conductive filling material 5744The internal layer 5748 of material 5744.Conductive cap layer 5750 is on the top of conductive filling material 5744.In one embodiment, conductive capLayer 5750 is only on the top of conductive filling material 5744.However in another embodiment, conductive cap layer 5750 is further being ledOn the top of the internal layer 5748 of resistance obstructing material 5742, i.e., at position 5752.In one suchembodiment, conductive cap layer5750 further on the top of the outer layer 5746 of conductive barrier materials 5742, i.e., at position 5754.
In embodiment, with reference to Figure 57 B and 57C, a kind of method manufacturing integrated circuit structure is included in shape on substrateAt interlayer dielectric (ILD) layer 5721 or 5741.ILD layer is spaced apart and forms multiple conductive interconnection lines in groove therein5720 or 5740, the correspondence of each conductive interconnection line in the trench in the multiple conductive interconnection line 5720 or 5740A groove in.Multiple conductive interconnection lines are formed by following procedure: being formed lead in the bottom and side wall of groove firstResistance obstructing material 5722 or 5724, and conductive filling material is then formed in conductive barrier materials 5722 or 5742 respectively5724 or 5744, and fill groove, wherein conductive barrier materials 5722 or 5742 respectively along conductive filling material 5730 or5750 bottom and along its side wall.Then conductive filling material 5724 or 5744 is handled with including the gas of oxygen and carbonTop.After with the gas treatment for the including oxygen and carbon top of conductive filling material 5724 or 5744, filled out respectively in conductionIt fills on the top of material 5724 or 5744 and forms conductive cap layer 5730 or 5750.
In one embodiment, include with the top for the gas treatment conductive filling material 5724 or 5744 for including oxygen and carbonThe top of conductive filling material 5724 or 5744 is handled with carbon monoxide (CO).In one embodiment, conductive filling material5724 or 5744 include copper, and the packet of conductive cap layer 5730 or 5750 is formed on the top of conductive filling material 5724 or 5744It includes using chemical vapor deposition (CVD) and forms the layer including cobalt.In one embodiment, conductive cap layer 5730 or 5750 is by shapeAt the top on the top of conductive filling material 5724 or 5744, without being formed in conductive barrier materials 5722 or 5742On.
In one embodiment, forming conductive barrier materials 5722 or 5744 includes being formed in the bottom and side wall of grooveFirst conductive layer, the first conductive layer include tantalum.First of the first conductive layer is formed using atomic layer deposition (ALD) firstPoint, and then using physical vapor deposition (PVD) and then to form the second part of the first conductive layer.It is real as oneIt applies in example, forming conductive barrier materials further comprises forming second on the first conductive layer in the bottom and side wall of groove to leadElectric layer, the second conductive layer includes ruthenium, and conductive filling material includes copper.In one embodiment, the first conductive layer is furtherIncluding nitrogen.
Figure 58 instantiates two had in a kind of metal wire of utilization composition and smaller pitch according to an embodiment of the present disclosureBeing constituted using different metal wire for a metallization layer is transversal with the integrated circuit structure of four metalization layers of pitchFace view.
With reference to Figure 58, integrated circuit structure 5800 is included in 5801 top of substrate in the first interlayer dielectric (ILD) layerMore than first a conductive interconnection lines 5804 being spaced apart in 5802 and by the first interlayer dielectric (ILD) layer 5802.More than firstEach conductive interconnection line in conductive interconnection line 5804 include along the first conductive filling material 5808 side wall and bottomOne conductive barrier materials 5806.Each conductive interconnection line more than first in a conductive interconnection line 5804 along a first direction 5898(for example, the neutralization into the page is left except the page).
A conductive interconnection line 5814 more than second is above the first ILD layer 5802 in the second ILD layer 5812 and by secondILD layer 5812 is spaced apart.Each conductive interconnection line more than second in a conductive interconnection line 5814 includes along the first conductive fillThe side wall of material 5808 and the first conductive barrier materials 5806 of bottom.Each conduction more than second in a conductive interconnection line 5814Interconnection line is along the second direction 5899 orthogonal with first direction 5898.
The multiple conductive interconnection lines 5824 of third are above the second ILD layer 5812 in third ILD layer 5822 and by thirdILD layer 5822 is spaced apart.Each conductive interconnection line in the multiple conductive interconnection lines 5824 of third includes along the second conductive fillThe side wall of material 5828 and the second conductive barrier materials 5826 of bottom.Second conductive filling material 5828 is gone up and first in compositionConductive filling material 5808 is different.Each conductive interconnection line in the multiple conductive interconnection lines 5824 of third is along a first direction5898。
A conductive interconnection line 5834 is above third ILD layer 5822 in the 4th ILD layer 5832 and by the 4th more than 4thILD layer 5832 is spaced apart.Each conductive interconnection line more than 4th in a conductive interconnection line 5834 includes along the second conductive fillThe side wall of material 5828 and the second conductive barrier materials 5826 of bottom.Each conduction more than 4th in a conductive interconnection line 5834Interconnection line is along second direction 5899.
A conductive interconnection line 5844 is above the 4th ILD layer 5832 in the 5th ILD layer 5842 and by the 5th more than 5thILD layer 5842 is spaced apart.Each conductive interconnection line more than 5th in a conductive interconnection line 5844 includes along the second conductive fillThe side wall of material 5828 and the second conductive barrier materials 5826 of bottom.Each conduction more than 5th in a conductive interconnection line 5844Interconnection line along a first direction 5898.
A conductive interconnection line 5854 is above the 5th ILD layer in the 6th ILD layer 5852 and by the 6th ILD layer more than 6th5852 are spaced apart.Each conductive interconnection line more than 6th in a conductive interconnection line 5854 includes along the second conductive filling material5828 side wall and the second conductive barrier materials 5826 of bottom.Each conductive interconnection more than 6th in a conductive interconnection line 5854Line is along second direction 5899.
In embodiment, the second conductive filling material 5828 mainly includes copper, and the first conductive filling material 5808 is mainIt to include cobalt.In embodiment, the first conductive filling material 5808 includes having dopant impurities atom (dopantImpurity atom) the first concentration copper, and the second conductive filling material 5828 includes having dopant impurities atomThe copper of second concentration, the second concentration of dopant impurities atom are less than the first concentration of dopant impurities atom.
In embodiment, the first conductive barrier materials 5806 are upper different from the second conductive barrier materials 5826 in composition.?In another embodiment, the first conductive barrier materials 5806 and the composition having the same of the second conductive barrier materials 5826.
In embodiment, an other conduction of first conductive through hole 5819 in conductive interconnection line 5804 a more than firstOn interconnection line 5804A and it is electrically coupled to the other conductive interconnection line 5804A of this.More than second in a conductive interconnection line 5814An other conductive interconnection line 5814A on the first conductive through hole 5819 and be electrically coupled to the first conductive through hole 5819.
Other conductive interconnection line 5814B of second conductive through hole 5829 in conductive interconnection line 5814 a more than secondAbove and it is electrically coupled to the other conductive interconnection line 5814B of this.A other one in the multiple conductive interconnection lines 5824 of thirdA conductive interconnection line 5824A is on the second conductive through hole 5829 and is electrically coupled to the second conductive through hole 5819.
Other conductive interconnection line 5824B of the third conductive through hole 5839 in the multiple conductive interconnection lines 5824 of thirdAbove and it is electrically coupled to the other conductive interconnection line 5824B of this.More than 4th in a conductive interconnection line 5834 other oneA conductive interconnection line 5834A is on third conductive through hole 5839 and is electrically coupled to third conductive through hole 5839.
Other conductive interconnection line 5834B of 4th conductive through hole 5849 in conductive interconnection line 5834 a more than the 4thAbove and it is electrically coupled to the other conductive interconnection line 5834B of this.More than 5th in a conductive interconnection line 5844 other oneA conductive interconnection line 5844A is on the 4th conductive through hole 5849 and is electrically coupled to the 4th conductive through hole 5849.
Other conductive interconnection line 5844B of 5th conductive through hole 5859 in conductive interconnection line 5844 a more than the 5thAbove and it is electrically coupled to the other conductive interconnection line 5844B of this.More than 6th in a conductive interconnection line 5854 other oneA conductive interconnection line 5854A is on the 5th conductive through hole 5859 and is electrically coupled to the 5th conductive through hole 5859.
In one embodiment, the first conductive through hole 5819 includes the side wall along the first conductive filling material 5808 and bottomFirst conductive barrier materials 5806 in portion.The conductive through hole of 2nd 5829, the 3rd 5839, the 4th 5849 and the 5th 5859 include alongThe side wall of second conductive filling material 5828 and the second conductive barrier materials 5826 of bottom.
In embodiment, the one 5802, second are made by the corresponding etching stopping layer 5890 between adjacent ILD layer5812, the ILD layer of the 3rd 5822, the 4th 5832, the 5th 5842 and the 6th 5852 is separated from each other.In embodiment, the 1st,The ILD layer of 2nd 5812, the 3rd 5822, the 4th 5832, the 5th 5842 and the 6th 5852 includes silicon, carbon and oxygen.
In embodiment, a conductive interconnection line more than the one 5804 and the 2nd 5814 and in each conductive interconnection line have theOne width (W1).Each conductive interconnection in a conductive interconnection line of 3rd 5824, the 4th 5834, the 5th 5844 and more than the 6th 5854Line has the second width (W2) greater than the first width (W1).
Figure 59 A-59D instantiates the through-hole arrangement and various interconnection according to an embodiment of the present disclosure with bottom conductive layerThe viewgraph of cross-section of line.
With reference to Figure 59 A and 59B, integrated circuit structure 5900 includes interlayer dielectric (ILD) layer above substrate 59025904.Conductive through hole 5906 is in ILD layer 5904 in first groove 5908.Conductive interconnection line 5910 is in conductive through hole 5906Top and it is electrically coupled to conductive through hole 5906.Conductive interconnection line 5910 is in ILD layer 5904 in second groove 5912.TheTwo grooves 5912 have the opening 5913 bigger than the opening 5909 of first groove 5908.
In embodiment, conductive through hole 5906 and conductive interconnection line 5910 include the first electrically conductive barrier 5914, theOn the bottom of one groove 5908, but not along the side wall of first groove 5908 and not along the bottom of second groove 5912 andSide wall.Second electrically conductive barrier 5916 is on the bottom of first groove 5908 on the first electrically conductive barrier 5914.Second leadsElectrical barrier 5916 further along first groove 5908 side wall, and further along the bottom and side of second groove 5912Wall.Third electrically conductive barrier 5918 is on the bottom of first groove 5908 on the second electrically conductive barrier 5916.Third is conductiveBarrier layer 5918 further along first groove 5908 side wall and along the bottom and side wall of second groove 5912 secondOn electrically conductive barrier 5916.Conductive filling material 5920 is on third electrically conductive barrier 5918 and fills the one 5908 andTwo grooves 5912.Third electrically conductive barrier 5918 is along the bottom of conductive filling material 5920 and along conductive filling material5920 side wall.
In one embodiment, the first electrically conductive barrier 5914 and the composition having the same of third electrically conductive barrier 5918,And the second electrically conductive barrier 5916 is upper different from the first electrically conductive barrier 5914 and third electrically conductive barrier 5918 in composition.?In one such embodiment, the first electrically conductive barrier 5914 and third electrically conductive barrier 5918 include ruthenium, and second is conductiveBarrier layer 5916 includes tantalum.In specific such embodiment, the second electrically conductive barrier 5916 further comprises nitrogen.ImplementingIn example, conductive filling material 5920 mainly includes copper.
In embodiment, conductive cap layer 5922 is on the top of conductive filling material 5920.In such embodimentIn, conductive cap layer 5922 is not on the top of the second electrically conductive barrier 5916 and not at the top of third electrically conductive barrier 5918On.However in another embodiment, conductive cap layer 5922 is further on the top of third electrically conductive barrier 5918, for example,At position 5924.In one suchembodiment, conductive cap layer 5922 is still further on the top of the second electrically conductive barrier 5916In portion, for example, at position 5926.In embodiment, conductive cap layer 5922 mainly includes cobalt, and conductive filling material 5920It mainly include copper.
With reference to Figure 59 C and 59D, in embodiment, conductive through hole 5906 is below ILD layer 5904 in the second ILD layer 5952In on the second conductive interconnection line 5950, and be electrically connected to the second conductive interconnection line 5950.Second conductive interconnection line 5950 packetInclude conductive filling material 5954 and conductive cap 5956 thereon.Etching stopping layer 5958 can be on conductive cap 5956, such as instituteAs description.
In one embodiment, the first electrically conductive barrier 5914 of conductive through hole 5906 is in the second conductive interconnection line 5950Conductive cap 5956 opening 5960 in, as in Figure 59 C describe as.In one suchembodiment, conductive through hole5906 the first electrically conductive barrier 5914 includes ruthenium, and the conductive cap 5956 of the second conductive interconnection line 5950 includes cobalt.
In another embodiment, the first electrically conductive barrier 5914 of conductive through hole 5906 is in the second conductive interconnection line 5950Conductive cap 5956 a part on, as in Figure 59 D describe as.In one suchembodiment, conductive through hole 5906The first electrically conductive barrier 5914 include ruthenium, and the conductive cap 5956 of the second conductive interconnection line 5950 include cobalt.SpecificIn embodiment, although not describing, the first electrically conductive barrier 5914 of conductive through hole 5906 is in recess, is not passed throughThe conductive cap 5956 of second conductive interconnection line 5950.
In another aspect, a kind of BEOL metalization layer has non-planar pattern, such as leads in conductor wire with described in receivingLadder height difference between the ILD layer of electric wire.In embodiment, it is conformally formed the etching stopping layer being superimposed with the pattern,And the pattern is presented in the etching stopping layer of the superposition.In embodiment, which facilitates the through hole etching process that will be superimposedIt is directed towards conductor wire, to prevent " the non-landing (non-landedness) " of conductive through hole.
In the first example of etching stopping layer pattern, Figure 60 A-60D instantiates according to an embodiment of the present disclosure be used forThe viewgraph of cross-section of the structure arrangement of the linear looks of recess of BEOL metalization layer.
With reference to Figure 60 A, integrated circuit structure 6000 is included in 6002 top of substrate in interlayer dielectric (ILD) layer 6004And the multiple conductive interconnection lines 6006 being spaced apart by interlayer dielectric (ILD) layer 6004.For exemplary purposes, the multipleOne in conductive interconnection line 6006 is illustrated as coupled to following through-hole 6007.In the multiple conductive interconnection line 6006Each conductive interconnection line has the upper surface 6008 below the upper surface of ILD layer 6,004 6010.Etching stopping layer 6012 is inIt is on ILD layer 6004 and the multiple conductive interconnection line 6006 and conformal with them.Etching stopping layer 6012 has nonplanarUpper surface, wherein the topmost 6014 of nonplanar upper surface is on ILD layer 6004, and nonplanar upper surface is most lowerPortion 6016 is on the multiple conductive interconnection line 6006.
Conductive through hole 6018 on other conductive interconnection line 6006A in the multiple conductive interconnection line 6006 simultaneouslyAnd it is electrically coupled to the other conductive interconnection line 6006A of this.Conductive through hole 6018 is in the opening of etching stopping layer 6012In 6020.Opening 6020 on other conductive interconnection line 6006A in the multiple conductive interconnection line 6006 butIt is to be not on ILD layer 6004.Conductive through hole 6018 is in 6012 top of etching stopping layer in the second ILD layer 6022.?In one embodiment, the second ILD layer 6022 is on etching stopping layer 6012 and conformal therewith, as described in Figure 60 A.
In embodiment, a other one in the center 6024 of conductive through hole 6018 and the multiple conductive interconnection line 6006The center 6026 of a conductive interconnection line 6006A is aligned, as described in Figure 60 A.However in another embodiment, conductive logicalThe center 6024 in hole 6018 is from the center of other conductive interconnection line 6006A in the multiple conductive interconnection line 60066026 offsets, as described in Figure 60 B.
In embodiment, each conductive interconnection line in the multiple conductive interconnection line 6006 includes along conductive fill materialThe side wall of material 6030 and the barrier layer 6028 of bottom.In one embodiment, barrier layer 6028 and conductive filling material 6,030 2Person has the upper space below the upper surface of ILD layer 6,004 6010, as described in Figure 60 A, 60B and 60C.?In specific such embodiment, the upper space on barrier layer 6028 is above the upper space of conductive filling material 6030, such asAs describing in Figure 60 C.In another embodiment, conductive filling material 6030 has in the upper surface of ILD layer 6,004 6010The upper space of lower section, and barrier layer 6028 has the upper space coplanar with the upper surface 6010 of ILD layer 6004, such as schemesAs describing in 60D.
In embodiment, ILD layer 6004 includes silicon, carbon and oxygen, and etching stopping layer 6012 includes silicon and nitrogen.ImplementingIn example, the upper surface 6008 of each conductive interconnection line in the multiple conductive interconnection line 6006 is in the upper surface of ILD layer 60046010 lower sections reach the amount in 0.5-1.5 nanometers of range.
Collective reference Figure 60 A-60D, in accordance with an embodiment of the present disclosure, it is a kind of manufacture integrated circuit structure method be included in6002 top of substrate forms multiple conductive interconnection lines, and the multiple conduction in the first interlayer dielectric (ILD) layer 6004Interconnection line is spaced apart by the first interlayer dielectric (ILD) layer 6004.Keep the multiple conductive interconnection line recessed relative to the first ILD layerIt falls into provide in the multiple conductive interconnection line with the upper surface 6008 below the upper surface 6010 of the first ILD layer 6004Each conductive interconnection line 6006.After making the multiple conductive interconnection line be recessed, in the first ILD layer 6004 and the multipleEtching stopping layer 6012 is formed on conductive interconnection line 6006, and etching stopping layer 6012 is conformal with them.Etching stopping layer6012 have nonplanar upper surface, wherein the topmost 6016 of nonplanar upper surface is on the first ILD layer 6004, andThe lowest part 6014 of nonplanar upper surface is on the multiple conductive interconnection line 6006.It is formed on etching stopping layer 6012Second ILD layer 6022.The etching vias groove in the second ILD layer 6022.Etching stopping layer 6012 instructs second during etchingThe position of via trench in ILD layer 6022.Etching stopping layer 6012 is etched across the via trench, in etching stopping layerOpening 6020 is formed in 6012.An other conductive interconnection line of the opening 6020 in the multiple conductive interconnection line 6006On 6006A but it is not on the first ILD layer 6004.Opening in via trench and in etching stopping layer 6012Conductive through hole 6018 is formed in 6020.An other conduction of the conductive through hole 6018 in the multiple conductive interconnection line 6006On interconnection line 6006A and it is electrically coupled to the other conductive interconnection line 6006A of this.
In one embodiment, each conductive interconnection line in the multiple conductive interconnection line 6006 includes filling out along conductionThe side wall of material 6030 and the barrier layer 6028 of bottom are filled, and the multiple conductive interconnection line recess is made to include making barrier layerBoth 6028 and conductive filling material 6030 are all recessed, as described in Figure 60 A-60C.In another embodiment, describedEach conductive interconnection line in multiple conductive interconnection lines 6006 includes the resistance of side wall and bottom along conductive filling material 6030Barrier 6028, and the multiple conductive interconnection line recess is made to include making the recess of conductive filling material 6030 but not making substantiallyBarrier layer 6028 is recessed, as described in Figure 60 D.In embodiment, etching stopping layer 6012 instructs photoetching not right againNeat via trench pattern.In embodiment, it includes recessed relative to the first ILD layer 6004 for making the multiple conductive interconnection line recessThe amount being trapped in 0.5-1.5 nanometers of range.
In the second example of etching stopping layer pattern, Figure 61 A-61D instantiates according to an embodiment of the present disclosure be used forThe viewgraph of cross-section of the structure arrangement of the ladder-like linear looks of BEOL metalization layer.
With reference to Figure 61 A, integrated circuit structure 6100 is included in 6102 top of substrate in interlayer dielectric (ILD) layer 6104And the multiple conductive interconnection lines 6106 being spaced apart by interlayer dielectric (ILD) layer 6004.For exemplary purposes, the multipleOne in conductive interconnection line 6106 is illustrated as coupled to following through-hole 6107.In the multiple conductive interconnection line 6106Each conductive interconnection line has the upper surface 6108 above the upper surface of ILD layer 6,104 6110.Etching stopping layer 6112 is inIt is on ILD layer 6104 and the multiple conductive interconnection line 6106 and conformal with them.Etching stopping layer 6112 has nonplanarUpper surface, wherein the lowest part 6114 of nonplanar upper surface is on ILD layer 6104, and nonplanar upper surface is most upperPortion 6116 is on the multiple conductive interconnection line 6106.
Conductive through hole 6118 on other conductive interconnection line 6106A in the multiple conductive interconnection line 6106 simultaneouslyAnd it is electrically coupled to the other conductive interconnection line 6106A of this.Conductive through hole 6118 is in the opening of etching stopping layer 6112In 6120.Opening 6120 on other conductive interconnection line 6106A in the multiple conductive interconnection line 6106 butIt is to be not on ILD layer 6114.Conductive through hole 6118 is in 6112 top of etching stopping layer in the second ILD layer 6122.?In one embodiment, the second ILD layer 6122 is on etching stopping layer 6112 and conformal therewith, as described in Figure 61 A.
In embodiment, a other one in the center 6124 of conductive through hole 6118 and the multiple conductive interconnection line 6106The center 6126 of a conductive interconnection line 6106A is aligned, as described in Figure 61 A.However in another embodiment, conductive logicalThe center 6124 in hole 6118 is from the center of other conductive interconnection line 6106A in the multiple conductive interconnection line 61066126 offsets, as described in Figure 61 B.
In embodiment, each conductive interconnection line in the multiple conductive interconnection line 6106 includes along conductive fill materialThe side wall of material 6130 and the barrier layer 6128 of bottom.In one embodiment, barrier layer 6128 and conductive filling material 6,130 2Person has the upper space above the upper surface of ILD layer 6,104 6110, as described in Figure 61 A, 61B and 61C.?In specific such embodiment, the upper space on barrier layer 6128 is below the upper space of conductive filling material 6130, such asAs describing in Figure 61 C.In another embodiment, conductive filling material 6130 has in the upper surface of ILD layer 6,104 6110The upper space of top, and barrier layer 6128 has the upper space coplanar with the upper surface 6110 of ILD layer 6104, such as schemesAs describing in 61D.
In embodiment, ILD layer 6104 includes silicon, carbon and oxygen, and etching stopping layer 6112 includes silicon and nitrogen.ImplementingIn example, the upper surface 6108 of each conductive interconnection line in the multiple conductive interconnection line 6106 is in the upper surface of ILD layer 60046110 tops reach the amount in 0.5-1.5 nanometers of range.
Collective reference Figure 61 A-61D, in accordance with an embodiment of the present disclosure, it is a kind of manufacture integrated circuit structure method be included in6102 top of substrate forms multiple conductive interconnection lines 6106, and the multiple conduction in the first interlayer dielectric (ILD) layerInterconnection line 6106 is separated by the first interlayer dielectric (ILD) interlayer.Make the first ILD layer 6104 relative to the multiple conductive interconnectionThe recess of line 6106 is to provide the multiple conduction with the upper surface 6108 above the upper surface 6110 of the first ILD layer 6104Each conductive interconnection line in interconnection line 6106.After making the first ILD layer 6104 be recessed, in the first ILD layer 6104 and describedEtching stopping layer 6112 is formed on multiple conductive interconnection lines 6106, and etching stopping layer 6012 is conformal with them.Etch stopLayer 6112 has nonplanar upper surface, wherein the lowest part 6114 of nonplanar upper surface is on the first ILD layer 6104, andAnd the topmost 6116 of nonplanar upper surface is on the multiple conductive interconnection line 6106.The shape on etching stopping layer 6112At the second ILD layer 6122.The etching vias groove in the second ILD layer 6122.Etching stopping layer 6112 instructs during etchingThe position of via trench in two ILD layers 6122.Etching stopping layer 6112 is etched across the via trench, in etch stopOpening 6120 is formed in layer 6112.An other conductive interconnection of the opening 6120 in the multiple conductive interconnection line 6106On line 6106A but it is not on the first ILD layer 6104.Opening in via trench and in etching stopping layer 6112Conductive through hole 6118 is formed in mouth 6120.Other one in the multiple conductive interconnection line 6106 of conductive through hole 6118 leadsOn electrical interconnection line 6106A and it is electrically coupled to the other conductive interconnection line 6106A of this.
In one embodiment, each conductive interconnection line in the multiple conductive interconnection line 6106 includes filling out along conductionThe side wall of material 6130 and the barrier layer 6128 of bottom are filled, and the first ILD layer 6104 recess is made to include relative to barrier layerBoth 6128 and conductive filling material 6130 are all recessed, as described in Figure 61 A-61C.In another embodiment, describedEach conductive interconnection line in multiple conductive interconnection lines 6106 includes the resistance of side wall and bottom along conductive filling material 6130Barrier 6128, and the first ILD layer 6104 recess is made to include being recessed relative to conductive filling material 6130 but not relative to resistanceBarrier 6128 is recessed, as described in Figure 61 D.In embodiment, wherein etching stopping layer 6112 instructs photoetching not againThe via trench pattern of alignment.In embodiment, making the first ILD layer 6104 recess includes relative to the multiple conductive interconnection lineAmount of 6106 recess in 0.5-1.5 nanometers of range.
In another aspect, it describes for carrying out patterned technology to metal wire end.In order to provide context,In the advanced node of semiconductors manufacture, line grid (line grating), the isolated pattern of line end and through-hole can be passed throughChange process interconnects to generate junior (lower level).However, constituting the fidelity of pattern may be intended to occupy with through-holeLine end and degrade and vice versa.Embodiment described herein, which provides, eliminates the associated line end close to ruleProcess is also referred to as plug process.Embodiment can take into account the through-hole that be placed online end and large through-hole with cross-line endEnd is to tie up (strap).
In order to provide further context, Figure 62 A instantiate plan view according to an embodiment of the present disclosure and alongThe corresponding viewgraph of cross-section of a-a ' the axis interception of the plan view of metalization layer.Figure 62 B instantiates the implementation according to the disclosureThe line end of example or the viewgraph of cross-section of plug.Figure 62 C instantiates the another of line end according to an embodiment of the present disclosure or plugOne viewgraph of cross-section.
With reference to Figure 62 A, metalization layer 6200 includes the metal wire 6202 being formed in dielectric layer 6204.Metal wire 6202It may be coupled to following through-hole 6203.Dielectric layer 6204 may include line end or plug area 6205.With reference to Figure 62 B,It can be by carrying out patterning and the then quilt of etching dielectric layer 6204 to the hard mask layer 6210 on dielectric layer 6204Expose portion manufactures line end or the plug area 6205 of dielectric layer 6204.It can be by the portion that is exposed of dielectric layer 6204Divide and be etched to the depth for suitably forming line trenches 6206, or is further etched into the depth for suitably forming via trench 6208Degree.With reference to Figure 62 C, can be manufactured in single big exposed portion 6216 adjacent with the opposing sidewalls of line end or plug 6205Two through-holes, to ultimately form line trenches 6212 and via trench 6214.
However, referring again to Figure 62 A-62C, fidelity problem and/or hard mask erosion problem may cause defectiveIt patterns method for organizing (regime).In contrast, one or more embodiment described herein includes being related in grooveWith the realization of the process flow of the construction line end dielectric (plug) after through-hole pattern process.
Then in an aspect, one or more embodiments described herein are related in metal (metals) lineBetween the method that constructs non-conductive space or interrupt (referred to as " line end ", " plug " or " notch "), and in some embodimentsIn, it is related to associated conductive through hole.According to definition, conductive through hole is for landing (land) in preceding layer metal pattern.?This respect, embodiment described herein can be more steady mutual by being aligned so that for lithographic equipment due to being less dependent onEven fabrication scheme.Such interconnection fabrication scheme can be used for loosening about the constraint of alignment/exposed portion, can be used for improving electricityIt contacts (for example, by reducing through hole resistance) and can be used for reducing and pattern such feature script institute using conventional methodThe total process needed operates and handles the time.
Figure 63 A-63F instantiates the various operations in expression plug extreme trace processing scheme according to an embodiment of the present disclosurePlan view and corresponding viewgraph of cross-section.
With reference to Figure 63 A, it is a kind of manufacture integrated circuit structure method be included in interlayer dielectric (ILD) material layer 6302Line trenches 6306 are formed in top 6304, interlayer dielectric (ILD) material layer 6302 is formed on following metalization layer 6300Top.Via trench 6308 is formed in the lower part of ILD material layer 6,302 6310.The following metallization of the exposure of via trench 6308The metal wire 6312 of layer 6300.
With reference to Figure 63 B, is formed and sacrificed above ILD material layer 6302 and in line trenches 6306 and via trench 6308Material 6314.Expendable material 6314 can have hard mask 6315 formed thereon, as described in Figure 63 B.OneIn a embodiment, expendable material 6314 includes carbon.
With reference to Figure 63 C, expendable material 6314 is patterned to interrupt the expendable material 6314 in line trenches 6306Continuity, for example, to provide the opening 6316 in expendable material 6314.
With reference to Figure 63 D, with the opening 6316 in dielectric substance filling expendable material 6314 to form dielectric plug6318.In embodiment, after the opening 6316 being filled in expendable material 6314 with dielectric substance, hard mask is removed6315 to provide dielectric plug 6318, has the upper surface 6320 above the upper surface of ILD material 6,302 6322, such as schemesAs describing in 63D.Expendable material 6314 is removed to leave dielectric plug 6318.
It in embodiment, include using metal oxide materials with the opening 6316 of dielectric substance filling expendable material 6314It is filled.In one suchembodiment, metal oxide materials are aluminium oxide.In embodiment, dielectric substance is usedThe opening 6314 of filling expendable material 6316 includes being filled using atomic layer deposition (ALD).
With reference to Figure 63 E, line trenches 6306 and via trench 6308 are filled with conductive material 6324.In embodiment, conductiveMaterial 6324 be formed on dielectric plug 6318 and the top of ILD layer 6302 and on, as depicted.
With reference to Figure 63 F, conductive material 6324 and dielectric plug 6318 are planarized, interrupt line trenches to provideThe dielectric plug 6318 ' of successional flattenedization of conductive material 6324 in 6306.
Referring again to Figure 63 F, in accordance with an embodiment of the present disclosure, integrated circuit structure 6350 includes the interlayer above substrateDielectric (ILD) layer 6302.Conductive interconnection line 6324 is in ILD layer 6302 in groove 6306.Conductive interconnection line 6324 hasThere are first part 6324A and second part 6324B, first part 6324A and second part 6324B are laterally adjacent.Dielectric is insertedPlug 6318 ' is between the first part 6324A and second part 6324B of conductive interconnection line 6324 and laterally adjacent with them.Although not describing, in embodiment, conductive interconnection line 6324 includes conductive barrier liner and conductive filling material, is retouched aboveThe exemplary materials for it are stated.In one suchembodiment, conductive filling material includes cobalt.
In embodiment, dielectric plug 6318 ' includes metal oxide materials.In one suchembodiment, goldenBelonging to oxide material is aluminium oxide.In embodiment, the first part of dielectric plug 6318 ' and conductive interconnection line 63246324A and second part 6324B are directly contacted.
In embodiment, dielectric plug 6318 ' has substantially coplanar with the bottom 6324C of conductive interconnection line 6324Bottom 6318A.In embodiment, the first conductive through hole 6326 is in ILD layer 6302 in groove 6308.As oneIn embodiment, the first conductive through hole 6326 is below the bottom 6324C of interconnection line 6324, and 6326 thermocouple of the first conductive through holeClose the first part 6324A of conductive interconnection line 6324.
In embodiment, the second conductive through hole 6328 is in ILD layer 6302 in third groove 6330.Second is conductive logicalHole 6328 is below the bottom 6324C of interconnection line 6324, and the second conductive through hole 6328 is electrically coupled to conductive interconnection line 6324Second part 6324B.
The filling process of such as chemical vapor deposition processes etc can be used to form dielectric plug.Product(artifact) it can be retained in manufactured dielectric plug.As an example, Figure 64 A instantiates the implementation according to the disclosureThe viewgraph of cross-section for wherein having apertured conductive line plug of example.
With reference to Figure 64 A, dielectric plug 6418 has mutual with the first part 6324A of conductive interconnection line 6324 and with conductionThe gap 6400 for the near vertical that the second part 6324B of line 6324 is substantially equally spaced.
It is to be appreciated that constitute it is upper be housed inside the different dielectric plug of ILD material therein with them can be byIncluding only selecting in metalization layer, such as in lower metalization layer.As an example, Figure 64 B instantiates the reality according to the disclosureApply example includes the viewgraph of cross-section of the metallization layer stack of conductive line plug at lower metal line position.
With reference to Figure 64 B, integrated circuit structure 6450 is included in 6452 top of substrate in the first interlayer dielectric (ILD) layerMore than first a conductive interconnection lines 6456 being spaced apart in 6454 and by the first interlayer dielectric (ILD) layer 6454.More than firstEach conductive interconnection line in conductive interconnection line 6456 has the continuity interrupted by one or more dielectric plugs 6458.?In embodiment, one or more of dielectric plugs 6458 include the material different from ILD layer 6452.More than second conductive mutualLine 6466 is spaced apart above the first ILD layer 6454 in the second ILD layer 6464 and by the second ILD layer 6464.ImplementingIn example, each conductive interconnection line more than second in a conductive interconnection line 6466 has by the one or more of the second ILD layer 6464The continuity that part 6468 is interrupted.It is to be appreciated that may include other gold in integrated circuit structure 6450 as depictedCategoryization layer.
In one embodiment, one or more of dielectric plugs 6458 include metal oxide materials.At oneIn such embodiment, metal oxide materials are aluminium oxide.In one embodiment, the first ILD layer 6454 and the second ILD layerOne or more parts 6568 of 6464(and the second ILD layer 6464 therefore) include carbon dope silica material.
In one embodiment, each conductive interconnection line more than first in a conductive interconnection line 6456 includes the first conductive resistanceGear liner 6456A and the first conductive filling material 6456B.Each conductive interconnection line packet more than second in a conductive interconnection line 6466Include the second conductive barrier liner 6466A and the second conductive filling material 6466B.In one suchembodiment, first is conductivePacking material 6456B is upper different from the second conductive filling material 6466B in composition.In specific such embodiment, firstConductive filling material 6456B includes cobalt, and the second conductive filling material 6466B includes copper.
In one embodiment, a conductive interconnection line 6456 more than first has first segment away from (P1, such as in similar layer (like-Layer) shown in 6470).A conductive interconnection line 6466 more than second has the second pitch (P2, such as the institute in similar layer 6480Show).Second pitch (P2) is greater than first segment away from (P1).In one embodiment, each in a conductive interconnection line 6456 more than firstA conductive interconnection line has the first width (W1, as shown in similar layer 6470).More than second in a conductive interconnection line 6466Each conductive interconnection line has the second width (W2, as shown in similar layer 6480).Second width (W2) is greater than the first width(W1).
It is to be appreciated that with back-end process (back end of line) (BEOL) structure and processing in association aboveThe layer and material of description can be formed on above following semiconductor substrate or structure, semiconductor substrate or knot below(one or more) device layer below structure such as integrated circuit.In embodiment, semiconductor substrate expression below is used forManufacture the general workpiece objects of integrated circuit.Semiconductor substrate generally includes wafer or other silicon wafers or another semiconductor materialThe piece of material.Suitable semiconductor substrate include but is not limited to monocrystalline silicon, polysilicon and silicon-on-insulator (SOI) and by other halfThe similar substrate that conductor material is formed, such as substrate including germanium, carbon or III-V material.Depending on fabrication stage, semiconductorSubstrate generally includes transistor, integrated circuit and the like.Substrate can also include semiconductor material, metal, dielectric,Dopant and common other materials in semiconductor substrate.It is retouched furthermore, it is possible to be manufactured on following junior's interconnection layerThe structure drawn.
Although part, the BEOL metalization layer of manufacture metalization layer or metalization layer are described in detail about selection operationPreceding method, but it is to be appreciated that, the additional or intermediary operation for manufacture may include standard micro manufacturing process,Such as photoetching, etching, film deposition, planarizing (such as chemically mechanical polishing (CMP)), diffusion, metering, the use of sacrificial layer,The use of etching stopping layer, the use for planarizing stop-layer or any other movement associated with microelectronic component manufacture.SeparatelyIt is to be appreciated that, the process operation for the description of aforementioned process process can be practiced in the order to replace outside, not need to holdEach operation of row can perhaps execute additional process operation or the two.
In embodiment, as used throughout this specification, interlayer dielectric (ILD) material is by dielectric or insulating materialsLayer constitutes or including dielectric or insulation material layer.The example of suitable dielectric substance includes but is not limited to the oxide of silicon(for example, silica (SiO2)), doping the oxide of silicon, the oxide of fluorinated silicon, the oxide of the silicon of carbon dope, abilityIn domain known various low k dielectric materials with and combinations thereof.Inter-level dielectric material can be formed by following technology, such asSuch as chemical vapor deposition (CVD), physical vapor deposition (PVD) or pass through other deposition methods.
In embodiment, also as used throughout this specification, metal wire or interconnection material (and via material) byOne or more metals or other conductive structures are constituted.Usual examples can or can not be wrapped using copper wire and structureInclude the barrier layer between copper and the ILD material surrounded.As used in this article, term metal includes alloy, various metalsIt stacks and other is combined.For example, metal interconnecting wires may include barrier layer (e.g., including one in Ta, TaN, Ti or TiNKind or a variety of layers), different metal or the stacking of alloy etc..Therefore, interconnection line can be single material layer, or can be bySeveral layers including conductive spacer layer and filled layer are formed.Any deposition process appropriate can be used to form interconnection line, appointWhat deposition process appropriate is such as electroplated, chemical vapor deposition or physical vapour deposition (PVD).In embodiment, interconnection line is by conduction materialMaterial is constituted, conductive material such as, but not limited to Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or its alloy.MutuallyLine is otherwise referred to as trace, lead, line, metal in the art or referred to as interconnects.
In embodiment, also as used throughout this specification, hard mask material is by different from inter-level dielectric materialDielectric substance is constituted.In one embodiment, different hard mask materials can be used in different regions, to provideGrowth or etching selectivity different from each other and different from following dielectric and metal layer.In some embodiments, hard maskLayer includes the layer of the layer (for example, silicon nitride) of the nitride of silicon or the oxide of silicon, or both, or combinations thereof.Other are suitableMaterial may include the material based on carbon.In another embodiment, hard mask material includes metal species.For example, hard maskOr other superposition materials may include the layer of the nitride (for example, titanium nitride) of titanium or another metal.It can be in these layersOne or more layers in include potentially less amount of other materials, such as oxygen.Alternatively, can depend on specific implementation andUse other hard mask layers as known in the art.Hard mask can be formed by CVD, PVD or by other deposition methodsLayer.
In embodiment, 193nm immersion lithography (i193), extreme ultraviolet also are used as used throughout this specification(EUV) photoetching or electron-beam direct writing formula (EBDW) photoetching or the like executes lithography operations.Positive-workingresist can be used(positive tone resist) or transoid resist (negative tone resist).In one embodiment, photoetchingMask is the tri-layer mask being made of pattern masked portion, antireflection coated (ARC) layer and photoresist layer.Specifically in this wayEmbodiment in, pattern masked portion is carbon hard mask (CHM) layer, and anti-reflection coatings are silicon ARC layers.
In another aspect, one or more embodiments described herein are related to internal node wire jumper (jumper)Memory bitcell.Specific embodiment may include realizing memory bitcell with advanced self-aligned process technology(layout) the efficient technology of layout.Embodiment can be related to 10 nanometers or lesser technology node.Embodiment can pass through benefitWith the contact portion (cotact over active gate) (COAG) on effective grid or have rodent metal 1(M1) pitchScaling or the two are single to provide the memory position that exploitation has improved properties in identical package area (footprint)The ability of member.Embodiment may include or be related to bit location layout, make relative to the identical of previous technology nodeOr the bit location of the higher performance in lesser package area is possibly realized.
In accordance with an embodiment of the present disclosure, higher metal layer (for example, metal 1 or M1) wire jumper is realized to connect internal sectionPoint, rather than traditional grid-trench contact portion-gate contact (poly-tcn-polycon) is used to connect.In embodimentIn, combined with 1 wire jumper of metal with connect contact portion (COAG) Integrated Solution on effective grid of internal node mitigate or completelyEliminate the needs for increasing package area for the bit location of higher performance.Also that is, improved transistor ratio may be implemented.ImplementingIn example, such method enables aggressive scaling (aggressive scaling), for such as 10 nanometers of (10nm) skillsArt node provides the cost of improved each transistor.It can be in SRAM, RF and dual-port bit location (Dual in 10nm technologyPort bit cell) in realize internal node M1 wire jumper to generate very compact layout.
As comparative example, Figure 65 instantiates the first view of the cell layout for memory cell.
With reference to Figure 65, (14 nm) 14 nanometers exemplary layout 6500 includes bit location 6502.Bit location 6502 includes gridOr it polymerize line 6504 and metal 1(M1) line 6506.In the example shown, polymerization line 6504 has 1x pitch, and M1 line6506 have 1x pitch.In certain embodiments, polymerization line 6504 has 70 nm pitches, and M1 line 6506 has 70 nmPitch.
Opposite with Figure 65, Figure 66 instantiates according to an embodiment of the present disclosure for the memory with internal node wire jumperThe first view of the cell layout of unit.
With reference to Figure 66, (10 nm) 10 nanometers exemplary layout 6600 includes bit location 6602.Bit location 6602 includes gridOr it polymerize line 6604 and metal 1(M1) line 6606.In the example shown, polymerization line 6604 has 1x pitch, and M1 line 6606With 0.67x pitch.The result is that double line 6605 comprising the M1 line directly on polymerization line.In certain embodiments,Polymerizeing line 6604 has 54 nm pitches, and M1 line 6606 has 36 nm pitches.
Compared with layout 6500, in layout 6600, M1 pitch is less than grid pitch, so that every three lines vacate (freeUp) additional line (6605) (for example, for every two polymerization line, there are three M1 lines)." vacating " M1 line is referred to herein asInternal node wire jumper.The internal node wire jumper can be used to grid to interconnect to grid (being aggregated to polymerization) or connect for grooveContact portion is interconnected to trench contact portion.In embodiment, polymerization is realized by contact portion (COAG) arrangement on effective gridContact, thus the manufacture of enabled internal node wire jumper.
Figure 66 is more generally referred to, in embodiment, integrated circuit structure includes the memory bitcell on substrate6602.Memory bitcell 6602 includes first and second grid lines 6604 parallel along the second direction 2 of substrate.First HeSecond gate line 6604 has along the first segment of the first direction (1) of substrate away from first direction (1) is perpendicular to second direction(2).First, second, and third interconnection line 6606 is on the first and second grid lines 6604.First, second, and third interconnectionLine 6606 is parallel along the second direction (2) of substrate.First, second, and third interconnection line 6606 has the along a first directionTwo pitches, wherein the second pitch be less than first segment away from.In one embodiment, in the first, second, and third interconnection line 6606One is internal node wire jumper for memory bitcell 6602.
As can be throughout disclosure application, grid line 6604 be properly termed as on trace to form cell structure.CauseThis, grid-like patterns described herein can have with constant pitch interval and with constant width grid line orInterconnection line.Pattern can be manufactured by pitch bisection or the pitch quartering or other pitch split plot designs.
As comparative example, Figure 67 instantiates the second view of the cell layout 6700 for memory cell.
With reference to Figure 67,14 nm bit locations 6502 are shown as having N diffusion 6702(the active region for example, p-type doping(active region), such as below substrate boron-doping diffusion zone) and P spread 6704(for example, n-type doping active areaDomain, such as diffusion zone for mixing phosphorus or arsenic or both of following substrate), wherein in order to clearly eliminate M1 line.Bit location 102Layout 6700 include grid line or polymerization line 6504, trench contact portion 6706, (for being specific for 14nm node) gridPole contact portion 6708 and contact through hole 6710.
Comparative diagram 67, Figure 68 instantiate according to an embodiment of the present disclosure for the memory list with internal node wire jumperSecond view of the cell layout 6800 of member.
With reference to Figure 68,10 nm bit locations 6602 are shown as having N diffusion 6802(the active region for example, p-type doping,The boron-doping diffusion zone of substrate below such as) and P diffusion 6804(for example, n-type doping active region, such as following baseThe diffusion zone for mixing phosphorus or arsenic or both of plate), wherein in order to clearly eliminate M1 line.The layout 6800 of bit location 202 includesGrid line or polymerization line 6604, trench contact portion 6806, (for being specific for 10nm node) gate via 6808 and ditchSlot contact through hole 6710.
When comparing layout 6700 and 6800, in accordance with an embodiment of the present disclosure, in 14 nm layout, only connect by gridContact portion (GCN) connects internal node.Due to being aggregated to the space constraint of GCN, increasing can not be generated in identical package areaEpistasis can be laid out.In 10 nm layout, which, which takes into account, makes contact portion (VCG) to land on grid to eliminate to polymerization contactThe needs in portion.In one embodiment, the connection of the enabled internal node using M1 of the arrangement, encapsulates to take into account in 14 nmAdditional active region density (for example, increased fin number) in area.In 10 nm layout, COAG framework is being usedWhen, the interval between diffusion zone can do it is smaller because they are not by trench contact portion to the limit at gate contact intervalSystem.In embodiment, the layout 6700 of Figure 67 is known as 112(1 fin pull-up, 1 fin is pulled down by grid, 2 fins) arrangement.PhaseOver the ground, the layout 6800 of Figure 68 is known as 122(1 fin pull-up, 2 fins are pulled down by grid, 2 fins) arrangement, specificIt is in package area identical with the 112 of Figure 67 layouts in embodiment.In embodiment, 122 arrangements are provided compared to 112The improved performance of arrangement.
As comparative example, Figure 69 instantiates the third view of the cell layout 6900 for memory cell.
With reference to Figure 69,14 nm bit locations 6502 are shown with metal 0(M0) line 6902, wherein poly- in order to clearly eliminateZygonema.Also show metal 1(M1) line 6506, contact through hole 6710,0 structure 6904 of through-hole.
Comparative diagram 69, Figure 70 instantiate according to an embodiment of the present disclosure for the memory list with internal node wire jumperThe third view of the cell layout 7000 of member.
With reference to Figure 70,10 nm bit locations 6602 are shown with metal 0(M0) line 7002, wherein poly- in order to clearly eliminateZygonema.Also show metal 1(M1) line 6606,0 structure 7004 of gate via 6808, trench contact through-hole 6810 and through-hole.?When comparing Figure 69 and 70, in accordance with an embodiment of the present disclosure, for 14 nm layout, only connected by gate contact (GCN)Internal node is connect, and for 10 nm layout, one in internal node is connected using M1 wire jumper.
Collective reference Figure 66,68 and 70, in accordance with an embodiment of the present disclosure, a kind of integrated circuit structure includes on substrateMemory bitcell 6602.Memory bitcell 6602 includes the first (top parallel along the first direction (1) of substrate6802), second (top 6804), third (bottom 6804) and the 4th (bottom 6802) active region.First (left side 6604) andSecond (right side 6604) grid line is on the first, second, third and fourth active region 6802/6804.First and secondGrid line 6604 along substrate second direction (2) in parallel, second direction (2) is perpendicular to first direction (1).First (left side is remoteEnd 6606), second (left proximal 6606) and third (right proximal 6606) interconnection line the first and second grid lines 6604 itOn.First, second, and third interconnection line 6606 is parallel along the second direction (2) of substrate.
In embodiment, first (left distal 6606) and the second (left proximal 6606) interconnection line are first, second,(example at the position of the first and second grid lines 6604 on one or more of three and the 4th active region 6802/6804Such as, at so-called " effective grid " position) it is electrically connected to the first and second grid lines 6604.In one embodiment, first(left distal 6606) and the second (left proximal 6606) interconnection line pass through vertically in the first and second interconnection lines 6606 and theMultiple interconnection lines 7004 between two parties between one and second gate line 6604 are electrically connected to the first and second grid lines 6604.Between two partiesMultiple interconnection lines 7004 it is parallel along the first direction (1) of substrate.
In embodiment, third interconnection line (right proximal 6606) is by the gate electrode of memory bitcell 6602 to being electrically coupledTogether, the gate electrode is to being included in the first and second grid lines 6604.In another embodiment, third interconnection line is (rightSide proximal end 6606) by the trench contact portion of memory bitcell 6602 to being electrically coupled together, the trench contact portion is to being includedIn multiple trench contact lines 6806.In embodiment, third interconnection line (right proximal 6606) is internal node wire jumper.
In embodiment, the first active region (top 6802) is the active region of p-type doping (for example, with for NMOS devicePart provides N diffusion), the second active region (top 6804) is the active region of n-type doping (for example, to provide P for PMOS deviceDiffusion), third active region (bottom 6804) is the active region (for example, to provide P diffusion for PMOS device) of n-type doping,And the 4th active region (bottom 6802) is the active region (for example, to provide N diffusion for NMOS device) of n-type doping.?In embodiment, the first, second, third and fourth active region 6802/6804 is in silicon fin.In embodiment, memory positionUnit 6602 include pulling up transistor based on single silicon fin, based on two silicon fins by gridistor and be based onThe pull-down transistor of two silicon fins.
In embodiment, the first and second grid lines 6604 multiple grooves parallel with second direction (2) along substrateEach trench contact line in contact line 6806 replaces (alternate).The multiple trench contact line 6806 includes memoryThe trench contact portion of bit location 6602.First and second grid lines 6604 include the gate electrode of memory bitcell 6602.
In embodiment, the first and second grid lines 6604 have along a first direction (1) first segment away from.The first,Two and third interconnection line 6606 there is second pitch of (2) along a first direction.In one suchembodiment, the second pitchLess than first segment away from.In specific such embodiment, first segment is away from 50 nanometers to 60 nanometers of range, and secondPitch is in 30 nanometers to 40 nanometers of range.In specific such embodiment, first segment is away from being 54 nanometers, and secondPitch is 36 nanometers.
Embodiment described herein may be implemented in the bit location package area relatively the same with prior art nodeIt is interior that increased number of fins is provided, thus the property of the smaller technology node memory bitcell of performance enhancement relative to prior-generationEnergy.As an example, Figure 71 A and 71B are illustrated respectively and according to an embodiment of the present disclosure are used for six transistors (6T) static randomAccess the bit location layout and schematic diagram of memory (SRAM).
With reference to Figure 71 A and 71B, bit location layout 7102 include wherein along direction (2) parallel grid line 7104(itsIt is referred to as polymerization line).Trench contact line 7106 replaces with grid line 7104.Grid line 7104 and trench contact line 7106 existAlong direction (1) parallel NMOS diffusion zone 7108(for example, the active region of p-type doping, such as boron-doping of following substrateDiffusion zone) and PMOS diffusion zone 7110(for example, n-type doping active region, such as below substrate mix phosphorus or arsenic orThe diffusion zone of the two) on.In embodiment, each of both NMOS diffusion zones 7108 include two silicon fins.Each of both PMOS diffusion zones 7110 include a silicon fin.
Referring again to Figure 71 A and 71B, from grid line 7104 and NMOS diffusion zone 7108 and PMOS diffusion zone 7110It forms NMOS and passes through gridistor 7112, NMOS pull-down transistor 7114 and PMOS pull-up transistor 7116.Further depict wordLine (WL) 7118, internal node 7120 and 7126, bit line (BL) 7122, bit line item (bit line bar) (BLB) 7124, SRAMVCC 7128 and VSS 7130.
In embodiment, make the contact pin for being laid out 7102 the first and second grid lines 7104 with bit location to first and theEffective gate location of two grid lines 7104.In embodiment, 6T SRAM bit cell 7104 includes all inside described aboveNode wire jumper.
In embodiment, layout described herein can be compatible with uniform plug and mask pattern, uniform plug andMask pattern includes uniform fin finishing (trim) mask.Layout can be compatible with non-EUV process.Additionally, layout mayIt requires only that and modifies mask with intermediate fin.Embodiment described herein can be laid out in terms of area to enable compared to otherIncreased density.Embodiment may be implemented to provide layout efficient memory embodiment party with advanced self-aligned process technologyFormula.The advantage in terms of die area or memory performance or both may be implemented.Can layout method in this way come it is specificGround enables circuit engineering.
One or more embodiment described herein is related to when parallel interconnection line (for example, 1 line of metal) and grid lineMulti version library unit disposition when being misaligned.Embodiment can be related to 10 nanometers or smaller technology node.Embodiment can wrapIt includes or is related to so that the unit of the higher performance in the same or less package area relative to prior art node becomesPossible cell layout.In embodiment, the interconnection line manufacture for being superimposed grid line had into increasing at relative to following grid lineThe density added.Such embodiment can hit the increase of (pin hit), increased wiring possibility to enable pin or to singleThe increased access of first pin.Embodiment may be implemented to provide the block grade density for being greater than 6%.
In order to provide context, the next parallel stage (next parallel level) of grid line and interconnection is (usuallyReferred to as metal 1, wherein 0 layer of metal it is orthogonal between metal 1 and grid line) need at block grade be aligned.However in embodiment,So that the pitch of 1 line of metal is different from the pitch of grid line, for example, being less than the pitch of grid line.So that being directed to each unit twoA standard block version (for example, two different unit patterns) can be used for adapting to the difference of pitch.Selected particular version is abided byFollow the rule placement for being attached to block grade.If do not properly selected, dirty registration (dirty may occurRegistration) (DR).In accordance with an embodiment of the present disclosure, realize has increased pitch close relative to following grid lineThe higher metal layer (for example, metal 1 or M1) of degree.In embodiment, such method enables the aggressive scaling beSuch as 10 nanometers of (10nm) technology nodes provide the cost of improved each transistor.
Figure 72 instantiates the cross section of two kinds of different layouts according to an embodiment of the present disclosure for identical standard unitView.
With reference to the part (a) of Figure 72, the set of grid line 7204A is superimposed upon on substrate 7202A.Metal 1(M1) interconnectionThe collection that the set of 7206A is superimposed upon grid line 7204A closes.The metal 1(M1) set of 7206A is interconnected with than the gridThe closer pitch of the set of line 7204A.However, outermost metal 1(M1) interconnection 7206A have and outermost grid lineThe outer alignment of 7204A.For specified purpose, as used throughout the disclosure, the alignment of the part (a) of Figure 72 is referred to asIt is aligned with idol (even) (E).
The part (b) of Figure 72 is comparatively referred to part (a), the set of grid line 7204B is superimposed upon on substrate 7202B.Metal 1(M1) set of interconnection 7206B is superimposed upon the collection of grid line 7204B and closes.The metal 1(M1) interconnection 7206B collectionClosing has the pitch more closer than the set of grid line 7204B.Outermost metal 1(M1) interconnection 7206B do not have with mostThe outer alignment of external grid line 7204B.For specified purpose, as used throughout the disclosure, the part (b) of Figure 72 is notThe arrangement of alignment, which is referred to as, has odd (odd) (O) alignment.
Figure 73 instantiates four kinds of different unit cloth according to an embodiment of the present disclosure for indicating that even (E) or odd (O) is specifiedThe plan view set.
With reference to the part (a) of Figure 73, unit 7300A has grid (or polymerization) line 7302A and metal 1(M1) line 7304A.Unit 7300A is designated as EE unit, because the left side of unit 7300A and the right side of unit 7300A have the grid of alignment7302A and M1 7304A line.In contrast, unit 7300B has grid (or polymerization) line 7302B with reference to the part (b) of Figure 73With metal 1(M1) line 7304B.Unit 7300B is designated as OO unit, because of the right side in the left side of unit 7300B and unit 7300BSide has unjustified grid 7302B and M1 7304B line.
With reference to the part (c) of Figure 73, unit 7300C has grid (or polymerization) line 7302C and metal 1(M1) line 7304C.Unit 7300C is designated as EO unit, because the left side of unit 7300C has grid 7302C and M1 the line 7304C of alignment, butIt is the right side of unit 7300C with unjustified grid 7302C and M1 7304C line.In contrast, with reference to the part of Figure 73(d), unit 7300D has grid (or polymerization) line 7302D and metal 1(M1) line 7304D.It is mono- that unit 7300D is designated as OEMember, because the left side of unit 7300D has unjustified grid 7302D and M1 7304D line, but the right side of unit 7300D hasThere is grid 7302D and M1 the 7304D line of alignment.
The basis of first or second version as the selection for placing standard block type, Figure 74 are instantiated according to the disclosureEmbodiment block grade polymerization grid plan view.With reference to Figure 74, it includes grid line 7402 that block grade, which polymerize grid 7400, is walkedTo parallel along direction 7404.The cell layout boundary 7406 and 7408 specified is shown trend as in the second orthogonal directionOn.Grid line 7402 replaces between odd (E) and even (O) is specified.
Figure 75 is instantiated according to an embodiment of the present disclosure to be connect based on the exemplary of the standard block with different editionsIt is laid out by (qualifying).With reference to Figure 75, layout 7500 includes three units that type is 7300C/7300D, such as in 7406 He of boundaryIt is placed between 7408 with sequence from left to right: 7300D, the first 7300C adjoined and the 2nd 7300C spaced apart.?Selection between 7300C and 7300D be based on corresponding grid line 7402 E or the specified alignment of O.Being laid out 7500 further includesType is the unit of 7300A/7300B, as with sequence from left to right is placed below boundary 7408: the first 7300A and theTwo 7300A are spaced apart.Selection between 7300A and 7300B is the alignment specified based on the E or O corresponded on grid line 7402.ClothOffice 7500 just be laid out in 7500 and do not occur in the sense that dirty registration (DR) to be qualifying unit.It is to be appreciated that p specifies electric power(power), and a, b, c or o are exemplary pins.In arrangement 7500, the cross-border 7408 mutual arrangement (line of power line pUp).
Figure 75 is more generally referred to, in accordance with an embodiment of the present disclosure, integrated circuit structure includes multiple grid lines 7402,The pitch parallel and with the edge second direction orthogonal with first direction along the first direction of substrate.The first of cell typeVersion 7300C is on the first part of multiple grid lines 7402.The first version 7300C of cell type includes having along theMore than first a interconnection lines of second pitch in two directions, the second pitch be less than first segment away from.The second edition 7300D of cell typeThe side first version 7300C on the second part of the multiple grid line 7402, with the cell type along second directionTo adjacent.The second edition 7300D of cell type includes more than second a interconnection lines with the second pitch along second direction.The second edition 7300D of cell type is structurally different from the first version 7300C of cell type.
In embodiment, each interconnection line in more than first a interconnection lines of the first version 7300C of cell type is on edgeAt the first edge (for example, left edge) of the first version 7300C of the cell type of second direction without in second edge (exampleSuch as, right hand edge) at be aligned with each grid line in multiple grid lines 7402 along a first direction.Implement as oneIn example, the first version 7300C of cell type is the first version of NAND cell.The of the second edition 7300D of cell typeEach interconnection line more than two in a interconnection line is not in the first edge of the second edition 7300D of the cell type along second directionIt is aligned but with each grid line in multiple grid lines 7402 along a first direction in second edge at (for example, left edge)It is aligned at (for example, right hand edge) with each grid line in multiple grid lines 7402 along a first direction.As oneIn embodiment, the second edition 7300D of cell type is the second edition of NAND cell.
In another embodiment, the first and second versions are selected from cell type 7300A and 7300B.The first of cell typeThe first version of each interconnection line more than the first of version 7300A in a interconnection line in the cell type along second directionTwo edges of 7300A are aligned with each grid line in multiple grid lines 7402 along a first direction.Implement at oneIn example, the first version 7300A of cell type is the first version of phase inverter (inverter) unit.It is to be appreciated that unitEach interconnection line in more than second a interconnection lines of the second edition 7300B of type in other respects will be along second directionTwo edges of the second edition 7300B of cell type and each grid in multiple grid lines 7402 along a first directionLine is misaligned.In one embodiment, the second edition 7300B of cell type is the second edition of inverter module.
Figure 76 instantiate it is according to an embodiment of the present disclosure can not based on the exemplary of the standard block with different editionsReceive (failing) layout.With reference to Figure 76, layout 7600 includes three units that type is 7300C/7300D, such as on boundaryWhat the sequence between 7406 and 7408 from left to right was placed: 7300D, the first 7300C and spaced apart second adjoined7300C.Appropriate selection between 7300C and 7300D be based on corresponding grid line 7402 E or the specified alignment of O,As illustrated.However, layout 7600 further include type 7300A/7300B unit, such as with below boundary 7408 from a left sideIt places to right sequence: the first 7300A, being spaced apart with the 2nd 7300A.Layout 7600 and 7500 is the difference is that secondA 7300A is removed a line to the left.Although the selection between 7300A and 7300B should be based on the E on corresponding grid line 7402Or the alignment that O is specified, but it is really not so, and second unit 7300A is unjustified, and one consequence is unjustified electric power(p) line.Layout 7600 is due to having occurred the dirty unit for being registrated (DR) but failing in layout 7600.
Figure 77 instantiates the another exemplary according to an embodiment of the present disclosure based on the standard block with different editionsAcceptable (qualifying) layout.With reference to Figure 77, layout 7700 includes three units that type is 7300C/7300D, such as on boundaryWhat the sequence between 7406 and 7408 from left to right was placed: 7300D, the first 7300C and spaced apart second adjoined7300C.Selection between 7300C and 7300D be based on corresponding grid line 7402 E or the specified alignment of O.Layout7700 further include the unit of type 7300A/7300B, as placed with the sequence below boundary 7408 from left to right: 7300A,It is spaced apart with 7300B.The position of 7300B is identical as the position of 7300A in layout 7600, but the unit 7300B selected isIt is suitably aligned based on O on corresponding grid line 7402 is specified.Layout 7700, which is just laid out in 7700, does not have dirty registration (DR) to send outIt is qualifying unit in the sense that life.It is to be appreciated that p specifies electric power, and a, b, c or o are exemplary pins.It is arrangingIn 7700, cross-border 7408 mutual arrangement of power line p.
Collective reference Figure 76 and 77, a kind of method for manufacturing the layout of integrated circuit structure includes will be along first partyAlternate grid line into parallel multiple grid lines 7402 is appointed as idol (E) or surprise (O) along second direction.Then it isCell type on the multiple grid line 7402 selects position.This method further includes depending on position the of cell typeIt is selected between one version and the second edition of cell type, the second edition is structurally different from first version, wherein singleThe interconnection that the version of the selection of element type is directed in the edge of the cell type along second direction has even (E) or odd (O)It is specified, and wherein each grid line in the specified the multiple grid line with below interconnection at the edge of cell typeSpecified matching.
In another aspect, one or more embodiments are related to being included in FinFET (FET) frameworkIn the structure based on fin on manufacture metal resistor.In embodiment, the height as needed for faster message transmission rateFast IO, such precision resistor are implanted as the basic element of character of system on chip (SoC) technology.Due to low variation and closeThe characteristic of zero-temperature coefficient, such resistor can be to enable the IO framves of high speed analog circuit (such as CSI/SERDES) and scalingThe realization of structure.In one embodiment, resistor described herein is tunable resistor.
In order to provide context, traditional resistors used in current process technology are generally fallen in one of two classes: generalResistor or precision resistor.The general purpose resistor of such as trench contact resistor etc is cost neutrality, but by instituteAssociated big temperature coefficient of intrinsic variation or resistor or both in the manufacturing method used and can suffer from High variationDegree.Precision resistor can mitigate variation and temperature coefficient problem, but often with higher process costs and required systemThe increased quantity of manufacturing operation is cost.In high k/ metal gate process technology, the integrated of polysilicon precision resistor is demonstrate,provedIt is real more and more difficult.
According to embodiment, the thin film resistor (TFR) based on fin is described.In one embodiment, such resistanceDevice has the temperature coefficient close to zero.In one embodiment, such resistor shows the reduction from size ControlVariation.According to one or more other embodiments of the present disclosure, integrated precision resistor is manufactured in FinFET transistors framework.It is to be appreciated that the traditional resistors used in high k/ metal gate process technology are usually tungsten trench contact portion (TCN)Trap type resistor (well resistor) or polysilicon precision resistor.Such resistor increases process costs or complexityProperty, or High variation and poor temperature coefficient are subjected to due to the variation in used manufacturing process.In contrast, implementingIn example, the temperature system of the enabled cost neutrality for substituting known method of the manufacture of fin integrated thin-film resistor, good (close to zero)Several and low variation.
In order to provide further context, the polymerization line manufacture of two-dimentional (2D) metallic film or high doped has been usedThe precision resistor of the prior art.It is the mould with fixed value that such resistor, which tends to discretization (discretized),Plate, and therefore, it is difficult to realize the more fine granulation of resistance value.
One or more of to solve the above-mentioned problems, according to one or more other embodiments of the present disclosure, retouch hereinIt has stated using the fin pillar of such as silicon fin pillar (backbone) etc and has designed high density precision resistor.In a realityIt applies in example, includes that high density can be realized by using fin packaging density the advantages of such high density precision resistor.Additionally, in one embodiment, such resistor is integrated in rank identical with active transistor, so as to cause tightGather the manufacture of circuit.It can permit high packaging density using silicon fin pillar, and multiple freedom degrees be provided and carry out control resistorResistance.Therefore, in certain embodiments, the resistance value of wide scope is provided using the flexibility of fin pattern process, fromAnd tunable precision resistor is caused to manufacture.
As the exemplary geometric structure for being directed to the precision resistor based on fin, Figure 78 instantiates the reality according to the disclosureThe part cutting planes view and corresponding viewgraph of cross-section of the thin-film resistor structure based on fin of example are applied, wherein this is transversalFace view is intercepted along the a-a ' axis of part cutting planes view.
With reference to Figure 78, integrated circuit structure 7800 is included in above substrate 7804 outstanding across trench isolation region 7814Semiconductor fin 7802.In one embodiment, semiconductor fin 7802 is prominent from substrate 7804 and continuous with substrate 7804, such asDepicted in.Semiconductor fin has top surface 7805, first end 7806(since the fin in this view is capped,Therefore in the cutting planes view of part be shown as dotted line), second end 7808(since the fin in this view is capped,Therefore in the cutting planes view of part it is shown as dotted line) and an opposite side between first end 7806 and second end 7808Wall 7807.It is to be appreciated that the actually tegillum 7812 of side wall 7807 covers in the cutting planes view of part.
Top surface 7805, first end 7806, second end 7808 and opposite side of separation layer 7812 and semiconductor fin 7802Wall 7807 is conformal.Metal resistor layer 7810 and separation layer 7814 are conformal, the separation layer 7814 and semiconductor fin 7802Top surface 7805(metal resistor layer part 7810A), first end 7806(metal resistor layer part 7810B), second end7808(metal resistor layer part 7810C) and this to side wall 7807(metal resistor layer part 7810D) it is conformal.SpecificIn embodiment, metal resistor layer 7810 include it is adjacent with side wall 7807 have foot (footed) feature 7810E, as depictedLike that.Metal resistor layer 7810 and semiconductor fin 7802 are electrically isolated by separation layer 7812, and therefore with the electricity of substrate 7804 everyFrom.
In embodiment, metal resistor layer 7810 is constituted by being adapted to provide for close to the material of zero temperature coefficient, becauseThe resistance of metal resistor layer part 7810 does not change significantly on the operating temperature range for the thin film resistor (TFR) being produced from itBecome.In embodiment, metal resistor layer 7810 is titanium nitride (TiN) layer.In another embodiment, metal resistor layer 7810It is tungsten (W) metal layer.It is to be appreciated that can replace titanium nitride (TiN) or tungsten (W) or in combination be used for other metalsMetal resistor layer 7810.In embodiment, metal resistor layer 7810 has the thickness about in 2-5 nanometers of range.In embodiment, metal resistor layer 7810 has the resistivity about in the range of 100-100000 ohms/square(resistivity).
In embodiment, anode electrode and cathode electrode are electrically connected to metal resistor layer 7810, hereinafter connection figure84 are more fully described its exemplary embodiment.In one suchembodiment, metal resistor layer 7810, anode electrodePrecision thin-film resistor device (TFR) passive device is formed with cathode electrode.In embodiment, the TFR of the structure 7800 based on Figure 78Allow based on 7802 height of fin, 7802 width of fin, 7810 thickness of metal resistor layer and 7802 length of total fin come accurateGround controls resistance.These freedom degrees can permit the resistance value that circuit designers realize selection.Additionally, due to resistor patternChange is based on fin, therefore on the scale of transistor density, high density is possible.
In embodiment, it processes operations to provide using the fin FET of the prior art and is suitable for resistance of the manufacture based on finThe fin of device.The advantages of such method, can be its high density and the degree of approach with active transistor, make it easy to integrateInto circuit.In addition, the flexibility of the geometry of following fin takes into account the resistance value of wide scope.In exemplary process schemeIn, fin is patterned using pillar photoetching and spatialization (spacerization) method first.Then isolation from oxygen is usedCompound covers fin, makes the isolation oxide recess to set the height of resistor.Then conformally deposition is exhausted on finEdge oxide separates conductive film with following substrate, such as following silicon substrate of the substrate.Then it is deposited on finThe polysilicon film of metal or high doped.Then spatialization (spacerized) is carried out to generate precision resistor to film.
In exemplary process scheme, Figure 79-83 instantiates expression manufacture according to an embodiment of the present disclosure based on finThin-film resistor structure method in various operations plan view and corresponding viewgraph of cross-section.
It instantiates with reference to Figure 79, plan view and along the cross section taken in correspondence view that the b-b ' axis of plan view intercepts halfThe stage of the process flow after pillar formwork structure 7902 is formed on conductor substrate 7801.Then side wall spacers are formed7904, it is conformal with the sidewall surfaces of pillar formwork structure 7902.In embodiment, in the patterning of pillar formwork structure 7902Later, the oxide material of depositing conformal, and being etched anisotropically through (spatialization) to it then to provide side wallInterlayer 7904.
With reference to Figure 80, plan view, which instantiates, is for example exposing side wall spacers by mask and process-exposedThe stage of process flow after 7904 region 7906.Then, such as by etching process removal it is included in region 7906In side wall spacers 7904 part.The part being removed is will to be used for those of final fin definition part.
It is instantiated with reference to Figure 81, plan view and along the corresponding viewgraph of cross-section that the c-c ' axis of plan view interceptsRemove the part of side wall spacers 7904 that is included in the region 7906 of Figure 80 with formed fin pattern mask (for example,Oxide fin pattern mask) after process flow stage.Then pillar formwork structure 7902 is removed, and will be remainingPattern mask is used as carrying out patterned etching mask to substrate 7801.In the patterning and fin figure of substrate 7801When the subsequent removal of case mask, semiconductor fin 7802 keeps prominent from new patterned semiconductor substrate 7804 and connects therewithIt is continuous.Semiconductor fin 7802 has top surface 7805, first end 7806, second end 7808 and between the first end and a second endA pair of sidewalls 7807, as Figure 78 as described above description.
It instantiates with reference to Figure 82, plan view and along the cross section taken in correspondence view that the d-d ' axis of plan view intercepts in shapeAt the stage of the process flow after trench isolation layer 7814.In embodiment, by deposition of insulative material and be then recessed withIt limits fin height (Hsi) and limits fin height to form trench isolation layer 7814.
It instantiates with reference to Figure 83, plan view and along the cross section taken in correspondence view that the e-e ' axis of plan view intercepts in shapeAt the stage of the process flow after separation layer 7812.In embodiment, separation layer is formed by chemical vapor deposition processes7812.With the top surface (7805) of semiconductor fin 7802, first end 7806, second end 7808 and this is conformal to side wall (7807)Ground forms separation layer 7812.Then be conformally formed metal resistor layer 7810 with separation layer 7812, separation layer 7812 with partly leadThe top surface of body fin 7802, first end, second end and this is conformal to side wall.
In embodiment, metal electricity is formed using blanket (blanket) deposition and subsequent anisotropic etch processHinder device layer 7810.In embodiment, metal resistor layer 7810 is formed using atomic layer deposition (ALD).In embodiment, goldenBelong to resistor layer 7810 and is formed the thickness in 2-5 nanometers of range.In embodiment, metal resistor layer 7810 be orIncluding titanium nitride (TiN) layer or tungsten (W) layer.In embodiment, metal resistor layer 7810 is formed with 100-100000Resistivity in the range of ohms/square.
In subsequent processing operation, pair of anode or cathode electrode can be formed, and figure can be electrically coupled toThe metal resistor layer 7810 of 83 structure.As an example, Figure 84 instantiate it is according to an embodiment of the present disclosure based on finThe plan view of thin-film resistor structure has the various exemplary positions for anode or cathode electrode contact.
With reference to Figure 84, in the first anode or cathode electrode, such as 8400,8402,8404,8406,8408,8410 oneIt is a, it is electrically connected to metal resistor layer 7810.Second plate or cathode electrode, for example, 8400,8402,8404,8406,8408,Another in 8410, is electrically connected to metal resistor layer 7810.In embodiment, metal resistor layer 7810, anode electrodePrecision thin-film resistor device (TFR) passive device is formed with cathode electrode.Accurate TFR passive device can be it is tunable becauseResistance can be selected based on the first anode or cathode electrode and the distance between second plate or cathode electrode.Shape can be passed throughAt various virtual electrodes, such as 8400,8402,8404,8406,8408,8410 and other possibilities, and then basePractical pairing is selected to provide option in interconnection circuit.Alternatively, Sole anode or cathode pairing can be formed, wherein in TFRPosition is selected for each during the manufacture of device.In any case, in embodiment, in anode or cathode electrodeOne position in the end (for example, at position 8400 or 8402) of fin 7802, in corner's (example of fin 7802Such as, at position 8404,8406 or 8408), or the center (for example, at position 8410) of the transition between turning.
In the exemplary embodiment, the first anode or cathode electrode close to semiconductor fin 7802 7806 ground of first end,Such as at position 8400, it is electrically connected to metal resistor layer 7810.Second plate or cathode electrode are close to semiconductor fin7802 7808 ground of second end, for example at position 8402, be electrically connected to metal resistor layer 7810.
In a further exemplary embodiment, the first end 7806 of the first anode or cathode electrode close to semiconductor fin 7802Ground, for example at position 8400, be electrically connected to metal resistor layer 7810.Second plate or cathode electrode are far from semiconductor fin7802 7808 ground of second end, for example at position 8410,8408,8406 or 8404, be electrically connected to metal resistor layer 7810.
In a further exemplary embodiment, the first end 7806 of the first anode or cathode electrode far from semiconductor fin 7802Ground, for example at position 8404 or 8406, be electrically connected to metal resistor layer 7810.Second plate or cathode electrode are far from partly leading7808 ground of second end of body fin 7802, for example at position 8410 or 8408, be electrically connected to metal resistor layer 7810.
More specifically, according to one or more other embodiments of the present disclosure, the shape characteristic of the transistor architecture based on finIt is used as manufacturing the basis of embedded resistor.In one embodiment, precision resistor is manufactured on fin structure.SpecificEmbodiment in, such method enables the with very high density integrated of the passive component of such as precision resistor etc.
It is to be appreciated that various fin geometries are suitable for manufacturing the precision resistor based on fin.Figure85A-85D instantiates according to an embodiment of the present disclosure for manufacturing the various fin geometric forms of the precision resistor based on finThe plan view of shape.
In embodiment, with reference to Figure 85 A-85C, semiconductor fin 7802 is non-linearity (non-linear) semiconductor finPiece.In one embodiment, semiconductor fin 7802 projects through trench isolation region above substrate.Metal resistor layer7810 is conformal with separation layer (not shown), and the separation layer and non-linearity semiconductor fin 7802 are conformal.In one embodiment,Two or more anode or cathode electrodes 8400 are electrically connected to metal resistor layer 7810, and exemplary optional position passes through figureDashed circle in 85A-85C is shown.
Non-linearity fin geometry includes one or more turnings, such as, but not limited to single turning (for example, L shape),Two turnings (for example, U-shaped), four turnings (for example, S-shaped) or six turnings (for example, structure of Figure 78).In embodiment,Non-linearity fin geometry is open architecture geometry.In another embodiment, non-linearity fin geometry is closingConstruction geometry structure.
As the exemplary embodiment of the open architecture geometry for non-linearity fin geometry, Figure 85 A is illustratedWith a turning to provide the non-linearity fin of open architecture L shape geometry.Figure 85 B instantiate tool there are two turning withThe non-linearity fin of open architecture U-shaped geometry is provided.In the case where open architecture, non-linearity semiconductor fin 7802 hasThere are top surface, first end, second end and a pair of sidewalls between the first end and a second end.Metal resistor layer 7810 with everyAbsciss layer (not shown) is conformal, this between the separation layer and top surface, first end, second end and first end and second end is rightSide wall is conformal.
In certain embodiments, referring again to Figure 85 A and 85B, the first anode or cathode electrode are non-close to open architectureThe first end of wire-type semiconductor fin it is electrically connected to metal resistor layer 7810, and second plate or cathode electrode are close to openingIt is electrically connected to metal resistor layer 7810 with putting the second end of structure non-linearity semiconductor fin.In another specific embodimentIn, the first anode or cathode electrode close to open architecture non-linearity semiconductor fin first end be electrically connected to metal resistorLayer 7810, and the second end of second plate or cathode electrode far from open architecture non-linearity semiconductor fin be electrically connected to goldBelong to resistor layer 7810.In another specific embodiment, the first anode or cathode electrode are partly led far from open architecture non-linearityIt is electrically connected to the first end of body fin metal resistor layer 7810, and second plate or cathode electrode are non-far from open architectureIt is electrically connected to metal resistor layer 7810 to the second end of wire-type semiconductor fin.
As the exemplary embodiment of the enclosed construction geometry for non-linearity fin geometry, Figure 85 C is illustratedThere are four turnings to provide the non-linearity fin of enclosed construction square or rectangular geometry for tool.In the feelings of enclosed constructionUnder condition, non-linearity semiconductor fin 7802 has top surface and a pair of sidewalls, and in particular inner sidewall and lateral wall.SoAnd enclosed construction does not include the first and second ends of exposure.Metal resistor layer 7810 and separation layer (not shown) are conformal, describedThe top surface, inner sidewall and lateral wall of separation layer and fin 7802 are conformal.
In another embodiment, with reference to Figure 85 D, semiconductor fin 7802 is wire-type semiconductor fin.In one embodimentIn, semiconductor fin 7802 projects through trench isolation region above substrate.Metal resistor layer 7810 (does not show with separation layerOut) conformal, the separation layer and wire-type semiconductor fin 7802 are conformal.In one embodiment, two or more anodes orCathode electrode 8400 is electrically connected to metal resistor layer 7810, and exemplary optional position is shown by the dashed circle in Figure 85 DOut.
In another aspect, in accordance with an embodiment of the present disclosure, it describes for photoetching for high-resolution phase shifting mask(PSM) new construction manufactured.Such PSM mask can be used for general (direct) photoetching or complementary photoetching (complementaryLithography).
Photoetching be commonly used to manufacture during to form pattern in photoresist layer.In a photolithographic process, photoresistLayer is deposited on the layer below to be etched.In general, following layer is semiconductor layer, but its can be it is any kind of hardMask or dielectric substance.Then it is selectively exposed to photoresist layer by photomask or reticle mask (reticle)Radiation.Then photoresist is made to develop, and in the case where " just " photoresist, removal is exposed to the photoresist of radiationThose parts.
For being placed on commonly referred to as " litho machine to the patterned photomask of wafer progress or reticle mask(stepper) " or in the photolithographic exposure tool of " scanner ".In litho machine or scanner machine, photomask or centre are coveredMould is placed between radiation source and wafer.Photomask or reticle mask are usually by placing patterned chromium on a quartz substrate(absorbed layer) is formed.It radiates in the position of not chromium substantially not damply by the quartzy portion of photomask or reticle maskPoint.On the contrary, radiation is not passed through the chromium part of mask.Because the radiation that is incident on mask or pass completely through quartz portions orStopped completely by chromium part, therefore this kind of mask is known as binary mask (binary mask).Mask is selectively passed through in radiationLater, by making the image of mask pass through a series of lens projects into photoresist, the pattern on mask is transferred to photoresistIn material.
As the feature on photomask or reticle mask becomes increasingly closer together, when the size and light of the feature on maskWhen the wavelength in source is suitable, diffraction effect comes into effect.The image that diffraction makes to project on photoresist is smudgy, leads to differenceResolution ratio.
A kind of method for preventing the desired pattern of diffraction pattern interference photoresist is with referred to as shift unit(shifter) opening of hyaline layer covering photomask or the selection in reticle mask.Shift unit and another contiguous set out-phaseGround shifts one of set of exposed radiation (exposing), this makes the interference figure for carrying out self-diffraction invalid.This method is claimedFor phase shifting mask (PSM) method.However, reducing defect and the alternative mask fabrication scheme of output increased in mask production is lightCarve the significant concern field of process development.
The mask that one or more other embodiments of the present disclosure are related to the method for manufacturing mask and obtain.ForOffer context, meet the aggressive device scaling target of semi-conductor industry proposition requirement nourish mask will be withHigh fidelity carrys out the ability of pattern smaller features.However, the method for patterning smaller and smaller feature proposes fabrication maskHuge challenge.In this respect, current widely used mask carrys out figure dependent on the concept of phase shifting mask (PSM) technologyCase feature.However, reduced while creating smaller and smaller pattern defect be still biggest obstacle in fabrication mask itOne.May be had the shortcomings that using phase shifting mask several.Firstly, the design of phase shifting mask is need vast resources relative complexProcess.Second, due to the property of phase shifting mask, it is difficult to check in phase shifting mask with the presence or absence of defect.In phase shifting mask in this wayDefect derived from current Integrated Solution for generating mask itself.Some phase shifting masks are using heaviness and are slightly easy to occurThe method of defect patterns thick light absorbing material, and then transfers the pattern onto the secondary layer for facilitating phase shift.Make to askTopic complicates, and absorbed layer is subjected to plasma etching twice, and therefore such as loading effect (loading effect),The undesirable effect of the plasma etching of reactive ion etching lag, charging and reproducible effect etc causes mask to produceThe defects of.
Innovation for manufacturing the material and novel integrated technology of zero defect mask keeps high priority with energy deviceScaling.Therefore, for whole benefits of utilization phase shift mask techniques, it may be necessary to use and (i) pattern displacement with high fidelityDevice layer and absorber is (ii) patterned during the final stage of manufacture and only the primary novelty of patterning absorber is integratedScheme.Additionally, such fabrication scheme can also provide other advantages, during the flexibility of such as material selection, manufactureThe substrate damage of reduction and the increased output in fabrication mask.
Figure 86 instantiates the viewgraph of cross-section of photoetching mask structure 8601 according to an embodiment of the present disclosure.Mask8601 include region (in-die) 8610, frame area 8620 and region tube core frame interface (interface) 8630 in tube core.Tube core frame interface zone 8630 includes the adjacent part of tube core inner region 8610 and frame area 8620.Tube core inner region 8610Including the patterned shift unit layer 8606 being placed directly on substrate 8600, wherein patterned shift unit layer hasThere is the feature of side wall.Frame area 8620 surrounds tube core inner region 8610 and the warp including being placed directly on substrate 8600Patterned absorbed layer 8602.
The tube core frame interface zone 8630 being disposed on substrate 8600 includes double stacked 8640.Double stacked 8640Including the upper layer 8604 being disposed on the patterned shift unit layer 8606 in lower part.The upper layer 8604 of double stacked 8640 by withThe identical material of patterned absorbed layer 8602 of frame area 8620 is constituted.
In embodiment, the upper space 8608 of the feature of patterned shift unit layer 8606, which has, is different from tube core-The height of the upper space 8612 of the feature of frame interface zone and the upper space 8614 for the feature being different from frame areaDegree.In addition, in embodiment, the height of the upper space 8612 of tube core-frame interface zone feature is different from frame areaFeature upper space 8614 height.The typical thickness of phase shifter layer 8606 is changed from 40-100nm, and the allusion quotation of absorbed layerType thickness is changed from 30-100nm.In embodiment, the absorbed layer 8602 in frame area 8620 with a thickness of 50nm, be arrangedThe combination thickness of absorbed layer 8604 on the shift unit layer 8606 in tube core-frame interface zone 8630 is 120nm, and frameAbsorber in frame region with a thickness of 70nm.In embodiment, substrate 8600 is quartz, and patterned shift unit layer includesFollowing material, such as, but not limited to molybdenum silicide (molybdenum-silicide), molybdenum silicide nitrogen oxides, molybdenum silicide nitride object,Silicon oxynitride or silicon nitride, and absorbent material is chromium.
Embodiment disclosed herein can be used for manufacturing various types of integrated circuit or microelectronic component.It is suchThe example of integrated circuit includes but is not limited to processor, chip set components, graphics processor, digital signal processor, microcontrollerDevice and the like.In other embodiments, semiconductor memory can be manufactured.In addition, integrated circuit or other microelectronicsDevice can be used in various electronic equipments known in the art.For example, in computer system (for example, desktop computer, above-kneeType computer, server), cellular phone, in personal electronic equipments etc..Integrated circuit can in system bus and other portionsPart coupling.For example, processor can be coupled to memory, chipset etc. by one or more buses.Processor, memory andEach of chipset can be manufactured potentially using method disclosed herein.
Figure 87 instantiates calculating equipment 8700 in accordance with one embodiment of the present disclosure.Calculate 8700 accommodates plate of equipment8702.Plate 8702 may include multiple components, including but not limited to processor 7904 and at least one communication chip 8706.ProcessingDevice 8704 is by physical coupling and is electrically coupled to plate 8702.In some embodiments, at least one communication chip 8706 also physicsIt couples and is electrically coupled to plate 8702.In other embodiment, communication chip 8706 is a part of processor 8704.
Depending on its application, calculating equipment 8700 may include other component, they can or can not physical couplingAnd it is electrically coupled to plate 8702.These other components include but is not limited to, and volatile memory (for example, DRAM) non-volatile is depositedReservoir (for example, ROM), flash memory, graphics processor, digital signal processor, encryption processor, chipset, antenna, display,Touch-screen display, touch screen controller, battery, audio codec, Video Codec, power amplifier, global location(such as hard disk drives for system (GPS) equipment, compass, accelerometer, gyroscope, loudspeaker, camera and mass-memory unitDynamic device, compact disk (CD), digital versatile disc (DVD) and the like).
Communication chip 8706 enable for from calculate equipment 8700 transmit data wireless communication.Term " wireless " andIts derivative can be used for describing circuit, equipment, system, method, technology, communication channel etc., they can be by using modulationElectromagnetic radiation data are transmitted by non-solid medium.The term does not imply that associated equipment does not include any conducting wire, to the greatest extentPipe in some embodiments they may not include.Communication chip 8706 may be implemented any in a variety of wireless standards or agreementStandard or agreement, any standard or agreement in a variety of wireless standards or agreement include but is not limited to Wi-Fi(IEEE 802.11Family), 802.16 family of WiMAX(IEEE), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+,HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, its derivative and it is designated as 3G, 4G, 5G or moreAny other wireless protocols.Calculating equipment 8700 may include multiple communication chips 8706.For example, the first communication chip 8706 canTo be exclusively used in compared with short-distance wireless communication, such as Wi-Fi and bluetooth, and the second communication chip 8706 can be exclusively used in longer range withoutLine communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and other.
The processor 8704 for calculating equipment 8700 includes the integrated circuit die being encapsulated in processor 8704.In this public affairsIn some embodiments for the embodiment opened, the integrated circuit die of processor includes one or more structures, such as according to thisThe integrated circuit structure of disclosed embodiment building.Term " processor " may refer to processing from register or memory orThe electronic data to be transformed into other electronics that can store in register or memory or both by the electronic data of the twoAny equipment of data or the part of equipment.
Communication chip 8706 also includes the integrated circuit die being encapsulated in communication chip 8706.According to the another of the disclosureOne embodiment constructs the integrated circuit die of communication chip according to embodiment of the present disclosure.
In other embodiment, being contained in another component calculated in equipment 8700 may include according to the disclosureThe embodiment of embodiment and the integrated circuit die constructed.
In various embodiments, calculating equipment 8700 can be laptop computer, net book, notebook, ultrabook, intelligenceEnergy number, PDA(Personal Digital Assistant), super mobile PC, mobile phone, desktop computer, server, is engaged tablet computerPrint machine, scanner, monitor, set-top box, amusement control unit, digital camera, portable music player or digital recordingMachine.In other embodiment, calculating equipment 8700 can be any other electronic equipment of processing data.
Figure 88 instantiates the intermediary layer (interposer) 8800 including one or more other embodiments of the present disclosure.Intermediary layer8800 be the substrate between two parties for first substrate 8802 to be bridged to the second substrate 8804.First substrate 8802, which can be, for example to be collectedAt circuit die.The second substrate 8804 can be such as memory module, computer motherboard or another integrated circuit die.It is logicalOften, the purpose of intermediary layer 8800 is will to connect to expand to broader pitch or connection is rerouted to different connections.For example,Integrated circuit die can be coupled to ball grid array (BGA) 8806 by intermediary layer 8800, then may be coupled to the second substrate8804.In some embodiments, the first and second substrates 8802/8804 are attached to the opposite side of intermediary layer 8800.In other realitiesIt applies in example, the first and second substrates 8802/8804 are attached to the same side of intermediary layer 8800.And in a further embodiment,Three or more substrates are interconnected by intermediary layer 8800.
Intermediary layer 8800 can be by epoxy resin, glass fiber reinforced epoxy resin, ceramic material or such as polyimidesEtc polymer material formed.In other embodiment, intermediary layer can be formed by alternate rigidity or flexible material,The rigidity or flexible material formation may include for the above-mentioned identical material used in semiconductor substrate, such as silicon, germanium andOther iii-vs and IV race material.
Intermediary layer may include metal interconnection 8808 and through-hole 8810, including but not limited to pass through through silicon via (through-Silicon via) (TSV) 8812.Intermediary layer 8800 can also include embedded devices 8814, including passive and active device twoPerson.Such devices include but is not limited to capacitor, decoupling capacitors, resistor, inductor, fuse, diode, transformer, biographySensor and Electrostatic Discharge device.Such as radio frequency (RF) equipment, power amplifier, power supply management device, antenna, array, biographyThe more complicated equipment of sensor and MEMS device etc can also be formed on intermediary layer 8000.According to the implementation of the disclosureExample, device disclosed herein or process can interlayers 8800 or in the portion that manufacture is included in intermediary layer 8800 during manufacturingIt is used in part.
Figure 89 is the collection according to an embodiment of the present disclosure using according to one or more process manufactures described hereinAt circuit (IC) or the isometric view of the mobile computing platform 8900 including one or more features described herein(isometric view).
Mobile computing platform 8900 can be configured for electronic data show, electronic data processing and radio subnumberAccording to any portable device of each of transmission.For example, mobile computing platform 8900 can be tablet computer, intelligence electricityAny equipment in words, laptop computer etc., and including be in the exemplary embodiment touch screen (condenser type, inductance type,Resistance-type etc.) display screen 8905, chip-scale (SoC) or package level integrated system 8910 and battery 8913.As shown, by moreIntegrated horizontal in the enabled system 8910 of high transistor packing density is bigger, then mobile computing platform 8900 can be by battery8913 or such as solid state drive etc the part that occupies of non-volatile memory device it is bigger, or be used for improved platformFunctional transistor gate counts bigger.Similarly, the carrier mobility of each transistor in system 8910(carrier mobility) is bigger, then functional bigger.As such, the technology of many descriptions can be flat to enable mobile computing hereinPerformance and form factor in platform 8900 are improved.
Integrated system 8910 is further illustrated in enlarged view 8920.In the exemplary embodiment, sealed in unit8977 include according to one or more processes manufactures described herein or including one or more features described herein extremelyA few memory chip (for example, RAM) or at least one processor chips are (for example, multi-core microprocessor and/or graphics processDevice).Sealed in unit 8977 also together with power management integrated circuits (PMIC) 8915, RF(is wireless) in integrated circuit (RFIC) 8925And the one or more of its controller 8911 is coupled to plate 8960, RF(is wireless) integrated circuit (RFIC) 8925 include broadband RF(wireless) transmitter and/or receiver (e.g., including digital baseband, and analog front-end module further includes on the transmit pathPower amplifier and low-noise amplifier on the receive path).Functionally, PMIC 8915 executes the power of battery and adjusts,DC to DC conversion etc., and therefore there is the input for being coupled to battery 8913, and have to every other functional module and provideThe output of electric current supply.As illustrated in further, in the exemplary embodiment, RFIC 8925 has the output for being coupled to antenna,Realize any standard or agreement in a variety of wireless standards or agreement to provide, a variety of wireless standards or agreement include butBe not limited to 802.11 family of Wi-Fi(IEEE), 802.16 family of WiMAX(IEEE), IEEE 802.20, long term evolution(LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, its derivative withAnd it is designated as any other wireless protocols of 3G, 4G, 5G or more.In an alternative embodiment, in these plate grade modulesEach can be integrated on the individual IC for the package substrate of equipment 8977 for being coupled to encapsulation, or be integrated inIt is coupled to the single IC(SoC of the package substrate of the equipment 8977 of encapsulation) in.
In another aspect, semiconductor packages is for protecting integrated circuit (IC) chip or tube core, and is also used to as pipeCore provides the electrical interface to external circuit.With more and more demands to smaller electronic device, semiconductor packages is designedIt obtains even more compact and must support bigger current densities.In addition, the demand to higher performance device causes to improvementSemiconductor packages needs, improved semiconductor packages is enabled with the subsequent compatible thin encapsulation profile of processing and low of assemblingWhole warpage (warpage).
In embodiment, the wire bonding (wire bonding) of ceramics or organic packaging substrates is used.In another realityIt applies in example, tube core is installed to ceramics or organic packaging substrates using C4 process.Particularly, C4 soldered ball may be implemented(solder ball) connection between semiconductor devices and substrate to provide flip-chip (flip chip) interconnection.Flip-chipOr controlled collapse chip connection (C4) is the semiconductor devices for such as integrated circuit (IC) chip, MEMS or component etcSetup Type utilizes pedestal (solder bump) rather than wire bonding.Pedestal is deposited on C4 pad,On the top side of substrate package.In order to which semiconductor devices is installed to substrate, overturn it so that effectively side faces downwardly peaceFill region.Semiconductor devices is directly connected to substrate using pedestal.
Figure 90 instantiates the viewgraph of cross-section of the tube core of flip-chip installation according to an embodiment of the present disclosure.
With reference to Figure 90, in accordance with an embodiment of the present disclosure, device 9000 includes tube core 9002, such as according to described herein oneA or multiple process manufactures or including one or more features described herein integrated circuits (IC).Tube core 9002 includesMetallized pads 9004 on it.The package substrate 9006 of such as ceramics or organic substrate etc includes connection on it9008.Soldered ball 9010 by being coupled to metallized pads 9004 and connection 9008 is electrically connected tube core 9002 and package substrate9006.Underfill (underfill) material 9012 surrounds soldered ball 9010.
Processing flip-chip may look like conventional IC manufacture, have several additional operations.Close to manufacturing processAt the end of, it is metallized attachment pad so that they are easier to receive welding.If this generally includes dry-cure.Then everySmall solder joint is deposited in a metallized pads.Then chip conventionally is cut from wafer.In order to which flip-chip is attached in circuit,By chip upside down so that solder joint is downward on the connector on following electronic device or circuit board.Then usually using ultrasound orAlternatively solder reflow process carrys out refuse solder to generate electrical connection.This is also between the circuit of chip and following installationLeave small space.In most cases, then " underfill " electrical isolation adhesive to provide stronger mechanical connection,Heat bridge is provided, and ensures that solder engagement will not be due to the different heating of chip and the rest part of system and by stress.
In other embodiments, in accordance with an embodiment of the present disclosure, the encapsulation for realizing update and tube core to tube core interconnecting method,Such as by through silicon via (TSV) and silicon intermediary layer, incorporated with manufacturing according to one or more process manufactures described hereinIntegrated circuit (IC) or high-performance multi-chip module (MCM) including one or more features described herein and system-levelIt encapsulates (System in Package) (SiP).
Therefore, embodiment of the disclosure includes advanced integrated circuit structure manufacture.
Although specific embodiment is hereinbefore described, these embodiments are not limiting as the scope of the present disclosure,Even if when describing only single embodiment about special characteristic.The example of the feature provided in the disclosure is intended that illustrationProperty and not restrictive, unless otherwise stated.Description above is intended to covering such as to the art technology for benefiting from the disclosureSuch replacement, modification and the equivalent that will be clear that for personnel.
The scope of the present disclosure includes the combination of any feature or feature disclosed in (explicitly or implicitly) herein, orIts any generalization of person, whether is it alleviating any problem or the whole issue in problem presented herein.Therefore,New claim can be planned to during the prosecution (prosecution) of the application (or the application for requiring its priority)Any such combination of feature.Particularly, with reference to appended claims, can by from dependent claims feature withThose of independent claims feature is combined, and can be wanted in any suitable manner and not only with the right of accompanyingSpecific combination cited by asking in book is to combine the feature from each independent claims.
Following example is related to other embodiment.Can by the various features of different embodiments and some features for including andOther features being excluded carry out various combinations to adapt to various different applications.
Example embodiment 1: a kind of integrated circuit structure includes: the fin including silicon, and the fin has lower fin portionWith upper fin portion.First insulating layer is directly on the side wall of the lower fin portion of fin, wherein the first insulating layer is to include siliconWith the undoped insulating layer of oxygen.Directly on the first insulating layer, the first insulating layer is directly in the lower fin of fin for second insulating layerOn partial side wall, second insulating layer includes silicon and nitrogen.Dielectric filler material and direct second on the first insulating layer are absolutelyEdge layer is directly laterally adjacent, and the first insulating layer is directly on the side wall of the lower fin portion of fin.
Example embodiment 2: the integrated circuit structure of example embodiment 1, wherein the first insulating layer includes silicon and oxygen, andWithout other atomic species with the atomic concentration greater than 1E15 atoms per cubic centimeter.
Example embodiment 3: the integrated circuit structure of example embodiment 1 or 2 is received wherein the first insulating layer has in 0.5-2Thickness in the range of rice.
Example embodiment 4: the integrated circuit structure of example embodiment 1,2 or 3, wherein second insulating layer has and receives in 2-5Thickness in the range of rice.
Example embodiment 5: the integrated circuit structure of example embodiment 1,2,3 or 4, wherein dielectric filler material includes siliconAnd oxygen.
Example embodiment 6: the integrated circuit structure of example embodiment 1,2,3,4 or 5 further includes in the upper fin portion of finPoint top on and the gate electrode laterally adjacent with the side wall of the upper fin portion of fin.
Example embodiment 7: a kind of integrated circuit structure includes: the first fin including silicon, under first fin hasShoulder feature at fin portion and upper fin portion and region between lower fin portion and upper fin portion.The collectionAt circuit structure further include: the second fin including silicon, second fin have lower fin portion and upper fin portion andThe shoulder feature at region between lower fin portion and upper fin portion.The integrated circuit structure further includes the first insulationLayer, first insulating layer includes silicon and oxygen, and is not had with the atomic concentration greater than 1E15 atoms per cubic centimeterOther atomic species, the first insulating layer is directly on the side wall of the lower fin portion of the first fin and directly in the second finOn the side wall of lower fin portion, the first insulating layer has the first end substantially coplanar with the shoulder feature of the first fin, andAnd first insulating layer have the second end substantially coplanar with the shoulder feature of the second fin.The integrated circuit structure also wrapsInclude second insulating layer, the second insulating layer includes silicon and nitrogen, the second insulating layer directly on the first insulating layer, describedOne insulating layer is directly on the side wall of the lower fin portion of the first fin and directly in the side of the lower fin portion of the second finOn wall.Dielectric filler material and second insulating layer directly on the first insulating layer are directly laterally adjacent, first insulationLayer is directly on the side wall of the lower fin portion of the first fin and directly on the side wall of the lower fin portion of the second fin.
Example embodiment 8: the integrated circuit structure of example embodiment 7, wherein dielectric filler material has upper surface,A part of the upper surface of middle dielectric filler material is below the shoulder feature of the first fin and in the shoulder of the second finBelow feature.
Example embodiment 9: the integrated circuit structure of example embodiment 7 or 8, wherein the first insulating layer has to be received in 0.5-2Thickness in the range of rice.
Example embodiment 10: the integrated circuit structure of example embodiment 7,8 or 9, wherein second insulating layer has in 2-5Thickness in the range of nanometer.
Example embodiment 11: the integrated circuit structure of example embodiment 7,8,9 or 10, wherein dielectric filler material includeSilicon and oxygen.
Example embodiment 12: the integrated circuit structure of example embodiment 7,8,9,10 or 11 further includes in the first finThe laterally adjacent gate electrode of the side wall of upper fin portion on the top of upper fin portion and with the first fin, in the second finUpper fin portion top on and the gate electrode laterally adjacent with the side wall of the upper fin portion of the second fin, andThe gate electrode on dielectric filler material between one fin and the second fin.
Example embodiment 13: it is a kind of manufacture integrated circuit structure method include: to form the fin including silicon.The methodFurther include: form first insulating layer conformal directly on fin and with fin, the first insulating layer includes silicon and oxygen, and notWith other atomic species with the atomic concentration greater than 1E15 atoms per cubic centimeter.The method also includes: it is formed straightThe second insulating layer conformal on the first insulating layer and with the first insulating layer is connect, second insulating layer includes silicon and nitrogen.The sideMethod further include: form dielectric filler material directly over the second dielectric.The method also includes: make dielectric filler materialMaterial, the first insulating layer and second insulating layer recess, to provide the fin of the upper fin portion with exposure.
Example embodiment 14: the method for example embodiment 13, wherein forming the first insulating layer includes using chemical vapor depositionProduct process.
Example embodiment 15: the method for example embodiment 13 or 14, wherein forming second insulating layer includes using chemical gasPhase deposition process.
Example embodiment 16: the method for example embodiment 13,14 or 15, wherein forming dielectric filler material includes usingSpin coating process.
Example embodiment 17: the method for example embodiment 13,14,15 or 16, wherein formation dielectric filler material includesSpin-on material is exposed to steam treatment, to provide the curing materials for including silicon and oxygen.
Example embodiment 18: the method for example embodiment 13,14,15,16 or 17, wherein make dielectric filler material,One insulating layer and second insulating layer recess include using wet etch process.
Example embodiment 19: the method for example embodiment 13,14,15,16 or 17, wherein make dielectric filler material,One insulating layer and second insulating layer recess include using dry etch process.
Example embodiment 20: the method for example embodiment 13,14,15,16,17,18 or 19 further includes the upper fin in finLaterally it is adjacent to form gate electrode on the top of piece part and with the side wall of the upper fin portion of fin.