CN109841526B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate is provided with an initial fin part, and the initial fin part is internally provided with a first atom and a second atom; concentrating the top of the initial fin part to form a fin part and a first material layer positioned on the fin part, wherein second atoms in the fin part have first atomic percent concentration, second atoms in the first material layer have second atomic percent concentration, the second atomic percent concentration is greater than the first atomic percent concentration, and the bonding force between the second atoms and oxygen atoms is greater than that between the first atoms and the oxygen atoms; and oxidizing the side wall of the fin part, the side wall of the first material layer and the top surface to form an interface layer. The transistor formed by the method has stable performance and long service life.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and integration of the semiconductor device are increased, the gate size of the planar transistor is also shortened, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.

In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. The structure of the fin field effect transistor comprises: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, and the top surface of the isolation layer is lower than the top surface of the fin part and covers part of the side wall of the fin part; the grid electrode structure is positioned on the surface of the isolation layer, the side wall of the fin part and the surface of the top part; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.

However, the performance of the conventional finfet is poor.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.

To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with an initial fin part, and the initial fin part is internally provided with a first atom and a second atom; concentrating the top of the initial fin part to form a fin part and a first material layer positioned on the fin part, wherein a second atom in the fin part has a first atomic percent concentration, a second atom in the first material layer has a second atomic percent concentration, the second atomic percent concentration is greater than the first atomic percent concentration, and the bonding force between the second atom and oxygen atoms is greater than that between the first atom and the oxygen atoms; and oxidizing the side wall of the fin part, the side wall of the first material layer and the top surface to form an interface layer.

Optionally, the material of the initial fin portion includes silicon germanium, the first atoms are germanium atoms, and the second atoms are silicon atoms; the atomic percentage concentration of the first atoms in the initial fin portion is 25% -65%.

Optionally, the concentration process includes an annealing process; the parameters of the annealing process comprise: the temperature is 450-650 ℃, the time is 20-240 minutes, the pressure is 1-760 torr, and the ambient gas comprises oxygen.

Optionally, the material of the first material layer is silicon.

Optionally, the thickness of the first material layer is: 2 to 4 nanometers.

Optionally, the concentration process further includes forming a second material layer between the fin and the first material layer, where an atomic percent concentration of the first atoms in the second material layer is greater than an atomic percent concentration of the first atoms in the fin.

Optionally, the material of the second material layer includes silicon germanium, and the atomic percentage concentration of the first atoms in the second material layer is: 50 to 75 percent.

Optionally, the thickness of the second material layer is: 1 to 7 nanometers.

Optionally, the substrate further has an insulating layer thereon; the forming method of the initial fin portion comprises the following steps: forming a fin material layer on the insulating layer, wherein the fin material layer is provided with a pattern layer, and part of the fin material layer is exposed out of the pattern layer; and etching the fin part material layer by taking the pattern layer as a mask until the insulating layer is exposed to form an initial fin part.

Optionally, the material of the fin material layer includes silicon germanium, the first atoms include germanium atoms, and the atomic percentage concentration of the first atoms in the fin material layer is 25% to 65%; the forming process of the fin material layer comprises the following steps: an epitaxial growth process; the thickness of the fin material layer is as follows: 10 to 70 nanometers.

Optionally, the substrate comprises a first region and a second region; the first region is used for forming devices in a peripheral region, and the second region is used for forming devices in a core region; the interface layer comprises a first interface layer positioned in the first area and a second interface layer positioned in the second area, and the thickness of the first interface layer is greater than that of the second interface layer.

Optionally, the material of the first interface layer includes silicon oxide; the forming process of the first interface layer comprises an in-situ water vapor generation process; the thickness of the first interface layer is as follows: 10 to 20 angstroms.

Optionally, the material of the second interface layer includes silicon oxide; the forming process of the second interface layer comprises a chemical oxidation process; the thickness of the second interface layer is 5-15 angstroms.

Optionally, the forming step of the first interface layer and the second interface layer includes: oxidizing the side wall of the fin part, the side wall and the top of the first material layer to form a first interface film; removing the first interface film of the second area, and forming a first interface layer on the side wall of the fin part of the first area, the side wall and the top of the first material layer of the first area; and after the first interface layer is formed, forming a second interface layer on the side wall of the fin part in the second area and the side wall and the top of the first material layer in the second area.

The present invention also provides a semiconductor structure, comprising: a substrate having a fin portion thereon, the fin portion having first atoms and second atoms therein, the second atoms in the fin portion having a first atomic percent concentration; a first material layer on the fin, second atoms in the first material layer having a second atomic percent concentration, the second atomic percent concentration being greater than the first atomic percent concentration; and the interface layer is positioned on the side wall of the fin part, the side wall of the first material layer and the top surface.

Optionally, the fin portion is made of a material including silicon germanium, the first atoms are germanium atoms, and the second atoms are silicon atoms; the atomic percentage concentration of the first atoms in the fin portion is 25% -65%.

Optionally, the material of the first material layer is silicon.

Optionally, the thickness of the first material layer is: 2 to 4 nanometers.

Optionally, the material of the interfacial layer includes silicon oxide.

Optionally, a second material layer is further included between the first material layer and the fin portion; the atomic percent concentration of the first atoms in the second material layer is greater than the atomic percent concentration of the first atoms in the fin; the material of the second material layer comprises silicon germanium, and the atomic percentage concentration of the first atoms in the second material layer is 50-75%.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, before the interface layer is formed, the top surface of the initial fin part is subjected to concentration treatment to form the fin part and the first material layer. The second atoms in the fin portion have a first atomic percent concentration, the second atoms in the first material layer have a second atomic percent concentration, the second atomic percent concentration is larger than the first atomic percent concentration, and the binding capacity of the second atoms and oxygen atoms is larger than the binding capacity of the first atoms and oxygen atoms, so that interface layer trapped charges formed by subsequently oxidizing the first material layer are less, therefore, the interface state between the interface layer and a subsequently formed gate dielectric layer is good, and the instability of a semiconductor device is favorably reduced and the service life of the transistor is prolonged when the transistor works under the conditions of a strong electric field and high temperature.

Further, the concentration process further includes forming a second material layer between the fin and the first material layer, wherein an atomic percent concentration of the first atoms in the second material layer is greater than an atomic percent concentration of the first atoms in the fin. And the mobility of the transistor carrier is related to the atomic percent concentration of the first atom. Specifically, the higher the atomic percent concentration of the first atoms, the higher the mobility of the transistor carriers. Therefore, the atomic percentage concentration of the first atoms in the second material layer is higher, so that the mobility of carriers of the formed transistor is higher, and the performance of the transistor is improved.

Further, the fin material layer comprises silicon germanium, and the fin material layer is formed by an epitaxial growth process so that the fin material layer has the maximum thickness. The first atoms are germanium atoms, the atomic percentage concentration of the first atoms in the fin portion material layer is low, the maximum thickness of the second base portion is large, the maximum thickness of the second base portion determines the height of a subsequently formed fin portion, and therefore the height of the fin portion is high. The fin part is higher, so that the cross section area of the channel region of the grid electrode structure formed by the method is larger, the contact resistance between the channel regions is smaller, and the performance of the transistor is favorably improved.

Drawings

FIG. 1 is a schematic diagram of a P-type FinFET structure;

fig. 2 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As mentioned in the background, the P-type finfet has poor performance.

Fig. 1 is a schematic diagram of a P-type finfet structure.

Referring to fig. 1, asubstrate 100, thesubstrate 100 having aninsulating layer 101 thereon, theinsulating layer 101 having afin 102 thereon; aninterfacial layer 103 covering the fin 102 sidewalls and top surface.

In the above P-type finfet structure, in order to improve carrier mobility of a channel region of the P-type finfet, silicon germanium is used as a material of thefin portion 102. And the magnitude of the carrier mobility is closely related to the concentration of germanium atoms. Specifically, when the atomic percentage concentration of the germanium atoms is less than 25%, the mobility of carriers is low, which is not beneficial to improving the electrical performance of the P-type fin field effect transistor; on the contrary, when the atomic percentage concentration of germanium atoms is greater than 25%, the electrical performance of the P-type fin field effect transistor is improved.

The forming of thefin 102 includes: forming a fin material layer, wherein the fin material layer is provided with a mask layer, and the mask layer exposes the top surface of part of the fin material layer; and etching the fin material layer by taking the mask layer as a mask until the top surface of theinsulating layer 101 is exposed to form thefin 102. The forming process of the fin material layer comprises the following steps: and (5) an epitaxial growth process. The fin material layer is made of silicon germanium and formed by an epitaxial growth process, so that the fin material layer has the maximum thickness, and the maximum thickness is reduced along with the increase of the concentration of germanium atoms.

Specifically, when the atomic percentage concentration of germanium atoms is greater than 65%, the maximum thickness of the fin material layer is smaller. Since the fin material layer is used for the subsequent formation of thefin 102, the height of thefin 102 is small. When the height of thefin portion 102 is small, so that the cross-sectional area of the P-type fin field effect transistor channel is small, the resistance of the P-type fin field effect transistor channel region is large, and the performance of the P-type fin field effect transistor is not improved.

A method of increasing the height of thefin 102 while increasing carrier mobility comprises: the atomic percentage concentration of germanium atoms is: 25 to 65 percent. The forming step of theinterface layer 103 includes: the sidewalls and top surface of thefin 102 are oxidized to form aninterfacial layer 103. In the process of forming theinterface layer 103, germanium atoms and silicon atoms are both combined with oxygen, wherein the germanium atoms and the oxygen atoms are combined into germanium dioxide, and the germanium dioxide is easily hydrolyzed when meeting water, so that the surface of the formedinterface layer 103 has trapped charges. In addition, the atomic percentage concentration of germanium atoms in thefin portion 102 is high, so that more trapped charges are on the surface of theinterface layer 103, and when the P-type fin field effect transistor formed by the method works under a strong electric field and a high Temperature condition, Negative Bias Instability (NBTI) of the P-type fin field effect transistor is easily caused.

In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: the initial fin portion is provided with a first atom and a second atom; performing concentration treatment on the initial fin portion to form a fin portion and a first material layer located on the fin portion, wherein second atoms in the fin portion have a first atomic percent concentration, second atoms in the first material layer have a second atomic percent concentration, the second atomic percent concentration is greater than the first atomic percent concentration, and the bonding force between the second atoms and oxygen atoms is greater than that between the first atoms and the oxygen atoms; and oxidizing the side wall of the fin part, the side wall and the top of the first material layer to form an interface layer. The method is beneficial to reducing the performance instability of the transistor.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 2, asubstrate 200 is provided, thesubstrate 200 having afin material layer 202 thereon, thefin material layer 202 having first atoms and second atoms therein.

In this embodiment, the material of thesubstrate 200 includes: silicon.

In this embodiment, the material of thefin material layer 202 is silicon germanium, the first atoms are germanium atoms, and the second atoms are silicon atoms.

The first atoms are used to increase the mobility of the transistor carriers.

The forming process of thefin material layer 202 comprises an epitaxial growth process; the parameters of the epitaxial growth process comprise: the reaction gas comprises a silicon source gas and a germanium source gas, wherein the silicon source gas comprises SiH₄The flow rate of the silicon source gas is 10-100 standard milliliters/minute, and the germanium source gas comprises GeH₄And the flow rate of the germanium source gas is 20-120 standard milliliters/minute.

Thefin material layer 202 is formed using an epitaxial growth process such that thefin material layer 202 has a maximum thickness. The maximum thickness is related to the atomic percent concentration of the first atoms in thefin material layer 202. Specifically, the higher the atomic percentage concentration of the first atoms in thefin material layer 202, the smaller the maximum thickness.

In this embodiment, the atomic percentage concentration of the first atoms in thefin material layer 202 is: 25% -65%, because the atomic percentage concentration of the first atoms in thefin material layer 202 is relatively low, the maximum thickness of thefin material layer 202 formed by the epitaxial growth process is relatively large, and the maximum thickness of thefin material layer 202 determines the thickness of thefin material layer 202, so the thickness of thefin material layer 202 is relatively thick.

In this embodiment, the thickness of thefin material layer 202 is: 10 nm to 70 nm, and the thickness of thefin material layer 202 determines the height of the subsequently formed fin.

In addition, the atomic percentage concentration of the first atoms in thefin material layer 202 is not too low, that is: the atomic percentage concentration of the first atoms in thefin material layer 202 is relatively high, so that the mobility of carriers in a channel of the formed P-type fin field effect transistor is high, and the electrical performance of the P-type fin field effect transistor is improved.

In this embodiment, an insulatinglayer 201 is further disposed between thesubstrate 200 and thefin material layer 202.

The material of the insulatinglayer 201 includes silicon oxide. The insulatinglayer 201 is used to achieve electrical isolation between the subsequently formed fin and thesubstrate 200.

In this embodiment, the top surface of thefin material layer 202 has abuffer Film 203, and thebuffer Film 203 has an Advanced Pattern Film (APF) 204 thereon.

In other embodiments, only the pattern film is arranged on the fin material layer.

The material of thebuffer film 203 includes: silicon oxide, and the formation process of thebuffer film 203 includes: chemical vapor deposition process.

Thebuffer film 203 functions include: in one aspect, thebuffer film 203 is used as a buffer layer between thepattern film 204 and thefin material layer 202; on the other hand, thebuffer film 203 is used as a stopper layer for forming a pattern layer later.

The materials of thegraphic film 204 include: amorphous carbon, the process of forming thepattern film 204 includes: and (5) a deposition process.

Thepatterning film 204 is used to subsequently form a patterning layer.

Thepattern film 204 has a first mask layer (not shown) thereon, which exposes a portion of the top surface of thepattern film 204.

The material of the first mask layer comprises: the forming process of the first mask layer comprises the following steps: chemical vapor deposition process. The first mask layer is used for forming a mask of a pattern layer in the follow-up process.

In this embodiment, thesubstrate 200 includes a first region a for forming a periphery region P-type finfet and a second region B for forming a core region P-type finfet.

In other embodiments, the substrate includes only a first region for forming a periphery region P-type finfet; or the first region is used for forming a P-type fin field effect transistor of the core region.

Referring to fig. 3, the first mask layer is used as a mask to etch the pattern film 204 (see fig. 2) until the buffer film 203 (see fig. 2) is exposed, so as to form apattern layer 206; etching thebuffer film 203 by taking thepattern layer 206 and the first mask layer as masks until thefin material layer 202 is exposed to form abuffer layer 205; after thebuffer layer 205 is formed, the first mask layer is removed.

The process for etching thegraphic film 204 by using the first mask layer as a mask comprises the following steps: one or two of the dry etching process and the wet etching process are combined.

The process for etching thebuffer film 203 by using thepattern layer 206 and the first mask layer as masks comprises the following steps: one or two of the dry etching process and the wet etching process are combined.

Thepattern layer 206 and thebuffer layer 205 are used as mask layers for subsequent fin formation.

The process for removing the first mask layer comprises the following steps: one or two of the dry etching process and the wet etching process are combined.

Referring to fig. 4, thefin material layer 202 is etched using thepattern layer 206 and thebuffer layer 205 as masks until the insulatinglayer 201 is exposed, so as to form aninitial fin 207; after theinitial fin 207 is formed, thepattern layer 206 and thebuffer layer 205 are removed.

With thepattern layer 206 and thebuffer layer 205 as masks, the process of etching thefin material layer 202 includes: one or two of the dry etching process and the wet etching process are combined.

The height of theinitial fin 207 is determined by the thickness of the fin material layer 202 (see fig. 3), and thus the height of theinitial fin 207 is: 10 nm to 70 nm, and the height of theinitial fin portion 207 is higher, so that the cross-sectional area of a channel region of the transistor formed by the method is larger, and the reduction of the resistance of the transistor is facilitated.

The process of removing thepattern layer 206 includes: one or more of a dry etching process, a wet etching process and an ashing process.

The process of removing thebuffer layer 205 includes: one or more of a dry etching process and a wet etching process.

The material of theinitial fin 207 includes silicon germanium, theinitial fin 207 has therein first atoms and second atoms, the first atoms are germanium atoms, the second atoms are silicon atoms, and the atomic percentage concentration of the first atoms in theinitial fin 207 is: 25 to 65 percent.

Theinitial fin 207 is used for subsequent formation of a fin, a second material layer on the fin, and a first material layer on the second material layer.

Referring to fig. 5,sidewalls 208 are formed on sidewalls of theinitial fin 207.

The forming step of theside wall 208 includes: forming sidewall films on the insulatinglayer 201 and the sidewalls and the top surface of theinitial fin 207; and removing the insulatinglayer 201 and the sidewall film on the top of theinitial fin portion 207 to form thesidewall 208.

The material of the side wall film comprises: silicon nitride, the forming process of the side wall film comprises the following steps: and (5) an atomic layer deposition process.

Thesidewalls 208 are used to protect the sidewalls of thefin 207.

Referring to fig. 6, the top of theinitial fin 207 is concentrated to form afin 227 and afirst material layer 210 on thefin 227, wherein second atoms in thefin 227 have a first atomic percent concentration, second atoms in thefirst material layer 210 have a second atomic percent concentration, the second atomic percent concentration is greater than the first atomic percent concentration, and the binding capacity of the second atoms to oxygen atoms is greater than the binding capacity of the first atoms to oxygen atoms.

In this embodiment, theinitial fin 207 is made of sige, and the concentration process includes: annealing process; the parameters of the annealing process comprise: the temperature is 450-650 ℃, the time is 20-240 minutes, the pressure is 1-760 torr, the ambient gas comprises oxygen, and the mass fraction of the oxygen is 0.001-1%. The material of thefirst material layer 210 is silicon.

Since the second atomic percent concentration is greater than the first atomic percent concentration, and the binding capacity of the second atoms and the oxygen atoms is greater than that of the first atoms and the oxygen atoms, the trapped charges of the interface layer formed by oxidizing thefirst material layer 210 subsequently are less, so that the instability of the semiconductor device can be reduced and the service life of the transistor can be prolonged when the transistor works under the conditions of a strong electric field and high temperature.

The thickness of thefirst material layer 210 is: 2 to 4 nanometers.

In the concentration treatment process, the method further comprises the following steps: asecond material layer 209 is formed overfin 227 andfirst material layer 210, wherein an atomic percent concentration of the first atoms insecond material layer 209 is greater than an atomic percent concentration of the first atoms infin 227.

In this embodiment, thefin 227 is made of silicon germanium, the first atoms are germanium atoms, the second atoms are silicon atoms, and the atomic percentage concentration of the first atoms in thefin 227 is: 25 to 65 percent.

In this embodiment, the atomic percentage concentration of the first atoms in thesecond material layer 209 is 50% to 75%, and the atomic percentage concentration of the first atoms in thesecond material layer 209 is larger, which is beneficial to improving the mobility of carriers, and thus, is beneficial to improving the electrical performance of the transistor. After theinitial fin 207 is formed, the top surface of theinitial fin 207 is concentrated, so that the height of theinitial fin 207 is not too high to be lengthened due to the too high concentration of the first atoms. The height of theinitial fin portion 207 is high, so that the cross-sectional area of a channel of the formed semiconductor device is large, and the resistance of the semiconductor device is favorably reduced.

The thickness of thesecond material layer 209 is: 1 to 7 nanometers.

The principle of forming thefirst material layer 210 and thesecond material layer 209 using the concentration process includes: during the annealing process, second atoms in theinitial fin 207 are emitted towards the top surface of theinitial fin 207, forming alayer 210 of the first material in a second atom-rich state. Accordingly, the second atoms in theinitial fins 207 are emitted towards the top surface of theinitial fins 207, such that the atomic percentage concentration of the second atoms in theinitial fins 207 at the bottom of thefirst material layer 210 is reduced, and the atomic percentage concentration of the first atoms in theinitial fins 207 at the bottom of thefirst material layer 210 is increased, i.e. thesecond material layer 209 is formed below thefirst material layer 210.

During the annealing process, the top of thefirst material layer 210 is oxidized into anoxide layer 211. The material of theoxide layer 211 includes: silicon oxide.

Referring to fig. 7, the spacers 208 (shown in fig. 6) and the oxide layer 211 (shown in fig. 6) are removed.

The process for removing theside wall 208 includes: one or two of the dry etching process and the wet etching process are combined.

The removal of thespacers 208 facilitates the exposure of the sidewalls of thefin 207 and theinterface layer 210.

The process for removing theoxide layer 211 comprises the following steps: one or two of the dry etching process and the wet etching process are combined.

Theoxide layer 211 is removed to expose the top surface of theinterfacial layer 210.

After removing theside wall 208 and theoxide layer 211, the method further includes: the sidewalls of thefins 227, the sidewalls and the top surface of thefirst material layer 210 are oxidized to form an interfacial layer.

In this embodiment, thesubstrate 200 includes a first region a and a second region B, the interface layers include a first interface layer located in the first region a and a second interface layer located in the second region B, and the thickness of the first interface layer is greater than that of the second interface layer. The steps of forming the first interface layer and the second interface layer refer to fig. 8 to 13.

Referring to fig. 8, after removing the spacers 208 (shown in fig. 6) and the oxide layer 211 (shown in fig. 6), the sidewalls of thefins 227 in the first region a and the second region B, and the sidewalls and the top surface of thefirst material layer 210 are oxidized to form thefirst interface film 212.

The materials of thefirst interface film 212 include: silicon oxide, the first interfaceThe formation process of thefilm 212 includes: an in-situ water vapor generation process; the parameters of the in-situ water vapor generation process include: the temperature is 900 ℃ to 1100 ℃, the pressure is 0.1 mm Hg to 100 mm Hg, H₂The volume flow rate of (A) is 0.2 to 20 standard liters per minute, O₂The volume flow rate of the reactor is 5 standard liters/minute to 100 standard liters/minute, and the time is 5 seconds to 300 seconds.

In this embodiment, thefirst material layer 210 is made of silicon, and silicon oxide is formed by the in-situ water vapor generation process, where the silicon and oxygen in the silicon oxide have strong binding ability, that is: the second atoms in thefirst interface film 212 have a strong bonding ability with oxygen atoms. Thefirst interface film 212 is used for forming a first interface layer in a subsequent step, and therefore, the bonding capability of the second atoms and the oxygen atoms in the first interface layer is strong, so that the trapped charges at the interface between the first interface layer and the gate dielectric layer formed in the subsequent step are less, and the bias instability of the transistor is favorably reduced when the transistor works under the conditions of a strong electric field and high temperature.

The thickness of thefirst interface film 212 is: 10 to 20 angstroms.

In this embodiment, the first region a is used to form a periphery region P-type finfet, and the thickness of thefirst interface film 212 is relatively thick, which is beneficial to improving the performance of the first region a device; the second region B is used for forming a P-type finfet in the core region, and the thickness of thefirst interface film 212 is relatively thick, which is not beneficial to improving the performance of the device in the first region a, so thefirst interface film 212 in the second region B is used as a dummy gate dielectric layer of the device in the second region B.

Referring to fig. 9, adummy gate layer 213 is formed on thefirst interface film 212.

The forming step of thedummy gate layer 213 includes: forming a dummy gate film having a second mask layer (not shown) thereon on thefirst interface film 212 and the insulatinglayer 201; and etching the dummy gate film by using the second mask layer as a mask until thefirst interface film 212 is exposed, thereby forming thedummy gate layer 213.

The material of the pseudo-gate film comprises: silicon, the forming process of the pseudo gate film comprises the following steps: chemical vapor deposition process.

The material of the second mask layer comprises: silicon nitride, which serves as a mask for forming thedummy gate layer 213.

Referring to fig. 10, adielectric layer 214 is formed on the insulatinglayer 201, thedielectric layer 214 covers the sidewalls of thedummy gate layer 213 and thefirst interface film 212, and thedielectric layer 214 exposes the top surface of thedummy gate layer 213.

The forming step of thedielectric layer 214 includes: forming a dielectric film on the insulatinglayer 201, the sidewall of thefirst interface film 212, and the sidewall and top surface of thedummy gate layer 213; and flattening the dielectric film until the top surface of thedummy gate layer 213 is exposed to form thedielectric layer 214.

The dielectric film comprises the following materials: the forming process of the dielectric film comprises the following steps: chemical vapor deposition process.

The process for flattening the dielectric film comprises the following steps: and (5) carrying out a chemical mechanical polishing process.

Thedielectric layer 214 is used to electrically isolate the semiconductor during different periods.

Referring to fig. 11, thedummy gate layer 213 is removed (as shown in fig. 10), and a dummy gate opening 215 is formed in thedielectric layer 214.

The process for removing thedummy gate layer 213 includes: one or two of the dry etching process and the wet etching process are combined.

The dummy gate opening 215 is used for subsequently accommodating a gate dielectric layer and a gate layer located on the gate dielectric layer.

Referring to fig. 12, aphotoresist 216 is formed in the dummy gate opening 215 (see fig. 11) in the first region a; thephotoresist 216 is used as a mask to remove thefirst interface film 212 in the second region B, and afirst interface layer 222 is formed on the sidewalls of the first region a fin and the sidewalls and the top of thefirst material layer 210 in the first region a (see fig. 11).

Thephotoresist 216 is used to protect thefirst interface film 212 of the first region a.

The significance of removing thefirst interface film 212 of the second region B is: the second region B is used for forming a P-type fin field effect transistor in the core region, thefirst interface film 212 is thick, which is not beneficial to improving the performance of the device in the second region B, and the removal of thefirst interface film 212 in the second region B is beneficial to forming a second interface layer suitable for the requirement of the device in the second region B subsequently.

Referring to fig. 13, after removing thefirst interface film 212 in the second region B, the sidewalls of thefins 207 in the second region B, and the sidewalls and the top surface of thefirst material layer 210 in the second region B are oxidized to form asecond interface layer 217.

The material of thesecond interface layer 217 includes: silicon oxide, and the forming process of thesecond interface layer 217 comprises the following steps: a chemical oxidation process, the parameters of the chemical oxidation process comprising: the reactants include hydrogen peroxide and ozone.

The material of thefirst material layer 210 includes silicon, thefirst material layer 210 is formed by a chemical oxidation process to form a portion of thesecond interface layer 217, the material of thefirst material layer 210 is silicon oxide, and the silicon and oxygen in the silicon oxide have a strong binding ability, that is: the second atoms in thesecond interface layer 217 have a strong binding ability with oxygen atoms, so that trapped charges at an interface between thesecond interface layer 217 and a subsequently formed gate dielectric layer are less, and the second region B semiconductor device is beneficial to reducing the negative bias instability of the semiconductor device when working under a strong electric field and a high temperature condition.

Thesecond interface layer 217 is used to improve an interface state between thefin 227 in the second region B and a subsequently formed gate dielectric layer. The thickness of thesecond interface layer 217 is: 5-15 angstroms, and the thickness of thesecond interface layer 217 is small, thereby being beneficial to improving the performance of the second region B device.

Referring to fig. 14, agate dielectric layer 218 is formed on thefirst interface layer 222 and thesecond interface layer 217 in the dummy gate opening 215 (see fig. 11); agate layer 219 is formed on thegate dielectric layer 218.

Before forming thegate dielectric layer 218, further comprising: thephotoresist 216 is removed (as shown in fig. 13).

The process of removing thephotoresist 216 includes: dry etching process, wet etching process and ashing process.

The forming steps of thegate dielectric layer 218 and thegate layer 219 include: forming a gate dielectric film in thedummy gate opening 215 and on thedielectric layer 214; forming a gate electrode film on the gate dielectric film; the gate film and the gate dielectric film are planarized until the top surface ofdielectric layer 214 is exposed, forming agate dielectric layer 218 and agate layer 219 overlyinggate dielectric layer 218.

The gate dielectric film is made of a high-K dielectric material, and the K value range is as follows: k is greater than 3.9. In this embodiment, the gate dielectric film is made of hafnium oxide, and correspondingly, thegate dielectric layer 218 is made of hafnium oxide.

In other embodiments, the material of the gate dielectric film comprises: zirconia, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide, and correspondingly, the material of the gate dielectric layer comprises: zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

The material of the gate electrode film is metal, such as: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. Accordingly, the material of thegate layer 219 includes: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel.

Accordingly, the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 13, including:

asubstrate 200, thesubstrate 200 having afin 227 thereon, thefin 227 having first atoms and second atoms therein, the second atoms in thefin 227 having a first atomic percent concentration;

afirst material layer 210 onfin 227, thefirst material layer 210 having a second atomic percent concentration of second atoms, the second atomic percent concentration being greater than the first atomic percent concentration;

an interfacial layer on the sidewalls offin 207, and on the sidewalls and top surface offirst material layer 210.

Thefin 227 is made of silicon germanium, and the first atoms are germanium atoms and the second atoms are silicon atoms; the atomic percentage concentration of the first atoms in thefin 227 is 25% to 65%.

The material of thefirst material layer 210 is silicon.

The thickness of thefirst material layer 210 is: 2 to 4 nanometers.

The material of the interfacial layer comprises silicon oxide.

Asecond material layer 209 is further included between thefirst material layer 210 and thefin 227; the atomic percent concentration of the first atoms in thesecond material layer 209 is greater than the atomic percent concentration of the first atoms in thefin 227; the atomic percentage concentration of the first atoms in thesecond material layer 209 is 50% to 75%.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with an initial fin part, and the initial fin part is internally provided with a first atom and a second atom;

concentrating the top of the initial fin part to form a fin part and a first material layer positioned on the fin part, wherein a second atom in the fin part has a first atomic percent concentration, a second atom in the first material layer has a second atomic percent concentration, the second atomic percent concentration is greater than the first atomic percent concentration, and the bonding force between the second atom and oxygen atoms is greater than that between the first atom and the oxygen atoms;

oxidizing the side wall of the fin part, the side wall and the top of the first material layer to form an interface layer;

the substrate comprises a first region and a second region; the first region is used for forming devices in a peripheral region, and the second region is used for forming devices in a core region; the interface layer comprises a first interface layer positioned in the first area and a second interface layer positioned in the second area, and the thickness of the first interface layer is greater than that of the second interface layer.

2. The method of claim 1, wherein a material of the initial fin portion comprises silicon germanium, the first atoms are germanium atoms, and the second atoms are silicon atoms; the atomic percentage concentration of the first atoms in the initial fin portion is 25% -65%.

3. The method of claim 2, wherein the concentrating comprises: annealing process; the parameters of the annealing process comprise: the temperature is 450-650 ℃, the time is 20-240 minutes, the pressure is 1-760 torr, and the ambient gas comprises oxygen.

4. The method of forming a semiconductor structure of claim 3, wherein the material of the first material layer is silicon.

5. The method of forming a semiconductor structure of claim 1, wherein the first material layer has a thickness of: 2 to 4 nanometers.

6. The method of claim 3, wherein the concentration process further comprises forming a second material layer between the fin and the first material layer, the second material layer having a greater atomic percent concentration of the first atoms than the fin.

7. The method of forming a semiconductor structure of claim 6, wherein the material of the second material layer comprises silicon germanium, and wherein the atomic percent concentration of the first atoms in the second material layer is: 50 to 75 percent.

8. The method of forming a semiconductor structure of claim 6, wherein the second material layer has a thickness of: 1 to 7 nanometers.

9. The method of forming a semiconductor structure of claim 1, further comprising providing an insulating layer over the substrate; the forming method of the initial fin portion comprises the following steps: forming a fin material layer on the insulating layer, wherein the fin material layer is provided with a pattern layer, and part of the fin material layer is exposed out of the pattern layer; and etching the fin part material layer by taking the pattern layer as a mask until the insulating layer is exposed to form an initial fin part.

10. The method of claim 9, wherein the material of the fin material layer comprises silicon germanium, the first atoms are germanium atoms, and the atomic percent concentration of the first atoms in the fin material layer is 25% to 65%; the forming process of the fin part material layer is an epitaxial growth process; the thickness of the fin material layer is as follows: 10 to 70 nanometers.

11. The method of forming a semiconductor structure of claim 1, wherein the material of the first interfacial layer comprises: silicon oxide; the forming process of the first interface layer comprises an in-situ water vapor generation process; the thickness of the first interface layer is as follows: 10 to 20 angstroms.

12. The method of forming a semiconductor structure of claim 1, wherein the material of the second interfacial layer comprises: silicon oxide, wherein the forming process of the second interface layer comprises a chemical oxidation process; the thickness of the second interface layer is 5-15 angstroms.

13. The method of forming a semiconductor structure of claim 1, wherein the step of forming the first and second interfacial layers comprises: oxidizing the side wall of the fin part, the side wall of the first material layer and the top surface to form a first interface film; removing the first interface film of the second area, and forming a first interface layer on the side wall of the fin part of the first area, the side wall and the top of the first material layer of the first area; and after the first interface layer is formed, forming a second interface layer on the side wall of the fin part in the second area and the side wall and the top surface of the first material layer in the second area.

14. A semiconductor structure, comprising:

a substrate having a fin portion thereon, the fin portion having first atoms and second atoms therein, the second atoms in the fin portion having a first atomic percent concentration;

a first material layer on the fin, second atoms in the first material layer having a second atomic percent concentration, the second atomic percent concentration being greater than the first atomic percent concentration;

the interface layer is positioned on the side wall of the fin part, the side wall of the first material layer and the top surface;

the substrate comprises a first region and a second region; the first region is used for forming devices in a peripheral region, and the second region is used for forming devices in a core region; the interface layer comprises a first interface layer positioned in the first area and a second interface layer positioned in the second area, and the thickness of the first interface layer is greater than that of the second interface layer.

15. The semiconductor structure of claim 14, wherein the material of the fin comprises silicon germanium, the first atoms are germanium atoms, and the second atoms are silicon atoms; the atomic percentage concentration of the first atom in the fin portion is 25% -65%.

16. The semiconductor structure of claim 14, wherein the material of the first material layer is silicon.

17. The semiconductor structure of claim 14, wherein the first material layer has a thickness of: 2 to 4 nanometers.

18. The semiconductor structure of claim 14, wherein a material of the interfacial layer comprises silicon oxide.

19. The semiconductor structure of claim 14, further comprising a second material layer between the first material layer and the fin; the atomic percent concentration of the first atoms in the second material layer is greater than the atomic percent concentration of the first atoms in the fin; the material of the second material layer comprises silicon germanium, and the atomic percentage concentration of the first atoms in the second material layer is 50-75%.

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