CN109828404B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panelDownload PDFInfo
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- CN109828404B CN109828404BCN201910101240.3ACN201910101240ACN109828404BCN 109828404 BCN109828404 BCN 109828404BCN 201910101240 ACN201910101240 ACN 201910101240ACN 109828404 BCN109828404 BCN 109828404B
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Abstract
Translated fromChinese
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.
Background
Liquid crystal display devices, which are currently the mainstream flat panel display mode, have been developed rapidly for over ten years, have the advantages of light weight, thinness, low energy consumption and the like, and are widely applied to modern information equipment such as televisions, computers, mobile phones, digital cameras and the like, and especially have been developed in large-size liquid crystal display screens quite mature. In a liquid crystal display device, light emitted from a backlight enters from a lower polarizer, passes through each layer, and is emitted from an upper polarizer, and the brightness of the emitted light is only 7% to 8% or less of the incident light. One reason for this is that the opaque metal layer (including the gate line, the data line, the gate electrode, the source and drain electrodes, etc.) on the array substrate blocks a portion of light from passing through, so that the light transmittance of the array substrate is about 60% or less. How to improve the transmittance of the lcd panel is a major problem in the lcd industry.
In the prior art, there are three methods for improving the transmittance of a liquid crystal display panel: firstly, the brightness of the backlight source is improved to improve the light transmission quantity and the brightness of the liquid crystal display panel so as to improve the display quality of the liquid crystal display panel, but the method can increase the power consumption of the display device; secondly, the aperture opening ratio of the array substrate is improved to improve the light transmittance of the display panel, at present, the method almost achieves the limit, and the improvement effect of the light transmittance is limited; thirdly, the light transmittance of the material used for the display panel is improved to improve the overall light transmittance of the display panel, but the method is limited by the development of various materials, and the improvement of the light transmittance of the display panel by the method is difficult to realize based on the current materials.
Disclosure of Invention
An object of the embodiments of the present invention is to provide an array substrate, a method for manufacturing the array substrate, and a display panel, so as to solve the problem of low transmittance of the display panel.
In order to solve the above technical problem, an embodiment of the present invention provides an array substrate, including a first substrate, and a gate line, a data line, and a thin film transistor disposed on the first substrate, where the gate line and the data line intersect with each other to define a plurality of pixel regions, and the thin film transistor corresponds to the pixel regions, and the array substrate further includes a first photonic crystal layer disposed on the first substrate and configured to emit light, which is irradiated to the gate line, the data line, and the thin film transistor, toward the pixel regions.
Optionally, the first photonic crystal layer has an entrance side and an exit side, and the exit side has a plurality of grooves.
Optionally, the plurality of grooves are uniformly arranged, the depth of each groove is less than or equal to 120nm, and the distance between every two adjacent grooves is 350nm to 600 nm.
Optionally, the material of the first photonic crystal layer includes at least one of p-type doped gallium nitride, n-type doped gallium nitride and indium tin oxide.
Optionally, orthographic projections of the gate lines, the data lines and the thin film transistors on the first substrate are all located within an orthographic projection range of the first photonic crystal layer on the first substrate.
Optionally, the first photonic crystal layer is disposed between the first substrate and the thin film transistor.
Optionally, the thin film transistor is a bottom gate thin film transistor, the thin film transistor includes a gate electrode on the first substrate, an active layer on the gate electrode, and a source electrode and a drain electrode on the active layer, and the first photonic crystal layer is located between the gate electrode and the first substrate.
Optionally, the array substrate further comprises a planarization layer disposed between the first photonic crystal layer and the thin film transistor.
Optionally, the array substrate further includes a pixel electrode disposed on the thin film transistor, an interlayer insulating layer disposed on the pixel electrode, and a common electrode disposed on the interlayer insulating layer, and the array substrate further includes a common electrode lead disposed on the same layer as the gate line and electrically connected to the common electrode, and a second photonic crystal layer disposed between the common electrode lead and the first substrate and configured to allow light irradiated to a region where the common electrode lead is located to be emitted toward the pixel region.
Optionally, an orthographic projection of the common electrode lead on the first substrate is located within an orthographic projection range of the second photonic crystal layer on the first substrate.
In order to solve the above technical problem, an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
the liquid crystal display device comprises a first substrate, a first photonic crystal layer, a grid line, a data line and a thin film transistor, wherein the grid line and the data line are crossed with each other to define a plurality of pixel regions, the thin film transistor corresponds to the pixel regions, and the first photonic crystal layer is used for enabling light rays irradiated to the grid line, the data line and the thin film transistor to be emitted towards the pixel regions.
Optionally, the forming a first photonic crystal layer, a gate line, a data line, and a thin film transistor on a first substrate includes:
forming a first photonic crystal layer on a first substrate, wherein the light outlet side of the first photonic crystal layer is provided with a plurality of grooves;
and forming a gate line, a data line and a thin film transistor on the first photonic crystal layer.
Optionally, the forming a first photonic crystal layer on a first substrate includes:
forming a photonic crystal film on a first substrate;
coating a layer of photoresist on the photonic crystal film;
step exposure and development are carried out on the photoresist by adopting a halftone mask or a gray scale mask, an unexposed region is formed at the non-groove position of the first photonic crystal layer, the photoresist is reserved, a partial exposed region is formed at the groove position of the first photonic crystal layer, a part of the photoresist is reserved, a complete exposed region is formed at other positions, and no photoresist exists;
etching the photonic crystal film in the complete exposure area;
ashing the photoresist, removing the photoresist in a partial exposure area, and reserving a part of photoresist in a non-exposure area;
and etching the photonic crystal film in the partial exposure area to form a pattern of the first photonic crystal layer.
Optionally, the forming of the gate line, the data line, and the thin film transistor on the first photonic crystal layer includes:
forming a planarization layer on the first photonic crystal layer;
and forming a grid line, a data line and a thin film transistor on the flat layer.
In order to solve the technical problem, an embodiment of the present invention further provides a display panel, including the array substrate described above, and further including a color film substrate disposed in an involution manner with the array substrate, where the color film substrate includes a second substrate, a color film disposed on one side of the second substrate facing the array substrate, and a black matrix disposed between adjacent color films, and an orthographic projection of the black matrix on the first substrate is located in an orthographic projection range of the first photonic crystal layer on the first substrate.
According to the array substrate provided by the embodiment of the invention, the first photonic crystal layer corresponding to the regions where the grid line, the data line and the thin film transistor are located is arranged on the first base, and the first photonic crystal layer is used for enabling the light rays irradiated to the regions where the grid line, the data line and the thin film transistor are located to be emitted towards the pixel region, so that the light rays irradiated to the opaque grid line, the opaque data line and the opaque thin film transistor are emitted towards the pixel region under the action of the first photonic crystal layer, and therefore, the light rays can penetrate through the array substrate from the pixel region, so that the light ray loss irradiated to the regions where the grid line, the data line and the thin film transistor are located is reduced, the light utilization rate is improved, and the light transmittance of the array substrate is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic top view of an array substrate according to a first embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of an array substrate according to a first embodiment of the present invention;
FIG. 3 is a schematic cross-sectional structure of the first photonic crystal layer;
FIG. 4a is a schematic structural view after a first etching in a process of forming a first photonic crystal layer;
FIG. 4b is a schematic view of the structure after photoresist ashing during formation of the first photonic crystal layer;
fig. 4c is a schematic structural view of the array substrate after the first photonic crystal layer is formed according to the first embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an array substrate after gate electrodes are formed according to the first embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating an array substrate after an active layer is formed thereon according to a first embodiment of the present invention;
fig. 7 is a schematic structural view of the array substrate after forming source/drain electrodes according to the first embodiment of the invention;
FIG. 8 is a schematic structural diagram of an array substrate after forming pixel electrodes according to a first embodiment of the present invention;
FIG. 9 is a schematic view illustrating a structure of an array substrate after an interlayer insulating layer is formed thereon according to a first embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display panel according to a second embodiment of the invention.
Description of reference numerals:
100-an array substrate; 101-a gate line; 103-pixel area;
121-a gate electrode; 122 — active layer; 123-source electrode;
124-drain electrode; 200-color film substrate; 300-a liquid crystal layer;
400-sealing the frame glue; 11 — a first substrate; 12-a thin film transistor;
13-a planarization layer; 14-pixel electrode; 15-interlayer insulating layer;
16-a common electrode; 17-common electrode lead; 18-a gate insulating layer;
19-a first alignment layer; 21 — a second substrate; 22-color film;
23-black matrix; 24-a second alignment layer; 41 — a first photonic crystal layer;
42 — a second photonic crystal layer; 411-incident light side; 412-light exit side;
413-groove; 102 — data lines.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The technical contents of the present invention will be described in detail by specific embodiments.
The first embodiment:
fig. 1 is a schematic top view illustrating an array substrate according to a first embodiment of the present invention, and fig. 2 is a schematic cross-sectional view illustrating the array substrate according to the first embodiment of the present invention. As shown in fig. 1 and 2, thearray substrate 100 includes afirst substrate 11, and agate line 101 and adata line 102 disposed on thefirst substrate 11. The gate lines 101 and thedata lines 102 perpendicularly cross each other to define a plurality ofpixel regions 103 arranged in a matrix. Thearray substrate 100 further includesthin film transistors 12 disposed on thefirst base 11 and corresponding to thepixel regions 103 one to one. Thearray substrate 100 further includes a firstphotonic crystal layer 41 disposed on thefirst substrate 11, the firstphotonic crystal layer 41 being located at a region corresponding to thegate line 101, thedata line 102, and thethin film transistor 12, the firstphotonic crystal layer 41 being configured to emit light irradiated to thegate line 101, thedata line 102, and thethin film transistor 12 toward thepixel region 103.
It is understood that light irradiated to thepixel region 103 may be directly emitted through thepixel region 103, and light irradiated to the regions where thegate line 101, thedata line 102, and thethin film transistor 12 are located is lost due to the inability to be emitted through thegate line 101, thedata line 102, and thethin film transistor 12. In the array substrate according to the embodiment of the invention, the firstphotonic crystal layer 41 corresponding to the regions where thegate line 101, thedata line 102 and thethin film transistor 12 are located is disposed on thefirst substrate 11, and the firstphotonic crystal layer 41 is configured to enable light rays irradiated to the regions where thegate line 101, thedata line 102 and thethin film transistor 12 are located to be emitted toward thepixel region 103, so that the light rays irradiated to theopaque gate line 101, thedata line 102 and thethin film transistor 12 are emitted toward thepixel region 103 under the action of the firstphotonic crystal layer 41, and thus, the light rays can penetrate through the array substrate from thepixel region 103, so that the light loss irradiated to the regions where thegate line 101, thedata line 102 and thethin film transistor 12 are located is reduced, the utilization rate of light is improved, and the light transmittance of the array substrate is improved.
Fig. 3 is a schematic cross-sectional structure view of the first photonic crystal layer. As shown in fig. 3, the firstphotonic crystal layer 41 includes a light-inside 411 and a light-outside 412, and the light-outside 412 has a plurality ofgrooves 413 thereon. The firstphotonic crystal layer 41 with such a structure diffracts the incident light entering the firstphotonic crystal layer 41 from thelight entrance side 411, and the propagation direction of the light is changed, so that the emergent light corresponding to the incident light is emitted toward thepixel region 103, and the emergent light can penetrate through the array substrate from thepixel region 103.
As shown in fig. 3, in the present embodiment, a plurality ofgrooves 413 are uniformly arranged on the light-emittingside 412, the depth h of eachgroove 413 is less than or equal to 120nm, and the distance d between twoadjacent grooves 413 is 350nm to 600 nm. Thegroove 413 of such a structure is easy to manufacture, and is suitable for practical production application of the firstphotonic crystal layer 41. In one embodiment, the ratio of the width w of thegroove 413 to the distance d between twoadjacent grooves 413 is 0.6-0.8. The groove with the structure can enable light rays to obtain a better diffraction effect in the first photonic crystal layer, ensures that emergent light rays can be emitted towards the pixel region, and further improves the utilization rate of light.
The material of the firstphotonic crystal layer 41 may include at least one of p-type doped gallium nitride (p-GaN), n-type doped gallium nitride (n-GaN), and indium tin oxide.
It is to be understood that the plurality of grooves may be a plurality of stripe-shaped grooves extending in the same direction, or a plurality of hole-shaped grooves arranged in a matrix on the light exit side, as long as a cross section of the first photonic crystal layer as shown in fig. 3 can be formed, which falls within the scope of the embodiments of the present invention.
In order to make all the light rays irradiated onto thegate line 101, thedata line 102 and thethin film transistor 12 can be emitted toward thepixel region 103 by the firstphotonic crystal layer 41, in the present embodiment, the orthographic projections of thegate line 101, thedata line 102 and thethin film transistor 12 on thefirst substrate 11 are all located within the orthographic projection range of the firstphotonic crystal layer 41 on thefirst substrate 11. Therefore, light irradiated to thegate line 101, thedata line 102 and thethin film transistor 12 are emitted toward thepixel region 103 by the firstphotonic crystal layer 41 and penetrate through the array substrate from thepixel region 103, thereby further reducing light loss and further improving light transmittance of the array substrate.
As shown in fig. 2, thethin film transistor 12 includes agate electrode 121, anactive layer 124, asource electrode 122, and adrain electrode 123. In general, thegate line 101 and thegate electrode 121 are located at the same layer, and thedata line 102 and the source/drain electrodes are located at the same layer, so that light irradiated to the region where thethin film transistor 12 is located, the region where thegate line 101 is located, and the region where thedata line 102 is located can be emitted toward thepixel region 103, the firstphotonic crystal layer 41 may be disposed at a side of the thin film transistor facing the incident light. Thus, light irradiated to the region where thethin film transistor 12 is located, the region where thegate line 101 is located, and the region where thedata line 102 is located first irradiates the firstphotonic crystal layer 41 and is emitted toward thepixel region 103 by the firstphotonic crystal layer 41.
Generally, the side of the array substrate facing away from the thin film transistor is the light incident side, and therefore, in the present embodiment, the firstphotonic crystal layer 41 is disposed between thefirst base 11 and thethin film transistor 12. In the present embodiment, as shown in fig. 2, thethin film transistor 12 is a bottom gate type thin film transistor, thegate electrode 121 is disposed on thefirst substrate 11, thegate insulating layer 18 is disposed on thegate electrode 121, theactive layer 124 is disposed on thegate insulating layer 18, and thesource electrode 122 and thedrain electrode 123 are located on the same layer and are disposed on theactive layer 124. The gate line (not shown in fig. 2) is disposed at the same layer as thegate electrode 121, and the data line (not shown in fig. 2) is disposed at the same layer as the source/drain electrodes. Light is incident on thearray substrate 100 from a side of thefirst substrate 11 away from thetft 12. The firstphotonic crystal layer 41 is disposed on the side of the thin film transistor facing the incident light, that is, the firstphotonic crystal layer 41 is located between thethin film transistor 12 and thefirst substrate 11, that is, the firstphotonic crystal layer 41 is located between thegate electrode 121 and thefirst substrate 11.
In other embodiments, the thin film transistor may be a top gate type thin film transistor, the active layer may be disposed on the first substrate, the gate insulating layer may be disposed on the active layer, the gate electrode may be disposed on the gate insulating layer, the interlayer insulating layer may be disposed on the gate electrode, the source electrode and the drain electrode may be disposed on the interlayer insulating layer, the source electrode and the drain electrode may be electrically connected to the active layer through vias, respectively, and the first photonic crystal layer may be disposed between the active layer and the first substrate.
As shown in fig. 2, the array substrate further includes aplanarization layer 13 between the firstphotonic crystal layer 41 and thethin film transistor 12. In this embodiment, theplanarization layer 13 is located between the firstphotonic crystal layer 41 and thegate electrode 121. Since the width of thegroove 413 is on the order of nanometers, theflat layer 13 is not filled in thegroove 413 of the firstphotonic crystal layer 41 when theflat layer 13 is formed, so that theflat layer 13 does not affect the function of the firstphotonic crystal layer 41. The side of theplanarization layer 13 facing thethin film transistor 12 has a planarized surface, so that a metal layer for forming thethin film transistor 12 can be formed on the planarized surface, thereby preventing the firstphotonic crystal layer 41 from affecting the metal layer process at a later stage.
In addition, in order to avoid total reflection of light emitted from the firstphotonic crystal layer 41 at the interface of the firstphotonic crystal layer 41 and theflattening layer 13, in the present embodiment, the refractive index of theflattening layer 13 is larger than that of the firstphotonic crystal layer 41. Therefore, when the light emitted from the firstphotonic crystal layer 41 enters theflat layer 13, the light enters the optically denser medium from the optically thinner medium, and the light emitted from the firstphotonic crystal layer 41 can be emitted towards the pixel region through theflat layer 13, so that the light loss caused by total reflection is avoided, and the utilization rate of the light is further improved.
The array substrate of the embodiment of the present invention is in an Advanced Super Dimension Switch (ADS) display mode, and as shown in fig. 2, the array substrate may further include apixel electrode 14 disposed on the source/drain electrode and electrically connected to thesource electrode 122 or thedrain electrode 123, aninterlayer insulating layer 15 disposed on thepixel electrode 14, and acommon electrode 16 disposed on theinterlayer insulating layer 15. Thepixel electrode 14 and thecommon electrode 16 may be made of Indium Tin Oxide (ITO). Thepixel electrode 14 is a plate electrode, and thecommon electrode 16 is a slit electrode. The array substrate further comprises acommon electrode lead 17, thecommon electrode lead 17 and the gate electrode are arranged on the same layer, and thecommon electrode 16 is electrically connected with thecommon electrode lead 17 through a through hole.
In order to enable the light irradiated to the region of thecommon electrode lead 17 to be emitted towards the pixel region, as shown in fig. 2, the array substrate further includes a secondphotonic crystal layer 42, and the region of the secondphotonic crystal layer 42 corresponds to the region of thecommon electrode lead 17, so that the light irradiated to the region of thecommon electrode lead 17 is emitted towards thepixel region 103 under the action of the secondphotonic crystal layer 42 and penetrates through the array substrate, thereby reducing the loss of the light irradiated to the region of thecommon electrode lead 17, further improving the utilization rate of the light, and improving the light transmittance of the array substrate.
In this embodiment, the secondphotonic crystal layer 42 and the firstphotonic crystal layer 41 may have the same structure and material, and the secondphotonic crystal layer 42 and the firstphotonic crystal layer 41 are located in the same layer and formed by the same patterning process.
In the present embodiment, an orthographic projection of thecommon electrode lead 17 on thefirst substrate 11 is located within an orthographic projection range of the secondphotonic crystal layer 42 on thefirst substrate 11. Therefore, light irradiated to the region where thecommon electrode lead 17 is located is emitted toward thepixel region 103 by the secondphotonic crystal layer 42, and penetrates through the array substrate from thepixel region 103, thereby further reducing light loss and further improving light transmittance of the array substrate.
The technical scheme of the embodiment of the invention is explained in detail through the preparation process of the array substrate. The "patterning process" described in the embodiments includes processes of coating a photoresist, mask exposure, development, etching, and stripping a photoresist, and is a well-established manufacturing process. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
The first patterning process forms a firstphotonic crystal layer 41 and a secondphotonic crystal layer 42 on thefirst substrate 11. The method comprises the following steps: a photonic crystal thin film is formed on thefirst substrate 11, and the firstphotonic crystal layer 41 and the secondphotonic crystal layer 42 are patterned through a patterning process, as shown in fig. 4c, where fig. 4c is a schematic structural diagram of the array substrate according to the first embodiment of the present invention after the first photonic crystal layer is formed. Thefirst substrate 11 may be a glass substrate or a quartz substrate, the firstphotonic crystal layer 41 is located in a region corresponding to the gate line, the data line, and the thin film transistor, and the secondphotonic crystal layer 42 is located in a region corresponding to the common electrode lead. The material of the photonic crystal thin film can be p-type doped gallium nitride (p-GaN), n-type doped gallium nitride (n-GaN), indium tin oxide or the like.
Fig. 4a is a schematic structural view after the first etching in the process of forming the first photonic crystal layer, and fig. 4b is a schematic structural view after photoresist ashing in the process of forming the first photonic crystal layer. In this embodiment, the structures of the first photonic crystal layer 41 and the second photonic crystal layer 42 are as shown in fig. 3, and the patterning process for forming the first photonic crystal layer 41 and the second photonic crystal layer 42 specifically includes: coating a layer of photoresist on the photonic crystal film; step exposure and development are carried out on the photoresist by adopting a half-tone mask or a gray-scale mask, an unexposed region is formed at the non-groove positions of the first photonic crystal layer 41 and the second photonic crystal layer 42, all the photoresist is reserved, a partial exposed region is formed at the groove positions of the first photonic crystal layer 41 and the second photonic crystal layer 42, a part of the photoresist is reserved, a complete exposed region is formed at other positions, the photoresist is removed, and the photonic crystal film is exposed; etching the photonic crystal film in the complete exposure area, as shown in fig. 4 a; ashing the photoresist, removing the photoresist in the exposed region, i.e. removing the photoresist in the groove position, and leaving a part of the photoresist in the unexposed region, i.e. in the non-groove positions of the first photonic crystal layer 41 and the second photonic crystal layer 42, as shown in fig. 4 b; the photonic crystal film of the partially exposed region is etched to form a pattern of the first photonic crystal layer 41 and the second photonic crystal layer 42, as shown in fig. 4 c.
And a second patterning process to form theplanarization layer 13 and thegate electrode 121. The method comprises the following steps: aplanarization layer 13 and a gate metal film are sequentially formed on thefirst substrate 11 on which the firstphotonic crystal layer 41 is formed, and patterns of thegate electrode 121, the gate line and thecommon electrode lead 17 are formed by using a patterning process, as shown in fig. 5, fig. 5 is a schematic structural view of the array substrate according to the first embodiment of the present invention after the gate electrode is formed. Wherein, the orthographic projections of thegate electrode 121 and the gate line on thefirst substrate 11 are both located within the orthographic projection range of the firstphotonic crystal layer 41 on thefirst substrate 11, and the orthographic projection of thecommon electrode lead 17 on thefirst substrate 11 is located within the orthographic projection range of the secondphotonic crystal layer 42 on thefirst substrate 11. The gate metal film may be made of one or more metals of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, etc., and the material of theplanarization layer 13 may include a transparent organic material, and the planarization layer may be formed by coating.
And a third patterning process to form thegate insulating layer 18 and theactive layer 124. The method comprises the following steps: agate insulating layer 18 and an active thin film are sequentially deposited on thefirst substrate 11 on which thegate electrode 121 is formed, and a pattern of anactive layer 124 is formed by using a patterning process, as shown in fig. 6, and fig. 6 is a schematic structural view of the array substrate according to the first embodiment of the present invention after the active layer is formed. The active thin film may be amorphous silicon, polycrystalline silicon, or microcrystalline silicon, or may be a metal Oxide material, and the metal Oxide material may be Indium Gallium Zinc Oxide (IGZO) or Indium Tin Zinc Oxide (ITZO). Thegate insulating layer 18 may be made of silicon nitride SiNx, silicon oxide SiOx, or a composite layer of SiNx/SiOx.
And a fourth patterning process to form thesource electrode 122 and thedrain electrode 123. The method comprises the following steps: a source/drain metal film is deposited on thefirst substrate 11 on which theactive layer 124 is formed, and a pattern of thesource electrode 122, thedrain electrode 123, and the data line (not shown) is formed using a patterning process. As shown in fig. 7, fig. 7 is a schematic structural view of the array substrate after forming the source/drain electrodes according to the first embodiment of the invention. Wherein orthographic projections of thesource electrode 122, thedrain electrode 123 and the data line on thefirst substrate 11 are all located within an orthographic projection range of the firstphotonic crystal layer 41 on thefirst substrate 11. The source/drain metal thin film may be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, and the like.
And a fifth patterning process, forming thepixel electrode 14. The method comprises the following steps: an ITO thin film is deposited on thefirst substrate 11 on which thesource electrode 122 and thedrain electrode 123 are formed, and a pattern of thepixel electrode 14 is formed by using a patterning process, as shown in fig. 8, fig. 8 is a schematic structural view of the array substrate according to the first embodiment of the present invention after the pixel electrode is formed.
And a sixth patterning process to form theinterlayer insulating layer 15. The method comprises the following steps: an insulating film is deposited on thefirst substrate 11 on which thepixel electrode 14 is formed, a pattern of an interlayer insulatinglayer 15 is formed by using a patterning process, a via hole for exposing thecommon electrode lead 17 is formed on theinterlayer insulating layer 15, as shown in fig. 9, and fig. 9 is a schematic structural view of the array substrate according to the first embodiment of the present invention after the interlayer insulating layer is formed.
And a seventh patterning process, forming thecommon electrode 16. The method comprises the following steps: an ITO thin film is deposited on theinterlayer insulating layer 15, a pattern of thecommon electrode 16 is formed using a patterning process, and thecommon electrode 16 is electrically connected to thecommon electrode lead 17 through a via hole, as shown in fig. 2. Thecommon electrode 16 is a slit electrode.
According to the array substrate provided by the embodiment of the invention, when light enters the array substrate from the side, away from the thin film transistor, of thefirst substrate 11, the light irradiating the gate line, the data line and the thin film transistor is irradiated on the firstphotonic crystal layer 41, the firstphotonic crystal layer 41 can guide light in a directional mode, the propagation direction of the light irradiating the first photonic crystal layer can be changed, the light irradiating the first photonic crystal layer is emitted towards thepixel region 103, and further the light can penetrate through the array substrate from thepixel region 103, so that the light loss of the gate line, the data line and the thin film transistor is reduced, the light utilization rate is improved, and the light transmittance of the array substrate is improved.
Second embodiment:
fig. 10 is a schematic structural diagram of a display panel according to a second embodiment of the invention. Based on the inventive concept of the above embodiments, a second embodiment of the present invention provides a display panel, as shown in fig. 10. The display panel includes thearray substrate 100 in the above embodiments, and further includes acolor filter substrate 200 and aliquid crystal layer 300. Thecolor film substrate 200 is arranged opposite to thearray substrate 100, and thecolor film substrate 200 is connected with thearray substrate 100 through the frame sealing adhesive 400. Theliquid crystal layer 300 is disposed between thearray substrate 100 and thecolor film substrate 200, and is located in an area surrounded by the frame sealing adhesive 400.
Thecolor filter substrate 200 includes asecond substrate 21, acolor filter 22, and ablack matrix 23. Thecolor films 22 are disposed on a side of thesecond substrate 21 facing thearray substrate 100, and theblack matrix 23 is located betweenadjacent color films 22. An orthographic projection of theblack matrix 23 on thefirst substrate 11 is located within an orthographic projection range of the firstphotonic crystal layer 41 on thefirst substrate 11. Therefore, as shown in fig. 10, when light enters the display panel from the side of the array substrate away from the color filter substrate, the light vertically irradiated to the area of theblack matrix 23 is firstly irradiated to the firstphotonic crystal layer 41, and the firstphotonic crystal layer 41 can change the propagation direction of the light vertically irradiated to the area of theblack matrix 23, so that the light vertically irradiated to the area of theblack matrix 23 is emitted toward the area of thecolor filter 22, and further, the light can penetrate the display panel from the area of thecolor filter 22, thereby reducing the light loss irradiated to the area of theblack matrix 23, improving the light utilization rate, improving the light transmittance of the display panel, and improving the brightness of the display panel. Therefore, the display panel of the embodiment of the invention can improve the light transmittance and the brightness of the display panel without increasing the power consumption and the brightness of the backlight source and the cost of other raw materials.
As can also be seen in fig. 4, the display panel further comprises afirst alignment layer 19 and asecond alignment layer 24. Thefirst alignment layer 19 is located on thecommon electrode 16 side facing theliquid crystal layer 300, and thesecond alignment layer 24 is located on thecolor filter 22 side facing theliquid crystal layer 300.
The display panel may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the description of the embodiments of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An array substrate comprises a first substrate, a grid line, a data line and a thin film transistor, wherein the grid line, the data line and the thin film transistor are arranged on the first substrate, the grid line and the data line are intersected with each other to define a plurality of pixel regions, the thin film transistor corresponds to the pixel regions, the array substrate further comprises a first photonic crystal layer and a flat layer, the first photonic crystal layer is arranged on the first substrate, and the first photonic crystal layer is used for enabling light rays irradiated to the regions where the grid line, the data line and the thin film transistor are located to be emitted towards the pixel regions;
the first photonic crystal layer is arranged between the first substrate and the thin film transistor, and a plurality of grooves are formed in one side, away from the first substrate, of the first photonic crystal layer;
the refractive index of the planarization layer is greater than the refractive index of the first photonic crystal layer.
2. The array substrate of claim 1, wherein the first photonic crystal layer has an entrance side and an exit side, and the exit side has a plurality of grooves.
3. The array substrate of claim 2, wherein the plurality of grooves are uniformly arranged, the depth of each groove is less than or equal to 120nm, and the distance between every two adjacent grooves is 350 nm-600 nm.
4. The array substrate of claim 1, wherein the material of the first photonic crystal layer comprises at least one of p-type doped gallium nitride, n-type doped gallium nitride and indium tin oxide.
5. The array substrate of claim 1, wherein orthographic projections of the gate lines, the data lines and the thin film transistors on the first substrate are all within an orthographic projection range of the first photonic crystal layer on the first substrate.
6. The array substrate of claim 1, wherein the thin film transistor is a bottom gate thin film transistor, the thin film transistor comprises a gate electrode on the first substrate, an active layer on the gate electrode, and source and drain electrodes on the active layer, and the first photonic crystal layer is between the gate electrode and the first substrate.
7. The array substrate of claim 1, further comprising a pixel electrode disposed on the thin film transistor, an interlayer insulating layer disposed on the pixel electrode, and a common electrode disposed on the interlayer insulating layer, wherein the array substrate further comprises a common electrode lead disposed on the same layer as the gate line and electrically connected to the common electrode, and a second photonic crystal layer disposed between the common electrode lead and the first substrate and configured to emit light irradiated to a region where the common electrode lead is located toward the pixel region.
8. The array substrate of claim 7, wherein an orthographic projection of the common electrode lead on the first base is within an orthographic projection of the second photonic crystal layer on the first base.
9. A preparation method of an array substrate is characterized by comprising the following steps:
forming a photonic crystal film on a first substrate;
coating a layer of photoresist on the photonic crystal film;
step exposure and development are carried out on the photoresist by adopting a halftone mask or a gray scale mask, an unexposed area is formed at the non-groove position of the photonic crystal film, the photoresist is reserved, a partial exposed area is formed at the groove position of the photonic crystal film, a part of the photoresist is reserved, a complete exposed area is formed at other positions, and no photoresist is used;
etching the photonic crystal film in the complete exposure area;
ashing the photoresist, removing the photoresist in a partial exposure area, and reserving a part of photoresist in a non-exposure area;
etching the photonic crystal film in the partial exposure area to form a pattern of a first photonic crystal layer;
forming a gate line, a data line, a thin film transistor and a flat layer arranged between the first photonic crystal layer and the thin film transistor on the first photonic crystal layer, wherein the gate line and the data line are crossed with each other to define a plurality of pixel regions, the thin film transistor corresponds to the pixel regions, the first photonic crystal layer is used for enabling light rays irradiated to the regions where the gate line, the data line and the thin film transistor are located to be emitted towards the pixel regions, and one side, away from a first substrate, of the first photonic crystal layer is provided with a plurality of grooves; the refractive index of the planarization layer is greater than the refractive index of the first photonic crystal layer.
10. A display panel, comprising the array substrate according to any one of claims 1 to 8, and further comprising a color filter substrate disposed in an involution manner with the array substrate, wherein the color filter substrate includes a second substrate, a color filter disposed on one side of the second substrate facing the array substrate, and a black matrix disposed between adjacent color filters, and an orthographic projection of the black matrix on the first substrate is located in an orthographic projection range of the first photonic crystal layer on the first substrate.
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| CN112882299A (en)* | 2021-03-10 | 2021-06-01 | 武汉京东方光电科技有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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| KR100736623B1 (en)* | 2006-05-08 | 2007-07-09 | 엘지전자 주식회사 | Vertical light emitting device and manufacturing method |
| CN101140962A (en)* | 2006-09-04 | 2008-03-12 | 上海蓝宝光电材料有限公司 | Method for enhancing chip brightness |
| CN100587571C (en)* | 2006-09-22 | 2010-02-03 | 北京京东方光电科技有限公司 | Liquid crystal display device with thin film transistor on color film and manufacturing method thereof |
| CN103076693A (en)* | 2011-10-26 | 2013-05-01 | 东莞万士达液晶显示器有限公司 | Active element array substrate and display |
| CN103413495A (en)* | 2013-07-17 | 2013-11-27 | 京东方科技集团股份有限公司 | Display device |
| CN107255885B (en)* | 2017-08-16 | 2020-02-21 | 京东方科技集团股份有限公司 | Display panel and manufacturing method thereof |
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