CN109817161B - Electro-optical device and electronic apparatus - Google Patents

Abstract

An electro-optical device and an electronic apparatus. An electro-optical device (10) comprises: a scan line (42); a signal line (43); a pixel circuit (41) provided in correspondence with an intersection of the scanning line (42) and the signal line (43); a 1 st high potential line (47) to which a 1 st potential is supplied; a low potential line (46) to which a 2 nd potential is supplied; a 2 nd high potential line (49) to which a 3 rd potential is supplied, the pixel circuit (41) including: a light-emitting element (20); a memory circuit (60) disposed between the 1 st high potential line (47) and the low potential line (46); a 1 st transistor (31) having a gate electrically connected to a memory circuit (60); and a 2 nd transistor (32) having a gate electrically connected to the scanning line (42), wherein the 2 nd transistor (32) is disposed between the memory circuit (60) and the signal line (43), and wherein a potential difference of the 1 st potential with respect to the 2 nd potential is smaller than a potential difference of the 3 rd potential with respect to the 2 nd potential.

Description

Electro-optical device and electronic apparatus

Technical Field

The present invention relates to an electro-optical device and an electronic apparatus.

Background

In recent years, as an electronic apparatus capable of forming and observing a virtual image, a Head Mounted Display (HMD) of a type that guides image light from an electro-optical device to the pupil of an observer has been proposed. In such electronic apparatuses, as an electro-optical device, for example, an organic EL device having an organic EL (electro luminescence) element as a light emitting element is used. In an organic EL device used for a head-mounted display, there are demands for higher resolution (finer pixels), higher gradation of display, and lower power consumption.

In the conventional organic EL device, when the selection transistor is turned on by a scanning signal supplied to the scanning line, a potential based on an image signal supplied from the signal line is held by a capacitive element connected to the gate of the driving transistor. When the driving transistor is turned on in accordance with the potential held by the capacitive element, that is, the gate potential of the driving transistor, a current of an amount corresponding to the gate potential of the driving transistor flows through the organic EL element, and the organic EL element emits light at a luminance corresponding to the current amount.

As described above, in the conventional organic EL device, since gray scale display is performed by analog driving in which the current flowing through the organic EL element is controlled in accordance with the gate potential of the driving transistor, there is a problem as follows: the display quality is degraded by variations in brightness and gray scales between pixels due to variations in voltage-current characteristics or threshold voltages of the driving transistors. In contrast, an organic EL device having a compensation circuit for compensating for variations in voltage-current characteristics or threshold voltages of driving transistors has been proposed (for example, see patent document 1).

Patent document 1: japanese laid-open patent application No. 2004-062199

However, when the compensation circuit is provided as described inpatent document 1, a current flows through the compensation circuit, which leads to an increase in power consumption. In addition, in the conventional analog driving, in order to make the display multi-gradation, it is necessary to increase the capacitance of the capacitor element for storing the image signal, and therefore, it is difficult to achieve high resolution (miniaturization of pixels) at the same time, and power consumption also increases with the charge and discharge of the capacitor element. In other words, the conventional technology has a problem that it is difficult to realize an electro-optical device capable of displaying high-resolution and multi-grayscale high-quality images with low power consumption.

Disclosure of Invention

The present invention has been made to solve at least part of the above problems, and can be realized as the following modes or application examples.

(application example 1) an electro-optical device according to the present application example is characterized by including: scanning a line; a signal line; pixel circuits provided corresponding to intersections of the scanning lines and the signal lines; a 1 st potential line to which a 1 st potential is supplied; a 2 nd potential line to which a 2 nd potential is supplied; and a 3 rd potential line to which a 3 rd potential is supplied, the pixel circuit including: a light emitting element; a storage circuit arranged between the 1 st potential line and the 2 nd potential line; a 1 st transistor having a gate electrically connected to the memory circuit; and a 2 nd transistor whose gate is electrically connected to the scanning line, the 2 nd transistor being disposed between the memory circuit and the signal line, the light-emitting element and the 1 st transistor being disposed in series between the 2 nd potential line and the 3 rd potential line, an absolute value of a potential difference of the 1 st potential with respect to the 2 nd potential being smaller than an absolute value of a potential difference of the 3 rd potential with respect to the 2 nd potential.

According to the configuration of the present application example, the pixel circuit includes a memory circuit arranged between a 1 st potential line and a 2 nd potential line, the 2 nd transistor is arranged between the memory circuit and the signal line, the 1 st transistor and the light emitting element are arranged in series between the 2 nd potential line and a 3 rd potential line, a gate of the 1 st transistor is electrically connected to the memory circuit, and a gate of the 2 nd transistor is electrically connected to the scanning line. Therefore, a digital signal represented by a binary value of on/off can be written into the memory circuit via the 2 nd transistor, and the ratio of light emission to non-light emission of the light-emitting element can be controlled via the 1 st transistor to perform gradation display. Thus, since the transistor is less susceptible to variations in voltage-current characteristics or threshold voltages of the transistors, variations in brightness or variations in gray scale between pixels can be reduced without using a compensation circuit. In addition, in the digital driving, the number of gradations can be easily increased without using a capacitor element by increasing the number of subfields which are units for controlling light emission and non-light emission of a light emitting element in a field where one image is displayed. Further, since it is not necessary to provide a capacitor element having a large capacitance, miniaturization of pixels can be achieved. This makes it possible to miniaturize pixels and achieve high resolution, and also to reduce power consumption associated with charging and discharging of a capacitor element.

Further, the absolute value of the potential difference of the 1 st potential with respect to the 2 nd potential supplied to the memory circuit is smaller than the absolute value of the potential difference of the 3 rd potential with respect to the 2 nd potential supplied to the light emitting element and the 1 st transistor. That is, the memory circuit is operated by the low-voltage system power supply of the 1 st potential and the 2 nd potential, and the light-emitting element is caused to emit light by the high-voltage system power supply of the 3 rd potential and the 2 nd potential. Therefore, the memory circuit can be miniaturized to realize high-speed operation, and the light emission luminance of the light emitting element can be improved. This makes it possible to speed up writing and rewriting of image signals and to make the display brighter. As a result, an electro-optical device capable of displaying a bright, high-resolution, multi-grayscale, high-quality image with low power consumption can be realized.

(application example 2) the electro-optical device according to the present application example is preferable that the memory circuit includes a 3 rd transistor, and a gate length of the 3 rd transistor is shorter than a gate length of the 1 st transistor.

According to the configuration of the present application example, the gate length of the 3 rd transistor included in the memory circuit is shorter than the gate length of the 1 st transistor arranged in series with the light emitting element, and therefore, even if the 3 rd transistor is smaller than the 1 st transistor, the memory circuit can be miniaturized. Therefore, the memory circuit can be operated at high speed, and the light-emitting element can be caused to emit light at a high voltage.

(application example 3) in the electro-optical device according to the application example, it is preferable that the area of the channel formation region of the 3 rd transistor is smaller than the area of the channel formation region of the 1 st transistor.

According to the configuration of the present application example, since the transistor capacitance of the 3 rd transistor included in the memory circuit is smaller than the transistor capacitance of the 1 st transistor, writing and rewriting of the image signal to the memory circuit can be speeded up.

(application example 4) in the electro-optical device according to the present application example, it is preferable that the source of the 1 st transistor is electrically connected to the 2 nd potential line, and the light emitting element is disposed between the drain of the 1 st transistor and the 3 rd potential line.

According to the configuration of the present application example, since the source potential of the 1 st transistor is fixed to the 2 nd potential, when the 1 st transistor is turned on, even if the absolute value of the source-drain voltage of the 1 st transistor is small, the conductivity of the 1 st transistor can be increased. That is, when the 1 st transistor is turned on and the light-emitting element emits light, the 1 st transistor can be operated substantially linearly (hereinafter, simply referred to as linear operation). Accordingly, most of the potential difference between the 2 nd potential and the 3 rd potential which are high-voltage system power supplies is applied to the light-emitting element, and therefore, when the light-emitting element emits light, the light-emitting element is less likely to be affected by variations in the threshold voltage of the 1 st transistor. As a result, the uniformity of brightness between pixels can be improved.

(application example 5) in the electro-optical device according to the present application example, it is preferable that the on-resistance of the 1 st transistor is lower than the on-resistance of the light emitting element.

According to the configuration of the present application example, the 1 st transistor can be linearly operated when the 1 st transistor is turned on and the light emitting element emits light. As a result, most of the potential difference generated between the light-emitting element and the 1 st transistor is applied to the light-emitting element, and therefore, when the light-emitting element is caused to emit light, the light-emitting element is less likely to be affected by variations in the threshold voltage of the 1 st transistor. This can reduce variations in brightness and gray scale among pixels.

(application example 6) in the electro-optical device according to the present application example, it is preferable that the 1 st transistor and the 2 nd transistor have the same polarity.

According to the configuration of the present application example, for example, when the 1 st transistor is turned on by an N-type or high signal, the 2 nd transistor is also turned on by an N-type or high signal. Since the potential of the selection signal supplied from the scanning line to the gate of the 2 nd transistor can be set to the 3 rd potential which is the highest of the 1 st potential, the 2 nd potential, and the 3 rd potential, and the non-selection signal can be set to the 2 nd potential which is the lowest of the 1 st potential, the 2 nd potential, and the 3 rd potential, the potential of the selection signal can be set to be higher than the potential of the image signal (the 1 st potential or the 2 nd potential). Therefore, when the 2 nd transistor is turned on and an image signal is written into the memory circuit, the gate-source voltage of the 2 nd transistor can be increased by the selection signal being high, and therefore, even if the source potential is increased by the writing of the image signal (even if the 1 st potential on the high potential side is supplied as the image signal), the on-resistance of the 2 nd transistor can be maintained low.

Similarly, when the 1 st transistor is turned on by a P-type or low signal, the 2 nd transistor is also turned on by a P-type or low signal. Since the potential of the selection signal supplied from the scanning line to the gate of the 2 nd transistor can be set to the 3 rd potential which is the lowest of the 1 st potential, the 2 nd potential, and the 3 rd potential, and the non-selection signal can be set to the 2 nd potential which is the highest of the 1 st potential, the 2 nd potential, and the 3 rd potential, the potential of the selection signal can be set to be lower than the potential of the image signal (the 1 st potential or the 2 nd potential). Therefore, when the 2 nd transistor is turned on and an image signal is written into the memory circuit, the gate-source voltage of the 2 nd transistor can be increased by the selection signal low, and therefore, even if the source potential is lowered by the writing of the image signal (even if the 1 st potential on the low potential side is supplied as the image signal), the on-resistance of the 2 nd transistor can be maintained low. This makes it possible to write and rewrite the image signal to and from the memory circuit at high speed and with reliability.

(application example 7) the electro-optical device of the present application example preferably includes a control line, the pixel circuit includes a 4 th transistor, a gate of the 4 th transistor is electrically connected to the control line, and the light-emitting element, the 1 st transistor, and the 4 th transistor are arranged in series between the 2 nd potential line and the 3 rd potential line.

According to the configuration of the present application example, the 4 th transistor arranged in series with the light emitting element and the 1 st transistor can be controlled independently of the 2 nd transistor through the control line. That is, a period in which the 2 nd transistor is turned on to write an image signal into the memory circuit and a period in which the 4 th transistor is turned on to make the light-emitting element emit light are controlled independently. Therefore, in each pixel, the light-emitting element can be set to a non-light-emitting state during a period in which an image signal is written in the memory circuit, and the light-emitting element can be set to a light-emitting state for a predetermined time as a display period after the image signal is written in the memory circuit.

(application example 8) in the electro-optical device according to the present application example, it is preferable that the drain of the 4 th transistor is electrically connected to the light emitting element.

According to the structure of the present application example, the drain of the 4 th transistor is electrically connected to the light emitting element, the light emitting element is disposed between the 1 st transistor and the 3 rd potential line, and the source of the 1 st transistor is electrically connected to the 2 nd potential line. Therefore, if the 4 th transistor is of the N type, the 4 th transistor is arranged on the lower potential side of the light emitting element, and if the 4 th transistor is of the P type, the 4 th transistor is arranged on the higher potential side of the light emitting element, and therefore, even if the source-drain voltage of the 4 th transistor is small when the 4 th transistor is in the on state, the conductivity of the 4 th transistor can be increased. That is, when the 4 th transistor is turned on and the light-emitting element emits light, the 4 th transistor can be operated linearly. Accordingly, most of the potential difference between the 2 nd potential and the 3 rd potential which are high-voltage system power supplies is applied to the light-emitting element, and therefore, when the light-emitting element emits light, the light-emitting element is less likely to be affected by variations in the threshold voltage of the 4 th transistor. As a result, the uniformity of brightness between pixels can be improved.

(application example 9) in the electro-optical device according to the present application example, it is preferable that the on-resistance of the 4 th transistor is lower than the on-resistance of the light emitting element.

According to the configuration of the present application example, when the 1 st transistor and the 4 th transistor are turned on to emit light from the light emitting element, the 4 th transistor can be linearly operated. As a result, most of the potential difference generated in the light-emitting element, the 1 st transistor, and the 4 th transistor is applied to the light-emitting element, and therefore, when the light-emitting element is caused to emit light, the light-emitting element is less likely to be affected by variations in the threshold voltage of the 4 th transistor. This can reduce variations in brightness and gray scale among pixels.

(application example 10) in the electro-optical device according to the present application example, it is preferable that the 1 st transistor and the 4 th transistor have opposite polarities.

According to the configuration of the present application example, the source of the 1 st transistor and the source of the 4 th transistor are electrically connected to potential lines having different potentials, respectively. Therefore, since the source potential of the 1 st transistor and the source potential of the 4 th transistor are fixed to the respective potentials, when the two transistors are turned on, the conductivity of the two transistors can be increased to perform a linear operation.

(application example 11) in the electro-optical device according to the present application example, it is preferable that the 4 th transistor is off when the 2 nd transistor is on.

According to the configuration of the present application example, when the 2 nd transistor is turned on and an image signal is written from the signal line to the memory circuit, the 4 th transistor is turned off and the light-emitting element is turned off, so that a signal can be written (or rewritten) to the memory circuit reliably and at high speed with low power consumption. This can suppress erroneous display and deterioration in image display quality due to incorrect writing of the image signal into the memory circuit.

(application example 12) in the electro-optical device according to the present application example, it is preferable that the control line is supplied with an inactive signal for turning off the 4 th transistor in a 1 st period in which any one of the scanning lines is supplied with a selection signal for turning on the 2 nd transistor.

According to the configuration of the present application example, since the 4 th transistor is turned off in the 1 st period in which the 2 nd transistor is turned on by the selection signal, the light emitting element can be made not to emit light in the 1 st period in which the image signal is written in the memory circuit.

(application example 13) in the electro-optical device according to the present application example, it is preferable that the scanning line is supplied with a non-selection signal for turning off the 2 nd transistor in the 2 nd period in which the control line is supplied with an activation signal for turning on the 4 th transistor.

According to the configuration of the present application example, since the 2 nd transistor is turned off in the 2 nd period in which the 4 th transistor is turned on by the activation signal, writing of the image signal to the memory circuit can be stopped in the 2 nd period in which the light emitting element can emit light. Further, the 1 st period and the 2 nd period can be independently controlled, and therefore, the length of the 2 nd period in which the light emitting element can emit light can be made different in various ways regardless of the length of the 1 st period. This enables display with higher gradation by digital time-division driving. Further, since signals (an active signal and an inactive signal) supplied to the control lines can be shared among the plurality of pixels, the electro-optical device can be easily driven even if there is a subfield in which the 2 nd period is shorter than one vertical period in which all of the plurality of scanning lines are selected.

(application example 14) in the electro-optical device according to this application example, it is preferable that the 1 st transistor is N-type, the 4 th transistor is P-type, and when the 1 st potential is V1, the 2 nd potential is V2, and the 3 rd potential is V3, the potential of the activation signal supplied to the control line is V3- (V1-V2) or less.

According to the structure of this application example, the source of the N-type 1 st transistor is electrically connected to the 2 nd potential line, and the source of the P-type 4 th transistor is electrically connected to the 3 rd potential line, so that the 3 rd potential is higher than the 2 nd potential. When the activation signal of "low" is supplied to the gate, the 4 th transistor is turned on, and therefore, the potential of the activation signal is made equal to or lower than V3- (V1-V2), that is, the low-voltage system power supply voltage is reduced from the 3 rd potential, which is the source potential of the 4 th transistor, and therefore, the 4 th transistor can be reliably turned on by the activation signal. Further, as the potential of the activation signal is lowered, the gate-source voltage of the 4 th transistor increases in a negative direction, and the on-resistance of the 4 th transistor in the on state decreases, so that the influence of variations in the threshold voltage of the 4 th transistor is less likely to be received when the light-emitting element is caused to emit light.

(application example 15) in the electro-optical device according to the present application example, it is preferable that the potential of the activation signal is the 2 nd potential.

According to the configuration of the present application example, by setting the potential of the activation signal to the 2 nd potential which is the lowest among the 1 st potential, the 2 nd potential, and the 3 rd potential, it is not necessary to introduce a new potential. Further, the absolute value of the gate-source voltage of the 4 th transistor can be sufficiently increased. Therefore, the on-resistance of the 4 th transistor in the on state can be sufficiently reduced, and the influence of the variation in the threshold voltage of the 4 th transistor on the light emission luminance of the light emitting element can be substantially eliminated.

(application example 16) in the electro-optical device according to the present application example, it is preferable that the 1 st transistor and the 2 nd transistor are N-type, and a potential of the selection signal supplied to the scan line is equal to or higher than the 1 st potential.

According to the configuration of the present application example, when a "high" signal is supplied from the memory circuit disposed between the 1 st potential line and the 2 nd potential line to the gate, the 1 st transistor of the N type is turned on, and therefore, the 1 st potential is higher than the 2 nd potential, and the source of the 1 st transistor of the N type is electrically connected to the 2 nd potential line. The source potential of the N-type 2 nd transistor is between the 1 st potential and the 2 nd potential, but the potential of the selection signal supplied from the scanning line to the gate of the 2 nd transistor is not less than the 1 st potential, and therefore the 2 nd transistor can be reliably brought into an on state. Further, the on-resistance of the 2 nd transistor in the on state decreases as the potential of the selection signal is higher than the 1 st potential, and thus writing and rewriting of the image signal to the memory circuit can be performed reliably and at high speed without erroneous operation.

(application example 17) in the electro-optical device according to the present application example, it is preferable that the potential of the selection signal is the 3 rd potential.

According to the configuration of the present application example, by setting the potential of the selection signal to the 3 rd potential which is the highest among the 1 st potential, the 2 nd potential, and the 3 rd potential, it is not necessary to introduce a new potential. Further, since the gate-source voltage of the 2 nd transistor can be sufficiently increased, the on-resistance of the 2 nd transistor in the on state can be sufficiently reduced, and writing and rewriting of the image signal to the memory circuit can be reliably performed at high speed without erroneous operation.

(application example 18) in the electro-optical device according to this application example, it is preferable that the 1 st transistor is P-type, the 4 th transistor is N-type, and the potential of the activation signal supplied to the control line is equal to or higher than V3+ (V2-V1) when the 1 st potential is V1, the 2 nd potential is V2, and the 3 rd potential is V3.

According to the structure of this application example, the source of the 1 st transistor of the P type is electrically connected to the 2 nd potential line, and the source of the 4 th transistor of the N type is electrically connected to the 3 rd potential line, so that the 3 rd potential is lower than the 2 nd potential. When the activation signal of "high" is supplied to the gate, the 4 th transistor is turned on, but the potential of the activation signal is set to be equal to or higher than V3+ (V2-V1), that is, the low-voltage system power supply voltage is higher than the 3 rd potential which is the source potential of the 4 th transistor, and therefore, the 4 th transistor can be reliably turned on by the activation signal. Further, as the potential of the activation signal is increased, the gate-source voltage of the 4 th transistor is increased, and the on-resistance of the 4 th transistor in the on state is decreased, so that the influence of variations in the threshold voltage of the 4 th transistor is less likely to be received when the light-emitting element is caused to emit light.

(application example 19) in the electro-optical device according to the present application example, it is preferable that the potential of the activation signal is the 2 nd potential.

According to the configuration of the present application example, by setting the potential of the activation signal to the 2 nd potential which is the highest among the 1 st potential, the 2 nd potential, and the 3 rd potential, it is not necessary to introduce a new potential. Further, the gate-source voltage of the 4 th transistor can be sufficiently increased. Therefore, the on-resistance of the 4 th transistor in the on state can be sufficiently reduced, and the influence of the variation in the threshold voltage of the 4 th transistor on the light emission luminance of the light emitting element can be substantially eliminated.

(application example 20) in the electro-optical device according to the application example, it is preferable that the 1 st transistor and the 2 nd transistor are P-type, and a potential of the selection signal supplied to the scan line is equal to or lower than the 1 st potential.

According to the configuration of the present application example, when a low signal is supplied to the gate from the memory circuit disposed between the 1 st potential line and the 2 nd potential line, the 1 st potential of the P-type transistor is lower than the 2 nd potential because the 1 st transistor of the P-type transistor is in an on state, and the source of the 1 st transistor of the P-type transistor is electrically connected to the 2 nd potential line. The source potential of the P-type 2 nd transistor is between the 1 st potential and the 2 nd potential, but the potential of the selection signal supplied from the scanning line to the gate of the 2 nd transistor is not more than the 1 st potential, and therefore the 2 nd transistor can be reliably brought into an on state. Further, as the potential of the selection signal is lower than the 1 st potential, the on-resistance of the 2 nd transistor in the on state is reduced, and thus, writing and rewriting of the image signal to the memory circuit can be performed reliably and at high speed without erroneous operation.

(application example 21) in the electro-optical device according to the present application example, it is preferable that the potential of the selection signal is the 3 rd potential.

According to the configuration of the present application example, by setting the potential of the selection signal to the 3 rd potential which is the lowest among the 1 st potential, the 2 nd potential, and the 3 rd potential, it is not necessary to introduce a new potential. Further, since the gate-source voltage of the 2 nd transistor can be sufficiently increased, the on-resistance of the 2 nd transistor in the on state can be sufficiently reduced, and writing and rewriting of the image signal to the memory circuit can be reliably performed at high speed without erroneous operation.

(application example 22) the electronic device according to the present application example is characterized by including the electro-optical device according to the application example.

According to the configuration of the present application example, it is possible to realize high quality of an image displayed on an electronic device such as a head mounted display, for example.

Drawings

Fig. 1 is a diagram illustrating an outline of an electronic apparatus according to the present embodiment.

Fig. 2 is a diagram illustrating an internal structure of the electronic apparatus according to the present embodiment.

Fig. 3 is a diagram illustrating an optical system of the electronic apparatus according to the present embodiment.

Fig. 4 is a schematic plan view showing the structure of the electro-optical device of the present embodiment.

Fig. 5 is a circuit block diagram of the electro-optical device of the present embodiment.

Fig. 6 is a diagram illustrating a structure of a pixel according to this embodiment.

Fig. 7 is a diagram illustrating digital driving of the electro-optical device according to the present embodiment.

Fig. 8 is a diagram illustrating the structure of a pixel circuit ofembodiment 1.

Fig. 9 is a diagram illustrating a driving method of a pixel circuit according to this embodiment.

Fig. 10 is a diagram illustrating the structure of a pixel circuit according tomodification 1.

Fig. 11 is a diagram illustrating a configuration of a pixel circuit according tomodification 2.

Fig. 12 is a diagram illustrating a configuration of a pixel circuit according tomodification 3.

Fig. 13 is a circuit block diagram of an electro-optical device according toembodiment 2 of the present invention.

Fig. 14 is a diagram illustrating the structure of a pixel according toembodiment 2 of the present invention.

Fig. 15 is a diagram illustrating the structure of a pixel circuit ofembodiment 2.

Fig. 16 is a diagram illustrating the structure of a pixel circuit according to modification 4.

Fig. 17 is a diagram illustrating a configuration of a pixel circuit according to modification 5.

Fig. 18 is a diagram illustrating a configuration of a pixel circuit according to modification 6.

Fig. 19 is a circuit block diagram of an electro-optical device according toembodiment 3 of the present invention.

Fig. 20 is a diagram illustrating the structure of a pixel according toembodiment 3 of the present invention.

Fig. 21 is a diagram illustrating the structure of a pixel circuit according toembodiment 3 of the present invention.

Description of the reference symbols

10: an electro-optical device; 20: a light emitting element; 31. 31A: a 1 st transistor; 32. 32A: a 2 nd transistor; 33: a 3 rd transistor; 34. 34A: a 4 th transistor; 41. 41A, 41B, 41C, 71A, 71B, 71C, 81: a pixel circuit; 42: scanning a line; 43: a signal line; 44: a control line; 46: a low potential line (2 nd potential line); 47: a 1 st high potential line (1 st potential line); 48: a 2 nd low potential line (3 rd potential line); 49: a 2 nd high potential line (3 rd potential line); 60: a storage circuit; 100: head mounted displays (electronic devices).

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, in order to make each layer or each member have a size that can be recognized on the drawings, the scale is different for each layer or each member.

"overview of electronic device"

First, an outline of the electronic apparatus will be described with reference to fig. 1. Fig. 1 is a diagram illustrating an outline of an electronic apparatus according to the present embodiment.

The head-mounteddisplay 100 is an example of the electronic apparatus of the present embodiment, and includes an electro-optical device 10 (see fig. 3). As shown in fig. 1, the head-mounteddisplay 100 has an appearance like glasses. The user wearing the head mounteddisplay 100 is allowed to visually recognize the video light GL (see fig. 3) as an image and to visually recognize the external light in a see-through manner. In short, the head-mounteddisplay 100 has a see-through function of displaying the external light and the image light GL in a superimposed manner, and the head-mounteddisplay 100 has a wide angle of view and high performance, and is small and lightweight.

The head mounteddisplay 100 includes: a see-throughmember 101 that covers the front of the user's eyes; aframe 102 that supports the see-throughmember 101; and a 1 st built-indevice portion 105a and a 2 nd built-indevice portion 105b attached to portions from the hood portions at the left and right ends of theframe 102 to the rear leg portions (temples).

The see-throughmember 101 is an optical member (see-through eye mask) that covers the front of the user's eye and is bent to a large thickness, and is divided into a 1 stoptical portion 103a and a 2 ndoptical portion 103 b. In fig. 1, the 1st display device 151 in which the 1 stoptical portion 103a on the left side and the 1 st built-indevice portion 105a are combined is a portion that transparently displays a virtual image for the right eye, and may function alone as an electronic device with a display function. In fig. 1, the 2nd display device 152 in which the 2 ndoptical portion 103b on the right side and the 2 nd built-indevice portion 105b are combined is a portion in which a virtual image for the left eye is formed transparently, and may function as an electronic device with a display function alone. The 1st display device 151 and the 2nd display device 152 incorporate the electro-optical device 10 (see fig. 3).

Internal structure of electronic equipment "

Fig. 2 is a diagram illustrating an internal structure of the electronic apparatus according to the present embodiment. Fig. 3 is a diagram illustrating an optical system of the electronic apparatus according to the present embodiment. Next, an internal structure and an optical system of the electronic apparatus will be described with reference to fig. 2 and 3. In addition, although the 1st display device 151 is described as an example of an electronic device in fig. 2 and 3, the 2nd display device 152 is bilaterally symmetrical to the 1st display device 151 and has almost the same configuration. Therefore, the 1st display device 151 will be described, and a detailed description of the 2nd display device 152 will be omitted.

As shown in fig. 2, the 1st display apparatus 151 has a projection see-throughdevice 170 and an electro-optical device 10 (refer to fig. 3). The projection see-throughdevice 170 includes aprism 110 as a light guide member, alight transmitting member 150, and aprojection lens 130 for image formation (see fig. 3). Theprism 110 and thelight transmission member 150 are integrated by joining, and are firmly fixed to the lower side of theframe 161, for example, such that theupper surface 110e of theprism 110 is in contact with thelower surface 161e of theframe 161.

Theprojection lens 130 is fixed to an end of theprism 110 via abarrel 162 that houses theprojection lens 130. Theprism 110 and thelight transmission member 150 in the projection see-throughdevice 170 correspond to the 1 stoptical part 103a in fig. 1, and theprojection lens 130 and the electro-optical device 10 of the projection see-throughdevice 170 correspond to the 1 st built-indevice 105a in fig. 1.

Theprism 110 in theprojection transilluminator 170 is an arc-shaped member curved along the face in a plan view, and may be divided into a 1st prism part 111 near the center of the nose and a 2nd prism part 112 far from the periphery of the nose. The 1st prism portion 111 is disposed on the light exit side, and has a 1 st surface S11 (see fig. 3), a 2 nd surface S12, and a 3 rd surface S13 as side surfaces having an optical function.

The 2nd prism part 112 is disposed on the light incident side, and has a 4 th surface S14 (refer to fig. 3) and a 5 th surface S15 as side surfaces having an optical function. The 1 st surface S11 is adjacent to the 4 th surface S14, the 3 rd surface S13 is adjacent to the 5 th surface S15, and the 2 nd surface S12 is disposed between the 1 st surface S11 and the 3 rd surface S13. Theprism 110 has anupper surface 110e adjacent to the 1 st surface S11 to the 4 th surface S14.

Theprism 110 is formed of a resin material exhibiting high light transmittance in a visible range, and is molded by injecting a thermoplastic resin into a mold and curing the resin, for example. Themain body portion 110s (see fig. 3) of theprism 110 is an integrally molded product, but may be divided into a 1st prism portion 111 and a 2nd prism portion 112. The 1st prism portion 111 can guide and emit the image light GL, and can make the external light see through. The 2nd prism portion 112 can enter and guide the image light GL.

The light-transmittingmember 150 is integrally fixed to theprism 110. Thelight transmission member 150 is a member (auxiliary prism) that assists the see-through function of theprism 110. Thelight transmission member 150 is formed of a resin material that exhibits high light transmittance in a visible range and has substantially the same refractive index as themain body portion 110s of theprism 110. Thelight transmitting member 150 is formed by molding a thermoplastic resin, for example.

As shown in fig. 3, theprojection lens 130 has, for example, 3lenses 131, 132, 133 along the incident-side optical axis. Each of thelenses 131, 132, and 133 is rotationally symmetric about the central axis of the light incident surface of the lens, and at least 1 or more of the lenses are aspheric lenses.

Theprojection lens 130 causes the image light GL emitted from the electro-optical device 10 to enter theprism 110, and re-forms an image of the eye EY. In short, theprojection lens 130 is a relay optical system for re-imaging the eye EY by the image light GL emitted from each pixel of the electro-optical device 10 through theprism 110. Theprojection lens 130 is held in alens barrel 162, and the electro-optical device 10 is fixed to one end of thelens barrel 162. The 2nd prism part 112 of theprism 110 is coupled to alens barrel 162 holding theprojection lens 130, and indirectly supports theprojection lens 130 and the electro-optical device 10.

In an electronic device of a type that is worn on the head of a user and covers the front of the eyes as in the head mounteddisplay 100, downsizing and weight saving are required. In addition, the electro-optical device 10 used in an electronic apparatus such as the head-mounteddisplay 100 is required to have higher resolution (finer pixels), higher gray-scale display, and lower power consumption.

[ Structure of electro-optical device ]

Next, the structure of the electro-optical device will be described with reference to fig. 4. Fig. 4 is a schematic plan view showing the structure of the electro-optical device according toembodiment 1. In the present embodiment, a case where the electro-optical device 10 is an organic EL device having an organic EL element as a light-emitting element will be described as an example. As shown in fig. 4, the electro-optical device 10 of the present embodiment includes anelement substrate 11 and aprotective substrate 12. A color filter, not shown, is provided on theelement substrate 11. Theelement substrate 11 and theprotective substrate 12 are arranged facing each other with a filler not shown interposed therebetween and bonded together.

Theelement substrate 11 is made of, for example, a single crystal semiconductor substrate (e.g., a single crystal silicon substrate). Theelement substrate 11 has a display region E and a non-display region D surrounding the display region E. In the display region E, for example, the sub-pixels 58B emitting blue (B) light, the sub-pixels 58G emitting green (G) light, and the sub-pixels 58R emitting red (R) light are arranged in a matrix, for example. The sub-pixels 58B, 58G, and 58R are provided with light-emitting elements 20 (see fig. 6). In the electro-optical device 10, apixel 59 including the sub-pixel 58B, thesub-pixel 58G, and the sub-pixel 58R is used as a display unit to provide full-color display.

In this specification, the sub-pixel 58B, thesub-pixel 58G, and the sub-pixel 58R may be collectively referred to as the sub-pixel 58 without distinction. The display region E is a region that transmits light emitted from the sub-pixel 58 and contributes to display. The non-display region D is a region that does not transmit light emitted from the sub-pixel 58 and does not contribute to display.

Theelement substrate 11 is larger than theprotective substrate 12, and a plurality ofexternal connection terminals 13 are arranged along the 1 st side of theelement substrate 11 exposed from theprotective substrate 12. A signalline driving circuit 53 is provided between the plurality ofexternal connection terminals 13 and the display region E. A scanningline driving circuit 52 is provided between the display region E and the other 2 nd side perpendicular to the 1 st side. A controlline driving circuit 54 is provided between the 3 rd side perpendicular to the 1 st side and facing the 2 nd side and the display region E.

Theprotective substrate 12 is smaller than theelement substrate 11 and is disposed so as to expose theexternal connection terminals 13. Theprotective substrate 12 is a light-transmissive substrate, and for example, a quartz substrate, a glass substrate, or the like can be used. Theprotective substrate 12 has a function of protecting the light-emittingelement 20 disposed in the sub-pixel 58 from damage in the display region E, and is disposed so as to face at least the display region E.

The color filter may be provided on the light-emittingelement 20 in theelement substrate 11, or may be provided on theprotective substrate 12. In the case of a structure in which light corresponding to each color is emitted from the light-emittingelement 20, a color filter is not necessary. Theprotective substrate 12 is not essential, and a protective layer for protecting the light-emittingelement 20 may be provided on theelement substrate 11 instead of theprotective substrate 12.

In this specification, a direction along the 1 st side on which theexternal connection terminals 13 are arranged is referred to as an X direction (row direction), and a direction along two other sides (2 nd side and 3 rd side) perpendicular to the 1 st side and facing each other (column direction) is referred to as a Y direction. In the present embodiment, for example, a so-called stripe (stripe) arrangement is adopted: the sub-pixels 58 that obtain light of the same color are arranged in the column direction (Y direction), and the sub-pixels 58 that obtain light of different colors are arranged in the row direction (X direction).

The arrangement of the sub-pixels 58 in the row direction (X direction) is not limited to the B, G, R shown in fig. 4, and may be R, G, B, for example. The arrangement of the sub-pixels 58 is not limited to the stripe type, but may be a delta type, a Bayer type, or an S-stripe (S-stripe) type, and the shape and size of the sub-pixels 58B, 58G, and 58R are not limited to the same.

(embodiment 1)

Circuit structure of electro-optical device "

Next, a circuit configuration of the electro-optical device will be described with reference to fig. 5. Fig. 5 is a circuit block diagram of the electro-optical device of the present embodiment. As shown in fig. 5, a plurality ofscanning lines 42 and a plurality ofsignal lines 43 are formed in the display region E of the electro-optical device 10 so as to intersect each other, and the sub-pixels 58 are arranged in a matrix corresponding to each intersection of thescanning lines 42 and the signal lines 43. Each sub-pixel 58 is provided with apixel circuit 41 including a light-emitting element 20 (see fig. 8) and the like.

In the display region E of the electro-optical device 10,control lines 44 are formed corresponding to the scanning lines 42. The scanning lines 42 and thecontrol lines 44 extend in the row direction (X direction). In the display region E,complementary signal lines 45 are formed corresponding to the signal lines 43. Thesignal line 43 and thecomplementary signal line 45 extend in the column direction (Y direction).

In the electro-optical device 10, M rows × N columns of sub-pixels 58 are arranged in a matrix in the display region E. Specifically,M scanning lines 42, Mcontrol lines 44, N signal lines 43, and Ncomplementary signal lines 45 are formed in the display region E. In the present embodiment, M and N are integers of 2 or more, and for example, M is 720 and N is 1280 × p. p is an integer of 1 or more and represents the number of displayed basic colors. In the present embodiment, a case where p is 3, that is, 3 colors whose basic color is R, G, B will be described as an example.

The electro-optical device 10 includes a drivingunit 50 outside the display region E. Various signals are supplied from the drivingunit 50 to thepixel circuits 41 arranged in the display region E, and an image is displayed in the display region E with the pixel 59 (sub-pixel 58 of 3 colors) as a display unit. Thedrive unit 50 includes adrive circuit 51 and acontrol device 55. Thecontrol device 55 supplies a display signal to thedrive circuit 51. Thedrive circuit 51 supplies a drive signal to eachpixel circuit 41 via the plurality ofscanning lines 42, the plurality ofsignal lines 43, and the plurality ofcontrol lines 44 in accordance with a display signal.

In the non-display area D and the display area E, a 1 st highpotential line 47 as a 1 st potential line to which a 1 st potential is supplied, a lowpotential line 46 as a 2 nd potential line to which a 2 nd potential is supplied, and a 2 nd highpotential line 49 as a 3 rd potential line to which a 3 rd potential is supplied are arranged. The 1 st highpotential line 47 supplies the 1 st potential to eachpixel circuit 41, the lowpotential line 46 supplies the 2 nd potential to eachpixel circuit 41, and the 2 nd highpotential line 49 supplies the 3 rd potential to eachpixel circuit 41.

In this embodiment, the 1 st potential (V1) is the 1 st high potential VDD1 (e.g., V1 ═ VDD1 ═ 3.0V), the 2 nd potential (V2) is the low potential VSS (e.g., V2 ═ VSS ═ 0V), and the 3 rd potential (V3) is the 2 nd high potential VDD2 (e.g., V3 ═ VDD2 ═ 7.0V). Therefore, the 1 st potential is higher than the 2 nd potential, and the 3 rd potential is higher than the 1 st potential.

In the present embodiment, the 1 st potential (1 st high potential VDD1) and the 2 nd potential (low potential VSS) constitute a low-voltage system power supply, and the 3 rd potential (2 nd high potential VDD2) and the 2 nd potential (low potential VSS) constitute a high-voltage system power supply. The 2 nd potential is a potential that is a reference in the low-voltage system power supply and the high-voltage system power supply.

In this embodiment, the 2 nd potential line (low potential line 46), the 1 st potential line (1 st high potential line 47), and the 3 rd potential line (2 nd high potential line 49) extend in the row direction in the display area E as an example, but they may extend in the column direction, or a part of them may extend in the row direction and the other part may extend in the column direction, or they may be arranged in a grid pattern in the row and column directions.

Thedrive circuit 51 includes a scanningline drive circuit 52, a signalline drive circuit 53, and a controlline drive circuit 54. The drivingcircuit 51 is provided in the non-display region D (see fig. 4). In this embodiment, thedriver circuit 51 and thepixel circuit 41 are formed on the element substrate 11 (a single crystal silicon substrate in this embodiment) shown in fig. 4. Specifically, thedriver circuit 51 and thepixel circuit 41 are formed of elements such as transistors formed on a single crystal silicon substrate.

The scanningline driving circuit 52 is electrically connected to the scanning lines 42. The scanningline driving circuit 52 outputs a scanning signal (Scan) for selecting or not selecting thepixel circuit 41 in the row direction to eachscanning line 42. Thescanning line 42 transmits the scanning signal to thepixel circuit 41. In other words, the scanning signal has a selected state and a non-selected state, and thescanning line 42 receives the scanning signal from the scanningline driving circuit 52 and can be selected appropriately. The scanning signal takes a potential between the 2 nd potential (low potential VSS) and the 3 rd potential (2 nd high potential VDD 2).

As will be described later, in this embodiment, since the 2nd transistor 32 and the complementary 2nd transistor 38 are both N-type (see fig. 8), the scanning signal (selection signal) in the selected state is "high" (high potential), and the scanning signal (non-selection signal) in the non-selected state is "low" (low potential). The selection signal is set to a high potential not lower than the 1 st potential (V1), preferably the 3 rd potential (V3). The non-selection signal is set to a low potential not higher than the 2 nd potential (V2), preferably the 2 nd potential (V2).

When the scanning signal supplied to thescanning line 42 in the ith row among the M scanning lines 42 is determined, the scanning signal Scan i in the ith row is denoted. The scanningline driving circuit 52 includes a shift register circuit, not shown, and outputs a signal shifted in the shift register circuit as a shift output signal for each stage. The shift output signals are used to form Scan signals Scan1 inrow 1 to Scan signal Scan M in row M.

The signalline drive circuit 53 is electrically connected to thesignal line 43 and thecomplementary signal line 45. The signalline driver circuit 53 includes a shift register circuit, a decoder circuit, a demultiplexer circuit, and the like, which are not shown. The signalline drive circuit 53 supplies an image signal (Data) to each of theN signal lines 43 and a complementary image signal (XData) to each of the Ncomplementary signal lines 45 in synchronization with the selection of thescanning line 42. The video signal and the complementary video signal are digital signals having either the 1 st potential (VDD1 in this embodiment) or the 2 nd potential (VSS in this embodiment).

In addition, when the image signal supplied to thesignal line 43 of the j-th column among the N signal lines 43 is determined, the image signal Data j of the j-th column is marked, and similarly, when the complementary image signal supplied to thecomplementary signal line 45 of the j-th column among the Ncomplementary signal lines 45 is determined, the complementary image signal XData j of the j-th column is marked.

The controlline driving circuit 54 is electrically connected to thecontrol line 44. The controlline driving circuit 54 outputs a row specific control signal to eachcontrol line 44 divided for each row. Thecontrol line 44 supplies the control signal to thepixel circuits 41 of the corresponding row. The control signal has an active state and an inactive state, and thecontrol line 44 receives the control signal from the controlline driving circuit 54 and can be appropriately brought into the active state. The control signal takes a potential between the 2 nd potential (low potential VSS) and the 3 rd potential (2 nd high potential VDD 2).

As will be described later, in this embodiment, since the 4th transistor 34 is of a P-type (see fig. 8), the control signal (active signal) in the active state is "low" (low potential), and the control signal (inactive signal) in the inactive state is "high" (high potential). When the 1 st potential is described as V1, the 2 nd potential as V2, and the 3 rd potential as V3, the activation signal is set to V3- (V1-V2) or less, preferably to the 2 nd potential (V2). The inactive signal is set to the 3 rd potential (V3) or higher, preferably the 3 rd potential (V3).

When the control signal supplied to thecontrol line 44 in the ith row among theM control lines 44 is determined, the control signal Enb i in the ith row is denoted as a control signal Enb i. The controlline driving circuit 54 may supply an activation signal (or an inactivation signal) as a control signal for each row, or may simultaneously supply an activation signal (or an inactivation signal) to a plurality of rows. In this embodiment, the controlline driving circuit 54 simultaneously supplies an activation signal (or a deactivation signal) to all thepixel circuits 41 located in the display region E via thecontrol line 44.

Thecontrol device 55 includes a displaysignal supply circuit 56 and a vram (video Random Access memory) circuit 57. The VRAM circuit 57 temporarily stores a frame image and the like. The displaysignal supply circuit 56 generates a display signal (an image signal, a clock signal, or the like) from the frame image temporarily stored in the VRAM circuit 57, and supplies the display signal to thedrive circuit 51.

In this embodiment, thedriver circuit 51 and thepixel circuit 41 are formed on the element substrate 11 (a single crystal silicon substrate in this embodiment). Specifically, thedriver circuit 51 and thepixel circuit 41 are formed of transistor elements formed on a single crystal silicon substrate.

Thecontrol device 55 is formed of a semiconductor integrated circuit formed on a substrate (not shown) such as a single crystal semiconductor substrate different from theelement substrate 11. The substrate on which thecontrol device 55 is formed is connected to theexternal connection terminals 13 provided on theelement substrate 11 by a Flexible Printed Circuit (FPC). A display signal is supplied from thecontrol device 55 to thedrive circuit 51 via the flexible printed circuit board.

"Structure of pixel"

Next, the structure of the pixel of this embodiment will be described with reference to fig. 6. Fig. 6 is a diagram illustrating a structure of a pixel according to this embodiment.

As described above, in the electro-optical device 10, an image is displayed with thepixel 59 including the sub-pixel 58 (sub-pixels 58B, 58G, and 58R) as a display unit. In the present embodiment, the length a of the sub-pixel 58 in the row direction (X direction) is 4 micrometers (μm), and the length b of the sub-pixel 58 in the column direction (Y direction) is 12 micrometers (μm). In other words, the arrangement pitch in the row direction (X direction) of the sub-pixels 58 is 4 micrometers (μm), and the arrangement pitch in the column direction (Y direction) of the sub-pixels 58 is 12 micrometers (μm).

Each sub-pixel 58 is provided with apixel circuit 41 including a Light Emitting element (LED) 20. Thelight emitting element 20 emits white light. The electro-optical device 10 includes a color filter, not shown, which transmits light emitted from the light-emittingelement 20. The color filter comprises a color filter of a color corresponding to the displayed primary color p. In the present embodiment, the primary color p is 3, and color filters of B, G, R are disposed corresponding to the sub-pixels 58B, 58G, and 58R, respectively.

In the present embodiment, an organic el (electro luminescence) element is used as an example of thelight emitting element 20. The organic EL element may have an optical resonance configuration that amplifies the intensity of light of a specific wavelength. That is, the following configuration may be adopted: the sub-pixel 58B extracts a blue light component from the white light emitted from the light-emittingelement 20, the sub-pixel 58G extracts a green light component from the white light emitted from the light-emittingelement 20, and the sub-pixel 58R extracts a red light component from the white light emitted from the light-emittingelement 20.

In addition to the above example, a color filter for a color other than B, G, R, for example, a color filter for white light (actually, the sub-pixel 58 without a color filter) may be prepared with the primary color p being 4, and a color filter for other color light such as yellow or cyan may be prepared. As thelight emitting element 20, a light emitting diode element such as gallium nitride (GaN), a semiconductor laser element, or the like may be used.

Digital driving of electro-optical devices "

Next, an image display method by digital driving of the electro-optical device 10 according to the present embodiment will be described with reference to fig. 7. Fig. 7 is a diagram illustrating digital driving of the electro-optical device according to the present embodiment.

The electro-optical device 10 displays a predetermined image in the display region E (see fig. 4) by digital driving. That is, the light-emitting elements 20 (see fig. 6) arranged in the sub-pixels 58 are in a state of either two values of light emission (bright display) or non-light emission (dark display), and the gradation of the displayed image is determined by the ratio of the light-emitting period of each light-emittingelement 20. This is called time-division driving.

As shown in fig. 7, in the time-division driving, 1 field (F) for displaying one image is divided into a plurality of Subfields (SF), and light emission and non-light emission of thelight emitting elements 20 are controlled for each Subfield (SF), thereby expressing gray scale display. Here, for example, 2 is performed by a time division gradation method of 6 bits⁶The display of 64 gradations is performed as an exampleAnd (4) explanation. In the 6-bit time division gray scale method, 1 field F is divided into 6 subfields SF1 to SF 6.

In fig. 7, the ith subfield is denoted by SFi in 1 field F, and 6 subfields from the 1 st subfield SF1 to the 6 th subfield SF6 are shown. Each subfield SF includes a display period P2(P2-1 to P2-6) as a 2 nd period and, as necessary, a non-display period (signal writing period) P1(P1-1 to P1-6) as a 1 st period.

In this specification, subfields SF1 to SF6 may be collectively referred to as subfield SF, non-display periods P1-1 to P1-6 may be collectively referred to as non-display period P1, and display periods P2-1 to P2-6 may be collectively referred to as display period P2.

The light-emittingelement 20 emits light or does not emit light during the display period P2, and does not emit light during the non-display period (signal writing period) P1. The non-display period P1 is used for writing an image signal into the memory circuit 60 (see fig. 8), adjusting the display time, and the like, and when the shortest subfield (for example, SF1) is relatively long, the non-display period P1(P1-1) may be omitted.

In the 6-bit time division gray scale method, the display period P2(P2-1 to P2-6) of each subfield SF is set to (P2-1 of SF 1): (P2-2 of SF 2): (P2-3 of SF 3): (P2-4 of SF 4): (P2-5 of SF 5): (P2-6 of SF 6) ═ 1: 2: 4: 8: 16: 32. for example, in the case of displaying an image in a progressive manner with a frame frequency of 30Hz, 1 frame is 1 field (F) is 33.3 milliseconds (msec).

In the above example, when the non-display period P1(P1-1 to P1-6) in each subfield SF is 1 ms, it is set to (P2-1 in SF1) 0.434 ms, (P2-2 in SF 2) 0.868 ms, (P2-3 in SF 3) 1.735 ms, (P2-4 in SF 4) 3.471 ms, (P2-5 in SF 5) 6.942 ms, and P2-6 in SF 6) 13.884 ms.

Here, when the time of the non-display period P1 is represented by x (sec), the time of the shortest display period P2 (in the above example, the display period P2-1 in the 1 st subfield SF1), the number of bits of gradation (the number of subfields SF), and the field frequency (f) (hz) are represented by y (sec), the relationship therebetween is represented by the followingexpression 1.

gx+(2^g-1)y-1/f…(I)

In the digital driving of the electro-optical device 10, gradation display is realized according to the ratio of the light emission period to the total display period P2 in 1 field F. For example, in black display with a gray scale of "0", the light-emittingelement 20 is turned off in all of the display periods P2-1 to P2-6 of the 6 subfields SF1 to SF 6. On the other hand, in white display with a gradation of "63", the light-emittingelement 20 emits light in all of the display periods P2-1 to P2-6 of the 6 subfields SF1 to SF 6.

In addition, when a display with an intermediate luminance of, for example, gradation "7" is obtained in 64 gradations, thelight emitting element 20 is caused to emit light in the display period P2-1 of the 1 st subfield SF1, the display period P2-2 of the 2 nd subfield SF2, and the display period P2-3 of the 3 rd subfield SF3, and thelight emitting element 20 is caused to emit no light in the display periods P2-4 to P2-6 of the other subfields SF4 to SF 6. In this way, by appropriately selecting whether the light-emittingelement 20 emits light or does not emit light in the display period P2 of each sub-field SF constituting 1 field F, display of intermediate gradation can be performed.

In addition, in a conventional analog-driven electro-optical device (organic EL device), since gray scale display is performed by analog control of a current flowing through an organic EL element according to a gate potential of a driving transistor, variation in brightness or variation in gray scale occurs between pixels due to variation in voltage-current characteristics or threshold voltage of the driving transistor, and display quality is degraded. On the other hand, when a compensation circuit for compensating for variations in the voltage-current characteristics or threshold voltage of the drive transistor is provided as described inpatent document 1, a current flows through the compensation circuit, which increases power consumption.

In addition, in the conventional organic EL device, in order to achieve multi-gradation display, it is necessary to increase the capacitance of a capacitor element for storing an image signal as an analog signal, and therefore it is difficult to achieve high resolution (miniaturization of pixels) at the same time, and power consumption increases with the charging and discharging of a large capacitor element. In other words, in the conventional organic EL device, there is a problem that it is difficult to realize an electro-optical device capable of displaying high-resolution and multi-grayscale high-quality images with low power consumption.

In the electro-optical device 10 of the present embodiment, since the digital driving is performed by binary on/off, thelight emitting element 20 is in a binary state of emitting light or not emitting light. Therefore, compared with the case of analog driving, the influence of variations in the voltage-current characteristics or threshold voltages of the transistors is less likely to occur, and therefore, a high-quality display image with less variations in brightness or grayscale between the pixels 59 (sub-pixels 58) can be obtained. Further, in the digital driving, since it is not necessary to have a capacitance element having a large capacity required in the case of the analog driving, it is possible to miniaturize the pixel 59 (sub-pixel 58), to easily perform the high resolution, and to reduce the power consumption associated with the charging and discharging of the large capacitance element.

In addition, in the digital driving of the electro-optical device 10, the number of gradations can be easily increased by increasing the number g of the subfields SF constituting 1 field F. In this case, if the non-display period P1 is provided as described above, the number of gradations can be increased by simply shortening the shortest display period P2. For example, when a 256-gradation display is performed with g being 8 in a progressive system in which the frame frequency f is 30Hz, the time of the shortest display period (P2-1 in SF1) can be set to y being 0.100 msec byonly equation 1 when the time of the non-display period P1 is set to x being 1 msec.

In the digital driving of the electro-optical device 10, the non-display period P1, which is the 1 st period, can be a signal writing period (or a signal writing period in which an image signal is written) in which an image signal is written in thememory circuit 60, which will be described later in detail. Therefore, the gradation display of 6 bits can be easily changed to the gradation display of 8 bits without changing the signal writing period (i.e., without changing the clock frequency of the drive circuit 51).

In the digital driving of the electro-optical device 10, the image signal of the memory circuit 60 (see fig. 8) of the sub-pixel 58 to change the display is rewritten during the period of the sub-field SF or the period of the field F. On the other hand, since the image signal of thememory circuit 60 of thesubpixel 58 to be displayed is not rewritten (held), low power consumption is achieved. That is, with this configuration, the following electro-optical device 10 can be realized: the power consumption is reduced, and a high-gradation and high-resolution image with less variation in brightness or shift in gradation between the pixels 59 (sub-pixels 58) is displayed.

(example 1)

"Structure of pixel Circuit"

Next, the structure of the pixel circuit according toembodiment 1 will be described by taking an example and a modification as examples. First, the structure of the pixel circuit of example 1 ofembodiment 1 will be described with reference to fig. 8. Fig. 8 is a diagram illustrating the structure of a pixel circuit ofembodiment 1.

As shown in fig. 8, apixel circuit 41 is provided for each sub-pixel 58 arranged corresponding to the intersection of thescanning line 42 and thesignal line 43. Thecontrol line 44 is disposed along thescanning line 42, and thecomplementary signal line 45 is disposed along thesignal line 43. Eachpixel circuit 41 corresponds to ascanning line 42, asignal line 43, acontrol line 44, and acomplementary signal line 45.

In embodiment 1 (embodiment 1 and the following modifications), the 1 st potential (VDD1) is supplied from the 1 st highpotential line 47 to eachpixel circuit 41, the 2 nd potential (VSS) is supplied from the lowpotential line 46 to eachpixel circuit 41, and the 3 rd potential (VDD2) is supplied from the 2 nd highpotential line 49 to eachpixel circuit 41.

Thepixel circuit 41 ofembodiment 1 includes the 1st transistor 31 of the N type, thelight emitting element 20, the 4th transistor 34 of the P type, thememory circuit 60, the 2nd transistor 32 of the N type, and the complementary 2nd transistor 38 of the N type. Since thepixel circuit 41 includes thememory circuit 60, the electro-optical device 10 can be digitally driven, and variation in light emission luminance of thelight emitting elements 20 for display between the sub-pixels 58 can be suppressed as compared with the case of analog driving, and thus variation in display between thepixels 59 can be reduced.

The 1st transistor 31, the light-emittingelement 20, and the 4th transistor 34 are arranged in series between a 3 rd potential line (2 nd high potential line 49) and a 2 nd potential line (low potential line 46). Thememory circuit 60 is disposed between the 1 st potential line (the 1 st high potential line 47) and the 2 nd potential line (the low potential line 46). The 2nd transistor 32 is disposed between thememory circuit 60 and thesignal line 43. The complementary 2nd transistor 38 is disposed between thememory circuit 60 and thecomplementary signal line 45.

Thememory circuit 60 includes a 1st inverter 61 and a 2nd inverter 62. Thememory circuit 60 is configured by connecting the twoinverters 61 and 62 in a ring shape, and forms a so-called static memory to store a digital signal as an image signal. Theoutput terminal 25 of the 1st inverter 61 is electrically connected to theinput terminal 28 of the 2nd inverter 62, and theoutput terminal 27 of the 2nd inverter 62 is electrically connected to theinput terminal 26 of the 1st inverter 61.

In the present specification, a state in which a terminal (output or input) a and a terminal (output or input) B are electrically connected means a state in which the logic of the terminal a and the logic of the terminal B can be the same, and for example, even when a transistor, a resistance element, a diode, or the like is arranged between the terminal a and the terminal B, the state can be referred to as an electrically connected state. In addition, the "arrangement" in the case where the expression "the transistor, the element are arranged between the terminal a and the terminal B" is not an arrangement on the layout but an arrangement on the circuit diagram.

The digital signal stored by thememory circuit 60 is binary of "high" or "low". In the present embodiment, the light-emittingelement 20 is in a state of being able to emit light when theoutput terminal 25 of the 1st inverter 61 is "low" (when theoutput terminal 27 of the 2nd inverter 62 is "high"), and the light-emittingelement 20 is not emitting light when theoutput terminal 25 of the 1st inverter 61 is "high" (when theoutput terminal 27 of the 2nd inverter 62 is "low").

In this embodiment, twoinverters 61 and 62 constituting thememory circuit 60 are arranged between the 1 st potential line (1 st potential line 47) and the 2 nd potential line (2 nd potential line 46), and VDD as the 1 st potential and VSS as the 2 nd potential are supplied to the twoinverters 61 and 62. Therefore, "high" corresponds to the 1 st potential (VDD1) and "low" corresponds to the 2 nd potential (VSS).

For example, when the digital signal is stored in thememory circuit 60 and theoutput terminal 25 of the 1st inverter 61 is "low", a "low" is input to theinput terminal 28 of the 2nd inverter 62 and theoutput terminal 27 of the 2nd inverter 62 is "high". Then, "high" is input to theinput terminal 26 of the 1st inverter 61, and theoutput terminal 25 of the 1st inverter 61 is set to "low". Thus, the digital signal stored in thememory circuit 60 is kept in a stable state until the next rewriting is performed.

The 1st inverter 61 includes the 3 rd transistor 33 of the N-type and the 5 th transistor 35 of the P-type, and has a CMOS structure. The 3 rd transistor 33 and the 5 th transistor 35 are arranged in series between the 1 st potential line (the 1 st high potential line 47) and the 2 nd potential line (the low potential line 46). The source of the 3 rd transistor 33 is electrically connected to the 2 nd potential line (low potential line 46). The source of the 5 th transistor 35 is electrically connected to the 1 st potential line (1 st high potential line 47).

The 2nd inverter 62 includes a 6th transistor 36 of a P type and a 7 th transistor 37 of an N type, and has a CMOS structure. The 6th transistor 36 and the 7 th transistor 37 are arranged in series between the 1 st potential line (the 1 st high potential line 47) and the 2 nd potential line (the low potential line 46). The source of the 6th transistor 36 is electrically connected to the 1 st potential line (1 st high potential line 47). The source of the 7 th transistor 37 is electrically connected to the 2 nd potential line (low potential line 46).

Theoutput terminal 25 of the 1st inverter 61 is the drain of the 3 rd transistor 33 and the 5 th transistor 35. Theoutput terminal 27 of the 2nd inverter 62 is the drain of the 6th transistor 36 and the 7 th transistor 37. Theinput terminal 26 of the 1st inverter 61 is a gate of the 3 rd transistor 33 and the 5 th transistor 35, and is electrically connected to theoutput terminal 27 of the 2nd inverter 62. Similarly, theinput terminal 28 of the 2nd inverter 62 is the gate of the 6th transistor 36 and the 7 th transistor 37, and is electrically connected to theoutput terminal 25 of the 1st inverter 61.

In the present embodiment, the 1st inverter 61 and the 2nd inverter 62 are both of a CMOS structure, but theseinverters 61 and 62 may be formed of a transistor and a resistance element. For example, the 1st inverter 61 may replace one of the 3 rd transistor 33 and the 5 th transistor 35 with a resistive element, and the 2nd inverter 62 may replace one of the 6th transistor 36 and the 7 th transistor 37 with a resistive element.

The light-emittingelement 20 is an organic EL element in the present embodiment, and includes an anode (pixel electrode) 21, a light-emitting portion (light-emitting functional layer) 22, and a cathode (counter electrode) 23. Thelight emitting section 22 forms excitons from holes injected from theanode 21 side and electrons injected from thecathode 23 side, and is configured to emit light by converting a part of energy into fluorescence or phosphorescence when the excitons disappear (when the holes and the electrons recombine) and to emit the fluorescence or phosphorescence.

In thepixel circuit 41 ofembodiment 1, thelight emitting element 20 is disposed between the 1st transistor 31 and the 4th transistor 34. Theanode 21 of the light-emittingelement 20 is electrically connected to the drain of the 4th transistor 34, and thecathode 23 of the light-emittingelement 20 is electrically connected to the drain of the 1st transistor 31.

The 1st transistor 31 is a driving transistor for thelight emitting element 20. That is, when the 1st transistor 31 is in an on state, the light-emittingelement 20 can emit light. The gate of the 1st transistor 31 is electrically connected to theoutput terminal 27 of the 2nd inverter 62 of thememory circuit 60. The source of the 1st transistor 31 is electrically connected to the 2 nd potential line (low potential line 46). The drain of the 1st transistor 31 is electrically connected to the light-emitting element 20 (cathode 23). That is, the 1st transistor 31 of the N-type is disposed at a lower potential side than thelight emitting element 20.

The 4th transistor 34 is a control transistor which controls light emission of thelight emitting element 20. When the 4th transistor 34 is in an on state, the light-emittingelement 20 can emit light. As described later, in this embodiment, when thecontrol line 44 is supplied with an activation signal as a control signal to turn on the 4th transistor 34 and theoutput terminal 27 of the 2nd inverter 62 is at a potential corresponding to light emission to turn on the 1st transistor 31, thelight emitting element 20 emits light.

The gate of the 4th transistor 34 is electrically connected to thecontrol line 44. The source of the 4th transistor 34 is electrically connected to the 3 rd potential line (2 nd high potential line 49). The drain of the 4th transistor 34 is electrically connected to the light-emitting element 20 (anode 21). That is, the 4th transistor 34 of the P-type is disposed on the higher potential side than thelight emitting element 20.

Here, in the N-type transistor, the source potential and the drain potential are compared, and the lower potential is the source. Alternatively, in a P-type transistor, the higher potential of the source and the drain is compared, and the source is used. The N-type transistor is disposed at a lower potential side than thelight emitting element 20. On the other hand, the P-type transistor is disposed on the higher potential side than the light-emittingelement 20. By disposing the N-type transistor and the P-type transistor in the light-emittingelement 20 in this manner, each transistor can be operated substantially linearly (hereinafter, simply referred to as linear operation).

The polarity of the 1st transistor 31 and the 4th transistor 34 is preferably reversed. Inembodiment 1, the 1st transistor 31 is of an N type, the 4th transistor 34 is of a P type, the 1st transistor 31 of the N type is disposed on a lower potential side than thelight emitting element 20, and the 4th transistor 34 of the P type is disposed on a higher potential side than thelight emitting element 20. Therefore, the 1st transistor 31 and the 4th transistor 34 can be operated linearly, and variations in threshold voltages of the 1st transistor 31 and the 4th transistor 34 can be prevented from affecting the display characteristics (the light emission luminance of the light emitting element 20).

Further, since the source of the 1st transistor 31 is electrically connected to the 2 nd potential line (low potential line 46) and the source of the 4th transistor 34 is electrically connected to the 3 rd potential line (2 nd high potential line 49), the source potential of the 1st transistor 31 is fixed to the 2 nd potential and the source potential of the 4th transistor 34 is fixed to the 3 rd potential. Thus, even if the source-drain voltages of the 1st transistor 31 and the 4th transistor 34 are small, the conductivities of the 1st transistor 31 and the 4th transistor 34 in the on state can be increased. As a result, most of the potential difference between the 3 rd potential (VDD2) and the 2 nd potential (VSS) is applied to the light-emittingelement 20, and therefore, the influence of the variation in the threshold voltage of the 1st transistor 31 and the 4th transistor 34 is less likely to be exerted, and the uniformity of the light-emitting luminance of the light-emittingelement 20 between the pixels 59 (sub-pixels 58) can be improved.

The 2nd transistor 32 is arranged between the memory circuit 60 (theinput terminal 28 of the 2nd inverter 62 is equal to theoutput terminal 25 of the 1 st inverter 61) and thesignal line 43. One of a source and a drain of the N-type 2nd transistor 32 is electrically connected to thesignal line 43, and the other is electrically connected to the gate of the 6th transistor 36 and the 7 th transistor 37 (drains of the 3 rd transistor 33 and the 5 th transistor 35), which is the memory circuit 60 (theinput terminal 28 of the 2 nd inverter 62). The gate of the 2nd transistor 32 is electrically connected to thescan line 42.

The complementary 2nd transistor 38 is arranged between the memory circuit 60 (theinput terminal 26 of the 1st inverter 61 is theoutput terminal 27 of the 2 nd inverter 62) and thecomplementary signal line 45. One of the source and the drain of the N-type complementary 2nd transistor 38 is electrically connected to thecomplementary signal line 45, and the other is electrically connected to the memory circuit 60 (theinput terminal 26 of the 1 st inverter 61), that is, the gates of the 3 rd transistor 33 and the 5 th transistor 35 (the drains of the 6th transistor 36 and the 7 th transistor 37). The gate of the complementary 2nd transistor 38 is electrically connected to thescan line 42.

The electro-optical device 10 of the present embodiment includes a plurality ofcomplementary signal lines 45 in the display region E (see fig. 5). The 1pixel circuit 41 corresponds to 1signal line 43 and 1complementary signal line 45. Signals complementary to each other are supplied to thesignal line 43 for 1pixel circuit 41 and thecomplementary signal line 45 paired therewith. That is, a signal (hereinafter, referred to as an inverted signal) obtained by inverting the polarity of the signal supplied to thesignal line 43 is supplied to thecomplementary signal line 45. For example, when "high" is supplied to thesignal line 43, "low" is supplied to thecomplementary signal line 45 paired therewith. When thesignal line 43 is supplied with "low", thecomplementary signal line 45 paired with thesignal line 43 is supplied with "high".

The 2nd transistor 32 and the complementary 2nd transistor 38 are selection transistors for thepixel circuit 41. The gate of the 2nd transistor 32 and the gate of the complementary 2nd transistor 38 are electrically connected to thescan line 42. The 2nd transistor 32 and the complementary 2nd transistor 38 simultaneously switch an on state and an off state in accordance with a scanning signal (a selection signal or a non-selection signal) supplied to thescanning line 42.

When the selection signal is supplied as the scanning signal to thescanning line 42, the 2nd transistor 32 and the complementary 2nd transistor 38 are selected to be both in the on state. Then, thesignal line 43 and theoutput terminal 28 of the 2nd inverter 62 of thememory circuit 60 are turned on, and thecomplementary signal line 45 and theoutput terminal 26 of the 1st inverter 61 of thememory circuit 60 are turned on.

Thereby, the digital image signal is written from thesignal line 43 to theinput terminal 28 of the 2nd inverter 62 via the 2nd transistor 32. Further, an inverted signal of the digital image signal (digital complementary image signal) is written from thecomplementary signal line 45 to theinput terminal 26 of the 1st inverter 61 via the complementary 2nd transistor 38. As a result, the digital image signal and the digital complementary image signal are stored in thestorage circuit 60.

The digital image signal and the digital complementary image signal stored in thememory circuit 60 are kept in a stable state until the 2nd transistor 32 and the complementary 2nd transistor 38 are selected to be turned on next, and the digital image signal and the digital complementary image signal are rewritten from thesignal line 43 and thecomplementary signal line 45.

It is preferable that the polarity, size (gate length and gate width), driving conditions (potential when the scanning signal is the selection signal), and the like of each transistor be determined so that the on-resistance of the 2nd transistor 32 is lower than the on-resistance of the 3 rd transistor 33 or the on-resistance of the 5 th transistor 35. Similarly, the polarity, size, driving conditions, and the like of each transistor are preferably determined so that the on-resistance of the complementary 2nd transistor 38 is lower than the on-resistance of the 6th transistor 36 or the 7 th transistor 37. This enables the signal stored in thememory circuit 60 to be quickly and reliably rewritten.

The electro-optical device 10 of the present embodiment includes a plurality ofcontrol lines 44 in the display region E.A control line 44 is electrically connected to the gate of the 4th transistor 34. The 4th transistor 34 as a control transistor for thelight emitting element 20 switches an on state and an off state in accordance with a control signal (an activation signal or a non-activation signal) supplied to thecontrol line 44.

When thecontrol line 44 is supplied with the activation signal as the control signal, the 4th transistor 34 is turned on. When the 4th transistor 34 is in an on state, the light-emittingelement 20 can emit light. On the other hand, when thecontrol line 44 is supplied with the inactive signal as the control signal, the 4th transistor 34 is turned off, and thelight emitting element 20 does not emit light. When the 4th transistor 34 is off, thememory circuit 60 can rewrite the stored image signal without malfunctioning. This point will be explained below.

In this embodiment, since thecontrol line 44 and thescanning line 42 are independent of each other for eachpixel circuit 41, the 2nd transistor 32 and the 4th transistor 34 operate in a state independent of each other. As a result, when the 2nd transistor 32 is turned on, the 4th transistor 34 needs to be turned off.

That is, when writing the image signal into thememory circuit 60, after the 4th transistor 34 is turned off, the 2nd transistor 32 and the complementary 2nd transistor 38 are turned on, and the image signal and the inversion signal of the image signal are supplied to thememory circuit 60. Since the 4th transistor 34 is turned off when the 2nd transistor 32 is turned on, the light-emittingelement 20 does not emit light while the image signal is written into thememory circuit 60. This enables accurate expression of the gradation by time division.

Then, when the light-emittingelement 20 emits light, the 2nd transistor 32 and the complementary 2nd transistor 38 are turned off, and then the 4th transistor 34 is turned on. At this time, when the 1st transistor 31 is turned on, a path from the 3 rd potential line (the 2 nd high potential line 49) to the 2 nd potential line (the low potential line 46) via the 4th transistor 34, thelight emitting element 20, and the 1st transistor 31 is turned on, and current flows through thelight emitting element 20.

Since the 2nd transistor 32 and the complementary 2nd transistor 38 are off when the 4th transistor 34 is on, the image signal and the inversion signal of the image signal are not supplied to thememory circuit 60 while the light-emittingelement 20 is emitting light. Thus, the image signal stored in thememory circuit 60 is not rewritten by mistake, and therefore, high-quality image display without display by mistake can be realized.

"relationship between each potential and threshold voltage of transistor"

As described above, in the present embodiment, the 1 st potential (VDD1) and the 2 nd potential (VSS) constitute a low-voltage system power supply, and the 3 rd potential (VDD2) and the 2 nd potential (VSS) constitute a high-voltage system power supply. With such a configuration, the electro-optical device 10 which operates at high speed and can obtain a bright display is realized. This point will be explained below.

In the following description, the 1 st potential is described as V1, the 2 nd potential as V2, and the 3 rd potential as V3. In the present embodiment, the potential difference (V1-V2-3.0V) between the 1 st potential (V1-3.0V, as an example) and the 2 nd potential (V2-0V, as an example) which is the voltage of the low-voltage system power supply is smaller than the potential difference (V3-V2-7.0V) between the 3 rd potential (V3-7.0V, as an example) and the 2 nd potential (V2-0V), as a voltage of the high-voltage system power supply (V1-V2< V3-V2).

When the potentials are set as described above, thedriver circuit 51 and thememory circuit 60 are operated by the low-voltage system power supply that supplies the 1 st potential and the 2 nd potential, and therefore, transistors constituting thedriver circuit 51 and thememory circuit 60 can be miniaturized to realize high-speed operation. On the other hand, since the light-emittingelement 20 is caused to emit light by the high-voltage system power supply that supplies the 3 rd potential and the 2 nd potential, the light-emitting luminance of the light-emittingelement 20 can be improved. That is, with the configuration of the present embodiment, it is possible to realize the electro-optical device 10 in which each circuit operates at high speed and thelight emitting element 20 emits light with high luminance to obtain bright display.

In general, a light-emitting element such as an organic EL element requires a high voltage (for example, 5V or more) to emit light. However, in the semiconductor device, when the power supply voltage is increased, the size (gate length L, gate width W) of the transistor must be increased to prevent erroneous operation, and therefore, the operation of the circuit is slowed down. On the other hand, when the power supply voltage is lowered to operate the circuit at high speed, the light emission luminance of the light emitting element is lowered. In short, in a configuration in which the power supply voltage for causing the light emitting element to emit light and the power supply voltage for causing the circuit to operate are the same as in the conventional case, it is difficult to achieve both high-luminance light emission of the light emitting element and high-speed operation of the circuit.

In contrast, in the present embodiment, a low-voltage system power supply and a high-voltage system power supply are provided as power supplies of the electro-optical device 10, and the power supply that operates thedrive circuit 51 and thememory circuit 60 is provided as the low-voltage system power supply. Thus, thedriver circuit 51 and thememory circuit 60 can be operated at high speed by driving the transistors constituting thedriver circuit 51 and thememory circuit 60 at a low voltage of V1 to V2 of about 3.0V, with the transistors having a size L of about 0.5 micrometers (μm) and smaller than the transistors L of the 1st transistor 31 and the 4th transistor 34 of about 0.75 micrometers (μm).

Further, since the light-emittingelement 20 is caused to emit light at a high voltage of 7.0V at V3 to V2 by the high-voltage system power supply, the light-emittingelement 20 can be caused to emit light at high luminance. As described later, by linearly operating the 1st transistor 31 and the 4th transistor 34 arranged in series with the light-emittingelement 20, most of the high voltage of V3-V2, which is 7.0V, can be applied to the light-emittingelement 20, and thus the luminance of the light-emittingelement 20 during light emission can be further improved.

In this embodiment, the threshold voltage (V) of the 1st transistor 31 as a driving transistor_th1) Is positive (0)<V_th1). When the image signal stored in thememory circuit 60 corresponds to non-light emission, the potential of theoutput terminal 27 of thememory circuit 60 is "low", that is, the 2 nd potential (V2). The source of the 1st transistor 31 is connected to the 2 nd potential line (low potential line 46), and therefore, the source potential and the gate potential of the 1st transistor 31 are both the 2 nd potential (V2), and therefore, the gate-source voltage V of the 1st transistor 31_gs1Is 0V.

Therefore, when the threshold voltage V of the 1st transistor 31 is set_th1(As an example, V_th10.36V) is positive (0)<V_th1) While, the gate-source voltage V of the 1st transistor 31 of N type_gs1Less than threshold voltage V_th1Therefore, the 1st transistor 31 is off. Thus, when the image signal does not emit light, the 1st transistor 31 can be reliably turned off.

In the present embodiment, the potential difference of the 1 st potential (V1) with reference to the 2 nd potential (V2) is larger than the threshold voltage V of the 1 st transistor 31_th1(V_th1<V1-V2). When the image signal stored in thememory circuit 60 corresponds to light emission, the potential of theoutput terminal 27 of thememory circuit 60 is "high". "high" is the 1 st potential (V1), and therefore, the gate-source voltage V of the 1st transistor 31_gs1A potential difference (V) between the 1 st potential (V1) and the 2 nd potential (V2)_gs1＝V1-V2＝3.0V-0V＝3.0V)。

When the potential difference (V1-V2) of the 1 st potential (V1) with respect to the 2 nd potential (V2) is greater than the threshold voltage V of the 1 st transistor 31 (3.0V)_th1(V_th1＝0.36V)(V_th1<V1-V2), when the potential of theoutput terminal 27 of thememory circuit 60 is "high", the gate-source voltage V of the N-type 1st transistor 31_gs1Greater than a threshold voltage V_th1Therefore, the 1st transistor 31 is turned on. Therefore, when the image signal emits light, the 1st transistor 31 can be reliably turned on.

When an inactive signal is supplied as a control signal from acontrol line 44 electrically connected to the gate, the 4th transistor 34 as a control transistor is turned off, and when an active signal is supplied, the 4th transistor 34 as a control transistor is turned on. In this embodiment (embodiment 1), since the 4th transistor 34 is of a P-type, the inactive signal is set to a high potential not lower than the 3 rd potential (V3), preferably the 3 rd potential (V3) as described above. The enable signal is set to a low potential of V3- (V1-V2) or less, preferably the 2 nd potential (V2).

When the inactive signal of the 3 rd potential (V3) is supplied from thecontrol line 44 to the gate of the 4th transistor 34, both the source potential and the gate potential of the 4th transistor 34 become the 3 rd potential (V3), and therefore, the gate-source voltage V of the 4th transistor 34 becomes the voltage V3_gs4Is 0V. Threshold voltage V of the 4th transistor 34 when P-type is adopted_th4(As an example, V_th4-0.36V), the gate-source voltage V of the 4th transistor 34 is set to_gs4Greater than a threshold voltage V_th4Therefore, the 4th transistor 34 is turned off. Therefore, when the control signal is the inactive signal, the 4th transistor 34 can be reliably turned off.

When an activation signal having a potential of V3- (V1-V2) or less, i.e., 7.0V- (3.0V-0V) ═ 4.0V or less, is supplied from thecontrol line 44, the gate-source voltage V of the 4th transistor 34 is equal to or lower than the gate-source voltage V_gs4The voltage is 4.0-7.0V-3.0V or less. Thus, the gate-source voltage V of the 4th transistor 34_gs4Substantially less than a threshold voltage V_th4Therefore, when the control signal is the activation signal, the 4th transistor 34 can be reliably turned on.

Further, the lower the potential of the activation signal, the gate-source voltage V of the 4th transistor 34_gs4The larger the increase. If the potential of the activation signal is set to the 2 nd potential (V2), the gate-source voltage V of the 4th transistor 34_gs4When the voltage becomes 0V to 7.0V — 7.0V, the on-resistance of the 4th transistor 34 in the on state decreases, and therefore, the influence of the variation in the threshold voltage of the 4th transistor 34 is not easily received when the light-emittingelement 20 emits light.

By setting the highest 3 rd potential (V3) among the existing 3 potentials (1 st potential, 2 nd potential, and 3 rd potential) as the potential of the inactive signal and the lowest 2 nd potential (V2) as the potential of the active signal, it is possible to set the potentials of the inactive signal and the active signal without setting a new potential (potential line). Further, since the absolute value of the gate-source voltage of the 4th transistor 34 can be sufficiently increased by the activation signal, the on-resistance of the 4th transistor 34 in the on state can be sufficiently reduced, and the influence of the variation in the threshold voltage of the 4th transistor 34 on the light emission luminance of the light emitting element can be substantially eliminated.

That is, with the configuration of the present embodiment, even if two types of electric systems, i.e., the low-voltage system power supply and the high-voltage system power supply, are used, the 1st transistor 31 and the 4th transistor 34 can be turned off to reliably stop light emission when the light-emittingelement 20 is to be caused to emit no light, and the 1st transistor 31 and the 4th transistor 34 can be turned on to reliably emit light when the light-emittingelement 20 is to be caused to emit light.

When a non-selection signal is supplied as a scanning signal from thescanning line 42 electrically connected to the gate, the 2nd transistor 32 as a selection transistor is turned off, and when a selection signal is supplied, the 2nd transistor 32 as a selection transistor is turned on. In the present embodiment, since the 2nd transistor 32 is of an N-type, the non-selection signal is set to a low potential not higher than the 2 nd potential (V2), preferably the 2 nd potential (V2) as described above. The selection signal is set to a high potential not lower than the 1 st potential (V1), preferably to the 3 rd potential (V3).

Preferably, the 1st transistor 31 and the 2nd transistor 32 have the same polarity. Inembodiment 1, the 1st transistor 31 and the 2nd transistor 32 are both N-type. Therefore, when the potential of the image signal supplied to the gate is "high", the 1st transistor 31 is turned on, and when the scanning signal supplied to the gate is a selection signal ("high"), the 2nd transistor 32 is turned on. The "high" of the image signal is the 1 st potential (V1), and the selection signal ("high") is set to the 1 st potential (V1) or higher, preferably the 3 rd potential (V3).

The potential of the selection signal is set to 3 rd potential (V3) and the memory circuit is set toThe case where the image signal of 60 is rewritten from "low" to "high" will be described. Before the image signal is rewritten, theinput terminal 28 of the 2 nd inverter 62 (i.e., theoutput terminal 25 of the 1 st inverter 61) electrically connected to one of the source and the drain of the 2nd transistor 32 is at the 2 nd potential (V2) of "low". When a selection signal of the 3 rd potential (V3) is supplied from thescanning line 42 to the gate of the 2nd transistor 32, the gate-source voltage V of the 2nd transistor 32_gs2V3-V2-7.0V-0V-7.0V, higher than the threshold voltage V of the 2 nd transistor 32_th2(As an example, V_th20.36V), the 2nd transistor 32 is turned on.

By writing the image signal of "high" (V1) from thesignal line 43 into thememory circuit 60, the potential of theoutput terminal 25 of the 1st inverter 61 gradually rises from "low" (V2) to "high" (V1), but accompanying this, the gate-source voltage V of the 2nd transistor 32_gs2Gradually decreases to V3-V1-7.0V-3.0V-4.0V. Even though the gate-source voltage V of the 2nd transistor 32_gs24.0V, the gate-source voltage V is the lowest_gs2Is also sufficiently higher than the threshold voltage V of the 2nd transistor 32_th2. Therefore, the on-resistance of the 2nd transistor 32 is maintained in a low state until the image signal is written into thememory circuit 60, and therefore, the image signal can be reliably written into thememory circuit 60.

Here, a case where the 2nd transistor 32 is a P-type transistor having characteristics opposite to those of the 1 st transistor 31 (referred to as a 2nd transistor 32A) is assumed. In this case, when the selection signal is "low", the 2nd transistor 32A is turned on. When the potential of the selection signal is set to the 2 nd potential (V2) and the image signal of thememory circuit 60 is rewritten from "high" to "low", the gate-source voltage V of the 2nd transistor 32A is set to the gate-source voltage V of the 2nd transistor 32A when the selection signal of the 2 nd potential (V2) is supplied from thescanning line 42_gs2V2-V1-0V-3.0V, which is lower than the threshold voltage V of the 2nd transistor 32A_th2(As an example, V_th2-0.36V), the 2nd transistor 32A is thus brought into an on state.

When the image signal of "low" (V2) is written from thesignal line 43 into thememory circuit 60, the potential of theinput terminal 28 of the 2nd inverter 62 gradually decreases from "high" (V1), and the 2 nd crystal is formedGate-source voltage V oftransistor 32A_gs2Gradually rises from-3.0V and reaches the threshold voltage V of the P-type 2nd transistor 32A before the potential of theinput terminal 28 becomes the 2 nd potential (V2)_th2The 2nd transistor 32A is turned off.

Before the 2nd transistor 32A is turned off, the gate-source voltage V is applied_gs2Rises to approach the threshold voltage V_th2Since the on-resistance of the 2nd transistor 32A increases, it takes time to rewrite the image signal in thememory circuit 60 or the rewriting fails. In order to avoid this problem, the potential of the selection signal may be set to a lower potential, but in this case, a potential line different from the conventional potential is also required.

As inembodiment 1, when the 1st transistor 31 and the 2nd transistor 32 are both of the same polarity of the N type, the potential of the selection signal is set to the 3 rd potential which is the highest between the 3 rd potential and the 1 st potential, and thus, the setting can be performed without providing a new potential line. Further, when the 2nd transistor 32 is turned on and an image signal is written into thememory circuit 60, the gate-source voltage V of the 2nd transistor 32 can be increased_gs2Therefore, even if the source potential rises due to writing of the image signal, the on-resistance of the 2nd transistor 32 can be maintained low. This enables writing and rewriting of the image signal to thememory circuit 60 to be performed reliably and at high speed.

From the above results, the preferred potentials (V1, V2, V3) and the threshold voltage (V) of the 1st transistor 31 in the present embodiment are summarized_th1) The relationship of (a) is represented by the followingformulae 2 and 3.

0<Vth1…(2)

V2+Vth1＜V1＜V3…(3)

"characteristics of transistor"

Next, characteristics of the transistor included in the electro-optical device 10 according to the present embodiment will be described. In the electro-optical device 10 of the present embodiment, the 1st transistor 31 and the 4th transistor 34 are arranged in series with thelight emitting element 20 between the 3 rd potential line (the 2 nd high potential line 49) and the 2 nd potential line (the low potential line 46) constituting the high voltage system power supply. The on-resistance of the 1st transistor 31 is preferably sufficiently lower than the on-resistance of thelight emitting element 20. Further, the on-resistance of the 4th transistor 34 is also preferably sufficiently lower than the on-resistance of thelight emitting element 20.

The sufficiently low level is a driving condition under which the 1st transistor 31 and the 4th transistor 34 perform a linear operation, and specifically indicates that the on-resistances of the 1st transistor 31 and the 4th transistor 34 are equal to or less than 1/100, preferably equal to or less than 1/1000 of the on-resistance of the light-emittingelement 20. Thus, when the light-emittingelement 20 emits light, the 1st transistor 31 and the 4th transistor 34 can be operated linearly.

As a result, most of the potential difference (in short, the potential difference between the 3 rd potential and the 2 nd potential which is the voltage of the high-voltage system power supply) generated in the 1st transistor 31, the 4th transistor 34, and the light-emittingelement 20 arranged in series is applied to the light-emittingelement 20, and therefore, when the light-emittingelement 20 emits light, the influence of the variation in the threshold voltages of the twotransistors 31, 34 is less likely to be received. That is, with such a configuration, since the influence of variations in the threshold voltages of the 1st transistor 31 and the 4th transistor 34 can be reduced, it is possible to realize image display with excellent uniformity while suppressing variations in brightness and variations in gradation between the pixels 59 (sub-pixels 58).

This is because, when the on-resistances of the 1st transistor 31 and the 4th transistor 34 are 1/100 or less of the on-resistance of the light-emittingelement 20, the light-emittingelement 20 receives 99% or more of the power supply voltage, and the potential difference between the twotransistors 31 and 34 is 1% or less. Since the potential difference between the twotransistors 31 and 34 is smaller than or equal to 1%, the influence of the variation in the threshold voltages of the twotransistors 31 and 34 on the light emission characteristics of the light-emittingelement 20 is reduced.

In this embodiment (embodiment 1), the series resistance of the 1st transistor 31 and the 4th transistor 34 is about 1/1000 of the on resistance of thelight emitting element 20. In this case, since the light-emittingelement 20 receives about 99.9% of the power supply voltage and the potential difference between the twotransistors 31 and 34 is about 0.1%, the influence of the variation in the threshold voltages of the twotransistors 31 and 34 on the light-emitting characteristics of the light-emittingelement 20 can be almost ignored.

The on-resistance of a transistor depends on the polarity, gate length, gate width, threshold voltage, gate insulating film thickness, and the like of the transistor. In this embodiment, the polarities, gate lengths, gate widths, threshold voltages, gate insulating film thicknesses, and the like of the twotransistors 31 and 34 are determined so that the on-resistances of the 1st transistor 31 and the 4th transistor 34 are sufficiently lower than the on-resistance of thelight emitting element 20. This point will be described below.

In this embodiment, the light-emittingelement 20 is an organic EL element, and transistors such as the 1st transistor 31 and the 4th transistor 34 are formed over theelement substrate 11 formed of a single crystal silicon substrate. The voltage-current characteristics of the light-emittingelement 20 are approximately represented by the following formula 4.

In formula 4, I_ELIs a current passing through thelight emitting element 20, V_ELIs a voltage, L, applied to thelight emitting element 20_ELIs a length in plan view, W, of thelight emitting element 20_ELIs a width of thelight emitting element 20 in a plan view, J₀Is a current density coefficient, V, of thelight emitting element 20_tmIs a temperature-dependent coefficient voltage (constant voltage at constant temperature) V of thelight emitting element 20₀Is a threshold voltage for light emission of thelight emitting element 20.

In addition, in use V_PVoltage, denoted by V, of the high-voltage system power supply_dsV represents the potential difference generated by the 1st transistor 31 and the 3 rd transistor 33_EL+V_ds＝V_P. In the present embodiment, L is_EL11 micrometers (μm),W_EL3 micrometers (μm), J₀1.449 milliamps per square centimeter (mA/cm)²)，V₀3.0 volts (V), V_tm0.541 volts (V).

On the other hand, when the 1st transistor 31, the 4th transistor 34, and the like are denoted as the ith transistor (I is 1 or 4), the drain current I thereof_dsiRepresented by the following formula 5.

In formula 5, W_iIs the gate width of the ith transistor, L_iIs the gate length of the ith transistor,. epsilon₀Dielectric constant of vacuum,. epsilon_oxIs the dielectric constant of the gate insulating film, t_oxiIs the thickness of the gate insulating film, μ_iIs the mobility of the ith transistor, V_gsiIs the gate voltage, V_dsiIs a drain voltage based on a potential difference caused by the ith transistor, V_thiIs the threshold voltage of the ith transistor.

In example 1, W₁1.0 micrometer (mum), W₄1.25 micrometers (. mu.m), L₁＝L₄0.75 micrometer (mum),t_ox20 nanometers (nm), μ₁240 square centimeters per volt second (cm)²/V·s)，μ₄150 square centimeters per volt second (cm)²/V·s)，V_th1＝0.36V，V_th4＝-0.36V、V_gs1＝V1-V2＝3.0V，V_gs4＝V2-V3＝-7V。

In addition, when the 1st transistor 31 and the 4th transistor 34 are operated linearly, the potential difference V between the twotransistors 31 and 34 is used_dsThe voltage-current characteristic of thelight emitting element 20 is V_dsThe vicinity of 0V is approximated by the following equation 6.

I_EL＝-kV_ds+I₀…(6)

In example 1, the coefficient k defined by formula 6 is 1.39 × 10^-6(Ω^-1)。I₀Is the voltage V of the power supply of the high-voltage system_PThe amount of current in the case where all of them are applied to thelight emitting element 20, I₀＝7.82×10^-7(A)。

Under such conditions, the voltage at which thelight emitting element 20 emits light is I according to formulas 4 and 6_EL＝I_dsThe voltage of (c). In the present embodiment, V_P＝V3-V2＝7V，V_ds1＝0.0053V，V_ds4＝0.0027V，V_EL＝6.9920V，I_EL＝I_ds1＝I_ds4＝7.672×10^-7A. And at this timeThe on-resistance of the transistor was 6.859 × 10³Omega, the on-resistance of the 4th transistor 34 is 3.491 x 10³Ω, and the on-resistance of the light-emittingelement 20 is 9.113 × 10⁶Ω。

Therefore, the on-resistance of the 1st transistor 31 is about 1/1300 lower than 1/1000 of the on-resistance of thelight emitting element 20, and the on-resistance of the 4th transistor 34 is about 1/2600 lower than 1/1000 of the on-resistance of thelight emitting element 20, and therefore, most of the voltage of the high-voltage system power supply can be applied to thelight emitting element 20.

Under these conditions, even if the threshold voltage of the transistor fluctuates by 30% or more (in example 1, V is set to be_th1、V_th4Varying between 0.29 and 0.53V), V_EL＝6.99V、I_EL＝I_ds1＝I_ds4＝7.67×10^-7A is also constant. In general, the threshold voltage of a transistor does not vary so much. Therefore, by setting the on-resistance of the 4th transistor 34 to about 1/1000 or less of the on-resistance of the light-emittingelement 20, the variation in the threshold voltage between the 1st transistor 31 and the 4th transistor 34 does not substantially affect the light-emission luminance of the light-emittingelement 20.

Approximately, by making formula 5 and formula 6 stand together, I_EL＝I_dsiAccordingly, the deviation of the threshold voltage of the ith transistor with respect to the current I can be expressed as the following expression 7_EL＝I_dsiThe influence of (c).

I₀Voltage V for high voltage system power supply_PSince the current is applied to all thelight emitting elements 20, it can be seen from equation 7 that thelight emitting elements 20 are set to the power supply voltage V_PEmitting light nearby by increasing V_gsi、Z_iAnd (4) finishing. In other words, the larger Z is_iThe light emission intensity of the light-emittingelement 20 is less susceptible to variations in the threshold voltage of the transistor.

In example 1, since it is as small as k/Z₁＝2.52×10^-2V、k/Z₄＝3.22×10^-2V, so the left 2 nd term of equation 7 is k/(Z) with respect to the 1 st transistor 31₁(V_gs1-V_th1) 0.01, and k/(Z) with respect to the 4 th transistor 34₄(V_gs4-V_th4) Not more than 0.005 but less than about 0.01 (1%). As a result, the current (light emission luminance) when thelight emitting element 20 emits light is hardly affected by the threshold voltages of the twotransistors 31 and 34. Namely, by making k/(Z)_i(V_gsi-V_thi) A value of less than about 0.01 (1%), and the threshold voltages (V) of the twotransistors 31 and 34 can be substantially excluded_th1、V_th4) With respect to the deviation of the light emission luminance of thelight emitting element 20.

In formula 7, k and Z_iIs defined by formula 5 and formula 6. In addition, the mobility μ of the P-type transistor_iSmaller than the N-type transistor, and therefore, the W (W in this embodiment) of the P-type transistor₃) W is larger than that of the N-type transistor (W in this embodiment mode)₁) Z of the 4th transistor 34 of the P type₄Z of the 1st transistor 31 of N type₁Are substantially identical.

To make thelight emitting element 20 at the power supply voltage V_PNear light emission, gate voltage V_gsiPreferably as large as possible. In this embodiment (embodiment 1), the potential of the control signal (activation signal) in the activated state is set to the 2 nd potential (V2) with respect to the 3 rd potential (V3) which is the source potential of the 4th transistor 34, whereby the gate-source voltage V of the 4th transistor 34 is increased_gs4。

In the electro-optical device 10 of the present embodiment, the 3 rd transistor 33 and the 5 th transistor 35 constituting the 1st inverter 61 included in thememory circuit 60, and the 6th transistor 36 and the 7 th transistor 37 constituting the 2nd inverter 62 are arranged between the 1 st potential line (the 1 st high potential line 47) and the 2 nd potential line (the low potential line 46) constituting the low-voltage system power supply.

Thesetransistors 33, 35, 36, and 37 flow a smaller amount of current than the 1st transistor 31 and the 4th transistor 34 which operate by the high-voltage system power supply, and thus the area of the channel formation region can be reduced. That is, thememory circuit 60 can be miniaturized. When the area of the channel formation region of thetransistors 33, 35, 36, and 37 is small, the transistor capacitance is small, and thus high-speed charge and discharge can be performed. That is, writing and rewriting of the image signal to thememory circuit 60 can be speeded up.

In this embodiment, the gate length of the 3 rd transistor 33, the 5 th transistor 35, the 6th transistor 36, and the 7 th transistor 37 included in thememory circuit 60 in a plan view is shorter than the gate length of the 1st transistor 31 and the 4th transistor 34 arranged in series with the light-emittingelement 20 in a plan view.

The 3 rd transistor 33, the 5 th transistor 35, the 6th transistor 36, and the 7 th transistor 37 have gate lengths L in plan view₃＝L₅＝L₆＝L₇0.5 micrometers (μm). As described above, the gate length of the 1st transistor 31 and the 4th transistor 34 in plan view is L₁＝L₄0.75 micrometers (μm), therefore, the gate lengths of the 3 rd transistor 33, the 5 th transistor 35, the 6th transistor 36, and the 7 th transistor 37 are shorter.

In this embodiment, the area of the channel formation region in a plan view of the 3 rd transistor 33, the 5 th transistor 35, the 6th transistor 36, and the 7 th transistor 37 is smaller than the area of the channel formation region in a plan view of the 1st transistor 31 and the 4th transistor 34. The area of the channel formation region of the transistor is substantially equal to the area of the gate electrode disposed to face the channel formation region, that is, the product of the gate length and the gate width in a plan view.

The gate widths of the 3 rd transistor 33 and the 7 th transistor 37 of the N-type are W₃＝W₇0.5 micrometers (μm), the gate width of the 5 th transistor 35 and the 6th transistor 36 of the P type is W₅＝W₆0.75 micrometers (μm). Therefore, the channel formation regions of the 3 rd transistor 33 and the 7 th transistor 37 have an area of 0.5 × 0.5 — 0.25 micrometers (μm) per square²) The channel formation regions of the 5 th transistor 35 and the 6th transistor 36 have an area of 0.5 × 0.75 ═ 0.375 per square micrometer (μm)²)。

As described above, the 1st transistor 31 has the gate width W₁1.0 micrometers (μm), and thus, a channel of the 1st transistor 31 is formedThe area of the region was 0.75 × 1.0 ═ 0.75 per square micrometer (μm)²). In addition, the gate width of the 4th transistor 34 is W₄1.25 micrometers (μm), the area of the channel formation region of the 4th transistor 34 is, therefore, 0.75 × 1.25 — 0.9375 micrometers per square (μm)²). Therefore, the channel formation regions of the 3 rd transistor 33, the 5 th transistor 35, the 6th transistor 36, and the 7 th transistor 37 are smaller in area.

As described above, in the present embodiment, by making the area of the channel formation region of thetransistors 33, 35, 36, and 37 included in thememory circuit 60 smaller than the area of the channel formation region of thetransistors 31 and 34 arranged in series with the light-emittingelement 20, thememory circuit 60 can be miniaturized and operated at high speed, and the light-emittingelement 20 can emit light with high luminance.

Driving method of pixel circuit "

Next, a method of driving the pixel circuit in the electro-optical device 10 according to the present embodiment will be described with reference to fig. 9. Fig. 9 is a diagram illustrating a driving method of a pixel circuit according to this embodiment. In fig. 9, the horizontal axis represents a time axis, and the 1 st period (non-display period) and the 2 nd period (display period) are provided. The 1 st period corresponds to P1(P1-1 to P1-6) shown in FIG. 7. The 2 nd period corresponds to P2(P2-1 to P2-6) shown in FIG. 7.

In the vertical axis of fig. 9, Scan1 to Scan M indicate scanning signals supplied to thescanning lines 42 in the 1 st to M-th rows of the M scanning lines 42 (see fig. 5). The scan signal has a scan signal in a selected state (selection signal) and a scan signal in a non-selected state (non-selection signal). Enb indicates a control signal supplied to the control line 44 (see fig. 5). The control signal includes a control signal in an active state (active signal) and a control signal in an inactive state (inactive signal).

As described with reference to fig. 7, 1 field (F) for displaying one image is divided into a plurality of Subfields (SF), and each Subfield (SF) includes a 1 st period (non-display period) and a 2 nd period (display period) starting after the 1 st period ends. The 1 st period (non-display period) is a signal writing period in which an image signal is written into the memory circuit 60 (see fig. 8) of each pixel circuit 41 (see fig. 5) located in the display region E. The 2 nd period (display period) is a period in which the light-emitting element 20 (see fig. 8) can emit light in eachpixel circuit 41 located in the display region E.

As shown in fig. 9, in the electro-optical device 10 of the present embodiment, an inactive signal is supplied as a control signal to all thecontrol lines 44 in the 1 st period (non-display period). When thecontrol line 44 is supplied with the inactive signal, the 4 th transistor 34 (see fig. 8) is turned off, and therefore, the light-emittingelements 20 are not in a light-emitting state in all thepixel circuits 41 located in the display region E.

In the 1 st period, a selection signal is supplied as a scan signal to any one of thescan lines 42 in each Subfield (SF). When the selection signal is supplied to thescanning line 42, the 2nd transistor 32 and the complementary 2 nd transistor 38 (see fig. 8) are turned on in the selectedpixel circuit 41. Thus, in the selectedpixel circuit 41, an image signal is written from thesignal line 43 and the complementary signal line 45 (see fig. 8) to thememory circuit 60. In this way, the image signal is written into and stored in thememory circuit 60 of eachpixel circuit 41 in the 1 st period.

In the 2 nd period (display period), an activation signal is supplied as a control signal to all the control lines 44. When the activation signal is supplied to thecontrol line 44, the 4th transistor 34 is turned on, and therefore, the light-emittingelements 20 can emit light in all thepixel circuits 41 located in the display region E. In the 2 nd period, a non-selection signal for turning off the 2nd transistor 32 is supplied to all thescanning lines 42 as a scanning signal. Thus, in thememory circuit 60 of eachpixel circuit 41, the image signal written in the Subfield (SF) is held.

As described above, in this embodiment, since the 1 st period (non-display period) and the 2 nd period (display period) can be independently controlled, gradation display by digital time-division driving can be performed. As a result, the 2 nd period can be made shorter than the 1 st period, and thus, higher gradation display can be realized.

Further, since the control signal supplied to thecontrol line 44 can be shared among the plurality ofpixel circuits 41, driving of the electro-optical device 10 is facilitated. Specifically, in the case of digital driving without the 1 st period, a very complicated driving is required to make the light emission period shorter than one vertical period in which all thescanning lines 42 are selected. In contrast, in the present embodiment, since the control signal supplied to thecontrol line 44 is shared among the plurality ofpixel circuits 41, even if there is a Subfield (SF) whose light emission period is shorter than one vertical period in which all thescanning lines 42 are selected, the electro-optical device 10 can be easily driven by simply shortening the 2 nd period.

As described above, according to the configuration of thepixel circuit 41 of the present embodiment, the electro-optical device 10 can be realized which can display high-quality images with high resolution and multiple grayscales with low power consumption, and can operate at higher speed to obtain brighter display.

A modified example of the structure of the pixel circuit according toembodiment 1 will be described below. In the following description of the modification, points different fromembodiment 1 or the above-described modification are described, and the same reference numerals are given to the same components as those ofembodiment 1 or the above-described modification, and the description thereof is omitted. The driving method of the pixel circuit described above is the same as that ofembodiment 1, and the following modified example configuration can also obtain the same effects as those ofembodiment 1.

(modification 1)

"Structure of pixel Circuit"

First, a pixel circuit according tomodification 1 ofembodiment 1 will be described. Fig. 10 is a diagram illustrating the structure of a pixel circuit according tomodification 1. As shown in fig. 10, apixel circuit 41A according tomodification 1 is different from thepixel circuit 41 according toembodiment 1 in that the 4th transistor 34A is an N-type transistor and is disposed between the light-emittingelement 20 and the 1st transistor 31, and other configurations are the same.

Thepixel circuit 41A ofmodification 1 includes a light-emittingelement 20, a 1st transistor 31 of an N-type 4th transistor 34A, N, amemory circuit 60, a 2nd transistor 32 of an N-type, and a complementary 2nd transistor 38 of an N-type. Theanode 21 of the light-emittingelement 20 is electrically connected to the 3 rd potential line (2 nd high potential line 49), and thecathode 23 of the light-emittingelement 20 is electrically connected to the drain of the 4th transistor 34A.

The source of the 4th transistor 34A is electrically connected to the drain of the 1st transistor 31. The source of the 1st transistor 31 is electrically connected to the 2 nd potential line (low potential line 46). Therefore, in thepixel circuit 41A according tomodification 1, the 4th transistor 34A of the N-type is disposed at a position on the lower potential side than thelight emitting element 20, and the 1st transistor 31 of the N-type is disposed at a position on the lower potential side than the 4th transistor 34A.

Inmodification 1, since the 4th transistor 34A is of an N type, the inactive signal is set to a potential lower than the source potential of the 4th transistor 34A, preferably, the 2 nd potential (V2). Alternatively, the activation signal is set to a potential higher than the source potential of the 4th transistor 34A, preferably, the 3 rd potential (V3).

The 1st transistor 31 is disposed between the 4th transistor 34A and the 2 nd potential line (low potential line 46). Therefore, when the 1st transistor 31 is turned on and the 4th transistor 34A is also turned on, the source potential of the 4th transistor 34A is slightly higher than the 2 nd potential (V2). However, since the source potential of the 1st transistor 31 is fixed to the 2 nd potential (V2) and the 1st transistor 31 can be operated linearly, the source potential of the 4th transistor 34A can be made substantially equal to the 2 nd potential (V2).

When an inactive signal of the 2 nd potential (V2) is supplied from thecontrol line 44 to the 4th transistor 34A, the gate-source voltage V of the 4th transistor 34A_gs4Approximately 0V. Threshold voltage V of the 4th transistor 34A when the N-type is adopted_th4(As an example, V_th40.36V), the gate-source voltage V of the 4th transistor 34 is set to the value of_gs4Specific threshold voltage V_th4Therefore, the 4th transistor 34A is turned off. Therefore, when the control signal is the inactive signal, the 4th transistor 34A can be reliably turned off.

When the activation signal of the 3 rd potential (V3) is supplied from thecontrol line 44, the gate-source voltage V of the 4th transistor 34A_gs4The potential difference (V3-V2-7.0V-0V-7.0V) between the 3 rd potential (V3) and the 2 nd potential (V2) is substantially equal to each other. Thus, the gate-source voltage V of the 4th transistor 34A_gs4Substantially greater than a threshold voltage V_th4Thus, in the control signalWhen the signal is active, the 4th transistor 34A can be reliably turned on to perform a linear operation.

When the 1st transistor 31 and the 4th transistor 34A are turned on, a path from the 3 rd potential line (the 2 nd high potential line 49) to the 2 nd potential line (the low potential line 46) via the light-emittingelement 20, the 4th transistor 34A, and the 1st transistor 31 is turned on, and a current flows through the light-emittingelement 20. Further, since the 1st transistor 31 and the 4th transistor 34A can be operated linearly when the light-emittingelement 20 emits light, the transistors are less likely to be affected by variations in threshold voltages of thetransistors 31 and 34A. In addition, in thepixel circuit 41A according tomodification 1, most of the high voltage of V3 to V2 equal to 7.0V can be applied to the light-emittingelement 20, and thus the luminance of the light-emittingelement 20 during light emission can be improved.

(modification 2)

Next, a pixel circuit according tovariation 2 ofembodiment 1 will be described. Fig. 11 is a diagram illustrating a configuration of a pixel circuit according tomodification 2. As shown in fig. 11, apixel circuit 41B ofmodification 2 is different from thepixel circuit 41A ofmodification 1 in that the 1st transistor 31 is disposed between the light-emittingelement 20 and the 4th transistor 34A, and the other configurations are the same.

Apixel circuit 41B according tomodification 2 includes a light-emittingelement 20, an N-type 1st transistor 31, an N-type 4th transistor 34A, amemory circuit 60, an N-type 2nd transistor 32, and an N-type complementary 2nd transistor 38. Theanode 21 of the light-emittingelement 20 is electrically connected to the 3 rd potential line (2 nd high potential line 49), and thecathode 23 of the light-emittingelement 20 is electrically connected to the drain of the 1st transistor 31.

The source of the 1st transistor 31 is electrically connected to the drain of the 4th transistor 34A. The source of the 4th transistor 34A is electrically connected to the 2 nd potential line (low potential line 46). Therefore, in thepixel circuit 41B according tomodification 2, the 1st transistor 31 of the N-type is disposed at a position on the lower potential side than thelight emitting element 20, and the 4th transistor 34A of the N-type is disposed at a position on the lower potential side than the 1st transistor 31.

Inmodification 2, since the source of the 4th transistor 34A is electrically connected to the 2 nd potential line (low potential line 46), when the light-emittingelement 20 emits light,That is, when the activation signal of the 3 rd potential (V3) is supplied to thecontrol line 44, the gate-source voltage V of the 4th transistor 34A_gsA potential difference (V) based on the 2 nd potential (V2) to be the 3 rd potential (V3)_gs4V3-V2-7.0V). Therefore, the 4th transistor 34A can be reliably turned on to perform a linear operation.

Inmodification 2, since the 4th transistor 34A is disposed between the 1st transistor 31 and the 2 nd potential line (low potential line 46), when the 4th transistor 34A is turned on and the 1st transistor 31 is also turned on, the source potential of the 1st transistor 31 is higher than the 2 nd potential (V2). However, since the source potential of the 4th transistor 34A is fixed to the 2 nd potential (V2) and the 4th transistor 34A can be operated linearly, the source potential of the 1st transistor 31 can be made substantially equal to the 2 nd potential (V2).

Therefore, when the potential of theoutput terminal 27 of thememory circuit 60 is "high" (1 st potential), the gate-source voltage V of the 1st transistor 31_gs1Is substantially equal to the potential difference (V1-V2-3.0V) between the 1 st potential (V1) and the 2 nd potential (V2), and is larger than the threshold voltage (V) of the 1st transistor 31_th10.36V), the 1st transistor 31 can be reliably turned on to perform a linear operation.

In thepixel circuit 41B according tomodification 2, since the 1st transistor 31 and the 4th transistor 34A can be operated linearly when the light-emittingelement 20 emits light, the pixel circuit is less likely to be affected by variations in threshold voltages of the twotransistors 31 and 34A. In addition, since most of the high voltage of V3 to V2 equal to 7.0V can be applied to the light-emittingelement 20, the luminance of the light-emittingelement 20 during light emission can be improved.

(modification 3)

Next, a pixel circuit according tovariation 3 ofembodiment 1 will be described. Fig. 12 is a diagram illustrating a configuration of a pixel circuit according tomodification 3. As shown in fig. 12, apixel circuit 41C according tomodification 3 is different from those according toembodiment 1 and modifications in that the 4 th transistor 34 (or the 4th transistor 34A) is not provided, and the other configurations are the same.

Apixel circuit 41C according tomodification 3 includes a light-emittingelement 20, an N-type 1st transistor 31, amemory circuit 60, an N-type 2nd transistor 32, and an N-type complementary 2nd transistor 38. Theanode 21 of the light-emittingelement 20 is electrically connected to the 3 rd potential line (2 nd high potential line 49), and thecathode 23 of the light-emittingelement 20 is electrically connected to the drain of the 1st transistor 31. The source of the 1st transistor 31 is electrically connected to the 2 nd potential line (low potential line 46).

In thepixel circuit 41C ofmodification 3, thelight emitting element 20 and the 1st transistor 31 are arranged in series between the 3 rd potential line (the 2 nd high potential line 49) and the 2 nd potential line (the low potential line 46). When the potential of theoutput terminal 27 of thememory circuit 60 is "high" (1 st potential) and the 1st transistor 31 is turned on, the light-emittingelement 20 emits light. When the light-emittingelement 20 emits light, the source potential of the 1st transistor 31 is fixed to the 2 nd potential (V2), and the 1st transistor 31 can be operated linearly, so that the 1st transistor 31 is less susceptible to variations in threshold voltage. Accordingly, most of the high voltage of V3-V2 equal to 7.0V can be applied to the light-emittingelement 20, and thus the luminance of the light-emittingelement 20 during light emission can be improved.

In thepixel circuit 41C ofmodification 3, thecontrol line 44 is not necessary, and therefore, the number of wirings can be reduced, and therefore, the number of wiring layers can also be reduced. In general, when the number of wiring layers is large, each wiring layer is formed with an interlayer insulating layer interposed therebetween, which may increase the manufacturing workload of the electro-optical device (element substrate) and reduce the manufacturing yield. According to the configuration ofmodification 3, even if the number of wiring layers is small, image display by digital driving can be performed. Therefore, as compared with theabove embodiment 1 and the modification, the manufacturing workload can be reduced and the manufacturing yield can be improved. Further, the number of wirings having light-shielding properties is reduced, whereby the light-shielding region can be reduced, and high resolution (miniaturization of pixels) can be achieved.

(embodiment 2)

Next, the structure of the electro-optical device according toembodiment 2 will be described. The electro-optical device ofembodiment 2 is different from the electro-optical device 10 ofembodiment 1 in that the 1 st transistor and the 2 nd transistor are P-type, and the 2 nd potential (V2) is higher than the 1 st potential (V1) and the 3 rd potential (V3). Accordingly, the pixel circuit ofembodiment 2 also has a different structure from the pixel circuit ofembodiment 1. Fig. 13 is a circuit block diagram of an electro-optical device according toembodiment 2 of the present invention. Fig. 14 is a diagram illustrating the structure of a pixel according toembodiment 2 of the present invention. As shown in fig. 13 and 14, in the electro-optical device 10 of the present embodiment, the 1 st low potential VSS1, the 2 nd low potential VSS2, and the high potential VDD are supplied to the drivingsection 50, and the 1 st low potential VSS1, the 2 nd low potential VSS2, and the high potential VDD are supplied to thepixel circuit 71.

The following describes the structure of the pixel circuit according toembodiment 2, taking an example and a plurality of modifications as examples. In the following description of the examples and modifications, differences from example 1 or modification ofembodiment 1 will be described, and the same components as those of example 1 or modification ofembodiment 1 will be denoted by the same reference numerals in the drawings and their description will be omitted.

(example 2)

"Structure of pixel Circuit"

First, the structure of a pixel circuit in example 2 ofembodiment 2 will be described with reference to fig. 15. Fig. 15 is a diagram illustrating the structure of a pixel circuit ofembodiment 2. As shown in fig. 15, apixel circuit 71 ofembodiment 2 includes a 1st transistor 31A of a P type, alight emitting element 20, a 4th transistor 34A of an N type, amemory circuit 60, a 2nd transistor 32A of a P type, and a complementary 2nd transistor 38A of a P type.

In embodiment 2 (example 2 and the following modifications), the high potential and the low potential are switched from those ofembodiment 1. Specifically, the 1 st potential (V1) is the 1 st low potential VSS1 (e.g., V1-VSS 1-4.0V), the 2 nd potential (V2) is the high potential VDD (e.g., V2-VDD-7.0V), and the 3 rd potential (V3) is the 2 nd low potential VSS2 (e.g., V3-VSS 2-0V). Therefore, the 1 st potential is lower than the 2 nd potential, and the 3 rd potential is lower than the 1 st potential.

In the present embodiment, the 1 st potential (1 st low potential VSS1) and the 2 nd potential (high potential VDD) constitute a low-voltage system power supply, and the 3 rd potential (2 nd low potential VSS2) and the 2 nd potential (high potential VDD) constitute a high-voltage system power supply. The 2 nd potential is a potential that is a reference in the low-voltage system power supply and the high-voltage system power supply.

In embodiment 2 (embodiment 2 and the following modifications), the 1 st potential (VSS1) is supplied to eachpixel circuit 71 from the 1 st low-potential line 46 as the 1 st potential line, the 2 nd potential (VDD) is supplied to eachpixel circuit 71 from the 2 nd high-potential line 47 as the 2 nd potential line, and the 3 rd potential (VSS2) is supplied to eachpixel circuit 71 from the 2 nd low-potential line 48 as the 3 rd potential line.

Inembodiment 2, the 1st transistor 31A, thelight emitting element 20, and the 4th transistor 34A are arranged in series between the 2 nd potential line (the high potential line 47) and the 3 rd potential line (the 2 nd low potential line 48). As inembodiment 1, thememory circuit 60 is disposed between the 1 st potential line (the 1 st low potential line 46) and the 2 nd potential line (the high potential line 47). The 2nd transistor 32A is disposed between thememory circuit 60 and thesignal line 43. The complementary 2nd transistor 38A is arranged between thememory circuit 60 and thecomplementary signal line 45.

The gate of the 1st transistor 31A is electrically connected to theoutput terminal 27 of the 2nd inverter 62 of thememory circuit 60. The source of the 1st transistor 31A is electrically connected to the 2 nd potential line (high potential line 47). The drain of the 1st transistor 31A is electrically connected to theanode 21 of the light-emittingelement 20. The gate of the 4th transistor 34A is electrically connected to thecontrol line 44. The source of the 4th transistor 34A is electrically connected to the 3 rd potential line (2 nd low potential line 48). The drain of the 4th transistor 34A is electrically connected to thecathode 23 of the light-emittingelement 20.

In thepixel circuit 71 ofembodiment 2, the polarities of the 1st transistor 31A and the 4th transistor 34A are opposite. The 1st transistor 31A of the P-type is disposed on the higher potential side than thelight emitting element 20, and the 4th transistor 34A of the N-type is disposed on the lower potential side than thelight emitting element 20. When the 4th transistor 34A and the 1st transistor 31A are in an on state, the light-emittingelement 20 can emit light. When the 1st transistor 31A and the 4th transistor 34 are turned on, a path from the 2 nd potential line (the high potential line 47) to the 3 rd potential line (the 2 nd low potential line 48) via the 1st transistor 31A, the light-emittingelement 20, and the 4th transistor 34A is turned on, and a current flows through the light-emittingelement 20.

In embodiment 2 (embodiment 2 and the following modifications), when the potential of theoutput terminal 25 of the 1st inverter 61 of thememory circuit 60 is "high" (when the potential of theoutput terminal 27 of the 2nd inverter 62 is "low"), the light-emittingelement 20 is in a state of being able to emit light, and when the potential of theoutput terminal 25 of the 1st inverter 61 is "low" (when the potential of theoutput terminal 27 of the 2nd inverter 62 is "high"), the light-emittingelement 20 does not emit light.

"relationship between each potential and threshold voltage of transistor"

In embodiment 2 (example 2 and the following modifications), the low-voltage system power supply is also configured by the 1 st potential (V1) and the 2 nd potential (V2), and the high-voltage system power supply is configured by the 3 rd potential (V3) and the 2 nd potential (V2). The potential difference (V2-V1-7.0V-4.0V-3.0V) of the 2 nd potential (V2) with respect to the 1 st potential (V1) which is the voltage of the low-voltage system power supply is smaller than the potential difference (V2-V3-7.0V-0V-7.0V) of the 2 nd potential (V2) with respect to the 3 rd potential (V3) which is the voltage of the high-voltage system power supply (V2-V1< V2-V3).

Inembodiment 2, since thedrive circuit 51 and thememory circuit 60 are driven by the low-voltage system power supply at a low voltage of 3.0V from V2 to V1, thedrive circuit 51 and thememory circuit 60 can be operated at high speed. Further, since the light-emittingelement 20 is caused to emit light by the high-voltage system power supply at a high voltage of V2 to V3 equal to 7.0V, the light-emittingelement 20 can be caused to emit light at high luminance. Further, by linearly operating the 1st transistor 31A and the 4th transistor 34A which are arranged in series with the light-emittingelement 20, most of the high voltage of V2-V3, which is 7.0V, can be applied to the light-emittingelement 20, and therefore, the luminance when the light-emittingelement 20 emits light can be further improved.

Inembodiment 2, 2inverters 61 and 62 constituting amemory circuit 60 are arranged between a 1 st potential line (1 st low potential line 46) and a 2 nd potential line (high potential line 47), and VSS1 as a 1 st potential and VDD as a 2 nd potential are supplied to the 2inverters 61 and 62. Therefore, "low" corresponds to the 1 st potential (VSS1) and "high" corresponds to the 2 nd potential (VDD).

In this embodiment, the threshold voltage (V) of the 1st transistor 31A as the driving transistor_th1) Is negative (V)_th1<0). Stored in the memory circuit 60When the stored image signal corresponds to non-light emission, the potential of theoutput terminal 27 of thememory circuit 60 is "high" (2 nd potential). The source of the 1st transistor 31A is connected to the 2 nd potential line (high potential line 47), so that the source potential is the 2 nd potential (VDD), and the gate-source voltage V of the 1st transistor 31A_gs1Is 0V.

Therefore, when the gate-source voltage V is applied_gs1Relative to the threshold voltage V of the 1st transistor 31A_th1(As an example, V_th10.36V) is 0V, the gate source voltage V is_gs1Greater than a threshold voltage V_th1Therefore, the 1st transistor 31A is turned off. Thus, when the image signal does not emit light, the 1st transistor 31A can be reliably turned off.

When the image signal stored in thememory circuit 60 corresponds to light emission, the potential of theoutput terminal 27 of thememory circuit 60 is "low" (1 st potential). The source potential of the 1st transistor 31A is the 2 nd potential, and therefore, the gate-source voltage V of the 1st transistor 31A_gs1Is a potential difference (V) of the 1 st potential (V1) with respect to the 2 nd potential (V2)_gs1V1-V2-4.0V-7.0V-3.0V). Thus, the gate-source voltage V of the 1st transistor 31A_gs1Less than threshold voltage V_th1Therefore, the 1st transistor 31A is turned on. This makes it possible to reliably turn on the 1st transistor 31A when the image signal is emitted.

Inembodiment 2 as well, since the non-active signal is supplied as the control signal to all thecontrol lines 44 in the 1 st period (non-display period), the 4th transistor 34A is turned off, and thus the light-emittingelement 20 is turned off. When a selection signal is supplied to any one of thescanning lines 42 as a scanning signal in the 1 st period, the selected 2nd transistor 32A and the complementary 2nd transistor 38A are turned on, and an image signal is written from thesignal line 43 and thecomplementary signal line 45 to thememory circuit 60.

In the 2 nd period (display period), an activation signal is supplied as a control signal to all thecontrol lines 44, and the 4th transistor 34A is turned on, so that thelight emitting element 20 can emit light. In the 2 nd period, a non-selection signal for turning off the 2nd transistor 32A is supplied to all thescanning lines 42 as a scanning signal. As described above, inembodiment 2, since the 1 st period (non-display period) and the 2 nd period (display period) can be independently controlled, gradation display by digital time-division driving can be performed.

In embodiment 2 (embodiment 2), since the 4th transistor 34A is of an N-type, the control signal (active signal) in the active state is at a high potential, and the control signal (inactive signal) in the inactive state is at a low potential. Specifically, the inactive signal is set to a low potential of not more than the 3 rd potential (V3), preferably the 3 rd potential (V3). The activation signal is set to a high potential of V3+ (V2-V1) or higher, preferably the 2 nd potential (V2).

When the inactive signal of the 3 rd potential (V3) is supplied from thecontrol line 44 to the gate of the 4th transistor 34A, both the source potential and the gate potential of the 4th transistor 34A become the 3 rd potential (V3), and therefore, the gate-source voltage V of the 4th transistor 34A_gs4Becomes 0V. Threshold voltage V of the 4th transistor 34A when the N-type is adopted_th4(As an example, V_th40.36V), the gate-source voltage V of the 4th transistor 34A_gs4Specific threshold voltage V_th4Therefore, the 4th transistor 34A is turned off. Therefore, when the control signal is the inactive signal, the 4th transistor 34A can be reliably turned off.

When an activation signal having a potential of not less than V3+ (V2-V1), that is, not less than 0V + (7.0V-4.0V) ═ 3.0V is supplied from thecontrol line 44, the gate-source voltage V of the 4th transistor 34A is set to the source voltage V_gs4The voltage is 3.0-0V-3.0V or more. Thus, the gate-source voltage V of the 4th transistor 34A_gs4Substantially greater than a threshold voltage V_th4Therefore, when the control signal is the activation signal, the 4th transistor 34A can be reliably turned on.

Then, the gate-source voltage V of the 4th transistor 34A increases as the potential of the activation signal increases_gs4The larger the increase. If the potential of the activation signal is set to the 2 nd potential (V2), the gate-source voltage V of the 4th transistor 34A_gs4In order to turn V2 to V3 to 7.0V to 0V to 7.0V, the on-resistance of the 4th transistor 34A in the on state is decreased, and thus the light-emittingelement 20 is caused to emit lightWhen light is emitted, the 4th transistor 34A is less likely to be affected by variations in the threshold voltage.

When a non-selection signal is supplied as a scanning signal from thescanning line 42 electrically connected to the gate, the 2nd transistor 32A as a selection transistor is turned off, and when a selection signal is supplied, the 2nd transistor 32A as a selection transistor is turned on. Inembodiment 2, since the 2nd transistor 32A is P-type, the non-selection signal is set to a high potential not lower than the 2 nd potential (V2), preferably the 2 nd potential (V2) as described above. The selection signal is set to a low potential not higher than the 1 st potential (V1), preferably, to the 3 rd potential (V3).

Inembodiment 2, it is preferable that the 1st transistor 31A and the 2nd transistor 32A have the same polarity. Inembodiment 2, the 1st transistor 31A and the 2nd transistor 32A are both of a P type. Therefore, when the potential of the image signal supplied to the gate is "low", the 1st transistor 31A is turned on, and when the scan signal supplied to the gate is a selection signal ("low"), the 2nd transistor 32A is turned on. The "low" of the image signal is the 1 st potential (V1), but the selection signal ("low") is set to the 1 st potential (V1) or less, preferably the 3 rd potential (V3).

A case will be described in which the potential of the selection signal is set to the 3 rd potential (V3) and the image signal of thememory circuit 60 is rewritten from "high" to "low". Before the image signal is rewritten, theinput terminal 28 of the 2 nd inverter 62 (i.e., theoutput terminal 25 of the 1 st inverter 61) electrically connected to one of the source and the drain of the 2nd transistor 32A is at the 2 nd potential (V2) of "high". When a selection signal of the 3 rd potential (V3) is supplied from thescanning line 42 to the gate of the 2nd transistor 32A, the gate-source voltage V of the 2nd transistor 32A_gs2V3-V2 is 0V-7.0V, and is lower than the threshold voltage V of the 2nd transistor 32A_th2(As an example, V_th2-0.36V), the 2nd transistor 32A is thus brought into an on state.

By writing the image signal of "low" (V1) from thesignal line 43 into thememory circuit 60, the potential of theinput terminal 28 of the 2nd inverter 62 gradually decreases from "high" (V2) to "low" (V1), but accompanying this, the gate-source of the 2 nd transistor 32AVoltage V_gs2Gradually decreases to an absolute value of V3-V1-0V-4.0V. Even though the gate-source voltage V of the 2nd transistor 32A_gs2Becomes the highest (near zero) -4.0V, gate-source voltage V_gs2Is also higher than the threshold voltage V of the 2nd transistor 32A_th2Is sufficiently low. Therefore, the state in which the on-resistance of the 2nd transistor 32A is low is maintained until the image signal is written into thememory circuit 60, and therefore, the image signal can be reliably written into thememory circuit 60.

Here, assume that the 2nd transistor 32A is an N-type transistor (referred to as the 2 nd transistor 32) having a polarity opposite to that of the 1st transistor 31A. In this case, when the selection signal is "high", the 2nd transistor 32 is turned on. When the potential of the selection signal is set to the 2 nd potential (V2) and the image signal of thememory circuit 60 is rewritten from "low" to "high", the selection signal of the 2 nd potential (V2) is supplied from thescanning line 42, and the gate-source voltage V of the 2nd transistor 32 is set to the voltage V_gs2V2-V1-7.0V-4.0V-3.0V, higher than the threshold voltage V of the 2 nd transistor 32_th2(As an example, V_th20.36V), the 2nd transistor 32 is turned on.

When the high (V2) video signal is written from thesignal line 43 to thememory circuit 60, the potential of theinput terminal 28 of the 2nd inverter 62 gradually rises from low (V1), and the gate-source voltage V of the 2nd transistor 32 is increased accordingly_gs2Gradually decreases from 3.0V to reach the threshold voltage V of the N-type 2nd transistor 32 before the potential of theinput terminal 28 reaches the 2 nd potential (V2)_th2(e.g., 0.36V), the 2nd transistor 32 is turned off.

Before the 2nd transistor 32 is turned off, the gate-source voltage V is applied_gs2Drops to approach the threshold voltage V_th2Since the on-resistance of the 2nd transistor 32 increases, it takes time to rewrite the image signal in thememory circuit 60 or the rewriting fails. In order to avoid this problem, the potential of the selection signal may be set to a lower potential, but in this case, a potential line different from the conventional potential is also required.

When the 1st transistor 31A and the 2nd transistor 32A are both of the P type as in this embodiment modeWhen the polarity of the selection signal is the same as that of the first potential, the potential of the selection signal is set to the 3 rd potential which is the lowest potential between the 3 rd potential and the 2 nd potential, whereby the selection signal can be set without providing a new potential line. Further, when the 2nd transistor 32A is turned on and an image signal is written into thememory circuit 60, the gate-source voltage V of the 2nd transistor 32A can be increased_gs2Therefore, even if the source potential rises due to writing of the image signal, the on-resistance of the 2nd transistor 32A can be maintained low. This enables writing and rewriting of the image signal to thememory circuit 60 to be performed reliably and at high speed.

Therefore, according to the configuration of thepixel circuit 71 of example 2 ofembodiment 2, the electro-optical device 10 which can display high-quality images with high resolution and multiple gradations with low power consumption, can operate at higher speed, and can obtain brighter display can be realized.

A modified example of the structure of the pixel circuit according toembodiment 2 will be described below. In the following description of the modification, differences fromembodiment 2 or the above-described modification are described, and the same components as those ofembodiment 2 or the above-described modification are given the same reference numerals in the drawings, and the description thereof is omitted.

(modification 4)

Next, a pixel circuit according to a modification (modification 4) ofembodiment 2 will be described. Fig. 16 is a diagram illustrating the structure of a pixel circuit according to modification 4. As shown in fig. 16, apixel circuit 71A according to modification 4 is different from thepixel circuit 71 according toembodiment 2 in that the 4th transistor 34 is of a P-type and is disposed between the 1st transistor 31A and the light-emittingelement 20, and other configurations are the same.

Thepixel circuit 71A according to modification 4 includes the P-type 1st transistor 31A, P-type 4th transistor 34, the light-emittingelement 20, thememory circuit 60, the P-type 2nd transistor 32A, and the P-type complementary 2nd transistor 38A. The drain of the 1st transistor 31A is electrically connected to the source of the 4th transistor 34. The drain of the 4th transistor 34 is electrically connected to theanode 21 of the light-emittingelement 20. That is, in thepixel circuit 71A according to modification 4, the P-type 4th transistor 34 is disposed on the higher potential side than thelight emitting element 20, and the P-type 1st transistor 31A is disposed on the higher potential side than the 4th transistor 34.

In modification 4, since the 4th transistor 34 is P-type, the 2 nd potential (V2) at which the potential of the inactive signal is high and the 3 rd potential (V3) at which the potential of the active signal is low are set. When the activation signal is supplied to thecontrol line 44 and the gate potential of the 4th transistor 34 becomes the same potential as the 3 rd potential, the 4th transistor 34 becomes on. When the 1st transistor 31A and the 4th transistor 34 are turned on, a path from the 2 nd potential line (high potential line 47) to the 3 rd potential line (2 nd low potential line 48) via the 1st transistor 31A, the 4th transistor 34, and thelight emitting element 20 is turned on, and a current flows through thelight emitting element 20.

In modification 4, the 1st transistor 31A is disposed between the 4th transistor 34 and the 2 nd potential line (high potential line 47). Therefore, when the 4th transistor 34 is turned on, the source potential of the 4th transistor 34 is slightly lower than the 2 nd potential (V2). However, by linearly operating the 1st transistor 31A, the source potential of the 4th transistor 34 can be made substantially equal to the 2 nd potential.

Thus, the gate-source voltage V of the 4th transistor 34_gs4Is substantially equal to the potential difference (V3-V2-7.0V) between the 3 rd potential (V3) and the 2 nd potential (V2), and is lower than the threshold voltage V of the P-type 4 th transistor 34_th4(V_th4-0.36V), the 4th transistor 34 is reliably brought into an on state. The gate-source voltage V of the 4th transistor 34 in the on state_gs4Much less than the threshold voltage V_th4Therefore, the 4th transistor 34 can be operated linearly.

(modification 5)

Next, a pixel circuit according to a modification (modification 5) ofembodiment 2 will be described. Fig. 17 is a diagram illustrating a configuration of a pixel circuit according to modification 5. As shown in fig. 17, a pixel circuit 71B according to modification 5 is different from thepixel circuit 71A according to modification 4 in that a 1st transistor 31A is disposed between a 4th transistor 34 and a light-emittingelement 20, and the other configurations are the same.

A pixel circuit 71B according to modification 5 includes a P-type 4th transistor 34, a P-type 1st transistor 31A, a light-emittingelement 20, amemory circuit 60, a P-type 2nd transistor 32A, and a P-type complementary 2nd transistor 38A. The source of the 4th transistor 34 is electrically connected to the 2 nd potential line (high potential line 47). The source of the 1st transistor 31A is electrically connected to the drain of the 4th transistor 34, and the drain of the 1st transistor 31A is electrically connected to theanode 21 of the light-emittingelement 20. That is, in the pixel circuit 71B according to modification 5, the P-type 1st transistor 31A is disposed on the higher potential side than thelight emitting element 20, and the P-type 4th transistor 34 is disposed on the higher potential side than the 1st transistor 31A.

In modification 5, the 4th transistor 34 is disposed between the 1st transistor 31A and the 2 nd potential line (high potential line 47). Therefore, when the 1st transistor 31A is turned on, the source potential of the 1st transistor 31A is slightly lower than the 2 nd potential (V2). However, by linearly operating the 4th transistor 34, the source potential of the 1st transistor 31A can be made substantially equal to the 2 nd potential. Thus, the gate-source voltage V of the 1st transistor 31A_gs1Since the potential difference (V1-V2 — 3V) is substantially equal to the potential difference (V1-V2) between the 1 st potential (V1) and the 2 nd potential (V2), the 1st transistor 31A can be reliably turned on to perform a linear operation.

(modification 6)

Next, a pixel circuit according to a modification (modification 6) ofembodiment 2 will be described. Fig. 18 is a diagram illustrating a configuration of a pixel circuit according to modification 6. As shown in fig. 18, apixel circuit 71C according to modification 6 is different from those according toembodiment 2 and modifications in that it does not include the 4 th transistor 34 (or the 4th transistor 34A) and has the same configuration.

Thepixel circuit 71C according to modification 6 includes a light-emittingelement 20, a P-type 1st transistor 31A, amemory circuit 60, a P-type 2nd transistor 32A, and a P-type complementary 2nd transistor 38A. The source of the 1st transistor 31A is electrically connected to the 2 nd potential line (high potential line 47), and the drain of the 1st transistor 31A is electrically connected to theanode 21 of thelight emitting element 20. Thecathode 23 of the light-emittingelement 20 is electrically connected to a 3 rd potential line (2 nd low potential line 48).

In thepixel circuit 71C of modification 6, the 1st transistor 31A and the light-emittingelement 20 are arranged in series between the 2 nd potential line (high potential line 47) and the 3 rd potential line (2 nd low potential line 48). Thus, there is aWhen the potential of theoutput terminal 27 of thememory circuit 60 becomes "low" (1 st potential) and the 1st transistor 31A is in an on state, the light-emittingelement 20 emits light. In modification 6, as in the case ofembodiment 2 and modification, the luminance of the light-emittingelement 20 during light emission can be improved, and the threshold voltage V of the 1st transistor 31A can be substantially eliminated_th1With respect to the deviation of the light emission luminance of thelight emitting element 20.

In thepixel circuit 71C of modification 6, thecontrol line 44 is not necessary, and therefore, the number of wirings can be reduced, and therefore, the number of wiring layers can also be reduced. Therefore, the manufacturing workload can be reduced and the manufacturing yield can be improved as compared with the above-described embodiment and modification. Further, the number of wirings having light-shielding properties is reduced, whereby the light-shielding region can be reduced, and high resolution (miniaturization of pixels) can be achieved.

(embodiment 3)

Next, the structure of the electro-optical device according toembodiment 3 will be described. Fig. 19 is a circuit block diagram of an electro-optical device according toembodiment 3 of the present invention. Fig. 20 is a diagram illustrating the structure of a pixel according toembodiment 3 of the present invention. Fig. 21 is a diagram illustrating the structure of a pixel circuit according toembodiment 3 of the present invention.

As shown in fig. 19, in the present embodiment, the signalline drive circuit 53 supplies an image signal (Data) to each of theN signal lines 43 in synchronization with the selection of the scanning lines 42. However, in this embodiment, unlikeembodiments 1 and 2, the signalline drive circuit 53 does not output a complementary image signal. Therefore, as shown in fig. 20, the image signal (Data) is supplied to thepixel circuit 81, but the complementary image signal is not supplied. Therefore, as illustrated in fig. 21, in thepixel circuit 81, for example, the passage of current to thelight emitting element 20 is controlled by the 1st transistor 31A of the P type which supplies an image signal (Data) to the gate via the 2nd transistor 32A and thememory circuit 60, and the 4th transistor 34 of the P type which supplies the control signal Enb to the gate.

In the present embodiment, the configuration is based onembodiment 2 in which the 1 st low potential VSS1, the 2 nd low potential VSS2, and the high potential VDD are supplied to the drivingunit 50, but the configuration may be based onembodiment 1 in which the 1 st high potential VDD1, the 2 nd high potential VDD2, and the low potential VSS are supplied to the drivingunit 50.

The above-described embodiment (examples and modifications) is merely one embodiment of the present invention, and any modifications and applications can be made within the scope of the present invention. As another modification, for example, the following modifications are conceivable.

(modification 7)

In the pixel circuit of the above-described embodiment (example and modification), the gate of the 1 st transistor 31 (or the 1st transistor 31A) is electrically connected to theoutput terminal 27 of the 2nd inverter 62 of thememory circuit 60, but the present invention is not limited to this embodiment. The gate of the 1 st transistor 31 (or the 1st transistor 31A) may be electrically connected to theoutput terminal 25 of the 1st inverter 61 of thememory circuit 60.

(modification 8)

In the pixel circuit of the above-described embodiment (example and modification), the 2nd transistor 32 is disposed between theinput terminal 28 of the 2 nd inverter 62 (i.e., theoutput terminal 25 of the 1 st inverter 61) of thememory circuit 60 and thesignal line 43, and the complementary 2nd transistor 38 is disposed between theinput terminal 26 of the 1 st inverter 61 (i.e., theoutput terminal 27 of the 2 nd inverter 62) of thememory circuit 60 and thecomplementary signal line 45, but the present invention is not limited to such an embodiment. The 2nd transistor 32 may be disposed between theinput terminal 26 of the 1 st inverter 61 (i.e., theoutput terminal 27 of the 2 nd inverter 62) and thesignal line 43, and the complementary 2nd transistor 38 may be disposed between theinput terminal 28 of the 2 nd inverter 62 (i.e., theoutput terminal 25 of the 1 st inverter 61) and thecomplementary signal line 45.

(modification 9)

In the pixel circuit of the above-described embodiment (example and modification), thememory circuit 60 includes 2inverters 61 and 62, but the present invention is not limited to such an embodiment. Thememory circuit 60 may be configured to include an even number of inverters of 2 or more.

(modification 10)

In the above-described embodiments (examples and modifications), the description has been given of the organic EL device in which the light-emittingelements 20 made of organic EL elements are arranged in 720 rows × 3840(1280 × 3) columns on theelement substrate 11 made of a single crystal semiconductor substrate (single crystal silicon substrate) as an electro-optical device, but the electro-optical device of the present invention is not limited to such an embodiment. For example, the electro-optical device may have a structure in which Thin Film Transistors (TFTs) are formed on anelement substrate 11 made of a glass substrate, or may have a structure in which Thin Film transistors are formed on a flexible substrate made of polyimide or the like. The electro-optical device may be a micro LED display in which fine LED elements are arranged at a high density as light emitting elements, or a Quantum dot (Quantum Dots) display in which a semiconductor crystal substance having a nano size is used for the light emitting elements. In addition, quantum dots that convert incident light into light of other wavelengths may be used as the color filter.

(modification 11)

In the above-described embodiment, the see-through type head mounteddisplay 100 incorporating the electro-optical device 10 is described as an example of an electronic apparatus, but the electro-optical device 10 of the present invention may be applied to other electronic apparatuses typified by a closed type head mounted display. Examples of the other electronic devices include projectors, rear-projection televisions, direct-view televisions, cellular phones, portable audio devices, personal computers, monitors for video cameras, car navigation devices, head-up displays, pagers, electronic organizers, wearable devices such as calculators and watches, hand-held displays, word processors, workstations, video phones, POS terminals, digital still cameras, signage displays, and the like.

Claims (18)

Translated fromChinese

1.一种电光装置，其特征在于，1. An electro-optical device, characterized in that,该电光装置具有：扫描线；信号线；控制线；像素电路，其与所述扫描线和所述信号线的交叉处对应地设置；第1电位线，其被供给第1电位；第2电位线，其被供给第2电位；以及第3电位线，其被供给第3电位，The electro-optical device includes: a scanning line; a signal line; a control line; a pixel circuit provided corresponding to the intersection of the scanning line and the signal line; a first potential line to which a first potential is supplied; and a second potential line to which the second potential is supplied; and a third potential line to which the third potential is supplied,所述像素电路包含：发光元件；存储电路，其配置在所述第1电位线与所述第2电位线之间；第1晶体管，其栅极与所述存储电路电连接；以及第2晶体管，其栅极与所述扫描线电连接；以及第4晶体管，其栅极与所述控制线电连接，The pixel circuit includes: a light-emitting element; a storage circuit arranged between the first potential line and the second potential line; a first transistor whose gate is electrically connected to the storage circuit; and a second transistor , the gate of which is electrically connected to the scan line; and the fourth transistor, the gate of which is electrically connected to the control line,所述第2晶体管配置在所述存储电路与所述信号线之间，The second transistor is arranged between the memory circuit and the signal line,所述发光元件、所述第1晶体管、所述第4晶体管串联地配置在所述第2电位线与所述第3电位线之间，The light-emitting element, the first transistor, and the fourth transistor are arranged in series between the second potential line and the third potential line,所述第1电位相对于所述第2电位的电位差的绝对值小于所述第3电位相对于所述第2电位的电位差的绝对值，the absolute value of the potential difference between the first potential and the second potential is smaller than the absolute value of the potential difference between the third potential and the second potential,在所述扫描线中的任意一个被供给使所述第2晶体管成为导通状态的选择信号的第1期间，所述控制线被供给使所述第4晶体管成为截止状态的非激活信号，During a first period in which a selection signal for turning on the second transistor is supplied to any one of the scanning lines, an inactive signal for turning off the fourth transistor is supplied to the control line,在所述控制线被供给使所述第4晶体管成为导通状态的激活信号的第2期间，所述扫描线被供给使所述第2晶体管成为截止状态的非选择信号，During the second period in which the activation signal for turning on the fourth transistor is supplied to the control line, the scanning line is supplied with a non-selection signal for turning off the second transistor,所述第1晶体管为N型，所述第4晶体管为P型，The first transistor is N-type, the fourth transistor is P-type,在设所述第1电位为V1、所述第2电位为V2、所述第3电位为V3时，供给到所述控制线的所述激活信号的电位为V3-(V1-V2)以下。When the first potential is V1, the second potential is V2, and the third potential is V3, the potential of the activation signal supplied to the control line is V3-(V1-V2) or less.2.根据权利要求1所述的电光装置，其特征在于，2. The electro-optical device according to claim 1, characterized in that,所述存储电路包含第3晶体管，The storage circuit includes a third transistor,所述第3晶体管的栅极长度比所述第1晶体管的栅极长度短。The gate length of the third transistor is shorter than the gate length of the first transistor.3.根据权利要求2所述的电光装置，其特征在于，3. The electro-optical device according to claim 2, characterized in that,所述第3晶体管的沟道形成区域的面积比所述第1晶体管的沟道形成区域的面积小。The area of the channel formation region of the third transistor is smaller than the area of the channel formation region of the first transistor.4.根据权利要求1所述的电光装置，其特征在于，4. The electro-optical device according to claim 1, characterized in that,所述第1晶体管的源极与所述第2电位线电连接，The source of the first transistor is electrically connected to the second potential line,所述发光元件配置在所述第1晶体管的漏极与所述第3电位线之间。The light-emitting element is arranged between the drain of the first transistor and the third potential line.5.根据权利要求1所述的电光装置，其特征在于，5. The electro-optical device according to claim 1, wherein,所述第1晶体管的导通电阻低于所述发光元件的导通电阻。The on-resistance of the first transistor is lower than the on-resistance of the light-emitting element.6.根据权利要求1所述的电光装置，其特征在于，6. The electro-optical device according to claim 1, wherein,所述第1晶体管和所述第2晶体管的极性相同。The polarities of the first transistor and the second transistor are the same.7.根据权利要求1所述的电光装置，其特征在于，7. The electro-optical device according to claim 1, wherein,所述第4晶体管的漏极与所述发光元件电连接。The drain of the fourth transistor is electrically connected to the light-emitting element.8.根据权利要求1所述的电光装置，其特征在于，8. The electro-optical device according to claim 1, wherein,所述第4晶体管的导通电阻低于所述发光元件的导通电阻。The on-resistance of the fourth transistor is lower than the on-resistance of the light-emitting element.9.根据权利要求1所述的电光装置，其特征在于，9. The electro-optical device of claim 1, wherein:所述第1晶体管和所述第4晶体管的极性相反。The polarities of the first transistor and the fourth transistor are opposite.10.根据权利要求1所述的电光装置，其特征在于，10. The electro-optical device according to claim 1, wherein,在所述第2晶体管为导通状态时，所述第4晶体管为截止状态。When the second transistor is in an on state, the fourth transistor is in an off state.11.根据权利要求1所述的电光装置，其特征在于，11. The electro-optical device according to claim 1, wherein,所述激活信号的电位是所述第2电位。The potential of the activation signal is the second potential.12.根据权利要求1所述的电光装置，其特征在于，12. The electro-optical device of claim 1, wherein所述第1晶体管和所述第2晶体管为N型，The first transistor and the second transistor are N-type,供给到所述扫描线的所述选择信号的电位为所述第1电位以上。The potential of the selection signal supplied to the scanning line is equal to or higher than the first potential.13.根据权利要求12所述的电光装置，其特征在于，13. The electro-optical device of claim 12, wherein所述选择信号的电位是所述第3电位。The potential of the selection signal is the third potential.14.一种电光装置，其特征在于，14. An electro-optical device, characterized in that:该电光装置具有：扫描线；信号线；控制线；像素电路，其与所述扫描线和所述信号线的交叉处对应地设置；第1电位线，其被供给第1电位；第2电位线，其被供给第2电位；以及第3电位线，其被供给第3电位，The electro-optical device includes: a scanning line; a signal line; a control line; a pixel circuit provided corresponding to the intersection of the scanning line and the signal line; a first potential line to which a first potential is supplied; and a second potential line to which the second potential is supplied; and a third potential line to which the third potential is supplied,所述像素电路包含：发光元件；存储电路，其配置在所述第1电位线与所述第2电位线之间；第1晶体管，其栅极与所述存储电路电连接；以及第2晶体管，其栅极与所述扫描线电连接；以及第4晶体管，其栅极与所述控制线电连接，The pixel circuit includes: a light-emitting element; a storage circuit arranged between the first potential line and the second potential line; a first transistor whose gate is electrically connected to the storage circuit; and a second transistor , the gate of which is electrically connected to the scan line; and the fourth transistor, the gate of which is electrically connected to the control line,所述第2晶体管配置在所述存储电路与所述信号线之间，The second transistor is arranged between the memory circuit and the signal line,所述发光元件、所述第1晶体管、所述第4晶体管串联地配置在所述第2电位线与所述第3电位线之间，The light-emitting element, the first transistor, and the fourth transistor are arranged in series between the second potential line and the third potential line,所述第1电位相对于所述第2电位的电位差的绝对值小于所述第3电位相对于所述第2电位的电位差的绝对值，the absolute value of the potential difference between the first potential and the second potential is smaller than the absolute value of the potential difference between the third potential and the second potential,在所述扫描线中的任意一个被供给使所述第2晶体管成为导通状态的选择信号的第1期间，所述控制线被供给使所述第4晶体管成为截止状态的非激活信号，During a first period in which a selection signal for turning on the second transistor is supplied to any one of the scanning lines, an inactive signal for turning off the fourth transistor is supplied to the control line,在所述控制线被供给使所述第4晶体管成为导通状态的激活信号的第2期间，所述扫描线被供给使所述第2晶体管成为截止状态的非选择信号，During the second period in which the activation signal for turning on the fourth transistor is supplied to the control line, the scanning line is supplied with a non-selection signal for turning off the second transistor,所述第1晶体管为P型，所述第4晶体管为N型，The first transistor is P-type, the fourth transistor is N-type,在设所述第1电位为V1、所述第2电位为V2、所述第3电位为V3时，When the first potential is V1, the second potential is V2, and the third potential is V3,供给到所述控制线的所述激活信号的电位为V3+(V2-V1)以上。The potential of the activation signal supplied to the control line is equal to or higher than V3+(V2-V1).15.根据权利要求14所述的电光装置，其特征在于，15. The electro-optical device of claim 14, wherein所述激活信号的电位是所述第2电位。The potential of the activation signal is the second potential.16.根据权利要求14所述的电光装置，其特征在于，16. The electro-optical device of claim 14, wherein所述第1晶体管和所述第2晶体管为P型，The first transistor and the second transistor are P-type,供给到所述扫描线的所述选择信号的电位为所述第1电位以下。The potential of the selection signal supplied to the scanning line is equal to or lower than the first potential.17.根据权利要求16所述的电光装置，其特征在于，17. The electro-optical device of claim 16, wherein所述选择信号的电位是所述第3电位。The potential of the selection signal is the third potential.18.一种电子设备，其特征在于，18. An electronic device, characterized in that,所述电子设备具有权利要求1所述的电光装置。The electronic device has the electro-optical device of claim 1 .

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