Summary of the invention
The technical problem to be solved by the invention is to provide a kind of transistors and forming method thereof, reduce the body of transistorEffect.
The present invention provides a kind of transistor, comprising: substrate is formed with active area in the substrate and surrounds the active areaIsolated area；The active area includes channel region and source region and the drain region for being located at the channel region two sides；Gate dielectric layer, positionIn the channel region surface；Electrode layer, gate extension and the covering gate medium including being located at the isolated area surfaceLayer surface and the gate portion being connect with the gate extension.
Optionally, the gate extension is located at at least side in the channel region length direction；The gate portion is along ditchAt least one end in road sector width direction is connect with the gate extension.
Optionally, the electrode layer is H-shaped or T shape.
Optionally, the area of the gate extension is greater than or equal to the area of the channel region.
Optionally, the length of the gate extension is equal to or less than the length of the active area.
Optionally, the material of the electrode layer is polysilicon or metal.
Technical solution of the present invention also provides a kind of forming method of transistor, comprising: provides substrate, shape in the substrateAt the isolated area for having active area and the encirclement active area；Channel region is formed in the active area and is located at the channelThe source region of area two sides and drain region；Form the gate dielectric layer for being located at the channel region surface；Form electrode layer, including be located at it is described everyGate extension from area surface and covering the gate dielectric layer surface and the gate portion that is connect with the gate extension.
Optionally, it is initially formed the electrode layer in the substrate surface, the active area below the gate portion of the electrode layerAs the channel region；Then, then in the active area of the gate portion two sides it is respectively formed the source region and the drain region.
Optionally, the gate extension is located at at least side in the channel region length direction；The gate portion is along ditchAt least one end in road sector width direction is connect with the gate extension.
Optionally, the electrode layer is H-shaped or T shape.
Optionally, the area of the gate extension is greater than or equal to the area of the channel region.
Optionally, the length of the gate extension is equal to or less than the length of the active area.
Optionally, the material of the electrode layer is polysilicon or metal.
Optionally, the gate extension of the electrode layer and gate portion are formed simultaneously.
Technical solution of the present invention also provides a kind of memory, comprising: transistor described in any of the above embodiments.
The gate portion of transistor of the invention is connected to gate extension, the gate extension be located at outside active area everyFrom in area, while applying grid voltage to gate portion, charge on the gate extension can under the isolated areaThe depletion region charge balance of side, the voltage without increasing in the gate portion therefore will not be because of the consumption below isolated areaMost area leads to the drift of transistor threshold voltage, substantially reduces the bulk effect of narrow channel MOS transistor.
Specific embodiment
As described in the background art, the bulk effect of transistor is affected to the performance of transistor.
Further study show that the bulk effect has narrow-channel effect.Referring to FIG. 1, for along transistor channel widthThe diagrammatic cross-section in direction.Be formed in the substrate 10 of the transistor surround active area isolation structure 11, lining bias-voltage compared withWhen big, the depletion region formed in the channel region 12 of 14 lower section of grid can be laterally expanded to the channel width dimension of metal-oxide-semiconductor,Will form depletion region below isolation structure 11, be as shown in phantom in Figure 1 it is extending transversely after depletion region boundary signal.Ditch road widthSpend smaller, the depletion region accounting of the lower section of isolation structure 11 is bigger so that the bulk effect of MOS transistor become smaller with channel width andBecome larger, the threshold voltage of transistor is caused to increase.
Therefore, inventor proposes a kind of transistor and forming method thereof, by improving the narrow-channel effect of bulk effect, to dropThe bulk effect of low transistor.
It elaborates with reference to the accompanying drawing to the specific embodiment of transistor provided by the invention and forming method thereof.
Fig. 2 and Fig. 3 are please referred to, is the structural schematic diagram of the transistor of the embodiment of the invention, wherein Fig. 2 is to bowDepending on schematic diagram, Fig. 3 is the diagrammatic cross-section of the secant AA ' along Fig. 2.
The transistor includes: substrate 200, and active area 220 is formed in the substrate 200 and surrounds the active areaIsolated area 210；The active area 220 includes channel region 223 and the source region 221 for being located at 223 two sides of channel region and leakageArea 222；Gate dielectric layer 203 is located at 223 surface of channel region；Electrode layer 230, the grid including being located at the isolated area surfacePole extension 232 and the gate portion 231 for covering 203 surface of gate dielectric layer and being connect with the gate extension 232.
In the specific embodiment, the isolated area 210 is fleet plough groove isolation structure (STI)；In other specific embodiment partiesIn formula, the isolated area 210 can also be other isolation structures, such as localized oxidation of silicon isolation (LOCOS) isolation etc..
The gate extension 232 is located at at least side of 223 length direction of channel region (x-axis direction)；The gridPole portion 231 is connect along at least one end of 223 width direction of channel region (y-axis direction) with the gate extension 232.The specific realityIt applies in mode, the gate extension 232 is strip, and the length direction along the channel region 223 extends.The grid extendsPortion is protruded at 232 middle part to 231 direction of gate portion, to connect with the gate portion 231.In other specific embodiments, instituteGate extension 232 or other shapes, such as arc or irregular figure etc. are stated, as long as the gate extension 232It is fully located at 210 surface of isolated area, with 220 no overlap of active area.
There is certain safe distance, to avoid the grid between the gate extension 232 and the active area 220It is electrically connected between extension 232 and the active area 220.The safe distance receives the design rule of different process nodeIt then limits, under the premise of meeting the design rule, the safe distance is the smaller the better, to reduce the size of transistor.
Length of the gate extension 232 in the x-direction can be less than, be equal or slightly larger than the active area 220Length in the direction of the x axis, and it is greater than the length of the gate portion 231 in the direction of the x axis.Journey can be adjusted according to bulk effectThe length of the gate extension 232 is rationally arranged in the demand of degree.In the specific embodiment, the gate extension 232Both ends are aligned with the both ends of the active area 220.In other specific embodiments, the both ends of the gate extension 232 are alsoThe both ends of the active area 220 can be slightly protruded from, but to avoid the grid with the transistor of 210 other side of isolated areaContact.
In the specific embodiment, the electrode layer 230 is H-shaped；It, can also be only in institute in other specific embodimentsThe side for stating active area 220 forms gate extension 232, and the electrode layer 230 is T shape.
In Fig. 3, the surface of the electrode layer 230 has smooth pattern, only makees to illustrate, not practical pattern.ActualIn transistor arrangement, the top surface of the electrode layer 230 with the isolated area 210 and active area 220 surfacing situationDifference might have different patterns.For example, in some embodiments, the surface of the isolated area 210 is higher than describedThe surface of active area 220, therefore the surface of the gate extension 232 is higher than the surface of the gate portion 231, the grid prolongsThe junction of extending portion 232 and the gate portion 231 forms step-like pattern.
The material of the electrode layer 230 is the conductive materials such as polysilicon or metal.The transistor is during the work time, rightThe electrode layer 230 applies grid voltage.Since the gate extension 232 is located at 210 top of isolated area, the gridCharge on extension 232 can with the depletion region charge balance of 210 lower section of isolated area, without increasing the gridTherefore voltage in portion 231 will not lead to the drift of transistor threshold voltage, significantly because of the depletion region of 210 lower section of isolated areaReduce the bulk effect of narrow channel MOS transistor.
The size of the gate extension 232 can be reasonably adjusted, to obtain the improvement different to the bulk effect of transistorDegree, to meet the needs of different application scene.
In a specific embodiment, the area of the gate extension 232 is greater than or equal to the channel region 223Area can largely improve the bulk effect of transistor.Meeting, different process design of node is regular, such as minimum spacing,Under the premise of minimal critical dimensions etc., by adjusting size of the gate extension 232 in X-direction and Y direction, adjustmentThe area of the gate extension 232.
The gate portion of above-mentioned transistor is connected to gate extension, and the gate extension is located at the isolated area outside active areaOn, while applying grid voltage to gate portion, charge on the gate extension can with below the isolated areaDepletion region charge balance, the voltage without increasing in the gate portion therefore will not be because of the depletion region below isolated areaThe drift for leading to transistor threshold voltage substantially reduces the bulk effect of narrow channel MOS transistor.
A specific embodiment of the invention also provides a kind of depositing with transistor described in above-mentioned specific embodimentReservoir.The transistor can be used as the transistor in transistor or other circuit structures in the control circuit of memory.Since the bulk effect of the transistor is improved, the size of transistor can be reduced, thus improve memory performance andIntegrated level.
A specific embodiment of the invention also provides a kind of forming method of above-mentioned transistor.
Fig. 4 A and Fig. 4 B is please referred to, a substrate 400 is provided, is formed in the substrate 400 described in active area 420 and encirclementThe isolated area 410 of active area 420.Fig. 4 A is the diagrammatic cross-section of the secant BB ' along Fig. 4 B, and Fig. 4 B is schematic top plan view.
The substrate 400 can be the semiconductor substrates such as monocrystalline silicon, silicon-on-insulator, germanium on insulator, the substrate 400It is interior to be formed with n-type doping trap and/or p-type dopant well.Here, being not construed as limiting to the type of the substrate 400.
The isolated area 410 can be formed using shallow ditch groove separation process, specifically, include: the etching substrate 400,Groove is formed in the substrate 400, fills insulating dielectric materials in the groove, forms the isolated area 410.At otherIn specific embodiment, described isolated area 410, such as localized oxidation of silicon isolation technology etc. can also be formed using other techniques.The region that the isolated area 410 is surrounded is used to form transistor as active area 420.In other concrete modes, the substrateThere are multiple active areas 420 on 400, be isolated between adjacent active regions 420 by the isolated area 410.
The diagrammatic cross-section that Fig. 5 A and Fig. 5 B, Fig. 5 A are the secant CC ' along Fig. 5 B is please referred to, Fig. 5 B is schematic top plan view.
Gate dielectric material layer is formed on 410 surface of active area；Electrode layer 530 is formed, the electrode layer 530 includes positionGate extension 532 in 410 surface of isolated area and the gate portion 531 across the active area 420, the gridPortion 531 is connect with the gate extension 532.The active area of 531 lower section of gate portion is as the channel region 421.It is describedGate extension 532 is located at least in at least side of 421 length direction of channel region；The gate portion 531 is along channel region 421At least one end of width direction is connect with the gate extension 532.
In the specific embodiment, the two sides of the length direction of the channel region 421 are each formed with the gate extension532, the gate portion 531 is connect along the both ends of 421 width direction of channel region with the gate extension 532, the electrode layer530 be H-shaped.In other specific embodiments, the grid only can also be formed in the side of 421 length direction of channel regionPole extension 532, the shape of the electrode layer 530 are T shape.
The area of the gate extension 532 is greater than or equal to the area of the channel region 421, can largely changeThe bulk effect of kind transistor.In other specific embodiments, it is each can also to adjust the gate extension 532 according to demandThe size of a dimension.
The forming method of the electrode layer 530 includes: to form the electrode material for covering the isolated area 410, active area 420Layer；The electrode material layer is patterned, the electrode layer 530 is formed.Also, further to covering 420 table of active areaThe gate dielectric material layer in face is patterned, and removes the gate dielectric material layer not covered by the gate portion 531, is formed and is located at instituteState the gate dielectric layer 510 on 531 lower section of gate portion, 421 surface of the channel region.The material of the electrode material layer be polysilicon orThe material of the conductive materials such as metal, the gate dielectric layer 510 is silica, can be formed using thermal oxidation technology.
Referring to FIG. 6, forming source region 422 and drain region 423 in the active area 420 (please referring to Fig. 5 B).
It can be exposure mask with the electrode layer 530, ion implanting, shape are carried out to the active area 420 (please referring to Fig. 5 B)At the source region 422 and drain region 423 for being located at 531 two sides of gate portion.
The above are the transistor is formed using preceding grid technique, in other specific embodiments, rear grid can also be usedTechnique forms above-mentioned transistor, is initially formed after pseudo electrode layer, forms the interlayer dielectric layer for covering the substrate, then electricity consumption againPole layer substitutes the pseudo electrode layer.Compared with the method for forming transistor in the prior art, it is only necessary to change the domain of grid i.e.Can, without changing process flow, implementation method is simple.
Please refer to Fig. 7 be the embodiment of the invention transistor from existing collective's pipe under different lining bias-voltagesThreshold voltage curve.
When same source-drain area adulterates situation, channel length and width, in identical lining bias-voltage, this hairThe threshold voltage of the transistor of H-shaped electrode layer structure in a bright embodiment is respectively less than the threshold value electricity of the transistor of traditional structurePressure, improves significantly to the bulk effect of transistor.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the artMember, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded asProtection scope of the present invention.