CN109739677B - System for testing power-off protection based on NVME protocol - Google Patents

Abstract

The invention relates to a system for testing power-off protection based on an NVME protocol, which comprises a single chip microcomputer unit and a pc unit connected with the single chip microcomputer unit; the single chip microcomputer unit comprises a microprocessor, a single chip microcomputer minimum module, a switch module, a serial port module, an indicator light module, a function key module and a nixie tube display module; the switch module and the serial port module are connected with the pc unit. The invention solves the problems that the manual test power-off protection is complicated, and the time for manually simulating the forced shutdown is difficult to grasp, greatly saves the test time, and improves the test efficiency.

Description

System for testing power-off protection based on NVME protocol

Technical Field

The invention relates to the technical field of storage, in particular to a system for testing power-off protection based on an NVME protocol.

Background

The sudden power-off of the computer may cause the SSD to lose user data and important internal data in its cache (DRAM), so it is particularly important that the data in the DRAM is written into the NAND for stable storage until the computer is actually powered off.

Many customers prefer the power-off protection (PLP) technology, and SSD developers pay attention to the PLP. Meanwhile, for the test of the PLP in the research and development stage, in the prior art, a command is generally issued manually to inquire whether the SSD has a PLP function, then the command is issued manually to start the PLP, then the forced shutdown is simulated manually and continuously within a time specified by a manufacturer, and finally the command is issued manually to read the number of times of the currently completed PLP and the number of times of the incomplete PLP; the manual test scheme is very complicated in the research and development test process, and the maximum time for the SSD to finish the PLP is different according to the specification of each manufacturer, so that the time for manually simulating forced shutdown is more difficult to grasp; if this kind of scheme is used in producing the test of line large batch, often needs more people's cooperation, and work load is big, and is consuming time hard, and the human cost is higher, and efficiency of software testing is low.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a system for testing power-off protection based on an NVME protocol.

In order to achieve the purpose, the invention adopts the following technical scheme:

a system for testing power-off protection based on NVME protocol comprises a single chip microcomputer unit and a pc unit connected with the single chip microcomputer unit; the single chip microcomputer unit comprises a microprocessor, a single chip microcomputer minimum module, a switch module, a serial port module, an indicator light module, a function key module and a nixie tube display module; the switch module, and serial port module with the pc unit is connected.

The further technical scheme is as follows: the pc unit comprises a testing software tool, a hardware module and an SSD to be tested; the test software tool is provided with command codes for controlling the SSD, and the command codes comprise a power-off protection starting command, a power-off protection starting state reading command, a controller data reading command and a test statistical data reading command.

The further technical scheme is as follows: the microprocessor is of the type IAP15W4K58S4.

The further technical scheme is as follows: the minimum module of the single chip microcomputer comprises a capacitor C1, a capacitor C2, an external crystal oscillator, a polarity capacitor C4, a reset button and a resistor R1; the first end of the capacitor C1 and the first end of the capacitor C2 are respectively connected with an XTAL1 pin and an XTAL2 pin of the microprocessor, and the second end of the capacitor C1 and the second end of the capacitor C2 are both grounded; the first end of the external crystal oscillator is connected with the XTAL1 pin, and the second end of the external crystal oscillator is connected with the XTAL2 pin; the polar capacitor C4 is connected with the RST pin of the microprocessor after being connected with the reset button in parallel, and is connected with the resistor R1 in series and grounded.

The further technical scheme is as follows: the switch module comprises a relay, a triode Q1, a pull-up resistor R2, a pull-up resistor R4 and a pull-up resistor R5; the trigger port of the relay is electrically connected with a P1.0 pin of the microprocessor,ports 1 and 2 of the relay are respectively connected with the positive pole and the negative pole of a power key of the pc unit, the positive pole of the power supply is also connected with the base electrode of the triode Q1, the collector electrode of the triode Q1 is connected with an M.2 interface of the SSD to be tested, and the emitter electrode and the negative pole of the power supply are both grounded.

The further technical scheme is as follows: the pull-up resistor R2, the pull-up resistor R4 and the pull-up resistor R5 are also respectively connected with a power supply VCC and used for outputting stable voltage; the triode Q1 adopts a PNP junction.

The further technical scheme is as follows: the serial port module comprises a USB-to-serial port and a USB interface; a data sending port TXD, a data receiving port RXD and a trigger port TRIP of the USB to serial port are respectively connected with a P3.0 pin, a P3.1 pin and a P3.2 pin of the microprocessor; the power supply terminal VCC, the data terminal D-, the data terminal D + and the ground terminal GND of the USB transfer serial port are respectively and electrically connected with the VCC, the D +, the D-and the GND of the USB interface; the USB interface is also connected to a PC unit.

The further technical scheme is as follows: the indicating lamp module comprises a single chip microcomputer power supply state indicating lamp, a single chip microcomputer work completion indicating lamp, a resistor R13 and a resistor R14; the first end of the singlechip power supply status indicator lamp is connected with a P1.1 pin of the microprocessor, and the second end of the singlechip power supply status indicator lamp is connected with the first end of a resistor R13; the first end of the singlechip working completion indicator lamp is connected with P1.2 of the microprocessor, and the second end of the singlechip working completion indicator lamp is connected with the first end of the resistor R14; the second terminal of the resistor R13 and the second terminal of the resistor R14 are both connected to the power supply VCC.

The further technical scheme is as follows: the functional key module comprises a test counting reset key, a test pause key, a resistor R15 and a resistor R16; the first ends of the test count reset key and the resistor R15 are connected with a P2.5 pin of the microprocessor, the second end of the test count reset key is grounded, and the second end of the resistor R15 is connected with a power supply VCC; the first ends of the test pause key and the resistor R16 are connected with a P2.7 pin of the microprocessor, the second end of the test pause key is grounded, and the second end of the resistor R16 is connected with a power VCC.

The further technical scheme is as follows: the nixie tube display module is a 7-section 4-bit nixie tube, the display section ports A, B, C, D, E, F, G and DP of the nixie tube display module are respectively connected with the pins P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6 and P0.7 of the microprocessor, and thedisplay bit ports 1,2,3 and 4 are respectively connected with the pins P2.0, P2.1, P2.2 and P2.3 of the microprocessor.

Compared with the prior art, the invention has the beneficial effects that: the problem of manual test power-off protection loaded down with trivial details, manual simulation force time of shutting down be difficult to grasp is solved, save test time greatly, improved efficiency of software testing.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

FIG. 1 is a block diagram of a system for testing power-off protection based on NVME protocol according to the present invention;

FIG. 2 is a schematic circuit diagram of a system for testing power-off protection based on NVME protocol according to the present invention;

FIG. 3 is a schematic circuit diagram of the minimum module of the single chip microcomputer;

FIG. 4 is a circuit schematic of a switch module;

FIG. 5 is a schematic circuit diagram of a serial port module;

FIG. 6 is a circuit schematic of an indicator light module;

FIG. 7 is a schematic circuit diagram of a function key module;

fig. 8 is a schematic circuit diagram of the nixie tube display module.

10.Singlechip unit 11 microprocessor

12. Switch module of 13 minimum modules of single chip microcomputer

14.Serial port module 15 indicator lamp module

16.Function key module 17 nixie tube display module

20pc unit 21 test software tool

22.Hardware module 23 SSD to be tested

Detailed Description

In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.

As shown in fig. 1 to 8, the present invention discloses a system for testing power-off protection based on NVME protocol, which includes asingle chip unit 10 and apc unit 20 connected thereto; the singlechip microcomputer unit 10 comprises amicroprocessor 11, a single chipmicrocomputer minimum module 12, aswitch module 13, aserial port module 14, anindicator light module 15, afunction key module 16 and a nixietube display module 17; theswitch module 13 and theserial port module 14 are connected with the pc unit.

Thepc unit 20 includes atesting software tool 21, ahardware module 22, and a SSD23 to be tested; thetest software tool 21 is provided with command codes for controlling the SSD, including a command NVM _ SETF for turning on power-off protection (PLP), a command NVM _ GETF for reading PLP on state, a command NVM _ IDFY _ CTRLR for reading identifier controller data, and a command NVM _ GETLOG for reading test statistic data.

Further, a command NVM _ SETF for starting power-off protection (PLP) is packaged, and then a Feature ID and a parameter for starting a PLP function are added; feature ID of PLP is 800000F0H, parameter 01H to turn on PLP function.

Furthermore, the Feature ID is a 4-byte value, and the highest position is 1, which indicates that after the SSD is powered on, even if the SSD is restarted after power off, the power off protection (PLP) function is still in the powered on state; when the lowest bit of the parameter for starting the power-off protection (PLP) function is set to 1, the power-off protection (PLP) is started; if set to 0, it indicates that power-off protection (PLP) is turned off.

Wherein, read PLP open state command NVM _ GETF, according to its encapsulation, add Feature ID later.

Further, feature ID of power down protection (PLP) is 0F0H.

Furthermore, after the command is executed, if the lowest bit of the return value is 1, the power-off protection (PLP) is successfully started; if the lowest bit of the return value is 0, it indicates that the power-off protection (PLP) was not turned on.

Reading IDENTIFY controller data command NVM _ IDFY _ CTRLR, packaging according to the command, and adding no parameter at the back; after the command is successfully executed, all the functional parameters in the SSD are printed.

Further, the functional parameter printed by the execution command NVM _ IDFY _ CTRLR has 4096 bytes in total, wherein the 4000 th byte has the lowest bit value indicating whether the SSD supports power-off protection (a value of 1 indicates support and a value of 0 indicates non-support); in bytes 4002 and 4003, there is the longest time value in milliseconds, which is well defined by the SSD vendor, required to complete power down protection (PLP).

The reading test statistic data command NVM _ GETLOG is added with Feature ID and byte number to be fed back according to its package, and the unit is DWORD.

Further, feature ID is set to 0F0H, and the number of bytes that need to be fed back is set to 1.

Further, the first byte fed back has 4 bits lower to indicate the number of PLP completion, and 4 bits higher to indicate the number of PLP non-completion.

In this embodiment, thehardware module 22 and the software system are preferably a windows10pro system; the hardware system also supports a power down protection (PLP) function, which is preferably an X280 notebook computer.

The SSD23 to be tested is an SSD of a PCIE interface supporting power-off protection (PLP).

Specifically, as shown in fig. 1 to 8, themicroprocessor 11 has a model IAP15W4K58S4.

Specifically, as shown in fig. 3, theminimum module 12 of the single chip includes a capacitor C1, a capacitor C2, an external crystal oscillator (crystal), a polar capacitor C4, a RESET-KEY (RESET-KEY), and a resistor R1; the first end of the capacitor C1 and the first end of the capacitor C2 are respectively connected with an XTAL1 pin and an XTAL2 pin of themicroprocessor 11, and the second end of the capacitor C1 and the second end of the capacitor C2 are both grounded; the first end of the external crystal oscillator is connected with the XTAL1 pin, and the second end of the external crystal oscillator is connected with the XTAL2 pin; the polar capacitor C4 is connected with the RST pin of the microprocessor after being connected with the reset button in parallel, and is connected with the resistor R1 in series and grounded, and the external voltage is +5V.

Furthermore, the frequency of the external crystal oscillator is 12MHZ, which mainly plays a role of providing a reference frequency for the communication of the timer and the serial port; the resistance value of the resistor R1 can be selected according to actual needs, and a proper driving voltage can be provided for the RST pin; the reset button, when pressed, may reset themicroprocessor 11 to an initial state.

Specifically, as shown in fig. 4, theswitch module 13 includes a RELAY (RELAY), a transistor Q1, a pull-up resistor R2, a pull-up resistor R4, and a pull-up resistor R5; the trigger port (TRIP) of the relay is electrically connected with a P1.0 pin of themicroprocessor 11, theports 1 and 2 of the relay are respectively connected with a POWER key anode (POWER +) and a cathode (POWER-) of the pc unit, the anode of the POWER supply is also connected with a base electrode of the triode Q1, a collector electrode of the triode Q1 is connected with an M.2 INTERFACE (M.2-INTERFACE) of the SSD to be tested, and an emitter electrode of the triode Q1 and the cathode of the POWER supply are both grounded.

Furthermore, the pull-up resistor R2, the pull-up resistor R4 and the pull-up resistor R5 are also respectively connected with a power supply VCC, and the function in a loop is to keep the output voltage potential stable; the triode Q1 adopts a PNP junction, a collector open-circuit output gate circuit is formed by the PNP junction and surrounding circuits, and a signal (PLN) output by the collector is sent to the SSD-CONTROLLER end; the relay is set to be active by high level triggering through the short circuit cap.

Specifically, as shown in fig. 5, theserial port module 14 includes a USB to serial port (USB to serial port) and a USB interface (USB con); the data sending port TXD, the data receiving port RXD and the trigger port TRIP of the USB-to-serial port are respectively connected with the P3.0 pin, the P3.1 pin and the P3.2 pin of themicroprocessor 11; the power supply terminal VCC, the data terminal D-, the data terminal D + and the ground terminal GND of the USB transfer serial port are respectively and electrically connected with the VCC, the D +, the D-and the GND of the USB interface; the USB interface is also connected to the PC unit.

Specifically, as shown in fig. 6, theindicator light module 15 includes a single-chip microcomputer power status indicator light (STATE-RED), a single-chip microcomputer work completion indicator light (FINISH-GREEN), a resistor R13, and a resistor R14; the first end of the single chip power supply status indicator lamp is connected with a P1.1 pin of themicroprocessor 11, and the second end of the single chip power supply status indicator lamp is connected with the first end of the resistor R13; the first end of the singlechip working completion indicator lamp is connected with P1.2 of themicroprocessor 11, and the second end of the singlechip working completion indicator lamp is connected with the first end of the resistor R14; the second terminal of the resistor R13 and the second terminal of the resistor R14 are both connected to the power supply VCC.

Further, to turn on the indicator, the signals from the pin P1.1 and the pin P1.2 of themicroprocessor 11 are active low, and the resistors R13 and R14 function to operate the indicator in a suitable voltage range.

Specifically, as shown in fig. 7, thefunction KEY module 16 includes a TEST COUNT RESET-KEY (COUNT RESET-KEY), a TEST PAUSE-KEY (TEST PAUSE-KEY), a resistor R15, and a resistor R16; the first ends of the test count reset key and the resistor R15 are connected with a P2.5 pin of themicroprocessor 11, the second end of the test count reset key is grounded, and the second end of the resistor R15 is connected with a power supply VCC; the first ends of the test pause key and the resistor R16 are connected with a P2.7 pin of themicroprocessor 11, the second end of the test pause key is grounded, and the second end of the resistor R16 is connected with a power supply VCC.

Further, when the key is pressed, the level of the P2.5 pin and the P2.7 pin is pulled from high level to low level, and themicroprocessor 11 detects the level change of the P2.5 pin and the P2.7 pin, generates an interrupt, and then executes the corresponding function program.

Furthermore, at the priority of executing interrupts, themicroprocessor 11 resets the pin (RST) > test computation resets the pin (P2.5) > tests the suspend pin (P2.7).

Specifically, as shown in fig. 8, the nixieTUBE display module 17 is a 7-segment 4-digit display TUBE (DIGITAL TUBE) having display segment ports a, B, C, D, E, F, G, and DP connected to pins P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, and P0.7 of themicroprocessor 11, respectively, anddisplay bit ports 1,2,3, and 4 connected to pins P2.0, P2.1, P2.2, and P2.3 of themicroprocessor 11, respectively.

Furthermore, the digital display tube is a common cathode digital tube, the display segment ports (A to DP) are effectively lightened when receiving a high level signal, and the display position is determined by setting the display position ports (1 to 4) to be high level;

furthermore, the nixietube display module 17 further includes pull-up resistors (R3, R6, R8, R9, R10, R11, R12, R7), and the pull-up resistors (R3, R6, R8, R9, R10, R11, R12, R7) are connected to the power VCC to form a loop, so as to stabilize and prevent jitter of the driving signal from themicroprocessor 11.

In the invention, a test environment is successfully built by combining the figure 1 and the figure 2. At this time, the pin P1.1 of themicroprocessor 11 is switched from high level to low level, so that the power state indicator light of the single chip microcomputer is turned on, and then the specific working flow of the notebook computer test software tool is as follows:

step1: during the program execution process, the test software firstly declares some variables to be used and some environments required by the execution of the script.

Step2: the read IDENTIFY controller data command NVM _ IDFY _ CTRLR is executed, the read data value will be sent to the ReadA buffer, and then the program automatically sends the 4000 to 4003 bytes of value in sequence to the well-defined array.

The key codes are as follows:

finally, automatically judging whether the lowest bit in the 4000 th byte is anumerical value 1 or not in the program, and if so, indicating that the SSD to be tested has a PLP function; and simultaneously, automatically extracting 16-system values in the 4002 th byte and the 4003 th byte, sending the values to a serial port buffer variable of the notebook computer, and then sequentially sending data of two frames in total to a buffer register SBUF of the singlechip microcomputer system.

Step3: executing a command NVM _ SETF 800000F0H 01H for starting the PLP, and then executing a command NVM _ GETF 0F0H for reading the PLP starting state, wherein if the returned value is 01H, the PLP is successfully started; meanwhile, sending the defined 16-system state value 01H to a serial port buffer variable of the notebook computer; the data of one frame is then sent to the buffer registers SBUF of themicroprocessor 11.

With reference to fig. 1,2 and 4, after themicroprocessor 11 receives the 16-ary state value 01H, the P1.0 port of themicroprocessor 11 sends a high level signal to the TRIP terminal of the relay to trigger the relay to turn on theports 1 and 2 (i.e. the power key simulating the power source is pressed), and then the timer program of themicroprocessor 11 is immediately skipped; meanwhile, the triode Q1 in the open collector output gate circuit outputs a low level signal (PLN) to the SSD-CONTROLLER.

Before executing the timer program of themicroprocessor 11, the time value of 16-system number defined by manufacturer for completing PLP is automatically converted into 10-system number through the conversion function, then the 10-system number is divided by 1000 to be converted into the time value with the unit of second, and then the time value is sent to the variable chuzhi.

Themicroprocessor 11 timer program, the key code is as follows:

with reference to fig. 1,2, 5, and 7, when the 32 tests of the power-off protection setting are completed or the count reset key is pressed on themcu 10, the current 16-system status value (defined as 02H) is sent to the buffer SBUF of themcu 10; then, the pin P3.2 of themicroprocessor 11 outputs a high-level signal to the trigger terminal TRIP, so that the USB to serial port module is triggered to operate.

Before the value of the buffer register SBUF is sent to the notebook computer, some initialization settings are required for themicroprocessor 11, and the key codes are as follows:

with reference to fig. 1,2 and 6, when the pc unit receives the 16-system status value 02H, the pin P1.2 of themicroprocessor 11 is switched from the high level to the low level, so that the operation completion indicator is turned on; at the same time, the test software executes the read test statistic command (NVM _ GETLOG 0F0h, 1), and then the read data value will be sent to ReadA buffer, and then the following key codes are executed:

the invention automatically inquires and judges whether the SSD has a PLP function, automatically starts power-off protection, automatically obtains the longest time value of the SSD for completing the power-off protection specified by a manufacturer to the single chip unit for processing, and then the microprocessor outputs a signal to control a relay according to the setting of a program so as to control the pc unit to carry out forced shutdown; finally, automatically reading the times of current completion and failure of power-off protection by the program; the method solves the problems that in the prior art, a manual power-off protection test method is complicated, and the time for manually simulating forced shutdown is difficult to grasp, realizes full automation of power-off protection test, greatly saves test time, and improves test efficiency.

The technical contents of the present invention are further illustrated by the examples, so as to facilitate the reader to understand more easily, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation made by the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.

Claims (8)

1. A system for testing power-off protection based on NVME protocol is characterized by comprising a single chip microcomputer unit and a pc unit connected with the single chip microcomputer unit; the single chip microcomputer unit comprises a microprocessor, a single chip microcomputer minimum module, a switch module, a serial port module, an indicator light module, a function key module and a nixie tube display module; the switch module and the serial port module are connected with the pc unit; the pc unit comprises a testing software tool, a hardware module and an SSD to be tested; the test software tool is provided with command codes for controlling the SSD, wherein the command codes comprise a power-off protection starting command, a power-off protection reading starting state command, a controller data reading command and a test statistical data reading command;

the command for starting the power-off protection is NVM _ SETF, and according to the encapsulation of the NVM _ SETF, the Feature ID and the parameter for starting the power-off protection function are respectively added behind the NVM _ SETF; feature ID for starting power-off protection is 800000F0H, and parameter 01H for starting power-off protection function; the Feature ID is a 4-byte value, the highest position is 1, and the result shows that after the SSD is started with the power-off protection function, even if the SSD is restarted after power failure, the power-off protection function is still in a started state; when the lowest position of the parameter for starting the power-off protection function is set to be 1, the power-off protection is started; if the voltage is set to 0, the power-off protection is turned off;

reading a power-off protection opening state command as NVM _ GETF, and adding Feature ID according to the package of the NVM _ GETF; wherein, feature ID for reading the power-off protection on state is 0F0H; after the command is executed, if the lowest bit of the return value is 1, the power-off protection is successfully started; if the lowest bit of the return value is 0, the power-off protection is failed to be started;

the read controller data command is NVM _ IDFY _ CTRLR, and is packaged according to the NVM _ IDFY _ CTRLR, and no parameter is required to be added at the back; after the command is successfully executed, all the functional parameters in the SSD are printed out; after the command is executed, 4096 bytes are printed out from the NVM _ IDFY _ CTRLR, wherein the 4000 th byte, and the lowest value indicates whether the SSD supports power-off protection; in bytes 4002 and 4003, there is the longest time value defined by the SSD manufacturer to complete power-off protection, and the unit is millisecond;

the command for reading the test statistical data is NVM _ GETLOG, and according to the package, the Feature ID and the byte number needing to be fed back are respectively added at the back, and the unit is DWORD; setting Feature ID of the command for reading the test statistical data to be 0F0H, and setting the number of bytes needing to be fed back to be 1; the first byte is fed back, the low 4 bits of the first byte represent the times of completing the power-off protection, and the high 4 bits represent the times of not completing the power-off protection;

the nixie tube display module is a 7-section 4-bit nixie tube, the ports A, B, C, D, E, F, G and DP of the display section are respectively connected with the pins P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6 and P0.7 of the microprocessor, and the ports 1,2,3 and 4 of the display section are respectively connected with the pins P2.0, P2.1, P2.2 and P2.3 of the microprocessor;

the digital display tube is a common cathode digital tube, the ports A to DP of the display section are effectively lightened when receiving a high level signal, and the display position is determined by setting the high level of the ports 1 to 4 of the display position; the nixie tube display module 17 further comprises pull-up resistors R3, R6, R8, R9, R10, R11, R12 and R7, wherein the pull-up resistors R3, R6, R8, R9, R10, R11, R12 and R7 are connected with a power supply VCC to form a loop;

the pin P1.1 of the microprocessor is switched from high level to low level, so that the power state indicator lamp of the single chip microcomputer is turned on, and then the specific working flow of the notebook computer testing software tool is as follows:

step1: in the program execution process, the test software firstly declares some variables to be used and executes the environment required by running some scripts;

step2: executing a command NVM _ IDFY _ CTRLR for reading IDENTIFY controller data, sending the read data value to a ReadA buffer area, and then automatically sending the values of 4000 th to 4003 rd bytes to a defined array by a program;

step3: executing a command NVM _ SETF 800000F0H 01H for starting the PLP, and then executing a command NVM _ GETF 0F0H for reading the PLP starting state, wherein if the returned value is 01H, the PLP is successfully started; meanwhile, sending the defined 16-system state value 01H to a serial port buffer variable of the notebook computer; the data of one frame is then sent to the buffer registers SBUF of the microprocessor.

2. The system for testing power-off protection based on the NVME protocol as claimed in claim 1, wherein the microprocessor is IAP15W4K58S4.

3. The NVME protocol-based power-off protection test system according to claim 1, wherein the minimum module of the single chip microcomputer comprises a capacitor C1, a capacitor C2, an external crystal oscillator, a polar capacitor C4, a reset button, and a resistor R1; the first end of the capacitor C1 and the first end of the capacitor C2 are respectively connected with an XTAL1 pin and an XTAL2 pin of the microprocessor, and the second end of the capacitor C1 and the second end of the capacitor C2 are both grounded; the first end of the external crystal oscillator is connected with the XTAL1 pin, and the second end of the external crystal oscillator is connected with the XTAL2 pin; the polar capacitor C4 is connected with the RST pin of the microprocessor after being connected with the reset button in parallel, and is connected with the resistor R1 in series and grounded.

4. The system for testing power-off protection based on the NVME protocol according to claim 1, wherein the switch module comprises a relay, a triode Q1, a pull-up resistor R2, a pull-up resistor R4 and a pull-up resistor R5; the trigger port of the relay is electrically connected with a P1.0 pin of the microprocessor, ports 1 and 2 of the relay are respectively connected with the positive pole and the negative pole of a power key of the pc unit, the positive pole of the power is also connected with the base of the triode Q1, the collector of the triode Q1 is connected with an M.2 interface of the SSD to be tested, and the emitter of the triode Q1 and the negative pole of the power are both grounded.

5. The system for testing power-off protection based on the NVME protocol according to claim 4, wherein the pull-up resistor R2, the pull-up resistor R4 and the pull-up resistor R5 are further respectively connected with a power supply VCC for outputting a stable voltage; the triode Q1 adopts a PNP junction.

6. The system for testing power-off protection based on the NVME protocol as claimed in claim 1, wherein the serial port module comprises a USB to serial port and a USB interface; the data transmitting port TXD, the data receiving port RXD and the trigger port TRIP of the USB-to-serial port are respectively connected with a P3.0 pin, a P3.1 pin and a P3.2 pin of the microprocessor; the power supply terminal VCC, the data terminal D-, the data terminal D + and the grounding terminal GND of the USB transfer port are respectively and electrically connected with VCC, D +, D-and GND of the USB interface; the USB interface is also connected to a PC unit.

7. The system for testing power-off protection based on the NVME protocol as claimed in claim 1, wherein the indicator light module comprises a single chip microcomputer power status indicator light, a single chip microcomputer work completion indicator light, a resistor R13 and a resistor R14; the first end of the single chip microcomputer power supply state indicator lamp is connected with a P1.1 pin of the microprocessor, and the second end of the single chip microcomputer power supply state indicator lamp is connected with the first end of the resistor R13; the first end of the singlechip working completion indicator lamp is connected with P1.2 of the microprocessor, and the second end of the singlechip working completion indicator lamp is connected with the first end of the resistor R14; the second terminal of the resistor R13 and the second terminal of the resistor R14 are both connected to the power supply VCC.

8. The system for testing power-off protection based on NVME protocol of claim 1, wherein the function key module comprises a test count reset key, a test pause key, a resistor R15, and a resistor R16; the first ends of the test count reset key and the resistor R15 are connected with a P2.5 pin of the microprocessor, the second end of the test count reset key is grounded, and the second end of the resistor R15 is connected with a power supply VCC; the first ends of the test pause key and the resistor R16 are connected with a P2.7 pin of the microprocessor, the second end of the test pause key is grounded, and the second end of the resistor R16 is connected with a power VCC.

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