CN109638083B - Fast recovery diode and preparation method thereof - Google Patents

Abstract

The invention discloses a fast recovery diode, which comprises a front anode, a P+ boron-rich region, an N-light phosphorus region, an N-epitaxial layer, an N++ substrate region and a back cathode which are sequentially arranged from top to bottom, wherein the P+ boron-rich region and the N-light phosphorus region are provided with bilateral symmetry mesa grooves, and the P-light boron region is arranged between the mesa grooves at two sides of the N-light phosphorus region, and the preparation method comprises the following steps: the preparation of epitaxial materials, the front surface phosphorus injection, primary oxidation, primary photoetching, front surface boron injection, boron re-expansion, front surface boron supplement, platinum diffusion, front surface photoetching groove, mesa corrosion, glass passivation, front surface photoetching lead wire, front surface aluminum evaporation, front surface back surface reverse etching, back surface thinning, back surface silver evaporation, alloy evaporation and testing.

Description

Translated fromChinese

一种快恢复二极管及其制备方法A fast recovery diode and its preparation method

技术领域Technical Field

本发明涉及半导体功率器件技术领域，特别涉及一种快恢复二极管及其制备方法。The present invention relates to the technical field of semiconductor power devices, and in particular to a fast recovery diode and a preparation method thereof.

背景技术Background technique

半导体功率器件是电力电子系统进行能量控制和转换的基本电子元器件，电力电子技术的不断发展为半导体功率器件开拓了广泛的应用领域。在诸多的半导体功率器件中，快恢复二极管FRED（Fast Recovery Epitaxial Diode）是电力电子电路中最为常用的基础电子元器件之一，在电路中起着举足轻重的作用。其性能优劣通常成为电路设计是否成功，电路运行是否正常的关键元器件之一。Semiconductor power devices are basic electronic components for power electronic systems to control and convert energy. The continuous development of power electronic technology has opened up a wide range of application areas for semiconductor power devices. Among the many semiconductor power devices, the fast recovery diode FRED (Fast Recovery Epitaxial Diode) is one of the most commonly used basic electronic components in power electronic circuits and plays a vital role in the circuit. Its performance is usually one of the key components for the success of circuit design and the normal operation of the circuit.

FRED（Fast Recovery Epitaxial Diode）是一种用外延硅片做材料制作的快速恢复二极管，具有高频率、高电压、大电流、低损耗和无电磁干扰等优点，FRED可以作为PFC二极管、嵌位二极管、吸收二极管单独使用，也可以作为续流二极管与IGBT配套使用。FRED广泛应用于电焊机、开关电源、转换器、斩波器、逆变器等工业、医学和航空航天领域。FRED (Fast Recovery Epitaxial Diode) is a fast recovery diode made of epitaxial silicon wafers. It has the advantages of high frequency, high voltage, high current, low loss and no electromagnetic interference. FRED can be used as a PFC diode, a clamping diode, an absorption diode, or as a freewheeling diode in conjunction with an IGBT. FRED is widely used in welding machines, switching power supplies, converters, choppers, inverters and other industrial, medical and aerospace fields.

在电力电子电路中，为减少二极管自身的关断损耗，提高整机的运行效率与可靠性，要求二极管有较快的反向恢复特性，即FRED需要有反向恢复时间Trr短、反向恢复电荷Qrr少、通态压降Vf低、最大反向恢复电流Irrm小的特点。控制反向恢复时间Trr的方法是使用诸如金、铂等重金属元素的载流子寿命控制技术，使得Trr与Vf形成一种折衷的关系，即：Trr值越小，Vf值越大，这样关断损耗增大，降低了FRED自身的可靠性。In power electronic circuits, in order to reduce the turn-off loss of the diode itself and improve the operating efficiency and reliability of the whole machine, the diode is required to have a faster reverse recovery characteristic, that is, the FRED needs to have the characteristics of short reverse recovery time Trr, small reverse recovery charge Qrr, low on-state voltage drop Vf, and small maximum reverse recovery current Irrm. The method of controlling the reverse recovery time Trr is to use the carrier lifetime control technology of heavy metal elements such as gold and platinum, so that Trr and Vf form a compromise relationship, that is: the smaller the Trr value, the larger the Vf value, so that the turn-off loss increases, reducing the reliability of the FRED itself.

在如图1所示的传统结构FRED中，按照如图2的工艺流程制作台面结构FRED。传统FRED以N++区为衬底，外延生长的N--区为外延层制备外延片。通过正面补硼、硼再扩、铂扩散、正面刻槽、台面腐蚀、玻璃钝化、正面蒸铝、正面反刻、背面减薄、背面蒸银、合金等工艺，形成台面结构FRED。该工艺做法可以获得良好的Trr-Vf折衷关系，可以满足常规的电路应用。但是对于更高要求的应用环境，需要更低的二极管关断损耗，这就限制了传统结构FRED的应用，需要进一步优化FRED的产品结构，获得更优的Trr-Vf折衷关系，以适应更高的应用需求。In the traditional structure FRED shown in FIG1 , a mesa structure FRED is manufactured according to the process flow shown in FIG2 . The traditional FRED uses the N++ region as the substrate and the epitaxially grown N-- region as the epitaxial layer to prepare the epitaxial wafer. The mesa structure FRED is formed by processes such as front boron filling, boron re-expansion, platinum diffusion, front groove engraving, mesa etching, glass passivation, front aluminum evaporation, front reverse etching, back thinning, back silver evaporation, alloying, etc. This process can obtain a good Trr-Vf trade-off relationship and can meet conventional circuit applications. However, for more demanding application environments, lower diode turn-off losses are required, which limits the application of traditional structure FRED. It is necessary to further optimize the product structure of FRED to obtain a better Trr-Vf trade-off relationship to meet higher application requirements.

发明内容Summary of the invention

本发明的目的在于提供一种快恢复二极管及其制备方法。The object of the present invention is to provide a fast recovery diode and a preparation method thereof.

本发明采用的技术方案是：The technical solution adopted by the present invention is:

一种快恢复二极管，其特征在于：包括从上至下依次设置的正面阳极、P+浓硼区、N-淡磷区、N--外延层、N++衬底区、背面阴极，所述P+浓硼区、N-淡磷区开有左右对称的台面槽，所述N-淡磷区在两侧台面槽之间设有P-淡硼区。A fast recovery diode, characterized in that it includes a front anode, a P+ concentrated boron region, an N-light phosphorus region, an N--epitaxial layer, an N++ substrate region, and a back cathode which are arranged in sequence from top to bottom, wherein the P+ concentrated boron region and the N-light phosphorus region are provided with left-right symmetrical mesa grooves, and the N-light phosphorus region is provided with a P-light boron region between the mesa grooves on both sides.

所述快恢复二极管的制备方法包括以下步骤：The method for preparing the fast recovery diode comprises the following steps:

步骤1：外延材料的制备，外延片的衬底晶向为<1 1 1>，杂质为砷，电阻率为0.001-0.005Ω.cm，厚度为450-550um，外延杂质为磷，电阻率为5-8Ω.cm，厚度为25-40um；Step 1: Preparation of epitaxial material, the substrate crystal orientation of the epitaxial wafer is <1 1 1>, the impurity is arsenic, the resistivity is 0.001-0.005Ω.cm, the thickness is 450-550um, the epitaxial impurity is phosphorus, the resistivity is 5-8Ω.cm, and the thickness is 25-40um;

步骤2：正面注入磷，正面注入磷剂量为1E11-1E12cm-2，注入能量为50-80KeV；Step 2: implant phosphorus on the front side, with a phosphorus dose of 1E11-1E12cm-2 and an implant energy of 50-80KeV;

步骤3：一次氧化，硅片的工艺温度为1000-1150℃，氧化层厚度为1.4-2.0um；Step 3: primary oxidation, the process temperature of the silicon wafer is 1000-1150°C, and the thickness of the oxide layer is 1.4-2.0um;

步骤4：一次光刻，正面匀胶为100光刻胶，形成要求的光刻窗口；Step 4: One-time photolithography, with 100 photoresist on the front side to form the required photolithography window;

步骤5：正面注入硼，正面注入硼剂量为1E13-1E14cm-2，注入能量为60-100KeV；Step 5: inject boron into the front surface, the dosage of boron injected into the front surface is 1E13-1E14cm-2, and the injection energy is 60-100KeV;

步骤6：硼再扩，硼再扩温度在1200-1250℃进行硼再扩推结，形成P-区；Step 6: Boron re-expansion, the boron re-expansion temperature is 1200-1250°C to perform boron re-expansion and push the junction to form a P-region;

步骤7：正面补硼，硅片正面涂覆液态硼源，在1050-1150℃的扩散炉中进行预沉积；Step 7: Boron filling on the front side: liquid boron source is coated on the front side of the silicon wafer and pre-deposited in a diffusion furnace at 1050-1150°C;

步骤8：铂扩散，硅片涂覆液态铂源，在900-970℃的扩散炉中进行铂扩散，工艺时间根据Trr时间要求进行调整；Step 8: Platinum diffusion: the silicon wafer is coated with liquid platinum source and the platinum is diffused in a diffusion furnace at 900-970°C. The process time is adjusted according to the Trr time requirements.

步骤9：正面光刻刻槽，硅片正面、背面涂覆300胶，光刻曝光形成要求的槽；Step 9: Photolithography grooves on the front side, coating 300 resin on the front and back sides of the silicon wafer, and photolithography exposure to form the required grooves;

步骤10：台面腐蚀，硅片在HF: HNO3:CH3COOH:发烟硝酸的体积比为（8-10）：（6-8）：（8-10）：（3-5）的腐蚀液中，进行台面腐蚀，槽深要求在15-40um，槽形貌完整，平滑；Step 10: Mesa etching: the silicon wafer is etched in an etching solution with a volume ratio of HF: HNO3: CH3COOH: fuming nitric acid of (8-10): (6-8): (8-10): (3-5). The groove depth is required to be 15-40um, and the groove morphology is complete and smooth.

步骤11：玻璃钝化，配置玻璃粉，进行上粉，低温预烧，擦粉，高温烧结等操作；Step 11: Glass passivation, glass powder preparation, powder coating, low temperature pre-firing, powder rubbing, high temperature sintering and other operations;

步骤12：正面光刻引线，正面匀胶为300光刻胶，形成要求的引线孔窗口；Step 12: Photolithography of the leads on the front side, with 300 photoresist applied on the front side to form the required lead hole windows;

步骤13：正面蒸铝，正面蒸发铝层厚度为5±0.03um或者7±0.05um；Step 13: Aluminum is evaporated on the front side, and the thickness of the evaporated aluminum layer on the front side is 5±0.03um or 7±0.05um;

步骤14：正面反刻，正面匀胶为100光刻胶，形成要求的反刻窗口；Step 14: reverse etching on the front side, with 100 photoresist applied on the front side to form the required reverse etching window;

步骤15：背面减薄，根据不同产品，进行背面减薄；Step 15: Back thinning: back thinning is performed according to different products;

步骤16：背面蒸银，背面蒸银厚度分别为Ti=1400±200A，Ni=5000±500A，Ag=10000±1000A；Step 16: Silver is evaporated on the back side, and the thickness of the silver evaporated on the back side is Ti=1400±200A, Ni=5000±500A, Ag=10000±1000A;

步骤17：合金，合金工艺条件为：525±10℃/25±10min；Step 17: alloying, alloying process conditions are: 525±10℃/25±10min;

步骤18：测试。Step 18: Testing.

本发明的优点：在芯片正面形成P+/P-/N-的复合结构，形成近似对称的载流子浓度分布，产生阳极发射效率调整的效果，获得更为优化的Trr-Vf折衷关系，有效的降低了FRED的关断损耗，提升了RRED反向恢复过程中的可靠性与稳定性。The advantages of the present invention are as follows: a composite structure of P+/P-/N- is formed on the front side of the chip, an approximately symmetrical carrier concentration distribution is formed, an effect of adjusting the anode emission efficiency is produced, a more optimized Trr-Vf compromise relationship is obtained, the turn-off loss of the FRED is effectively reduced, and the reliability and stability of the RRED during reverse recovery are improved.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

下面结合附图和具体实施方式对本发明作进一步详细叙述。The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

图1为本发明背景技术的二极管的示意图；FIG1 is a schematic diagram of a diode according to the background technology of the present invention;

图2为本发明背景技术的二极管制备工艺流程图；FIG2 is a flow chart of a diode preparation process according to the background technology of the present invention;

图3为本发明二极管的结构图；FIG3 is a structural diagram of a diode of the present invention;

图4为本发明二极管的制备工艺流程图。FIG. 4 is a flow chart of the preparation process of the diode of the present invention.

其中：1、正面阳极；2、P+硼扩区；3、台面槽；4、N--外延层；5、N++衬底区；6、背面阴极；7、P+浓硼区；8、P-淡硼区；9、N-淡磷区。Among them: 1. Front anode; 2. P+ boron expansion area; 3. Mesa groove; 4. N-- epitaxial layer; 5. N++ substrate area; 6. Back cathode; 7. P+ concentrated boron area; 8. P- light boron area; 9. N- light phosphorus area.

具体实施方式Detailed ways

如图3-4所示，一种快恢复二极管，包括从上至下依次设置的正面阳极1、P+浓硼区7、N-淡磷区9、N--外延层4、N++衬底区5、背面阴极6，P+浓硼区7、N-淡磷区7开有左右对称的台面槽3，N-淡磷区9在两侧台面槽之间设有P-淡硼区8。As shown in FIG3-4, a fast recovery diode includes a front anode 1, a P+ concentrated boron region 7, an N-light phosphorus region 9, an N-- epitaxial layer 4, an N++ substrate region 5, and a back cathode 6, which are arranged in sequence from top to bottom. The P+ concentrated boron region 7 and the N-light phosphorus region 7 are provided with left-right symmetrical mesa grooves 3, and the N-light phosphorus region 9 is provided with a P-light boron region 8 between the mesa grooves on both sides.

快恢复二极管的制备方法包括以下步骤：The preparation method of the fast recovery diode comprises the following steps:

步骤1：外延材料的制备，外延片的衬底晶向为<1 1 1>，杂质为砷，电阻率为0.001-0.005Ω.cm，厚度为450-550um，外延杂质为磷，电阻率为5-8Ω.cm，厚度为25-40um；Step 1: Preparation of epitaxial material, the substrate crystal orientation of the epitaxial wafer is <1 1 1>, the impurity is arsenic, the resistivity is 0.001-0.005Ω.cm, the thickness is 450-550um, the epitaxial impurity is phosphorus, the resistivity is 5-8Ω.cm, and the thickness is 25-40um;

步骤2：正面注入磷，正面注入磷剂量为1E11-1E12cm-2，注入能量为50-80KeV；Step 2: implant phosphorus on the front side, with a phosphorus dose of 1E11-1E12cm-2 and an implant energy of 50-80KeV;

步骤3：一次氧化，硅片的工艺温度为1000-1150℃，氧化层厚度为1.4-2.0um；Step 3: primary oxidation, the process temperature of the silicon wafer is 1000-1150°C, and the thickness of the oxide layer is 1.4-2.0um;

步骤4：一次光刻，正面匀胶为100光刻胶，形成要求的光刻窗口；Step 4: One-time photolithography, with 100 photoresist on the front side to form the required photolithography window;

步骤5：正面注入硼，正面注入硼剂量为1E13-1E14cm-2，注入能量为60-100KeV；Step 5: inject boron into the front surface, the dosage of boron injected into the front surface is 1E13-1E14cm-2, and the injection energy is 60-100KeV;

步骤6：硼再扩，硼再扩温度在1200-1250℃进行硼再扩推结，形成P-区；Step 6: Boron re-expansion, the boron re-expansion temperature is 1200-1250°C to perform boron re-expansion and push the junction to form a P-region;

步骤7：正面补硼，硅片正面涂覆液态硼源，在1050-1150℃的扩散炉中进行预沉积；Step 7: Boron filling on the front side: liquid boron source is coated on the front side of the silicon wafer and pre-deposited in a diffusion furnace at 1050-1150°C;

步骤8：铂扩散，硅片涂覆液态铂源，在900-970℃的扩散炉中进行铂扩散，工艺时间根据Trr时间要求进行调整；Step 8: Platinum diffusion: the silicon wafer is coated with liquid platinum source and the platinum is diffused in a diffusion furnace at 900-970°C. The process time is adjusted according to the Trr time requirements.

步骤9：正面光刻刻槽，硅片正面、背面涂覆300胶，光刻曝光形成要求的槽；Step 9: Photolithography grooves on the front side, coating 300 resin on the front and back sides of the silicon wafer, and photolithography exposure to form the required grooves;

步骤10：台面腐蚀，硅片在HF: HNO3:CH3COOH:发烟硝酸的体积比为（8-10）：（6-8）：（8-10）：（3-5）的腐蚀液中，进行台面腐蚀，槽深要求在15-40um，槽形貌完整，平滑；Step 10: Mesa etching: the silicon wafer is etched in an etching solution with a volume ratio of HF: HNO3: CH3COOH: fuming nitric acid of (8-10): (6-8): (8-10): (3-5). The groove depth is required to be 15-40um, and the groove morphology is complete and smooth.

步骤11：玻璃钝化，配置玻璃粉，进行上粉，低温预烧，擦粉，高温烧结等操作；Step 11: Glass passivation, glass powder preparation, powder coating, low temperature pre-firing, powder rubbing, high temperature sintering and other operations;

步骤12：正面光刻引线，正面匀胶为300光刻胶，形成要求的引线孔窗口；Step 12: Photolithography of the leads on the front side, with 300 photoresist applied on the front side to form the required lead hole windows;

步骤13：正面蒸铝，正面蒸发铝层厚度为5±0.03um或者7±0.05um；Step 13: Aluminum is evaporated on the front side, and the thickness of the evaporated aluminum layer on the front side is 5±0.03um or 7±0.05um;

步骤14：正面反刻，正面匀胶为100光刻胶，形成要求的反刻窗口；Step 14: reverse etching on the front side, with 100 photoresist applied on the front side to form the required reverse etching window;

步骤15：背面减薄，根据不同产品，进行背面减薄；Step 15: Back thinning: back thinning is performed according to different products;

步骤16：背面蒸银，背面蒸银厚度分别为Ti=1400±200A，Ni=5000±500A，Ag=10000±1000A；Step 16: Silver is evaporated on the back side, and the thickness of the silver evaporated on the back side is Ti=1400±200A, Ni=5000±500A, Ag=10000±1000A;

步骤17：合金，合金工艺条件为：525±10℃/25±10min；Step 17: alloying, alloying process conditions are: 525±10℃/25±10min;

步骤18：测试。Step 18: Testing.

本发明的制作方法不仅适用于台面型FRED，还可以用于平面型FRED、穿通型FRED等类型的FRED结构，不仅适用于FRED，还可以用于BJT、SCR、MOSFET、MCT等可以引入阳极发射效率调整概念的功率半导体器件，不仅适用于体硅，还可以用于用碳化硅、砷化镓、磷化铟以及锗硅等半导体材料。The manufacturing method of the present invention is not only applicable to table-type FRED, but also to FRED structures of the planar FRED, through-type FRED and other types. It is not only applicable to FRED, but also to power semiconductor devices such as BJT, SCR, MOSFET, MCT, etc. that can introduce the concept of anode emission efficiency adjustment. It is not only applicable to bulk silicon, but also to semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide and germanium silicon.

本发明在芯片正面形成P+/P-/N-的复合结构，形成近似对称的载流子浓度分布，产生阳极发射效率调整的效果，获得更为优化的Trr-Vf折衷关系，有效的降低了FRED的关断损耗，提升了RRED反向恢复过程中的可靠性与稳定性。The present invention forms a P+/P-/N- composite structure on the front side of the chip, forms an approximately symmetrical carrier concentration distribution, produces an effect of adjusting the anode emission efficiency, obtains a more optimized Trr-Vf compromise relationship, effectively reduces the turn-off loss of the FRED, and improves the reliability and stability of the RRED during reverse recovery.

Claims (1)

1. A preparation method of a fast recovery diode is characterized by comprising the following steps: the diode comprises a front anode, a P+ boron concentration region, an N-light phosphorus region, an N-epitaxial layer, an N++ substrate region and a back cathode which are sequentially arranged from top to bottom, wherein the P+ boron concentration region and the N-light phosphorus region are provided with bilateral symmetry mesa grooves, and the P-light boron region is arranged between the mesa grooves at two sides of the N-light phosphorus region, and the preparation method comprises the following steps:

step 1: preparing an epitaxial material, wherein the crystal orientation of a substrate of an epitaxial wafer is < 1>, the impurity is arsenic, the resistivity is 0.001-0.005 omega cm, the thickness is 450-550 mu m, the epitaxial impurity is phosphorus, the resistivity is 5-8 omega cm, and the thickness is 25-40 mu m;

step 2: injecting phosphorus from the front side, wherein the dosage of the injected phosphorus from the front side is 1E11-1E12cm < -2 >, and the injection energy is 50-80KeV;

step 3: performing primary oxidation, wherein the process temperature of the silicon wafer is 1000-1150 ℃, and the thickness of an oxide layer is 1.4-2.0 mu m;

step 4: performing primary photoetching, wherein the front photoresist is 100 photoresist, so as to form a required photoetching window;

step 5: front surface boron implantation, wherein the dosage of the front surface boron implantation is 1E13-1E14cm < -2 >, and the implantation energy is 60-100KeV;

step 6: boron re-expansion is carried out, and boron re-expansion junction pushing is carried out at 1200-1250 ℃ to form a P-light boron region;

step 7: supplementing boron on the front surface, coating a liquid boron source on the front surface of the silicon wafer, and performing pre-deposition in a diffusion furnace at 1050-1150 ℃;

step 8: platinum diffusion, coating a silicon wafer with a liquid platinum source, and performing platinum diffusion in a diffusion furnace at 900-970 ℃ for a long time

Adjusting according to the Trr time requirement;

step 9: etching grooves on the front side by photoetching, coating 300 photoresist on the front side and the back side of a silicon wafer, and forming the required grooves by photoetching exposure;

step 10: etching a table surface, wherein the silicon wafer comprises the following components in volume ratio of HF, HNO3, CH3COOH and fuming nitric acid of (8-10): (6-8): (8-10): carrying out mesa corrosion in the corrosive liquid in the step (3-5), wherein the groove depth is required to be 15-40 mu m, and the groove appearance is complete and smooth;

step 11: passivating glass, preparing glass powder, performing operations such as powdering, low-temperature presintering, powdering, high-temperature sintering and the like;

step 12: front photoetching leads, wherein front photoresist is 300 photoresist, and a required lead hole window is formed;

step 13: evaporating aluminum from the front surface, wherein the thickness of the front surface evaporating aluminum layer is 5+/-0.03 mu m or 7+/-0.05 mu m;

step 14: back etching the front surface, wherein the front surface photoresist is 100 photoresist, and a required back etching window is formed;

step 15: thinning the back according to different products;

step 16: back surface silver steaming, wherein the thickness of the back surface silver steaming is Ti=1400+/-200 a, ni=5000+/-500 a, ag=10000+/-1000 a;

step 17: the alloy comprises the following technological conditions: 525+/-10 ℃/25+/-10 min;

step 18: and (5) testing.