Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of CPU to describe to hardware circuit transmitting order to lower levelsThe method and device of symbol.
To achieve the above object, the invention adopts the following technical scheme: a kind of CPU gives hardware circuit transmitting order to lower levels descriptorMethod, which comprises
Read the command description symbol in annular first in first out order slot；
Corresponding instruction operation is executed according to the current command descriptor；
Judge whether the current command descriptor is marked with next pending command description symbol；
If so, the step of returning to the command description symbol read in annular first in first out order slot；
If it is not, then entering inquiry waiting period；
Inquire whether the current command descriptor has new pending command description symbol after inquiring waiting period；
If so, the step of returning to the command description symbol read in annular first in first out order slot；
If it is not, then judging whether hardware circuit is stopped by CPU；
If so, terminating reading order descriptor；
If it is not, then returning to described the step of entering inquiry waiting period.
Its further technical solution are as follows: the step of the command description symbol read in annular first in first out order slot itBefore, comprising the following steps:
Initial address and the end address of the annular first in first out order slot in memory are configured, and by initial address and knotIn the address information write-in hardware circuit internal register of beam address；
Configuring hardware circuit inquires waiting period, will be in inquiry waiting time write-in hardware circuit internal register；
Pending command description symbol is written in CPU in memory from the initial address of annular first in first out order slot；
Judge whether the current command descriptor has write end address；
If so, the command description symbol after the current command descriptor is looped back to initial address write-in.
Its further technical solution are as follows: the command description symbol includes three parts, respectively command field, completion statusField and chained list tag field；The command field is filled in by CPU, for characterizing command information, for hardware circuit obtain andParsing, the completion status field is filled in by hardware circuit, for characterizing hardware circuit implementing result, the chained list tag fieldIt is filled in by CPU, for characterizing the current command descriptor, whether there are also pending command descriptions to accord with later.
Its further technical solution are as follows: described the step of corresponding instruction operation is executed according to the current command descriptor, toolBody the following steps are included:
Obtain the command field of the current command descriptor；
Specified command operation is executed according to command field；
Implementing result is write back in the completion status field of the current command descriptor.
Its further technical solution are as follows: described to judge whether the current command descriptor is marked with next pending orderThe step of descriptor, specifically includes the following steps:
Obtain the chained list tag field of the current command descriptor；
Judge chained list tag field with the presence or absence of label；
If so, determining that there are next pending command description symbols in annular first in first out order slot；
If it is not, then determining that there is no next pending command description symbols in annular first in first out order slot.
A kind of CPU to hardware circuit transmitting order to lower levels descriptor device, described device include reading unit, execution unit,First judging unit waits unit, query unit, second judgment unit and end unit；
The reading unit, for reading the symbol of the command description in annular first in first out order slot；
The execution unit is operated for executing corresponding instruction according to the current command descriptor；
First judging unit is retouched for judging whether the current command descriptor is marked with next pending orderState symbol；
The waiting unit, for entering inquiry waiting period；
The query unit, for inquired after inquiring waiting period the current command descriptor whether have it is new pendingCommand description symbol；
The second judgment unit, judges whether hardware circuit is stopped by CPU；
The end unit, for terminating reading order descriptor.
Its further technical solution are as follows: described device further includes the first configuration unit, the second configuration unit, the first write-in listMember, third judging unit and loopback unit；
First configuration unit, for configuring the initial address and end of the annular first in first out order slot in memoryAddress, and will be in initial address and the address information of end address write-in hardware circuit internal register；
Second configuration unit inquires waiting period for configuring hardware circuit, by inquiry waiting time write-in hardware electricityIn the internal register of road；
First writing unit is written in memory from the initial address of annular first in first out order slot for CPUPending command description symbol；
The third judging unit, for judging whether the current command descriptor has write end address；
The loopback unit is write for the command description symbol after the current command descriptor to be looped back to initial addressEnter.
Its further technical solution are as follows: the command description symbol includes three parts, respectively command field, completion statusField and chained list tag field；The command field is filled in by CPU, for characterizing command information, for hardware circuit obtain andParsing, the completion status field is filled in by hardware circuit, for characterizing hardware circuit implementing result, the chained list tag fieldIt is filled in by CPU, for characterizing the current command descriptor, whether there are also pending command descriptions to accord with later.
Its further technical solution are as follows: the execution unit includes the first acquisition module, execution module and writes back module；
Described first obtains module, for obtaining the command field of the current command descriptor；
The execution module, for executing specified command operation according to command field；
It is described to write back module, in the completion status field for implementing result to be write back to the current command descriptor.
Its further technical solution are as follows: first judging unit includes the second acquisition module and judgment module；
Described second obtains module, for obtaining the chained list tag field of the current command descriptor；
The judgment module, for judging chained list tag field with the presence or absence of label.
Compared with the prior art, the invention has the advantages that: a kind of CPU of the present invention is described to hardware circuit transmitting order to lower levelsThe annular first in first out order slot used in the method and device of symbol has the advantage of order chained list, and starting a hardware circuit canSuccessively to execute a string command, to reduce the interaction of CPU and hardware circuit, the operational efficiency of CPU is improved.And it usesAnnular first in first out order slot is without using chain table pointer, to save the resource of memory.In addition, being generated when CPU is calculatedIt after newer command, does not need triggering hardware circuit and executes newer command, hardware circuit can be regular according to inquiry waiting period of settingInquiry linked list label, to further reduce the interaction of CPU and hardware circuit, improves if discovery newer command can execute automaticallyThe operational efficiency of CPU.
The above description is only an overview of the technical scheme of the present invention, can in order to better understand technical measureIt is implemented in accordance with the contents of the specification, and in order to make above and other objects of the present invention, feature and advantage brighterShow understandable, special below to lift preferred embodiment, detailed description are as follows.
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention intoOne step introduction and explanation, but not limited to this.
It should be appreciated that herein, relational terms such as first and second and the like are used merely to an entity/behaviourWork/object is distinguished with another entity/operation/object, without necessarily requiring or implying these entity/operation/objectsBetween there are any actual relationship or orders.
It is also understood that the terms "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion,So that the process, method, article or the system that include a series of elements not only include those elements, but also including not havingThe other element being expressly recited, or further include for this process, method, article or the intrinsic element of system.Do not havingIn the case where having more limitations, the element that is limited by sentence "including a ...", it is not excluded that include the element process,There is also other identical elements in method, article or system.
As shown in figs. 3 to 9, the present invention provides a kind of CPU to the method for hardware circuit transmitting order to lower levels descriptor, this methodInclude:
S10, the command description read in annular first in first out order slot accord with；
S20, corresponding instruction operation is executed according to the current command descriptor；
S30, judge whether the current command descriptor is marked with next pending command description symbol；If so, returningStep S10；If it is not, S40, then entrance inquiry waiting period；
S50, inquire whether the current command descriptor has new pending command description symbol after inquiring waiting period；IfIt is, then return step S10；If it is not, S60, then judging whether hardware circuit is stopped by CPU；
If so, S70, then terminating reading order descriptor；
If it is not, then return step S40.
Specifically, annular FIFO (first in first out) order slot is meant that: CPU is under program-guide since initial addressWriting commands descriptor, one by one, centre do not have gap, write behind end address loopback again, write again from initial address；Hardware circuit takes command description to accord with since initial address, one by one, loopback again is got behind end address, again from startingAddress takes.Command description symbol includes three parts, respectively command field, completion status field and chained list tag field；LifeIt enables field be filled in by CPU, for characterizing command information, obtains and parse for hardware circuit, completion status field is by hardware circuitFill in, for characterizing hardware circuit implementing result, chained list tag field is filled in by CPU, for characterize the current command descriptor itWhether there are also pending command descriptions to accord with afterwards.
Annular fifo command slot structure has the advantage of order chained list, and starting a hardware circuit can be executed sequentially a stringOrder, to reduce the interaction of CPU and hardware circuit, improves the operational efficiency of CPU.Annular fifo command slot structure is compared to traditionOrder list structure save chain table pointer, to save memory resource.
After CPU calculating generates newer command, does not need triggering hardware circuit and execute newer command, hardware circuit oneself is regularInquiry linked list label, discovery has newer command that can execute automatically, to further reduce the interaction of CPU and hardware circuit, improvesThe operational efficiency of CPU.
For step S10, when CPU starts hardware circuit circuit block0, hardware circuit circuit block0According to the address that internal start addr register is specified, the order of first cmd0 is read from high speed memory by busField and chained list tag field.
In certain embodiments, before step the following steps are included:
S1, the initial address of annular first in first out order slot in configuration memory and end address, and by initial addressIn the address information write-in hardware circuit internal register of end address；
S2, configuring hardware circuit inquire waiting period, will be in inquiry waiting time write-in hardware circuit internal register；
Pending command description symbol is written in S3, CPU in memory from the initial address of annular first in first out order slot；
S4, judge whether the current command descriptor has write end address；If so, S5, then by the current command descriptor itCommand description symbol afterwards is looped back to initial address write-in；If it is not, then Next Command descriptor and then the previous commandThe subsequent address write-in in the address of descriptor write-in.
Specifically, CPU initializes hardware circuit, the initial address and end of the annular fifo command slot in memory are configuredAddress is written to the two address informations in hardware circuit internal register (inside circuit block0 as shown in Figure 3Start addr register and end addr register), while configuring hardware circuit inquire waiting period, this inquiry waitIt is written in hardware circuit internal register that (the waiting time inside circuit block0 as shown in Figure 3 is posted the timeStorage).
Pending cmd0, cmd1, cmd2 is written from the initial address of annular fifo command slot in high speed memory in CPUCommand description symbol.T0 moment annular fifo command slot order generate schematic diagram as shown in figure 5, in total there are three order, cmd0'sChained list represents behind cmd0 labeled as 1 there are cmd1, and the chained list of cmd1 represents behind cmd1 labeled as 1 there are cmd2, cmd2'sChained list represents behind cmd2 labeled as 0 without order.
Further, step S20 specifically includes the following steps:
S201, the command field for obtaining the current command descriptor；
S202, specified command operation is executed according to command field；
S203, implementing result is write back in the completion status field of the current command descriptor.
Specifically, hardware circuit executes specified command operation according to the command field of cmd0, it then will by busThe implementing result of cmd0 writes back the completion status field of cmd0.
Further, step S30 specifically includes the following steps:
S301, the chained list tag field for obtaining the current command descriptor；
S302, judge chained list tag field with the presence or absence of label；
If so, S303, then determining that there are next pending command description symbols in annular first in first out order slot；
If it is not, S304, then determining that there is no next pending command description symbols in annular first in first out order slot.
Specifically, the chained list tag field for the cmd0 that hardware circuit obtains before checking, it is found that the field is 1, then showAnnular FIFO Next Command slot there are pending order, therefore hardware circuit by bus read cmd1 command field andChained list tag field executes specified command operation according to command field and writes back completion status field；So circulation.When hardPart circuit reads the command field and chained list tag field of cmd2, after executing and writing back completion status field, finds chain list notationField is 0, then shows that annular FIFO Next Command slot does not have pending order, take newer command in being off, so farA batch order cmd0~cmd2, which is carried out, to be finished.
In addition, for example there is new a batch order to issue: in t0+ time Δt, CPU needs to issue newer command, as shown in Figure 5Order generates schematic diagram, and CPU continues to write to cmd3, cmd4 command description symbol into annular fifo command slot, and modifies cmd2'sChained list is labeled as 1.The behavior of hardware circuit at this time is divided into two kinds of situations:
The first, if t0+ time Δt, when the chained list that CPU modifies cmd2 is labeled as 1, hardware circuit not yet reads cmd2'sCommand field and chained list tag field after then hardware circuit has executed cmd1, can read the command field and chained list of cmd2 naturallyTag field, so that the chained list for seeing cmd2 labeled as 1, knows that there are also cmd3 is pending behind cmd2.
Second, if t0+ time Δt, when the chained list that CPU modifies cmd2 is labeled as 1, hardware circuit had read cmd2Command field and chained list tag field, then hardware circuit has been not considered as cmd3 since the cmd2 chained list seen before is labeled as 0Presence, but after hardware circuit can wait regular hour (inquiry waiting period), read again the chain list notation of cmd2, thereforeThe chain list notation for always reading cmd2 becomes 1, has been known that the presence of cmd3 at this time.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each processExecution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limitIt is fixed.
Corresponding to a kind of CPU described in above-described embodiment to the method for hardware circuit transmitting order to lower levels descriptor, the present invention is alsoA kind of CPU is provided to the device of hardware circuit transmitting order to lower levels descriptor.As shown in Fig. 3~5,10~12, which includes readingIt takes unit 10, execution unit 20, the first judging unit 30, wait unit 40, query unit 50, second judgment unit 60 and knotShu Danyuan 70；
Reading unit 10, for reading the symbol of the command description in annular first in first out order slot；
Execution unit 20 is operated for executing corresponding instruction according to the current command descriptor；
First judging unit 30, for judging whether the current command descriptor is marked with next pending command descriptionSymbol；
Unit 40 is waited, for entering inquiry waiting period；
Query unit 50, for inquiring whether the current command descriptor has new pending life after inquiring waiting periodEnable descriptor；
Second judgment unit 60, judges whether hardware circuit is stopped by CPU；
End unit 70, for terminating reading order descriptor.
Specifically, annular FIFO (first in first out) order slot is meant that: CPU is under program-guide since initial addressWriting commands descriptor, one by one, centre do not have gap, write behind end address loopback again, write again from initial address；Hardware circuit takes command description to accord with since initial address, one by one, loopback again is got behind end address, again from startingAddress takes.Command description symbol includes three parts, respectively command field, completion status field and chained list tag field；LifeIt enables field be filled in by CPU, for characterizing command information, obtains and parse for hardware circuit, completion status field is by hardware circuitFill in, for characterizing hardware circuit implementing result, chained list tag field is filled in by CPU, for characterize the current command descriptor itWhether there are also pending command descriptions to accord with afterwards.
Annular fifo command slot structure has the advantage of order chained list, and starting a hardware circuit can be executed sequentially a stringOrder, to reduce the interaction of CPU and hardware circuit, improves the operational efficiency of CPU.Annular fifo command slot structure is compared to traditionOrder list structure save chain table pointer, to save memory resource.
After CPU calculating generates newer command, does not need triggering hardware circuit and execute newer command, hardware circuit oneself is regularInquiry linked list label, discovery has newer command that can execute automatically, to further reduce the interaction of CPU and hardware circuit, improvesThe operational efficiency of CPU.
When CPU starts hardware circuit circuit block0, hardware circuit circuit block0 is according to internal startThe specified address of addr register, the command field and chain list notation of first cmd0 are read by bus from high speed memoryField.
In certain embodiments, the device further include the first configuration unit 1, the second configuration unit 2, the first writing unit 3,Third judging unit 4 and loopback unit 5；
First configuration unit 1, for configuring the initial address of the annular first in first out order slot in memory and terminating groundLocation, and will be in initial address and the address information of end address write-in hardware circuit internal register；
Second configuration unit 2 inquires waiting period for configuring hardware circuit, will post inside inquiry waiting time write circuitIn storage；
First writing unit 3 is written from the initial address of annular first in first out order slot wait hold in memory for CPUCapable command description symbol；
Third judging unit 4, for judging whether the current command descriptor has write end address；
Loopback unit 5, for the command description symbol after the current command descriptor to be looped back to initial address write-in.
Specifically, CPU initializes hardware circuit, the initial address and end of the annular fifo command slot in memory are configuredAddress is written to the two address informations in hardware circuit internal register (inside circuit block0 as shown in Figure 3Start addr register and end addr register), while configuring hardware circuit inquire waiting period, this inquiry waitIt is written in hardware circuit internal register that (the waiting time inside circuit block0 as shown in Figure 3 is posted the timeStorage).
Pending cmd0, cmd1, cmd2 is written from the initial address of annular fifo command slot in high speed memory in CPUCommand description symbol.T0 moment annular fifo command slot status command generate schematic diagram as shown in figure 5, in total there are three order,The chained list of cmd0 represents behind cmd0 labeled as 1 there are cmd1, and the chained list of cmd1 represents behind cmd1 labeled as 1 there are cmd2,The chained list of cmd2 represents behind cmd2 labeled as 0 without order.
Command description symbol includes three parts, respectively command field, completion status field and chained list tag field；LifeIt enabling field be filled in by CPU, for characterizing command information, obtains and parse for hardware circuit, completion status field is filled in by hardware,For characterizing hardware circuit implementing result, chained list tag field is filled in by CPU, for characterize after the current command descriptor whetherThere are also pending command descriptions to accord with.
Further, execution unit 20 includes the first acquisition module 201, execution module 202 and writes back module 203；
First obtains module 201, for obtaining the command field of the current command descriptor；
Execution module 202, for executing specified command operation according to command field；
Module 203 is write back, in the completion status field for implementing result to be write back to the current command descriptor.
Specifically, hardware circuit executes specified command operation according to the command field of cmd0, it then will by busThe implementing result of cmd0 writes back the completion status field of cmd0.
Further, the first judging unit 30 includes the second acquisition module 301 and judgment module 302；
Second obtains module 301, for obtaining the chained list tag field of the current command descriptor；
Judgment module 302, for judging chained list tag field with the presence or absence of label.
Specifically, the chained list tag field for the cmd0 that hardware circuit obtains before checking, it is found that the field is 1, then showAnnular FIFO Next Command slot there are pending order, therefore hardware circuit by bus read cmd1 command field andChained list tag field executes specified command operation according to command field and writes back completion status field；So circulation.When hardPart circuit reads the command field and chained list tag field of cmd2, after executing and writing back completion status field, finds chain list notationField is 0, then shows that annular FIFO Next Command slot does not have pending order, take newer command in being off, so farA batch order cmd0~cmd2, which is carried out, to be finished.
In addition, for example there is new a batch order to issue: in t0+ time Δt, CPU needs to issue newer command, as shown in Figure 5Order generates schematic diagram, and CPU continues to write to cmd3, cmd4 command description symbol into annular fifo command slot, and modifies cmd2'sChained list is labeled as 1.The behavior of hardware circuit at this time is divided into two kinds of situations:
The first, if t0+ time Δt, when the chained list that CPU modifies cmd2 is labeled as 1, hardware circuit not yet reads cmd2'sCommand field and chained list tag field after then hardware circuit has executed cmd1, can read the command field and chained list of cmd2 naturallyTag field, so that the chained list for seeing cmd2 labeled as 1, knows that there are also cmd3 is pending behind cmd2.
Second, if t0+ time Δt, when the chained list that CPU modifies cmd2 is labeled as 1, hardware circuit had read cmd2Command field and chained list tag field, then hardware circuit has been not considered as cmd3 since the cmd2 chained list seen before is labeled as 0Presence, but after hardware circuit can wait regular hour (inquiry waiting period), read again the chain list notation of cmd2, thereforeThe chain list notation for always reading cmd2 becomes 1, has been known that the presence of cmd3 at this time.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent productWhen, it can store in a computer readable storage medium.Based on this understanding, the technical solution of the embodiment of the present inventionSubstantially all or part of the part that contributes to existing technology or the technical solution can be with software product in other wordsForm embody, which is stored in a storage medium, including some instructions use so that oneComputer equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute this hairThe all or part of the steps of each embodiment the method in bright.And storage medium above-mentioned include: USB flash disk, it is mobile hard disk, read-onlyMemory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk orThe various media that can store program code such as person's CD.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each functionCan unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by differentFunctional unit, module are completed, i.e., the internal structure of described device is divided into different functional unit or module, more than completingThe all or part of function of description.Each functional unit in embodiment, module can integrate in one processing unit, can alsoTo be that each unit physically exists alone, can also be integrated in one unit with two or more units, it is above-mentioned integratedUnit both can take the form of hardware realization, can also realize in the form of software functional units.In addition, each function listMember, the specific name of module are also only for convenience of distinguishing each other, the protection scope being not intended to limit this application.Above-mentioned apparatusThe specific work process of middle unit, module, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosureMember and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actuallyIt is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technicianEach specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceedThe scope of the present invention.
In embodiment provided by the present invention, it should be understood that disclosed device and method can pass through othersMode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the division of the module or unit,Only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be withIn conjunction with or be desirably integrated into another device, or some features can be ignored or not executed.Another point, it is shown or discussedMutual coupling or direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING of device or unit orCommunication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unitThe component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multipleIn network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unitIt is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated listMember both can take the form of hardware realization, can also realize in the form of software functional units.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but notIt represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the inventionProtection.Protection scope of the present invention is subject to claims.