Hardware circuit	Main device	Function(s)
			FPGA	XC7K325TFFG900	Protocol parsing, channel coding and decoding and QPSK modulation and demodulation
AD9361	AD9361BBCZ	Modulation and demodulation of baseband signals to radio frequency signals
			DSP	TMS320DM368	Image decompression
Clock circuit	TDNCAN-40.00MHz	Generating a 40Mhz clock
			Power supply circuit	LTM4608AIV#PBF	Generating individual module power
FLASH circuit	N25Q128A13ESE40E	Storing FPGA and DSP parameters
			RS422	ADM3490ARZ	RS422 level and LVCOMS33 level conversion

The transmitting channel of the uplink radio frequency module receives 1 uplink transmitting signal sent by the uplink signal processing module, completes filtering and amplification of the uplink transmitting signal, and then sends the uplink transmitting signal to the downlink signal processing module through the receiving channel of the downlink radio frequency module; and a receiving channel of the uplink radio frequency module receives 4 paths of downlink transmitting signals sent by the downlink radio frequency transmitting module. The hardware circuit of the uplink radio frequency module comprises a filter circuit and a power amplifier circuit; the filter circuit filters the signal and suppresses out-of-band signals; the power amplifier circuit amplifies the filtered signals, and the main devices and functions of each circuit are shown in table 2.

TABLE 2 hardware circuit composition of uplink RF module

Hardware circuit	Main device	Function(s)
			Receiving power amplifier	SBB-5089Z	Signal gain 45dB
Receiving preselection filter 1	MB3818-100K8HA	Broadband filter with center frequency of 3818Mhz
			Receiving preselection filter 2	MB3908-100K8HA	Broadband filter with center frequency of 3908Mhz
Receiving preselection filter 3	MB3998-100K8HA	Broadband filter with center frequency of 3998Mhz
			Reception preselection filter 4	MB4088-100K8HA	Center frequency 4088Mhz broadband filter
Transmitting power amplifier	TGA2975-SM	Maximum transmit power of 30dBm
			Transmission filter	MB3766-300K8HA	Broadband filter with center frequency of 3766Mhz

The downlink signal processing module sends 4 downlink transmitting signals to a transmitting channel of the downlink radio frequency module through image compression coding, framing, channel coding, modulation and up-conversion; the downlink signal processing module also receives 1 uplink transmitted signal sent by a receiving channel of the downlink radio frequency module, and obtains instruction data through down-conversion, demodulation, channel decoding, frame decoding and protocol analysis processing. As shown in fig. 4, the hardware circuits include FPGA, AD9361, DSP, clock circuit, power circuit, FLASH circuit and RS422 circuit, and the main devices and functions of each circuit are shown in table 3.

Table 3 downlink signal processing module hardware circuit composition

The transmitting channel of the downlink radio frequency module receives 4 downlink transmitting signals sent by the downlink signal processing module, and after filtering and amplification, the 4 downlink transmitting signals are sent to the uplink signal processing module through the receiving channel of the uplink radio frequency module; and the receiving channel of the downlink radio frequency module receives the 1 path of uplink transmitting signals sent by the transmitting channel of the uplink radio frequency module. The downlink radio frequency module hardware is provided with a filter circuit and a power amplifier circuit, and the filter circuit filters the input signal of the downlink signal processing module and suppresses the signal outside the bandwidth; the power amplifier circuit amplifies the filtered signals and improves the transmitting power. The downlink radio frequency module hardware consists of a receiving preselection filter and a power amplifier, and the main devices and functions of each circuit are shown in table 4.

Table 4 downlink rf module hardware circuit composition

Hardware circuit	Main device	Function(s)
			Power amplifier	TGA2975-SM	Maximum transmit power of 30dBm
Receiving preselection filter	MB3766-300K8HA	Broadband filter with center frequency of 3766Mhz

FIG. 5 is a hardware circuit diagram of the present invention.

The product is in the communication test in static environment, and ground equipment and airborne equipment adopt the radio frequency line to connect, can realize four airborne equipment image transmission simultaneously, specifically can carry out the node extension according to user's demand.

The design requirement of the wireless communication transmission system is determined as the basis for designing and producing the wireless communication transmission system.

Claims

1. The instruction image wireless transmission system of the frequency division multiple access and time division multiple access mixed system is characterized by comprising an uplink signal processing module, an uplink radio frequency module, a downlink signal processing module and a downlink radio frequency module;

a transmitting channel of the downlink radio frequency module receives a plurality of downlink transmitting signals sent by the downlink signal processing module, and the downlink transmitting signals are filtered and amplified and then sent to a receiving channel of the uplink radio frequency module; a receiving channel of the downlink radio frequency module receives one path of uplink transmitting signals sent by a transmitting channel of the uplink radio frequency module and sends the uplink transmitting signals to the downlink signal processing module;

the uplink signal processing module and the downlink signal processing module both adopt AD9361+ FPGA + DSP architectures;

the plurality of downlink transmitting signals are 4 paths of parallel PAL gray level image signals;

the uplink signal processing module adopts 4 AD9361 chips to receive and transmit input and output signals, and 2K 7 series of FPGA and 4 DSP chips to perform signal processing operation;

the downlink signal processing module adopts 1 AD9361 chip to receive and transmit input and output signals, and 1 FPGA and 1 DSP of an A7 series carry out signal processing operation;

the uplink signal processing module and the downlink signal processing module adopt J30-21ZKP, J30-15ZKP, J30-9ZKP and SMP-JHD connectors; the uplink radio frequency module and the downlink radio frequency module adopt J30-9ZKP and SMA-KFB2 connectors.

2. The system according to claim 1, wherein the uplink signal processing module and the downlink signal processing module are an asynchronous RS422 communication interface with an external interface.

3. The method for wireless transmission of command images in a mixed system of frequency division multiple access and time division multiple access is characterized in that, based on the system of claim 1, the uplink adopts the time division multiple access system to transmit command data, and the downlink adopts the frequency division multiple access system to transmit image data;

one path of instruction data is transmitted in an uplink mode, and four paths of image data are transmitted in a parallel mode in a downlink mode;