Memory and forming method thereofTechnical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of memory and forming method thereof.
Background technique
OTP (One Time Programmable, one-time programming) memory belongs to nonvolatile storage, in use onlyAllow one-time programming, therefore there is very high data reliability.Currently, otp memory is applied primarily to initial information and closeThe data such as key preservation.There are two types of basic OTP memory cells, fuse-type and anti-fuse type.Antifuse otp memory is due to havingVery strong capability of resistance to radiation, very high safety and can high-low temperature resistant the advantages that, have in memory area and important answerWith.
The basic structure of antifuse OTP memory cell is by pressing from both sides one layer of very high Jie of dielectric constant among two conductive electrodesMatter layer.When unprogrammed, antifuse otp memory is equivalent to a capacitor, and the impedance between upper bottom crown is very high, is in circuitOpen-circuit condition.Plus high pressure is programmed on two-plate, the dielectric layer between two-plate is breakdown, is formed between two-plate logicalRoad, to realize antifuse programming front and back storage logical zero and " 1 " two states.
However, the performance of the otp memory of the prior art is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of memory and forming method thereof, can improve the performance of memory.
To solve the above problems, technical solution of the present invention provides a kind of memory, comprising: substrate, the substrate include depositingStorage area；Discrete selection gate and storage grid on the memory block substrate, the thickness of the storage grid are greater than describedThe thickness of selection gate；The first source and drain doping area and the second source and drain doping in the substrate of selection gate two sides memory blockArea, second source and drain doping area is between the selection gate and storage grid；Jie on the memory block substrateMatter layer, the dielectric layer cover the storage grid side wall and selection gate side wall；The first source and drain in the dielectric layerPlug, the first source and drain plug are electrically connected with first source and drain doping area；The second source and drain in the dielectric layer is insertedPlug has dielectric layer, the second source and drain plug and second source between the second source and drain plug and the storage gridLeak doped region electrical connection.
Optionally, further includes: the dummy grid on the memory block substrate, the dummy grid are located at the selection gateAnd on the second substrate between source and drain doping area, the width of the dummy grid is greater than or equal to the width of the selection gate, andLess than the width of the storage grid；Third source and drain doping between the dummy grid and the selection gate in substrateArea.
Optionally, further includes: the third source and drain plug in the dielectric layer, described in third source and drain plug connectionThird source and drain doping area；Connecting line on the dielectric layer, the connecting line connect the third source and drain plug and describedSecond source and drain plug.
Optionally, the thickness of the dummy grid is less than or equal to the selection gate thickness.
Optionally, the width of the storage grid is greater than the width of the selection gate.
Optionally, the width of the storage grid is greater than 0.1 μm；The width of the selection gate is less than 0.05 μm.
Optionally, further includes: the protective layer in the selection gate and storage grid, described in dielectric layer coveringProtective layer side wall, the material of the protective layer are silicon nitride, silica or silicon oxynitride.
Optionally, the number of the memory block is multiple, and the substrate further includes the isolation between adjacent storage zonesArea；The memory includes: the isolated gate on the isolated area substrate.
Technical solution of the present invention also provides a kind of forming method of memory, comprising: provides substrate, the substrate includes depositingStorage area；Dielectric layer, discrete selection gate and storage grid, the first source and drain doping area and the second source and drain doping area are formed, it is describedDielectric layer is located on the substrate, and the selection gate and storage grid are located on the memory block substrate, and the dielectric layer coversCovering the storage grid and selection gate side wall, the thickness of the storage grid is greater than the thickness of the selection gate, and described theOne source and drain doping area and the second source and drain doping area are located in the memory block substrate of the selection gate two sides, second sourceDoped region is leaked between the selection gate and storage grid；Form the first source and drain plug in the dielectric layer, describedOne source and drain plug is electrically connected with first source and drain doping area；Form the second source and drain plug in the dielectric layer, described secondThere is dielectric layer, the second source and drain plug is electrically connected with second source and drain doping area between source and drain plug and the storage gridIt connects.
Optionally, form storage grid and the step of selection gate include: formed on the memory block substrate it is discreteInitial storage grid and initial selected grid, the width of the initial storage grid are greater than the width of the initial selected grid；Grid etch is carried out to the storage selection gate and initial selected grid, removes the initial storage grid of segment thickness, is formedStorage grid, and the initial selected grid of segment thickness is removed, selection gate is formed, the thickness of the initial storage grid of removal is smallIn the thickness of the initial selected grid of removal.
Optionally, the step of forming the storage grid and selection gate includes: to be formed to divide on the memory block substrateVertical initial storage grid and initial selected grid carries out the first etching to the initial storage grid, removes segment thicknessInitial storage grid forms storage grid；Second etching is carried out to the initial selected grid, removes the initial choosing of segment thicknessGrid is selected, selection gate is formed.
Optionally, the dielectric layer includes: the isolation structure for covering the selection gate side wall and storage grid side wall；PositionFirst medium layer on the selection gate, storage grid and the isolation structure；The step of forming the dielectric layer include:Before removing the initial selected grid of segment thickness and the initial selected grid of segment thickness, isolation structure, the isolation are formedStructure covers the initial selected grid and initial storage gate lateral wall；Initial selected grid and the part for removing segment thickness are thickAfter the initial selected grid of degree, first medium is formed on the initial selected grid, initial storage grid and isolation structureLayer；After the initial storage grid for removing segment thickness, the second groove is formed in the isolation structure；Remove segment thicknessAfter initial selected grid, the first groove is formed in the isolation structure.
Optionally, it is formed before the first medium layer, further includes: formed and protected in second groove and the first grooveSheath.
Optionally, the step of forming the first source and drain plug and the second source and drain plug includes: to carry out to the dielectric layerEtching, the storage contact hole and selection contact hole, the storage contact hole bottom-exposed formed through the dielectric layer goes out describedSecond source and drain doping area, the selection contact hole bottom-exposed go out first source and drain doping area；In the selection contact holeForm the first source and drain plug；The second source and drain plug is formed in the storage contact hole.
Optionally, the step of forming the initial storage grid, initial selected grid and isolation structure includes: in the liningFirst grid layer is formed on bottom；The first grid layer is patterned, is formed and sacrifices storage grid and sacrifice selection gate；Form the covering isolation structure sacrificed storage grid side wall and sacrifice selection gate side wall；Remove the sacrifice selection gridPole forms the first opening in the isolation structure；The sacrifice storage grid is removed, forms second in the isolation structureOpening；Initial selected grid is formed in first opening；Initial storage grid is formed in second opening.
Optionally, the isolation structure includes: the side wall for covering the storage grid and selection gate side wall；Positioned at describedSecond dielectric layer on substrate, the second dielectric layer cover the side wall side wall；The step of forming the isolation structure include:Form the covering side wall sacrificed storage grid side wall and sacrifice selection gate side wall；Second medium is formed over the substrateLayer, the second dielectric layer cover the side wall side wall；It is formed after the side wall, is formed before the second dielectric layer, shapeAt first source and drain doping area and the second source and drain doping area.
Optionally, the step of forming the initial storage grid and initial selected grid includes: to be formed over the substrateSecond grid layer；The second grid layer is patterned, the initial storage grid and initial selected grid are formed；It is formedAfter initial storage grid and initial selected grid, first source and drain doping area and the second source and drain doping area are formed.
Optionally, the initial storage grid and initial selected grid is of same size；Described in the first etching removalInitial storage grid with a thickness of first thickness, the initial selected grid of the second etching removal with a thickness of second thickness,The first thickness is greater than the second thickness.
Optionally, further includes: form dummy grid and third source and drain doping layer, the dummy grid are located at the memory block substrateOn, for the dummy grid between second source and drain doping area and the selection gate, the width of the dummy grid is greater than instituteThe width of selection gate is stated, and is less than the width of the storage grid, third source and drain doping area is located at the selection gateIn memory block substrate between dummy grid, third source and drain doping area is electrically connected with second source and drain doping area.
Optionally, the dielectric layer also covers the dummy grid side wall；The forming method further include: in the dielectric layerThe middle third source and drain plug for forming connection third source and drain doping area；Connecting line, the connection are formed on the dielectric layerLine connects the third source and drain plug and the second source and drain plug.
Compared with prior art, technical solution of the present invention has the advantage that
In the memory that technical solution of the present invention provides, the thickness of the storage grid is greater than the selection gate thickness.The thickness of the storage grid is larger, can increase the area of storage grid side wall, as Jie of storage grid side wall any regionWhen matter layer is breakdown, the capacitor that the storage grid, the first source and drain plug and dielectric layer are formed becomes low resistive state, so as toMemory is programmed namely the thickness of storage grid is larger can increase medium between storage grid and the second source and drain plugThe breakdown probability of layer, and then the program voltage of formed memory is reduced, reduce the power consumption of memory.The thickness of the selection gateDegree is smaller, can reduce the area of selection gate side wall, to reduce dielectric layer between selection gate and the first source and drain plugBreakdown probability, and then improve the performance of formed memory.
Further, there is dummy grid, the thickness of the dummy grid is less than or equal to the selection on the memory block substrateThe thickness of grid, then the area of the dummy grid side wall is smaller, the dielectric layer quilt between the dummy grid and third source and drain plugThe probability of breakdown is smaller, and the breakdown probability of dielectric layer is smaller between dummy grid and the second source and drain plug, so as to improveForm the performance of storage.
In the forming method for the memory that technical solution of the present invention provides, the thickness of the storage grid is greater than the selectionGate.The thickness of the storage grid is larger, can increase the area of storage grid side wall, thus increase storage grid withThe breakdown probability of dielectric layer between second source and drain plug, and then the program voltage of formed memory is reduced, reduce memoryPower consumption；The thickness of the selection gate is smaller, can reduce the area of selection gate side wall, to reduce selection gate and firstThe breakdown probability of dielectric layer between source and drain plug, and then improve the performance of formed memory.
Further, the width of the initial storage grid is greater than the width of the initial selected grid.It is initially deposited to describedDuring storing up grid and initial selected grid progress grid etch, the polymerization that the initial storage gate surface is formed is more,The polymer is easily reduced the etch rate of initial storage grid, and the etch rate so as to cause the initial storage grid is bigIn the etch rate of the initial selected grid, and then make the thickness of the storage grid greater than the thickness of the selection gate.The width of the initial storage grid is greater than the width of the initial selected grid, can be to initial storage grid and initial selectedGrid is performed etching by same technique, to form selection gate and storage grid.Therefore, the forming method can simplifyProcess flow.
Further, the forming method further include: form dummy grid over the substrate, the dummy grid is located at described depositIt stores up between grid and selection gate, the width of the dummy grid is greater than or equal to the width of the selection gate, and is less than describedThe width of storage grid.During forming dummy grid, storage grid and selection gate, the dummy grid can reduce exposureThe distortion of the diffraction of light and refraction caused storage grid and selection gate size in the process, improves the property of formed memoryEnergy.
Further, initial storage grid and storage selection gate are carved respectively by the first etching and the second etchingErosion can make the thickness of storage grid be greater than the thickness of the selection gate.The initial storage grid and initial selected gridIt is of same size, during capable of making to be formed the initial storage grid and initial selected grid, in used light shieldFigure is identical, so as to reduce in photoetching process the distortion of exposure figure caused by figure in light shield influences each other, Jin ErnengThe width of enough accurate control initial storage grid and initial selected grid, and then increase the essence of storage grid and selection gate widthDegree improves the performance of formed memory.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of memory；
Fig. 2 to Figure 12 is the structural schematic diagram of each step of one embodiment of forming method of memory of the invention；
Figure 13 to Figure 16 is the structural schematic diagram of each step of another embodiment of forming method of memory of the invention.
Specific embodiment
There are problems for the semiconductor structure of the prior art, such as: the performance of memory is poor.
Now in conjunction with a kind of memory, the poor reason of the performance of the memory of the prior art is analyzed:
Fig. 1 is a kind of structural schematic diagram of memory.
Referring to FIG. 1, the memory includes: substrate 100, the substrate 100 is including isolated area A and is located at the isolationThe memory block B of the area two sides A；Isolated gate 121 on the isolated area A substrate 100；It is located at the memory block B liningSelection gate 110 and storage grid 120 on bottom 100；First be located in the 110 two sides substrate 100 of selection gateSource and drain doping area 113 and the second source and drain doping area 123；Cover the selection gate 110, storage grid 120, isolated gate 121,The dielectric layer 130 in the first source and drain doping area 113 and the second source and drain doping area 123；The first source and drain in the dielectric layer 130Plug 112 and the second source and drain plug 122, the first source and drain plug 112 connect first source and drain doping area 113, and describedTwo source and drain plugs 122 connect second source and drain doping area 123；Isolation in the 121 media of both sides layer of isolated gatePlug.
Wherein, between storage grid 120, the second source and drain plug 123 and storage grid 120 and the second source and drain plug 123Dielectric layer 130 constitute capacitor.During being programmed to the memory, in the storage grid 120 and the second sourceThe indirect biggish program voltage for leaking plug 123, makes the dielectric layer between the storage grid 120 and the second source and drain plug 123130 can be breakdown, and the capacitor is made to become low resistive state, and storage grid 120 and the second source and drain plug 123 is connected, fromAnd the memory is programmed.
In order to forming storage grid 120, selection gate 110 and during isolated gate 121, reduce light diffraction andInterfere the influence to exposure, so that the width for being formed by storage grid 120, selection gate 110 and isolated gate 121 be made relatively to holdEasy to control, the storage grid 120, selection gate 110 are equal with the width of isolated gate 121.
The step of forming the selection gate 110, storage grid 120 and isolated gate 121 includes: in the substrate 100Upper formation grid layer；Patterned photoresist is formed on the grid layer；It is exposure mask to the grid layer using the photoresistIt performs etching, forms selection gate 110, storage grid 120 and isolated gate 121.In order in the exposure process for forming photoresistIn, interference and scattering process of the figure to light make the selection to be formed to reduce the distortion of figure in photoresist in reduction light shieldGrid 110, storage grid 120 and 121 width of isolated gate are easy to control, and form the figure phase in light shield used in photoresistTogether, so that figure is identical in photoresist.Since figure is identical in the photoresist, when being performed etching to grid layer, lightFigure is identical to the barrier effect of etching reactant in photoresist, to keep the etch rate of grid layer identical, to make to be formedSelection gate 110, storage grid 120 it is identical with the width and thickness of isolated gate 121.
If the thickness of selection gate 110, storage grid 120 and isolated gate 121 is too small, 120 side of storage gridThe area of wall is smaller, causes the breakdown probability of dielectric layer 130 between storage grid 120 and the second source and drain plug 123 smaller, breakdownVoltage is higher, and the program voltage so as to cause the memory is higher, and the energy consumption of memory is larger；If selection gate 110 is depositedThe thickness for storing up grid 120 and isolated gate 121 is excessive, and the area of selection gate side wall is larger, leads to selection gate 110 and firstThe breakdown probability of dielectric layer 130 is larger between source and drain plug 112, and medium between selection gate 110 and the second source and drain plug 122The breakdown probability of layer 130 is larger, and the stability so as to cause the memory is poor.
To solve the technical problem, the present invention provides a kind of semiconductor structures, comprising: substrate, the substrate includeMemory block；The thickness of discrete selection gate and storage grid on the memory block substrate, the storage grid is greater than instituteState the thickness of selection gate；The first source and drain doping area and the second source and drain in the substrate of selection gate two sides memory block are mixedMiscellaneous area, second source and drain doping area is between the selection gate and storage grid.The thickness of the storage grid is larger,The area of storage grid side wall can be increased, so that the breakdown for increasing dielectric layer between storage grid and the second source and drain plug is generalRate, and then the program voltage of formed memory is reduced, reduce the power consumption of memory；The thickness of the selection gate is smaller, energyEnough reduce the area of selection gate side wall, so that the breakdown probability of dielectric layer between selection gate and the first source and drain plug is reduced,And then improve the performance for forming storage.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present inventionSpecific embodiment be described in detail.
Fig. 2 to Figure 10 is the structural schematic diagram of each step of one embodiment of forming method of memory of the invention.
In the present embodiment, it is formed by OTP (One Time Programmable, one-time programming) memory of memory.
Referring to FIG. 2, providing substrate 200, the substrate 200 includes memory block I.
The memory block I is used to form the storage unit of memory.
In the present embodiment, also there is fin (not shown) on the substrate 200.In other embodiments, the liningCan also not have the fin on bottom.
In the present embodiment, the substrate 200 includes multiple memory block I, has isolated area II between the I of adjacent storage zones.
The isolated area II is for realizing the isolation between the I of adjacent storage zones.
The forming method further include: storage well region is formed in the memory block I substrate 200, in the isolated area IIMiddle formation isolation well region.
There is the first ion in the device well region, there is the second ion in the isolation well region.
In the present embodiment, the storage unit that adjacent storage zones I is formed is electrically connected to each other, first ion and the second ionConduction type it is identical.In other embodiments, the storage unit that adjacent storage zones are formed mutually is not connected to, first ionIt is opposite with the conduction type of the second ion.
It is subsequently formed dielectric layer, discrete selection gate and storage grid, the first source and drain doping area and the second source and drain dopingArea, the dielectric layer are located on the substrate 200, and the selection gate and storage grid are located at the memory block I substrate 200On, the dielectric layer covers the storage grid and selection gate side wall, and the thickness of the storage grid is greater than the selection gridThe thickness of pole, the first source and drain doping area and the second source and drain doping area are located at the memory block I substrate of the selection gate two sidesIn 200, second source and drain doping area is between the selection gate and storage grid.
The first source and drain plug is electrically connected for realizing the first source and drain doping area and external circuit；Second source and drainDielectric layer between plug, storage grid and the second source and drain plug and storage grid constitutes antifuse device, and the second source and drain is insertedPlug and storage grid respectively constitute two electrodes of antifuse device.
The selection gate with a thickness of selection gate along perpendicular to the size in 200 surface direction of substrate, the storageGrid with a thickness of storage grid along perpendicular to the size in 200 surface direction of substrate.
In the present embodiment, the technique for forming the selection gate and storage grid is rear grid technique.The dielectric layer includes:Cover the isolation structure of the storage grid and selection gate side wall；Positioned at the storage grid, selection gate and isolation structureOn first medium layer.
In the present embodiment, the memory further include: the isolated gate on the isolated area II substrate 200；It is located atDummy grid on the memory block I substrate 200, the dummy grid is between the selection gate and storage grid, the puppetThe width of grid is greater than or equal to the width of the selection gate, and is less than the width of the storage grid, second source and drainDoped region is between the dummy grid and the storage grid；The substrate between the dummy grid and the selection gateThird source and drain doping area in 200, third source and drain doping area is electrically connected with second source and drain doping area.In other implementationsIn example, the memory can not also include one or both of the isolated gate and dummy grid.The memory may be used alsoNot include third source and drain doping area.
The dummy grid with a thickness of dummy grid along perpendicular to the size on the substrate surface direction.
In the present embodiment, the isolation structure, selection gate, storage grid, isolated gate, dummy grid and dielectric layer are formedThe step of it is as shown in Figures 3 to 6.
It is subsequent that discrete initial storage grid and initial selected grid are formed on the memory block I substrate 200, at the beginning of describedThe width of beginning storage grid is greater than the width of the initial selected grid.
The width of the initial storage grid is the initial storage grid along perpendicular to initial storage gate lateral wall sideUpward size；The width of the initial selected grid is the selection gate along perpendicular to the initial selected gate lateral wallSize on direction.
In the present embodiment, the step of forming the initial storage grid, initial selected grid and isolation structure such as Fig. 3 are to schemingShown in 5.
Referring to FIG. 3, forming first grid layer on the substrate 200；The first grid layer is patterned, shapeAt sacrifice storage grid 230 and sacrifice selection gate 210.
The first grid layer, which is used to form, sacrifices storage grid 230 and sacrifice selection gate 210；The sacrifice stores gridPole 230 is used to provide space to be subsequently formed initial storage grid 231；The sacrifice selection gate 210 is used to be subsequently formedInitial selected grid 211 provides space.
In the present embodiment, after being patterned to the first grid layer, is formed also on the substrate 200 and sacrifice puppetGrid 220.In other embodiments, dummy grid is not formed, then after graphical, the sacrifice dummy grid can not be formed.
The sacrifice dummy grid 220 stores light mask image to selection gate 212 for reducing in post-exposure treatment processThe influence of size.
In the present embodiment, the patterned step includes: offer light shield, and the light shield includes storage light mask image, choosingLight mask image and pseudo- light mask image are selected, the storage light mask image is corresponding with storage grid 230 is sacrificed, the selection light mask imageCorresponding with selection gate 210 is sacrificed, the puppet light mask image is corresponding with dummy grid 220 is sacrificed；The shape on the first grid layerAt initial light photoresist；Processing is exposed to the initial light photoresist by the light shield, forms photoresist；With the photoresistIt is exposure mask to the first grid layer, performs etching.
In the present embodiment, the width of sacrificed storage grid 230 is greater than the width for sacrificing selection gate 210.It is describedThe width for sacrificing dummy grid 220 is equal with the sacrifice width of selection gate 210.In other embodiments, the sacrifice is pseudo-The width of grid can be greater than the width for sacrificing selection gate, and be less than the width for sacrificing storage grid.
The width for sacrificing storage grid 230 is the sacrifice storage grid 230 along perpendicular to sacrifice storage gridSize in 230 sidewall directions；The width for sacrificing selection gate 210 is the selection gate 210 along perpendicular to describedSacrifice the size in 210 sidewall direction of selection gate；The width for sacrificing dummy grid 220 is to sacrifice dummy grid 220 along verticalSize in sacrifice 220 sidewall direction of dummy grid.
If the width for sacrificing storage grid 230 is too small, it is unfavorable for reducing in subsequent gate etching process, sacrifice is depositedThe etch rate of grid 230 is stored up, to be unfavorable for the thickness of storage grid 232 after increasing, and then is unfavorable for reducing memoryProgram voltage.In the present embodiment, the width of the storage grid 232 is greater than 0.1 μm.
If the width for sacrificing selection gate 210 is excessive, it is unfavorable for improving in subsequent gate etching process, sacrifices choosingThe etch rate for selecting grid 210 is unfavorable for reducing the thickness of selection gate 212, thus be easy to make subsequent selection gate 212 withDielectric layer between first source and drain plug or third source and drain plug be easy it is breakdown, to influence the stability of memory.Specifically, in the present embodiment, the width for sacrificing selection gate 210 is less than 0.05 μm.
It should be noted that the width for sacrificing dummy grid 220 is equal with the sacrifice width of selection gate 210,Then the width of the storage light mask image is equal with the selection width of light mask image.In the exposure process, the puppetLight mask image can reduce influence of the storage light mask image to 210 size of selection gate is sacrificed.The width for sacrificing dummy grid 220Degree is equal with the sacrifice width of selection gate 210, can reduce and scheme in photoresist corresponding with the selection light mask imageThe distortion of shape, so as to accurate 212 width of control selections grid.
In addition, the width of sacrificed storage grid 230 is greater than the width for sacrificing selection gate 210, light shield figure is storedShape width is greater than the width of the selection light mask image.The width for storing light mask image is larger, then in exposure process, stores light shieldFigure is smaller to the derivative and interference effect of light, to be not easy to cause figure in photoresist corresponding with storage light mask imageDistortion is formed by the precision for sacrificing 230 width of storage grid so as to improve.
It is subsequently formed and covers the isolation structure sacrificed 230 side wall of storage grid and sacrifice 210 side wall of selection gate；?The first source and drain doping area and the second source and drain doping area are formed in the memory block I substrate 200, second source and drain doping area is located atBetween the sacrifice selection gate and sacrifice storage grid.
In the present embodiment, the isolation structure includes: the covering sacrifice storage grid 210 and sacrifices selection gate 230The side wall of side wall；Second dielectric layer on the substrate 200, the second dielectric layer 252 cover the side wall side wall.
Specifically, forming the step of the isolation structure, the first source and drain doping area and the second source and drain doping area in the present embodimentIt is rapid as shown in Figure 3 and Figure 4.
With continued reference to Fig. 3, the covering side wall 251 sacrificed storage grid 230 and sacrifice selection gate 210 is formed.
When the side wall 251 is used for subsequent etching dielectric layer, protection storage grid 232 and sacrifice grid.
The step of forming side wall 251 includes: in the sacrifice storage grid 230, sacrifices selection gate 210, sacrificeSide wall layer is formed on dummy grid 220 and sacrifice 240 side wall of isolated gate and top and the substrate 200；Remove the sacrificeStorage grid 230 sacrifices selection gate 210, sacrifices dummy grid 220 and sacrifice on 240 top of isolated gate and the substrate 200Side wall layer, formed side wall 251.
The side wall 251 is not identical as the material for the second dielectric layer being subsequently formed, and with the first medium that is subsequently formedMaterial it is not identical.
In the present embodiment, the material of the side wall 251 is silicon nitride.In other embodiments, the material of the side wall is alsoIt can be silicon oxynitride or silica.
Referring to FIG. 4, being formed after the side wall 251, respectively in the memory block I substrate of 212 two sides of selection gateThe first source and drain doping area 281 and the second source and drain doping area 283 are formed in 200, second source and drain doping area 283 is located at the choosingIt selects between grid 212 and storage grid 232.
In the present embodiment, also has on the memory block I substrate 200 and sacrifice dummy grid 220.The forming method is also wrappedIt includes: forming third source and drain in the sacrifice storage grid 230 and the memory block I substrate 200 sacrificed between dummy grid 220Doped region 282.
In the present embodiment, third source and drain doping area 282, the second source and drain doping area 283 and the first source and drain doping are formedThe step of area 281 includes: the photoresist to be formed and cover the isolated area II substrate 200 and sacrifice isolated gate 240；With the lightPhotoresist, sacrifice selection gate 210, sacrifice storage grid 230 and sacrifice dummy grid 220 be exposure mask, to the substrate 200 carry out fromSon injection, injects source and drain ion in substrate 200, forms first source and drain doping area 281,283 and of the second source and drain doping areaThird source and drain doping area 282.
In other embodiments, it is formed and states third source and drain doping area, the second source and drain doping area and the first source and drain doping areaStep includes: the photoresist to be formed and cover the isolated area substrate and sacrifice isolated gate；With the photoresist, sacrifice selection gridPole sacrifices storage grid and sacrifices dummy grid for exposure mask, performs etching to the substrate, the substrate in the selection gate two sidesIn be respectively formed the first groove and third groove, the third groove between the dummy grid and the selection gate,The second groove is formed in substrate between the dummy grid and the storage grid；The first source and drain is formed in first groove to mixDiamicton；The second source and drain doping area is formed in second groove；Third source and drain doping area is formed in the third groove.
The source and drain ion is P-type ion or N-type ion.The P-type ion includes boron ion or BF2+One of or twoKind combination.The N-type ion includes: one of phosphonium ion, arsenic ion or antimony ion or multiple combinations.
Referring to FIG. 5, forming second dielectric layer 252 on the substrate 200, the second dielectric layer 252 covers describedIt sacrifices storage grid 230 and sacrifices 210 side wall of selection gate, and expose the sacrifice storage grid 230 and sacrifice selection grid210 top of pole.
The storage grid 232 and sacrifice the electric isolution between grid that the second dielectric layer 252 is used to be subsequently formed.
In the present embodiment, the second dielectric layer 252 also covers the sacrifice dummy grid 220 and sacrifices isolated gate 240Side wall.
In the present embodiment, the material of the second dielectric layer 252 is silica, silicon oxynitride or low k dielectric materials.It is describedThe dielectric constant of low k dielectric materials is less than 3.9.
The step of forming second dielectric layer 252 includes: in the substrate 200, sacrifices storage grid 230, sacrifice choosingIt selects grid 210, sacrifice isolated gate 240 and sacrifices and form initial second dielectric layer on dummy grid 220；It is situated between to described initial secondMatter layer carries out the first planarization process, removes the sacrifice storage grid 230, sacrifices selection gate 210, sacrifices isolated gate240 and sacrifice dummy grid 220 on initial second dielectric layer, formed second dielectric layer 252.
In the present embodiment, the technique for forming the initial second dielectric layer includes fluid chemistry gas-phase deposition.FluidThe gap-filling properties for the initial second dielectric layer that chemical vapor deposition process is formed is good, so as to increase second dielectric layer252 isolation performance.In other embodiments, the technique for forming the initial second dielectric layer includes high-aspect-ratio deposition workSkill.
The technique of first planarization process includes chemical mechanical grinding.
The isolation structure includes the second dielectric layer 252 and the side wall 251.
Referring to FIG. 6, the removal sacrifice selection gate 210, forms the first opening in the isolation structure；Removal instituteIt states and sacrifices storage grid 230, form the second opening in the isolation structure；Initial storage grid are formed in second openingPole 231；Initial selected grid 211 is formed in first opening.
Second opening is for accommodating the initial storage grid 231, and first opening is for accommodating initial selectedGrid 211.The initial storage grid 231 is for being subsequently formed storage grid 232, after the initial selected grid 211 is used forIt is continuous to form selection gate 212.
The forming method further include: the removal sacrifice dummy grid 220 forms third in the isolation structure and opensMouthful；The sacrifice isolated gate 240 is removed, forms the 4th opening in the isolation structure；It is formed in third openingInitial dummy grid 221；Initial isolated gate 241 is formed in the 4th opening.
Form the initial selected grid 211, initial storage grid 231, initial isolated gate 241 and initial dummy grid221 the step of includes: in first opening, the second opening, third opening and the 4th opening and on the isolation structureForm metal layer；Second planarization process is carried out to the metal layer, removes the metal layer on the isolation structure.
The material of the metal layer is Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
The technique of second planarization process includes chemical mechanical grinding.
It should be noted that second planarization process keeps the layer on surface of metal flat, thus the storage grid232, selection gate 212, dummy grid 222 are identical with the thickness of isolated gate 242.
The storage grid 232 with a thickness of storage grid 232 along perpendicular to the size in 200 surface direction of substrate；InstituteState selection gate 212 with a thickness of selection gate 212 along perpendicular to the size in 200 surface direction of substrate；The dummy grid 222With a thickness of dummy grid 222 along perpendicular to the size in 200 surface direction of substrate；The isolated gate 242 with a thickness of isolationGrid 242 is along perpendicular to the size in 200 surface direction of substrate.
Referring to FIG. 7, carrying out grid etch, removal to the initial storage selection gate 231 and initial selected grid 211The initial storage grid 231 of segment thickness forms storage grid 232, and removes the initial selected grid 211 of segment thickness, shapeAt selection gate 212, the thickness of the initial storage grid 231 of removal is less than the thickness of the initial selected grid 211 of removal.
The grid etch is used to make the thickness of the storage grid 232 to be greater than 212 thickness of selection gate.It is described to depositThe larger area that can increase by 232 side wall of storage grid of thickness for storing up grid 232, to increase storage grid 232 and subsequent shapeAt the second source and drain plug between dielectric layer breakdown probability, and then reduce the program voltage of formed memory, reduction storesThe power consumption of device；The thickness of the selection gate 212 is smaller, can reduce the area of 212 side wall of selection gate, to reduce selectionThe breakdown probability of dielectric layer between grid 212 and the first source and drain plug being subsequently formed, and reduce selection gate 212 and secondThe breakdown probability of dielectric layer between source and drain plug, and then improve the performance for forming storage.
It should be noted that the width of the initial storage grid 231 is greater than the initial selected grid in the present embodiment211 width.It is described initial during carrying out grid etch to the initial storage grid 231 and initial selected grid 211The polymerization that 231 surface of storage grid is formed is more, and the polymer is easily reduced the etch rate of initial storage grid 231, fromAnd cause the etch rate of the initial storage grid 231 greater than the etch rate of the initial selected grid 211.Therefore, instituteState the width that forming method can make the thickness of the storage grid 232 be greater than the selection gate 212.The initial storage gridThe width of pole 231 is greater than the width of the initial selected grid 211, can be to initial storage grid 231 and initial selected grid211 are performed etching by same technique, to form selection gate 212 and storage grid 232.Therefore, the forming method energyEnough simplification of flowsheet.
It in the present embodiment, is formed after the isolation structure, to the initial storage grid 231 and initial selected grid211 carry out grid etch.After the initial storage grid 231 for then removing segment thickness, second is formed in the isolation structureGroove 293；After the initial selected grid 211 for removing segment thickness, the first groove 291 is formed in the isolation structure.
In the present embodiment, during the grid etch, also to the initial isolated gate 241 and initial dummy grid221 carry out grid etch, and the dummy grid 222 for removing segment thickness forms third groove 292, remove the initial isolation of segment thicknessGrid 241 forms the 4th groove 294 in the isolation structure.
In the present embodiment, the technique of the grid etch includes: dry etch process.Dry etch process has goodLine width control, can relatively easily control the thickness of the storage grid 232.In other embodiments, the grid etchTechnique can also be the combination of wet-etching technology or dry method, wet-etching technology.
If the thickness for removing the initial storage grid 231 and initial selected grid 211 is excessive, it is easy to cause described depositThe thickness for storing up grid 232 and selection gate 212 is too small, and the thickness of storage grid 232 is too small, is unfavorable for increasing storage grid 232The area of side wall, and then be unfavorable for reducing the program voltage of memory；If the initial storage grid 231 of removal and initialThe thickness of selection gate 211 is too small, is easy to cause the thickness of the storage grid 232 excessive, to be easy to make storage grid 232Dielectric layer between storage plug or third source and drain plug 262 is breakdown, reduces the performance of memory.Specifically, this implementationExample in, the initial storage grid 231 of removal with a thickness of 15nm~18nm；The thickness of the initial selected grid 211 of removalFor 25nm~31nm.
Referring to FIG. 8, being formed in first groove 291 (as shown in Figure 7) and the second groove 293 (as shown in Figure 7)Protective layer 253.
During the protective layer 253 is used for subsequent etching dielectric layer, the storage grid 232 and selection gate are protected212, reduce the loss of storage grid 232 and selection gate 212.
The material of the protective layer 253 is not identical as the material of the dielectric layer.
In the present embodiment, the material of the isolation structure is silica.The material of the protective layer 253 is silicon nitride or nitrogenAoxidize SiClx.In other embodiments, the isolation structure is low k dielectric materials, and the material of the protective layer can be oxidationSilicon.
In the present embodiment, also there is protective layer 253 in the 4th groove 294 and third groove 292.
The step of forming protective layer 253 includes: in first groove 291, the second groove 293, the 4th groove 294Initial protective layers are formed in third groove 292 and on the isolation structure；It is flat that third is carried out to the initial protective layersChange processing, removes the initial protective layers on the isolation structure, forms protective layer 253.
The technique for forming the initial protective layers includes chemical vapor deposition process, physical gas-phase deposition or atomic layerDepositing operation.
The technique of the third planarization process includes chemical mechanical grinding.
It should be noted that in other embodiments, the protective layer can not also be formed.
Referring to FIG. 9, forming first medium layer 260 on the storage grid 232, selection gate 212 and isolation structure.
The first medium layer 260 is for realizing the second source and drain plug, the second grid plug, the first source and drain being subsequently formedElectric isolution between plug and first grid plug.
In the present embodiment, the first medium layer 260 is located on the protective layer 253.
In the present embodiment, the material of the first medium layer 260 is silica.In other embodiments, described first is situated betweenThe material of matter layer can also be low k dielectric materials or organic dielectric material.
In the present embodiment, the technique for forming the first medium layer 260 includes that chemical vapor deposition process, physical vapor are heavyProduct technique or atom layer deposition process.In other embodiments, the material of the first medium layer is organic dielectric material, is formedThe technique of the first medium layer includes spin coating proceeding.
Figure 10 to Figure 12 is please referred to, Figure 10 is subsequent step schematic diagram on the basis of Fig. 9, and Figure 12 (is not shown in Figure 12The dielectric layer and protective layer) be Figure 10 top view, Figure 10 is sectional view of the Figure 12 along cutting line 1-2, and Figure 11 is the edge Figure 12The sectional view of cutting line 3-4, forms the first source and drain plug 261 and the second source and drain plug 263 in the dielectric layer, and described firstSource and drain plug 261 is electrically connected with first source and drain doping area 281, and the second source and drain plug 263 is mixed with second source and drainMiscellaneous area 283 is electrically connected.
The first source and drain plug 261 is electrically connected for realizing the first source and drain doping area 281 and external circuit.DescribedTwo source and drain plugs 263, storage grid 232 and the medium between the second source and drain plug 263 and storage grid 232Layer formation capacitor.When being programmed memory, make to have between the second source and drain plug 263 and storage grid 232Biggish voltage difference makes second to keep the dielectric layer between the second source and drain plug 263 and storage grid 232 breakdownDielectric layer resistance decline between source and drain plug 263 and storage grid 232, and then realize programming.
In the present embodiment, the forming method further include: third source and drain plug 262 is formed in the dielectric layer, it is describedThird source and drain plug 262 is electrically connected with third source and drain doping area 282；Isolation plug 264, institute are formed in the dielectric layerState the substrate 200 between isolation plug 264 connection isolated gate 242 and storage grid 232.
The third source and drain plug 262 be used for the connecting line that is subsequently formed for realizing the second source and drain doping area 283 withElectrical connection between third source and drain doping area 282.
Form the first source and drain plug 261, the second source and drain plug 263, third source and drain plug 262 and isolation plug 264The step of include: to be performed etching to the dielectric layer, respectively in the dielectric layer formed selection contact hole, storage contact hole,Pseudo- contact hole and isolation contact hole；In the selection contact hole, storage contact hole, pseudo- contact hole and isolation contact hole, andPlug metal layer is formed on the dielectric layer；Remove the plug metal layer on the dielectric layer.
The isolation plug 264 is used to improve the homogeneity of the technique performed etching to dielectric layer, to guarantee the choosingThe precision of contact hole, storage contact hole and pseudo- contact pore size is selected, and then improves the first source and drain plug 261, the second source and drain plug263 and 262 size of third source and drain plug precision.
It should be noted that forming the selection contact hole by Self-aligned etching technique, storage contacts in the present embodimentHole, pseudo- contact hole and isolation contact hole.During performing etching to the dielectric layer, the protective layer 253 can be to instituteStorage grid 232, selection gate 212, isolated gate 242 and dummy grid 222 is stated to be protected, thus reduce storage grid 232,The loss of selection gate 212, isolated gate 242 and dummy grid 222.
In the present embodiment, the first source and drain plug 261, the second source and drain plug 263, isolation plug 264 and third source and drainThe material of plug 262 is copper, aluminium or tungsten.
The forming method further include: form the first grid plug 271 for connecting the selection gate 212；Form connectionThe second grid plug 272 of the storage grid 232.
The first grid plug 271 is electrically connected for realizing selection gate 212 and external circuit.The second gridPlug 272 is electrically connected for realizing storage grid 232 and external circuit.
In the present embodiment, the material of the second grid plug 272 and first grid plug 271 is copper, aluminium or tungsten.
0 to Figure 12 is continued to refer to figure 1, forms connecting line 270 on the dielectric layer, the connecting line 270 connects describedThird source and drain plug 262 and the second source and drain plug 263.
The connecting line 270 is for realizing being electrically connected between third source and drain plug 262 and the second source and drain plug 263It connects, to realize being electrically connected between the second source and drain doping area 283 and third source and drain doping area 282.
In the present embodiment, the material of the connecting line 270 is aluminium.In other embodiments, the material of the connecting line is alsoIt can be copper.
Figure 13 to Figure 16 is the structural schematic diagram of each step of another embodiment of forming method of memory of the invention.
This will not be repeated here for the something in common of the forming method of memory described in the present embodiment and Fig. 2 to Figure 12, differentPlace is as shown in figure 13 to figure 16.
Figure 13 is please referred to, Figure 13 is subsequent step schematic diagram on the basis of Fig. 2, the shape on the memory block I substrate 200At discrete sacrifice storage grid 330 and sacrifice selection gate 210.
It is described to sacrifice storage grid 330 and of same size, the memory block I substrate 200 for sacrificing selection gate 210It is upper not have sacrifice dummy grid 220.
It forms the sacrifice storage grid 330 and includes: to form the on substrate 200 the step of sacrificing selection gate 210One grid layer；The first grid layer is patterned, the sacrifice storage grid 330 is formed and sacrifices selection gate 210.
The patterned step includes: to form photoresist on the first grid layer；Light shield is provided, in the light shieldWith selection figure and storage figure, the selection figure is corresponding with the selection gate 212, and the storage figure is deposited with describedIt is corresponding to store up grid 232；Processing is exposed to the photoresist by the light shield, forms storage exposure in the photoresistFigure and selection exposure figure, the storage exposure figure is corresponding with storage figure, the selection exposure figure and the selectionFigure is corresponding.
The sacrifice storage grid 330 is of same size with sacrifice selection gate 210, then the selection figure and storage are schemedThe size of shape is identical.In the exposure process, selection figure can be reduced and store influencing each other between figure and drawnThe distortion of the storage exposure figure and selection exposure figure that rise sacrifices storage grid 330 so as to accurately control to be formed byWidth with selection gate 210 is sacrificed, and then can accurately control the width of the storage grid and selection gate that are subsequently formed.
In addition, due to the sacrifice storage grid 330 and sacrificing the of same size of selection gate 210, do not need to be formed sacrificialDomestic animal dummy grid.Therefore, the memory does not have dummy grid, so as to reduce the volume of formed memory, improves storageThe integrated level of device.
Figure 14 is please referred to, forms isolation structure on the substrate 200；The sacrifice selection gate 210 is removed, describedThe first opening is formed in isolation structure；The sacrifice storage grid 220 is removed, forms the second opening in the isolation structure；Initial selected grid 211 is formed in first opening；Initial storage grid 331 is formed in second opening.
Figure 15 is please referred to, the first etching is carried out to the initial storage grid 331, removes the initial storage grid of segment thicknessPole 331, formed storage grid 332, the initial storage grid 331 of removal with a thickness of first thickness.
In the present embodiment, described first etches the thickness for reducing the initial storage grid 331, in the dielectric layerThe second groove 293 of middle formation.
The step of carrying out the first etching to the initial storage grid 331 includes: the shape on the initial selected grid 211At the first photoetching compared with 311；It is that exposure mask carries out the first etching with first photoresist 311.
In the present embodiment, first photoresist 311 also covers the isolated gate 241.
In the present embodiment, the technique of first etching includes dry etch process.Dry etch process has goodLine width control, can relatively easily control the thickness of the storage grid 332.In other embodiments, it is described first etchingTechnique can also be wet-etching technology.
Figure 16 is please referred to, the second etching is carried out to the initial selected grid 211, removes the initial selected grid of segment thicknessPole 211, formed selection gate 212, the initial selected grid 211 of removal with a thickness of second thickness, the second thickness is less thanFirst thickness.
In the present embodiment, described second etches the thickness for reducing the initial selected grid 211, in the dielectric layerThe first groove 291 of middle formation, first groove 291 are used for subsequent receiving protective layer.
The step of carrying out the first etching to the initial selected grid 211 includes: that the is formed in the storage grid 332Two photoetching are compared with 312；It is that exposure mask carries out the second etching with second photoresist 312.
In the present embodiment, second photoresist 312 also covers the isolated gate 241.
In the present embodiment, the technique of second etching includes dry etch process.Dry etch process has goodLine width control, can relatively easily control the thickness of the selection gate 212.In other embodiments, it is described second etchingTechnique can also be wet-etching technology.
It should be noted that above embodiments are that the present invention will be described for later grid technique, in other realitiesIt applies in example, the material of the storage grid and selection gate is polysilicon, polycrystalline germanium or polycrystalline silicon germanium.In another embodiment alsoThe memory can be formed by preceding grid technique.
The something in common of the present embodiment and Fig. 2 to embodiment illustrated in fig. 12 does not repeat herein, the difference is that:
The step of forming the initial storage grid, initial selected grid includes: to form second grid over the substrateLayer；The second grid layer is patterned, the initial storage grid and initial selected grid are formed；Form initial storageAfter grid and initial selected grid, second source and drain doping area and the first source and drain doping area are formed.
In the present embodiment, formed after the second dielectric layer, to the initial storage grid and initial selected grid intoRow grid etch forms storage grid and selection gate.
In other embodiments, the first etching can also be carried out to the initial storage grid, remove the first of segment thicknessBeginning storage grid forms storage grid；Second etching is carried out to the initial selected grid, removes the initial selected of segment thicknessGrid forms selection gate.
In the present embodiment, is formed after second dielectric layer, remove the initial selected grid and initial storage grid of segment thicknessPole.In embodiment, forms selection gate and the step of storage grid includes: the removal portion before forming second dielectric layerDivide initial selected grid and initial storage grid.Before removing part initial selected grid and initial storage grid, in the choosingSelect grid and substrate that storage grid exposes on form graph layer.The graph layer is used in removal part initial selected gridDuring initial storage grid, substrate is protected.
0 to Figure 12 is continued to refer to figure 1, the embodiment of the present invention also provides a kind of memory, comprising: substrate 200, the substrate200 include memory block I；Discrete selection gate 212 and storage grid 232 on the memory block I substrate 200, it is describedThe thickness of storage grid 232 is greater than the thickness of the selection gate 212；Positioned at the 212 two sides memory block I substrate of selection gateThe first source and drain doping area 281 and the second source and drain doping area 283 in 200, second source and drain doping area 283 are located at the selectionBetween grid 212 and storage grid 232,200 electricity of second source and drain doping area 283 and 212 lower substrate of selection gateConnection；Dielectric layer on the memory block I substrate 200, the dielectric layer cover 232 side wall of storage grid and selection212 side wall of grid；The first source and drain plug 261 and the second source and drain plug 263 in the dielectric layer, first source and drain are inserted261 connection first source and drain doping area 281 of plug, the second source and drain plug 263 connect second source and drain doping area 283.
In the present embodiment, the memory further include: the dummy grid 222 on the memory block I substrate 200, it is describedFor dummy grid 222 between the selection gate 212 and storage grid 232, the width of the dummy grid 222 is greater than or equal to instituteThe width of selection gate 212 is stated, and is less than the width of the storage grid 232；Second source and drain doping area 283 is located at describedIn substrate 200 between dummy grid 222 and the storage grid 232；Positioned at the dummy grid 222 and the selection gate 212Between third source and drain doping area 282 in substrate 200, third source and drain doping area 282 and second source and drain doping area 283Electrical connection.In other embodiments, the memory can not also include the dummy grid (as shown in figure 15).
The width of the dummy grid 222 is dummy grid 222 along perpendicular to the ruler in 222 sidewall direction of dummy gridIt is very little；The width of the selection gate 212 is selection gate 212 along the 212 lower channels length direction of selection gateSize；The width of the storage grid 232 is storage grid 232 in the size along the 232 lower channels length of storage grid.
In the present embodiment, the memory further include: the third source and drain plug 262 in the dielectric layer, describedThree source and drain plugs 262 connect third source and drain doping area 282；Connecting line 270 on the dielectric layer, the connecting line270 connect the third source and drain plug 262 and the second source and drain plug 263.
In the present embodiment, the thickness of the dummy grid 222 is less than or equal to 212 thickness of selection gate.
In the present embodiment, the width of the storage grid 232 is greater than the width of the selection gate 212.In other implementationsIn example, the width of the storage grid 232 is equal to the width (as shown in figure 15) of the selection gate 212.
In the present embodiment, the width of the storage grid 232 is greater than 0.1 μm；The width of the selection gate 212 is less than0.05μm。
In the present embodiment, the memory further include: the protection in the selection gate 212 and storage grid 232Layer 253, the material of the protective layer 253 are silicon nitride, silica or silicon oxynitride.In other embodiments, the memoryIt can not include the protective layer.
The number of the memory block I be it is multiple, the substrate 200 further includes the isolated area between the I of adjacent storage zonesII；The memory includes: the isolated gate 242 on the isolated area II substrate 200.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from thisIt in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim instituteSubject to the range of restriction.