CN109449084B - A kind of dicing method of power chip and semiconductor device - Google Patents
A kind of dicing method of power chip and semiconductor deviceDownload PDFInfo
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- CN109449084B CN109449084BCN201811136919.8ACN201811136919ACN109449084BCN 109449084 BCN109449084 BCN 109449084BCN 201811136919 ACN201811136919 ACN 201811136919ACN 109449084 BCN109449084 BCN 109449084B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
Translated fromChinese
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a scribing method of a power chip and a semiconductor device.
Background
Insulated Gate Bipolar Transistor (IGBT) belongs to a voltage control type power electronic device, has the advantages of large input impedance, small driving power, simple control circuit, small switching loss, high switching speed, high working frequency, large element capacity, no absorption circuit and the like, and is widely applied to the fields of industrial current transformation, electric power traction and the like.
The direct current transmission technology can be used for long-distance large-capacity power transmission and power system networking, submarine cable power transmission and large-scale urban underground cable power transmission can be realized, and the direct current transmission technology is an important technical support for realizing energy optimal configuration and comprehensive utilization. In the High Voltage Direct Current (HVDC) transmission technology, a converter valve is required to be used as an electric energy conversion device to complete rectification of AC-DC and inversion of DC-AC, and an IGBT device becomes one of the most ideal semiconductor switching devices in a high voltage high power converter valve.
At present, a mechanical cutting mode of diamond grinding wheel scribing is mostly adopted in wafer scribing of a power chip. Because adopt mechanical stress to get rid of the scribing groove, lead to the chip positive and negative both sides edge after the scribing to produce and break up the limit, can cause the chip terminal protective layer on the one hand to break up and drop, the microcrack that on the other hand the scribing produced can expand to chip terminal inside along the chip edge, and then leads to chip terminal structure to destroy, leads to the withstand voltage inefficacy of chip.
Disclosure of Invention
In view of this, embodiments of the present invention provide a dicing method for a power chip and a semiconductor device, so as to solve the problem in the prior art that edge chipping occurs at edges of front and back sides of a diced chip due to dicing of the power chip by using a mechanical cutting method.
According to a first aspect, an embodiment of the present invention provides a dicing method for a power chip, including the following steps: forming a scribing groove on a scribing channel position on the front surface of the wafer, wherein the scribing groove exposes the metal layer on the back surface of the wafer; filling a plastic packaging material in the scribing groove; and cutting the wafer by adopting a blade cutting mode to obtain a plurality of independent chips.
Optionally, before the step of forming the scribing grooves on the scribing street positions on the front surface of the wafer, the method further includes: covering photoresist on the front side of the wafer; and removing the photoresist on the scribing channels to expose the scribing channels.
Optionally, before the step of cutting the wafer by using a blade cutting method, the method further includes: and removing the photoresist on the front surface of the wafer.
Optionally, before the step of forming the scribing grooves on the scribing street positions on the front surface of the wafer, the method further includes: and covering the back surface of the wafer with a film layer.
Optionally, the step of forming a scribe line at a scribe lane position on the front surface of the wafer includes: and forming a scribing groove on the scribing channel position on the front surface of the wafer by adopting a plasma dry etching process.
Optionally, the top of the scribe line is larger than the bottom.
Optionally, an included angle between the sidewall of the scribing groove and the bottom of the wafer is 45 to 90 degrees.
Optionally, the sidewalls of the scribe line are serrated.
Optionally, the molding compound includes a polymer material having a coefficient of thermal expansion in a range of 6-7ppm/° c.
Optionally, the step of filling a plastic package material in the scribe line includes: and filling plastic packaging materials in the scribing groove by adopting a spraying mode.
According to a second aspect, the embodiment of the present invention provides a semiconductor device, which is prepared by using the dicing method for a power chip according to any one of the first aspect of the present invention.
The invention has the following advantages:
1. the scribing method of the power chip provided by the invention comprises the following steps: forming a scribing groove on a scribing channel position on the front surface of the wafer, wherein the scribing groove exposes the metal layer on the back surface of the wafer; filling a plastic packaging material in the scribing groove; and cutting the wafer by adopting a blade cutting mode to obtain a plurality of independent chips. According to the scribing method of the power chip, the scribing groove is firstly prepared on the front side of the wafer and extends to the metal layer on the back side of the wafer, so that the cutting strength of mechanical cutting by subsequently adopting diamond grinding wheel scribing can be greatly reduced; then, plastic packaging materials are filled in the scribing grooves, the side walls of the chips are protected by the plastic packaging materials, and the voltage-resistant grade of the chips is improved; finally, cutting the wafer by adopting a blade to obtain a plurality of independent power chips; the problem of among the prior art power chip adopt the mechanical cutting mode to carry out the scribing and lead to the chip tow sides edge after the scribing to produce and break out the limit is solved.
2. The semiconductor device provided by the invention is prepared by adopting the dicing method of the power chip. The semiconductor device adopts the scribing method of the power chip provided by the invention, so that the problem of edge breakage at the edges of the front side and the back side of the chip in the cutting process is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a specific example of a dicing method of a power chip in an embodiment of the present invention;
fig. 2 is a flowchart of another specific example of a dicing method of a power chip in an embodiment of the present invention;
fig. 3 is a flowchart of another specific example of a dicing method of a power chip in an embodiment of the present invention;
fig. 4 is a flowchart of another specific example of a dicing method of a power chip in the embodiment of the present invention;
FIGS. 5-11 are diagrams illustrating a specific step of a dicing method for a power chip according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a specific example of the semiconductor device in the embodiment of the present invention.
Reference numerals:
1. a power chip; 2. a wafer; 3. a metal layer; 4. photoresist; 5. scribing a street; 51. scribing a groove; 6. and (5) plastic packaging material.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The embodiment provides a scribing method for a power chip, which is applied to scribing of a power wafer, and a plurality of mutually independent power chips are obtained after scribing, for example, the power chips may be Insulated Gate Bipolar Transistors (IGBTs), Fast Recovery Diodes (FRDs), and the like, so that the problem that edge breakage occurs at edges of the front and back sides of the scribed chips due to scribing of the power chips by using a mechanical cutting method in the prior art is solved.
Fig. 1 is a flowchart of a specific example of a dicing method of a power chip in the present embodiment, and as shown in fig. 1, the dicing method includes the following steps S1-S3.
Step S1: and forming scribing grooves at the scribing path positions on the front surface of the wafer, wherein the scribing grooves expose the metal layer on the back surface of the wafer. The scribing groove extends to the metal layer on the back of the wafer, and the substrate at the scribing channel position of the wafer is removed, so that subsequent scribing is facilitated.
In the process of manufacturing the power chips, firstly, the front side of the wafer is finished with the integrated circuit, then, metal is prepared (for example, by adopting an evaporation method) on the back side of the wafer, then, electrodes are led out from the back side, and then, the wafer is diced to form the individual power chips. For example, for an IGBT power chip, the emitter and gate are located on the front side of the wafer, and the collector is located on the metal layer on the back side of the wafer.
The scribing channels are reserved scribing cutting positions between adjacent chips on the wafer, and the wafer is cut at the scribing channels in the wafer scribing process, so that a plurality of power chips are obtained.
In an alternative embodiment, step S1 may use a plasma dry etching process to form scribe grooves on the scribe line positions on the front surface of the wafer. The side wall section of the scribing groove formed by adopting the plasma dry etching process is easy to control, and the etching process is simple and convenient to operate. Of course, in other embodiments, other preparation methods in the prior art may be used to form the scribe line, such as wet etching. When the plasma dry etching is carried out, due to the alternative implementation of etching gas, on one hand, the side wall of the formed scribing groove is in a sawtooth shape, and on the other hand, the included angle between the side wall of the scribing groove and the surface of the wafer is 45-90 degrees, which lays a foundation for the subsequent filling of plastic package materials.
In an alternative embodiment, the thickness of the wafer may be above 500 microns or even thicker; of course, in other embodiments, the thickness of the wafer may be set reasonably according to the requirement, and the dicing method may also be used for wafers smaller than 500um, which is not limited in this embodiment.
In an alternative embodiment, the top of the scribing groove is larger than the bottom, so that the preparation process of the scribing groove is simpler, and the subsequent mechanical cutting is facilitated; of course, in other embodiments, the shape of the scribing groove can be properly set as required, for example, the top of the scribing groove is equal to the bottom, or the top is smaller than the bottom, and the shape can be properly set as required.
In an optional embodiment, the included angle between the side wall of the scribing groove and the bottom of the wafer can be 45-90 degrees, and the preparation process is simple and easy to control; of course, in other embodiments, the included angle between the sidewall of the scribing groove and the bottom of the wafer may be set reasonably according to actual needs, which is not limited in this embodiment.
In an optional embodiment, the sidewall of the scribing groove is serrated, and the serrated sidewall reduces the fragment rate of the wafer in the etching process, so that the integrity of the wafer in the etching process is further ensured. Of course, in other embodiments, the shape of the sidewall of the scribing groove can be set reasonably according to actual needs, and those skilled in the art can set the shape of the sidewall reasonably according to the description of the embodiment.
Step S2: and plastic packaging materials are filled in the scribing grooves. Through the mode of removing the wafer substrate in the scribing channel and carrying out plastic package by using the plastic package material, the plastic package material is easy to perform blade scribing, so that the damage of scribing to a terminal is reduced on one hand, and on the other hand, the side wall which can be protected by adopting the plastic package material has the effect of isolating the diffusion of water vapor and the like to the chip, the pressure-resistant grade of the chip terminal is improved, and the reliability of subsequent chip package is improved
In an alternative embodiment, a plastic packaging material can be filled in the scribing groove by adopting a spraying mode, and the scribing groove is completely filled with the plastic packaging material, as shown in fig. 9, so that the preparation process is simple, and the production cost is low; of course, in other embodiments, the plastic package material may only cover the sidewall of the scribe line, and may be disposed correspondingly as needed. It should be noted that other methods in the prior art can be used to fill the plastic package material, and the plastic package material can be set reasonably as required.
In an alternative embodiment, the molding compound comprises a polymer material having a coefficient of thermal expansion in the range of 6-7 ppm/deg.C; the high polymer material with the thermal expansion coefficient within the range of 6-7 ppm/DEG C has stronger adhesive force and better adhesive force, so the high polymer material is not easy to fall off in the subsequent cutting process, and the side wall can be well protected. For example, the plastic packaging material can be common epoxy resin in the plastic packaging process, and the production cost is low. Of course, in other embodiments, other plastic package materials in the prior art can be adopted and reasonably selected according to needs.
Step S3: and cutting the wafer by adopting a blade cutting mode to obtain a plurality of independent chips.
In an optional embodiment, specifically, the plastic package material and the metal layer in the scribe grooves can be removed by cutting with a diamond grinding wheel blade, and finally, the material in the scribe lanes is completely removed to form a single power chip, and scribing is completed.
In an alternative embodiment, the power chip may be an IGBT or an FRD; of course, in other embodiments, the power chip may also be another type of power chip in the prior art, which is not limited in this embodiment.
According to the scribing method of the power chip, the scribing groove is firstly prepared on the front side of the wafer and extends to the metal layer on the back side of the wafer, so that the cutting strength of mechanical cutting by subsequently adopting diamond grinding wheel scribing can be greatly reduced; then, plastic packaging materials are filled in the scribing grooves, and the side walls of the chips are protected by the plastic packaging materials, so that the voltage-resistant grade of the chip terminals is improved, and the reliability of subsequent packaging of the chips is also ensured; and finally, cutting the wafer by adopting a blade to obtain a plurality of independent power chips. The scribing method solves the problem that in the prior art, the scribing of the power chip is carried out in a mechanical cutting mode, so that edge breakage is caused at the edges of the front side and the back side of the scribed chip.
In an alternative embodiment, as shown in fig. 2, the above-mentioned method for dicing a power chip further includes steps S4 and S5 before the step of forming a dicing groove at the dicing street position on the front surface of the wafer in step S1.
Step S4: and covering photoresist on the front surface of the wafer.
In an alternative embodiment, any method in the prior art (e.g., spin coating) may be used to form the photoresist covering the front surface of the wafer, the photoresist may be a positive photoresist or a negative photoresist, and the type of the photoresist may be appropriately selected according to the needs.
Step S5: and removing the photoresist on the scribing channels to expose the scribing channels.
In an optional embodiment, specifically, the reserved scribe line can be exposed by exposing and developing the photoresist through a mask plate; of course, other methods in the prior art can be adopted to remove the photoresist on the scribing path, and the photoresist can be reasonably arranged according to the requirement.
In another alternative embodiment, as shown in fig. 3, the above method for dicing a power chip further includes step S6 before the step of forming a dicing groove at the dicing street position on the front surface of the wafer in step S1.
Step S6: and covering the back surface of the wafer with a film layer.
Step S6 is to temporarily cover a thin film layer on the back side of the wafer before covering the photoresist on the front side of the wafer in step S4, wherein the thin film layer provides support for the wafer; and after scribing is finished, removing the thin film layer.
In an optional embodiment, the thin film layer may be a UV film, and in step S6, specifically, a UV film is applied to the back surface of thewafer 1, and the UV film may provide support for the wafer, and after scribing is completed, subsequent chip screening, chip picking and other operations may be performed through UV irradiation, so as to prevent scattering of single chips formed after scribing.
In another alternative embodiment, as shown in fig. 4, the method for dicing a power chip further includes a step S7 before the step of cutting the wafer by using a blade in the step S3.
Step S7: and removing the photoresist on the front surface of the wafer. The photoresist on the front surface of the wafer is removed before the wafer is cut, and the photoresist on a plurality of chips can be removed through one-time process, so that the process flow is saved, and the production cost is reduced. Specifically, any method in the prior art may be adopted to remove the photoresist, which is not limited in this embodiment, and the removal method may be reasonably selected according to the needs.
Fig. 5-11 are schematic diagrams illustrating a specific step of a dicing method for a power chip according to an embodiment of the present invention. The specific process is as follows: preparing awafer 2, wherein the front surface of thewafer 2 includes a plurality ofpower chips 1, the back surface of thewafer 2 is provided with ametal layer 3, andscribe lines 5 are formed between thepower chips 1, as shown in fig. 5. A layer ofphotoresist 4 is coated on the front surface of thewafer 2, as shown in fig. 6, please refer to step S4 for details. Thephotoresist 4 is exposed and developed to expose thereserved scribe lines 5, as shown in fig. 7, and the detailed process is shown in step S5. The front surface of thewafer 2 is dry etched by using plasma to expose themetal layer 3 on the back surface of thewafer 2 to form thescribe line 51, as shown in fig. 8, please refer to step S1 for details. Theplastic sealing material 6 is filled in thescribing groove 51 by using a plastic sealing process, as shown in fig. 9, please refer to step S2 for details. Thephotoresist 4 on the front surface of thewafer 2 is removed, as shown in fig. 10, please refer to step S7 for details. And (3) removing theplastic package material 6 and themetal layer 3 in thescribing groove 51 by cutting with a diamond grinding wheel blade, finally completely removing the material in thescribing street 5 to form asingle power chip 1, and completing scribing, as shown in fig. 11, please refer to step S3 for the detailed process.
In the prior art, the scribing is carried out by adopting a process mode of scribing by a diamond grinding wheel blade, and the following defects exist: because the scribing principle of the diamond grinding wheel blade is that the material in the scribing channel is removed through the mechanical stress generated by the high-speed rotation of the grinding wheel, edge breakage is inevitably generated on the front side and the back side of a wafer when the fragile material of a silicon wafer is scribed, and if the scribing process is not well controlled, the structure in the chip is damaged due to the overlarge edge breakage. When a diamond grinding wheel blade is used for scribing, defects such as edge breakage and the like after scribing are detected, however, microcracks which cannot be found through visual inspection are generated along with the edge breakage, and the generated microcracks can extend towards the interior of a chip in a way of being perpendicular to a scribing way in subsequent service, so that the terminal structure of the chip is damaged, and finally, the pressure resistance failure of the chip is caused. For high voltage and high power chips, the thickness of the wafer is usually over 500 μm or even thicker, and therefore, the problem of dicing is more serious.
Compared with the prior art, the scribing method of the power chip in the embodiment has the following advantages: the scribing method of the embodiment obviously improves the defects of edge breakage and the like caused by the conventional diamond grinding wheel scribing on the front and back surfaces of the wafer, and particularly edge breakage hardly occurs around the chip on the front surface of the wafer; micro cracks caused by scribing, which are difficult to find by visual inspection in the traditional scribing process of the diamond grinding wheel, are eliminated, and the service reliability of the power chip is greatly improved; the plastic packaging material is deposited on the slope-formed side wall morphology of the chip, so that the side wall of the chip is protected, the voltage-resistant grade of a chip terminal is improved, and the reliability of subsequent packaging of the chip is also ensured.
The embodiment also provides a semiconductor device prepared by adopting the dicing method of the power chip in any one of the above method embodiments. The invention obviously improves the defects of edge breakage and the like caused by the traditional diamond grinding wheel scribing on the front and back surfaces of the wafer, and particularly almost no edge breakage is generated around the chip on the front surface of the wafer.
Fig. 12 is a schematic structural diagram of a specific example of the semiconductor device in the embodiment of the present invention. As shown in fig. 12, the semiconductor device includes: the back of thepower chip 1 is covered with ametal layer 3, and the side wall of thepower chip 1 is covered with aplastic package material 6. For details, reference may be made to the related description in the method embodiment, and details are not repeated here.
In an optional embodiment, the power chip may be a silicon-based IGBT (double insulated gate transistor), an FRD (fast recovery diode), and the like, and may be reasonably set according to needs, which may specifically refer to the related description in the method embodiment.
In an alternative embodiment, the included angle between the side wall of the power chip and the bottom can be 45-90 degrees; reference is made in particular to the description relating to the method embodiments.
In an alternative embodiment, the side wall of the power chip is serrated; reference is made in particular to the description relating to the method embodiments.
In an optional embodiment, themolding compound 6 is a polymer material with a thermal expansion coefficient of about 6-7 ppm/deg.C, such as epoxy resin; reference is made in particular to the description relating to the method embodiments.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (9)
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| CN110208905A (en)* | 2019-05-24 | 2019-09-06 | 宁波东立创芯光电科技有限公司 | For improving the scribing etching of optical chip cut quality and the production method and optical chip of optical chip |
| CN110211885B (en)* | 2019-05-30 | 2021-08-06 | 全球能源互联网研究院有限公司 | Power chip pre-package, packaging method and structure thereof, wafer pre-package structure |
| CN112018027B (en)* | 2019-05-31 | 2024-08-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and wafer cutting method |
| CN110783327A (en)* | 2019-10-24 | 2020-02-11 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method and packaging structure |
| CN111170271A (en)* | 2019-12-30 | 2020-05-19 | 杭州臻镭微波技术有限公司 | Coordination method for chip cutting errors in embedded micro-system module |
| CN113161233A (en)* | 2020-12-30 | 2021-07-23 | 上海朕芯微电子科技有限公司 | Power device and scribing method thereof, chip-scale packaging method and packaging structure |
| CN114161591B (en)* | 2021-12-03 | 2023-06-02 | 江西省纳米技术研究院 | Nondestructive cleavage method of semiconductor chip |
| CN115050696A (en)* | 2022-05-27 | 2022-09-13 | 苏州聚谦半导体有限公司 | Wafer level chip packaging method |
| CN114986727A (en)* | 2022-06-27 | 2022-09-02 | 伯恩半导体(河南)有限公司 | Semiconductor wafer double-film cutting method |
| CN115295409A (en)* | 2022-07-20 | 2022-11-04 | 武汉光谷信息光电子创新中心有限公司 | Wafer scribing method |
| CN116207182B (en)* | 2023-01-29 | 2024-03-12 | 北京智创芯源科技有限公司 | Chip preparation method and electronic device |
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