Specific embodiment
" coupling (or connection) " word used in present disclosure specification full text (including claim) can refer to anyDirect or indirect connection means.For example, if it is described herein that first device coupling (or connection) then should in second deviceBe construed as the first device can be directly connected to the second device or the first device can by other devices or certainIt plants connection means and is coupled indirectly to the second device.In addition, all possible places, in the drawings and embodiments using identicalElement/component/step of label represents same or like part.Identical label is used in different embodiments or uses identical termElement/component/step can be with cross-referenced related description.
Fig. 1 is the circuit box (circuit according to a kind of display panel drive device 100 of one embodiment of the inventionBlock) schematic diagram.Display panel drive device 100 can drive display panel 10.According to design requirement, display panel 10 canTo be existing LCoS display panel, liquid crystal display panel or other display panels.When display panel drive device 100 includesSequence control circuit 110, memory 120, compensation circuit 130 and data drive circuit 140.
Fig. 2 is the flow diagram according to a kind of displaying panel driving method of one embodiment of the invention.Please refer to Fig. 1With Fig. 2.In step S210, the data that sequential control circuit 110 can provide multiple pixels of display panel 10 give compensation electricityRoad 130.For example, sequential control circuit 110 can be in step S210 by some current pixel in display panel 10Current pixel data be supplied to compensation circuit 130.According to design requirement, sequential control circuit 110 can be existing timingController or other pixel-data processing circuit/elements.In step S220, memory 120 can be provided in display panelAt least one coupled capacitor information between current pixel and at least one adjacent pixels in 10 is to compensation circuit 130.
Fig. 3 is the schematic diagram of the partial pixel of display panel 10 shown in Fig. 1 according to one embodiment of the invention.Display surfacePlate 10 include multiple pixels, such as pixel P1 shown in Fig. 3, pixel P2, pixel P3, pixel P4, pixel P5, pixel P6, pixel P7,Pixel P8 and pixel P9.The distance between two adjacent pixels/gap shown in Fig. 3 has been exaggerated.It is needed according to actual designIt asks, the distance between two adjacent pixels/gap is usually very small.There are coupled capacitors between two adjacent pixels(parasitic capacitance).For example, there are coupled capacitor C between pixel P2 and pixel P5P2P5, exist between pixel P4 and pixel P5Coupled capacitor CP4P5, there are coupled capacitor C between pixel P6 and pixel P5P6P5, and exist between pixel P8 and pixel P5 and couple electricityHold CP8P5, as shown in Figure 3.When pixel P5 is current pixel, memory 120 can provide in step S220 corresponds to couplingCapacitor CP2P5、CP4P5、CP6P5With CP8P5Coupled capacitor information to compensation circuit 130.
Compensation circuit 130 is coupled to sequential control circuit 110, to receive the current pixel data of current pixel P5.CompensationCircuit 130 is coupled to memory 120, to receive the coupled capacitor information.By using the coupled capacitor information, compensation electricityRoad 130 can compensate the current pixel data of current pixel P5 in step S230 and obtain compensated pixel data, to mendRepay the variation because of current pixel P5 caused by the coupled voltages of adjacent pixels P2, P4, P6 and P8.
Data drive circuit 140 be coupled to display panel 10 multiple pixels (such as current pixel P5 shown in Fig. 3 and otherPixel).Data drive circuit 140 is coupled to compensation circuit 130, to receive the compensated pixel data.In step S240,Data drive circuit 140 can remove the current pixel P5 of driving display panel 10 according to compensated pixel data.It is needed according to designIt asks, data drive circuit 140 can be existing data driver, existing source electrode driver or other driving circuit/membersPart.By considering that the voltage change of adjacent pixels, compensation circuit 130 can change the pixel data (example of current pixel P5 in advanceSuch as grayscale value).By way of pre-compensation, display panel drive device 100 can effectively reduce the voltage error of pixel.
For example, in some embodiments, by using the coupled capacitor information, and by using current pixelGrey scale between (such as pixel P5 shown in Fig. 3) and adjacent pixels (such as pixel P2, P4, P6 or P8 shown in Fig. 3), compensation electricityRoad 130 can compensate current pixel data and obtain compensated pixel data.For convenience of explanation, white with normality hereinIllustrative example of the LCoS display panel of (Normally white) as display panel 10, but the embodiment of display panel 10It is not limited to this.
Fig. 4 is the schematic diagram of the dipole inversion of the signal of display panel 10 shown in Fig. 1 according to one embodiment of the invention.Horizontal axis shown in Fig. 4 indicates the time, and the longitudinal axis indicates voltage.In embodiment illustrated in fig. 4, the common voltage VCOM of display panel 10 canTo be alternating voltage.For example, common voltage VCOM is in previous frame FN-1In can be low-voltage (such as 0V), therefore previouslyFrame FN-1It is positive polarity.Present frame F is arrivedNIn, common voltage VCOM can be changed into high voltage (such as 6V), therefore present frame FNIt is negative polarity.Remaining frame is referred to previous frame FN-1With present frame FNRelated description analogize, so it will not be repeated.
In embodiment illustrated in fig. 4, it is 8 bit Datas that pixel data, which is assumed, therefore the grey-scale range of pixel data is 0~255.If the grayscale of pixel data is 0, corresponding gray scale voltage is VGMA (0).If the grayscale of pixel data is 128,Then corresponding gray scale voltage is VGMA (128).If the grayscale of pixel data is 255, corresponding gray scale voltage is VGMA(255).Voltage difference (that is, pixel voltage maximum magnitude) between gray scale voltage VGMA (0) and gray scale voltage VGMA (255) isVGR, as shown in Figure 4.
Referring to figure 3. with Fig. 4.Assuming that the grayscale of current pixel P5 is M, then current pixel P5 is from frame FN-1To frame FNElectricityBuckling is dynamic about VGR* (M-128)/128, and from frame FNTo frame FN+1Variation in voltage be about VGR* (128-M)/128.Assuming that adjacentThe grayscale for meeting pixel P2 is the pixel of Q, then adjacent pixels P2 is from frame FN-1To frame FNVariation in voltage be about VGR* (Q-128)/128, and from frame FNTo frame FN+1Variation in voltage be about VGR* (128-Q)/128.Other adjacent pixels P4, P6 and P8 can joinAnalogize according to the related description of adjacent pixels P2, so it will not be repeated.
Explanation is directed to the application examples of tableaux herein.Please refer to Fig. 1, Fig. 3 and Fig. 4.Compensation circuit 130 can calculate downEquation 1 is stated, to obtain offset ERRP5.By using offset ERRP5, compensation circuit 130 can compensate current pixel P5Current pixel data MP5And obtain compensated pixel data COMPP5, as shown in equation 2.In equation 1, PAR2It indicatesCoupled capacitor information between current pixel P5 and the first adjacent pixels P2, PAR4Indicate current pixel P5 and the second adjacent pixelsCoupled capacitor information between P4, PAR6Indicate the coupled capacitor information between current pixel P5 and third adjacent pixels P6, PAR8Indicate the coupled capacitor information between current pixel P5 and the 4th adjacent pixels P8, QP2Indicate the pixel number of the first adjacent pixels P2According to QP4Indicate a pixel data of the second adjacent pixels P4, QP6Indicate the pixel data of third adjacent pixels P6, QP8Indicate theThe pixel data of four adjacent pixels P8, and PAR52、PAR54、PAR56、PAR58With PAR5For real number.PAR52、PAR54、PAR56、PAR58With PAR5Value can be determined according to design requirement.
ERRP5=PAR2*(MP5–QP2)+PAR52+
PAR4*(MP5–QP4)+PAR54+
PAR6*(MP5–QP6)+PAR56+
PAR8*(MP5–QP8)+PAR58+
PAR5Equation 1
COMPP5=MP5+ERRP5Equation 2
In equation 1, coupled capacitor information PAR2、PAR4、PAR6With PAR8It can come according to the characteristic of display panel 10It determines, and/or is determined according to pixel voltage maximum magnitude VGR.For example, in some embodiments, in equation 1Coupled capacitor information PAR2For (CP2P5*VGR*P)/(RG*CP5), coupled capacitor information PAR4For (CP4P5*VGR*P)/(RG*CP5), coupled capacitor information PAR6For (CP6P5*VGR*P)/(RG*CP5), coupled capacitor information PAR8For (CP8P5*VGR*P)/(RG*CP5), wherein CP5Indicate the storage capacitors value of current pixel P5, CP2P5It indicates between current pixel P5 and the first adjacent pixels P2Coupling capacitance, CP4P5Indicate the coupling capacitance between current pixel P5 and the second adjacent pixels P4, CP6P5Indicate current pixelCoupling capacitance between P5 and third adjacent pixels P6, CP8P5Indicate the coupling between current pixel P5 and the 4th adjacent pixels P8Capacitance is closed, P indicates that reversal coefficient, RG indicate to refer to grayscale value.Reversal FACTOR P is 1 or -1.It is drawn when by positive polarityFace (frame FN-1) change to negative polarity picture (frame FN) when, reversal FACTOR P is 1.When drawing (frame F by negative polarityN) change to positive polarity pictureFace (frame FN+1) when, reversal FACTOR P is -1.If being 128 with reference to grayscale value RG for the application conditions shown in Fig. 4.
Assuming that the storage capacitors value C of current pixel P5P5=20fF, coupling capacitance CP2P5、CP4P5、CP6P5With CP8P5It is0.5fF, and pixel voltage maximum magnitude VGR is 4V.Assuming that grayscale (the current pixel data M of current pixel P5P5) it is 128, andThe grayscale of adjacent pixels P2, P4, P6 and P8 are 0.When by positive polarity picture (frame FN-1) change to negative polarity picture (frame FN) when, it is adjacentIt is (VGR/128) (Q-M) * P=(VGR/128) (0-128) * 1=- that pixel P2, which is met, relative to the voltage variety of current pixel P5VGR.The rest may be inferred, other adjacent pixels (P4, P6 or P8) are also-VGR relative to the voltage variety of current pixel P5.Assuming thatPixel P1, pixel P3, pixel P7, pixel P9 are negligible relative to the coupled capacitor of pixel P5.It is calculated with capacitance equation,CP5*ΔVP5=CP2P5*ΔVP2P5+CP4P5*ΔVP4P5+CP6P5*ΔVP6P5+CP8P5*ΔVP8P5, wherein Δ VP2P5It is opposite for pixel P2In the variation in voltage amount of pixel P5, Δ VP4P5Variation in voltage amount for pixel P4 relative to pixel P5, Δ VP6P5It is opposite for pixel P6In the variation in voltage amount of pixel P5, and Δ VP8P5Variation in voltage amount for pixel P8 relative to pixel P5.ΔVP2P5=Δ VP4P5=ΔVP6P5=Δ VP8P5=(VGR/128) (Q-M) * P=(4/128) (0-128) * 1=-4.Therefore, because of picture caused by coupled capacitorThe variation in voltage Δ V of plain P5P5=(0.5/20) * (- 4)+(0.5/20) * (- 4)+(0.5/20) * (- 4)+(0.5/20) * (- 4)=-0.4V.Unit gray scale voltage VGRAY is VGR/255=4/255=15.7mV.Voltage error caused by coupling effect(ERRP5) it is Δ VP5/ VGRAY=-0.4V/15.7mV ≈ -25.Also that is, adjacent pixels P2, P4, P6 and P8 are to current pixel P5The coupled capacitor voltage error that current pixel P5 will be caused to have -25 grayscale.Therefore, compensated pixel data COMPP5For MP5+25=128+25, to compensate error caused by coupling effect.
In another embodiment, compensation circuit 130 can calculate current pixel P5 in present frame FNWith previous frame FN-1BetweenCurrent pixel variation.Compensation circuit 130 also calculates adjacent pixels (such as pixel P2, P4, P6 and P8 shown in Fig. 3) in present frameFNWith previous frame FN-1Between adjacent pixels variation.By using the coupled capacitor information, and by using described currentPixel variation changes with the adjacent pixels, and compensation circuit 130 can compensate the current pixel data M of current pixel P5P5And it obtainsObtain compensated pixel data COMPP5。
Explanation is directed to the application examples of dynamic menu herein.Please refer to Fig. 1, Fig. 3 and Fig. 4.Compensation circuit 130 can calculate downEquation 3 is stated, to obtain offset ERRP5.By using offset ERRP5, compensation circuit 130 can compensate current pixel P5Current pixel data MP5And obtain compensated pixel data COMPP5, as shown in Equation 2.In equation 3, C2Indicate meshCoupled capacitor information between preceding pixel P5 and the first adjacent pixels P2, C4Indicate current pixel P5 and the second adjacent pixels P4 itBetween coupled capacitor information, C6Indicate the coupled capacitor information between current pixel P5 and third adjacent pixels P6, C8Indicate currentCoupled capacitor information between pixel P5 and the 4th adjacent pixels P8, PV5Indicate current pixel P5 in present frame FNWith previous frameFN-1Between current pixel variation, PV2Indicate the first adjacent pixels P2 in present frame FNWith previous frame FN-1Between adjacent pixelsVariation, PV4Indicate the second adjacent pixels P4 in present frame FNWith previous frame FN-1Between adjacent pixels variation, PV6Indicate thirdAdjacent pixels P6 is in present frame FNWith previous frame FN-1Between adjacent pixels variation, PV8Indicate the 4th adjacent pixels P8 in currentFrame FNWith previous frame FN-1Between adjacent pixels variation, and PAR5For real number.PAR5Value can be determined according to design requirement.
ERRP5=C2*(PV2–PV5)+
C4*(PV4–PV5)+
C6*(PV6–PV5)+
C8*(PV8–PV5)+
PAR5Equation 3
In equation 3, coupled capacitor information C2、C4、C6With C8It can be determined according to the characteristic of display panel 10, withIt and/or is determined according to pixel voltage maximum magnitude VGR.For example, in some embodiments, the coupling in equation 3Capacitance information C2For (GT/VGR) * (CP2P5/CP5), coupled capacitor information C4For (GT/VGR) * (CP4P5/CP5), coupled capacitor informationC6For (GT/VGR) * (CP6P5/CP5), coupled capacitor information C8For (GT/VGR) * (CP8P5/CP5).Wherein, GT indicates maximum grayIt is worth range, VGR indicates pixel voltage maximum magnitude, CP5Indicate the storage capacitors value of current pixel P5.If with application bar shown in Fig. 4For part, then maximum gray value range GT is 256, and pixel voltage maximum magnitude VGR is 4V.
In positive polarity picture (such as frame F shown in Fig. 4N-1) in, the voltage of current pixel P5 is VGMA (128)+(VGR/2) *[(GT/2-MP5(N-1))/(GT/2)] * P, wherein reversal FACTOR P is 1.MP5(N-1)Indicate current pixel P5 in frame FN-1MeshPreceding pixel data.In frame with negative polarity (such as frame F shown in Fig. 4N) in, the voltage of current pixel P5 is VGMA (128)+(VGR/2)*[(GT/2-MP5(N))/(GT/2)] * P, wherein reversal FACTOR P is -1.MP5(N)Indicate current pixel P5 in frame FNMeshPreceding pixel data.Therefore, the current pixel of current pixel P5 changes PV5={ VGMA (128)+(VGR/2) * [(GT/2-MP5(N))/(GT/2)]*(-1)}–{VGMA(128)+(VGR/2)*[(GT/2-MP5(N-1))/(GT/2)] }=(VGR/GT) * (MP5(N)+MP5(N-1))–VGR。
In positive polarity picture (such as frame F shown in Fig. 4N-1) in, the voltage of the first adjacent pixels P2 be VGMA (128)+(VGR/2)*[(GT/2-QP2(N-1))/(GT/2)] * P, wherein reversal FACTOR P is 1.QP2(N-1)Indicate the first adjacent pixels P2In frame FN-1Pixel data.In frame with negative polarity (such as frame F shown in Fig. 4N) in, the voltage of current pixel P5 is VGMA (128)+(VGR/2)*[(GT/2-QP2(N))/(GT/2)] * P, wherein reversal FACTOR P is -1.QP2(N)Indicate the first adjacent pixels P2In frame FNPixel data.Therefore, the adjacent pixels of the first adjacent pixels P2 change PV2={ VGMA (128)+(VGR/2) *[(GT/2-QP2(N))/(GT/2)]*(-1)}–{VGMA(128)+(VGR/2)*[(GT/2-QP2(N-1))/(GT/2)] }=(VGR/GT)*(QP2(N)+QP2(N-1))–VGR.Remaining adjacent pixels can be with the rest may be inferred.The adjacent pixels of second adjacent pixels P4 changePV4For (VGR/GT) * (QP4(N)+QP4(N-1))-VGR, the adjacent pixels variation PV of third adjacent pixels P66For (VGR/GT) *(QP6(N)+QP6(N-1))-VGR, the adjacent pixels variation PV of the 4th adjacent pixels P88For (VGR/GT) * (QP8(N)+QP8(N-1))–VGR.Wherein, QP4(N)Indicate the second adjacent pixels P4 in frame FNPixel data, QP4(N-1)Indicate the second adjacent pixels P4 in frameFN-1Pixel data, QP6(N)Indicate third adjacent pixels P6 in frame FNPixel data, QP6(N-1)Indicate third adjacent pixels P6In frame FN-1Pixel data, QP8(N)Indicate the 4th adjacent pixels P8 in frame FNPixel data, QP8(N-1)Indicate the 4th adjacent picturePlain P8 is in frame FN-1Pixel data.
Fig. 5 is according to the step S230 for obtaining the compensated pixel data shown in one embodiment of the invention explanatory diagram 2Flow diagram.In embodiment illustrated in fig. 5, step S230 includes step S510, step S520 and step S530.In stepIn S510, the current pixel data of current pixel P5 can be converted to corresponding gray scale voltage value by compensation circuit 130.According to someLook-up table (lookup table), transfer equation sequence or algorithm can be used in design requirement, compensation circuit 130, so as to by meshPreceding pixel data are converted to corresponding gray scale voltage value.In step S520, compensation circuit 130 can be by using the coupling electricityHold information to compensate corresponding gray scale voltage value, and then obtains compensated gray scale voltage value.The compensation way that step S520 is carried out,The related description of Fig. 3, Fig. 4, equation 1, equation 2 and/or equation 3 is referred to analogize, so it will not be repeated.In stepIn S530, compensated gray scale voltage value can be converted into compensation pixel data com P by compensation circuit 130P5, so as to will be through mendingRepay pixel data COMPP5It is supplied to data drive circuit 140.According to some design requirements, lookup is can be used in compensation circuit 130Table, transfer equation sequence or algorithm, so that compensated gray scale voltage value is converted into compensation pixel data com PP5。
It is worth noting that, in some embodiments, compensation circuit 130 can be an independent integrated circuit, and depositReservoir 120 can be an additional integrated circuit.In further embodiments, memory 120 can be embedded in compensation electricityIn road 130.According to design requirement, sequential control circuit 110 and data drive circuit 140 can be two independent integrated electricityRoad, and compensation circuit 130 can be embedded in sequential control circuit 110 or compensation circuit 130 can be embedded in dataIn driving circuit 140.In other embodiments, sequential control circuit 110, compensation circuit 130 and data drive circuit 140 canTo be implemented as the same integrated circuit.
In different application situations, sequential control circuit 110, memory 120, compensation circuit 130 and/or data-drivenThe correlation function of circuit 140 can use general programming language (programming languages, such as C or C++), hardPart description language (hardware description languages, such as Verilog HDL or VHDL) or other are suitableProgramming language is embodied as software, firmware or hardware.Can be performed the correlation function programming language can be arranged to it is anyKnown computer can access media (computer-accessible medias), such as tape (magnetic tapes),Semiconductor (semiconductors) memory, disk (magnetic disks) or CD (compact disks, such as CD-ROM or DVD-ROM), or internet (Internet), wire communication (wired communication), channel radio can be passed throughBelieve that (wireless communication) or other communication medias transmit the programming language.The programming language can be depositedIt is placed on accessing in media for computer, in order to which the software (or firmware) is accessed/executed by the processor of computerIt programs code (programming codes).It is one or more controllers, microcontroller, microprocessor, special for hardware realizationApplication integrated circuit (Application-specific integrated circuit, ASIC), digital signal processor(digital signal processor, DSP), field can programmed logic lock array (Field Programmable GateArray, FPGA) and/or other processing units in various logic region, module and circuit can be used to realize or execute sheetFunction described in literary embodiment.In addition, apparatus and method of the present invention can be realized by the combination of hardware and software.
In conclusion display panel drive device 100 and driving method described in all embodiments of the present invention, it can be by storingDevice 120 provides the coupled capacitor between the current pixel P5 in display panel 10 and adjacent pixels (P2, P4, P6 and/or P8)Information.By using the coupled capacitor information, compensation circuit 130 can compensate the current pixel data of current pixel P5, andObtain the compensated pixel data of current pixel P5.Therefore, display panel drive device 100 can compensate current pixel P5 because of neighbourConnect variation caused by the coupled voltages of pixel.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical fieldMiddle technical staff, without departing from the spirit and scope of the invention, when can make a little variation and retouching, therefore protection of the inventionRange is subject to view appended claims institute defender.