技术领域technical field
本发明涉及芯片调试技术，尤其涉及一种芯片调试装置、方法及计算机可读存储介质。The present invention relates to chip debugging technology, in particular to a chip debugging device, method and computer-readable storage medium.
背景技术Background technique
目前国内微电子行业在市场需求的推动下发展非常的迅速，而芯片被应用到产品中时，最重要的一点是在芯片上开发软件应用，而在软件的在开发过程中就需要对芯片进行调试，这就需要相应的调试装置来完成芯片调试。At present, the domestic microelectronics industry is developing very rapidly under the impetus of market demand, and when chips are applied to products, the most important point is to develop software applications on the chips. Debugging, which requires a corresponding debugging device to complete the chip debugging.
目前对芯片的调试大多使用联合测试行动组(Joint Test Action Group，JTAG)标准来完成的，JTAG调试是依据JTAG标准形成的一种芯片调试方法，市场上很多芯片也是采用JTAG调试完成调试的，在实际应用中，很多芯片厂商都推出了与自己生产的芯片配套的调试装置，但这些调试装置的性能普遍不高，只能调试一些相对简单的应用程序，对于稍微复杂的应用程序则有些则力不从心。例如：对于新版本的应用程序下载时间往往是分钟级别的，在进行多线程调试时存在刷新速度慢、单步调试卡顿等问题，从而降低了芯片的调试速度。At present, most of the debugging of the chip is done using the Joint Test Action Group (JTAG) standard. JTAG debugging is a chip debugging method formed according to the JTAG standard. Many chips on the market also use JTAG debugging to complete the debugging. In practical applications, many chip manufacturers have introduced debugging devices that are matched with their own chips, but the performance of these debugging devices is generally not high, and they can only debug some relatively simple applications, while some are slightly more complex. Powerless. For example, the download time of the new version of the application is often at the minute level. When multi-threaded debugging is performed, there are problems such as slow refresh speed and single-step debugging freeze, which reduces the debugging speed of the chip.
发明内容SUMMARY OF THE INVENTION
为解决上述技术问题，本发明实施例期望提供一种芯片调试装置、方法及计算机可读存储介质，以提高芯片的调试速度。In order to solve the above technical problems, the embodiments of the present invention are expected to provide a chip debugging device, method and computer-readable storage medium, so as to improve the debugging speed of the chip.
本发明的技术方案是这样实现的：本发明实施例提供了一种芯片调试装置，该装置包括：命令获取单元和命令处理单元；其中，The technical solution of the present invention is realized as follows: an embodiment of the present invention provides a chip debugging device, the device includes: a command acquisition unit and a command processing unit; wherein,
所述命令获取单元，用于获取加密后的调试命令；对所述加密后的调试命令进行解密得到调试命令，所述调试命令用于指示对目标芯片的调试操作；The command obtaining unit is used for obtaining an encrypted debugging command; decrypting the encrypted debugging command to obtain a debugging command, the debugging command is used to instruct a debugging operation on the target chip;
所述命令获取单元，还用于将所述调试命令发送至所述命令处理单元；the command obtaining unit, further configured to send the debugging command to the command processing unit;
所述命令处理单元，用于接收所述调试命令，并将所述调试命令转换成对应的时序信号；the command processing unit, configured to receive the debug command and convert the debug command into a corresponding timing signal;
所述命令处理单元，还用于将所述时序信号发送至所述目标芯片，使所述目标芯片按照所述时序信号执行调试操作。The command processing unit is further configured to send the timing signal to the target chip, so that the target chip performs a debugging operation according to the timing signal.
上述方案中，所述命令获取单元为高级精简指令集处理器(Acorn RISC Machine，ARM)，所述命令处理单元为现场可编程门阵列(Field Programmable Gate Array，FPGA)。In the above solution, the command obtaining unit is an advanced reduced instruction set processor (Acorn RISC Machine, ARM), and the command processing unit is a Field Programmable Gate Array (Field Programmable Gate Array, FPGA).
上述方案中，所述调试命令为联合测试行动组JTAG调试命令，所述时序包括：测试时钟信号，测试模式选择信号、测试数据输入信号和测试数据输出信号；In the above solution, the debug command is a joint test action group JTAG debug command, and the timing sequence includes: a test clock signal, a test mode selection signal, a test data input signal and a test data output signal;
所述命令处理单元，具体用于将所述JTAG调试命令转换成包括测试时钟信号，测试模式选择信号和测试数据输入信号的JTAG时序信号；The command processing unit is specifically configured to convert the JTAG debugging command into a JTAG timing signal including a test clock signal, a test mode selection signal and a test data input signal;
所述命令处理单元，还用于接收所述目标芯片发送的测试数据输出信号。The command processing unit is further configured to receive the test data output signal sent by the target chip.
上述方案中，所述装置还包括：电平转换单元；In the above solution, the device further includes: a level conversion unit;
所述电平转换单元，用于将所述时序信号的电平转换成与所述目标芯片适配的电平；并将电平转换后的所述时序信号输出至所述目标芯片。The level conversion unit is configured to convert the level of the timing signal into a level suitable for the target chip; and output the level-converted timing signal to the target chip.
上述方案中，所述装置还包括：命令设置单元；In the above solution, the device further includes: a command setting unit;
所述命令设置单元，用于为所述目标芯片设置对应的调试命令；the command setting unit, configured to set a corresponding debugging command for the target chip;
所述调试命令包括：命令部分和数据部分；所述命令部分包含N个命令字节，所述数据部分包含M个数据字节，N和M取正整数；The debugging command includes: a command part and a data part; the command part includes N command bytes, the data part includes M data bytes, and N and M are positive integers;
所述命令部分用于指示所述目标芯片执行的调试操作，所述数据部分包括向所述目标芯片输入的数据。The command part is used to instruct the target chip to perform a debug operation, and the data part includes data input to the target chip.
上述方案中，所述命令部分中每一个命令字节包括：位于低四位的命令码和位于高四位的命令码参数，或者位于低四位的命令码和位于高四位的任意值；In the above scheme, each command byte in the command section includes: the command code at the lower four digits and the command code parameter at the upper four digits, or the command code at the lower four digits and any value at the upper four digits;
所述命令码参数是指位于同一字节中低四位的命令码对应的执行参数，所述执行参数用于具体指示所述目标芯片执行的调试操作。The command code parameter refers to the execution parameter corresponding to the command code located in the lower four bits in the same byte, and the execution parameter is used to specifically indicate the debugging operation performed by the target chip.
本发明实施例中还提供了一种芯片调试的方法，所述方法包括：An embodiment of the present invention also provides a method for chip debugging, the method comprising:
获取加密后的调试命令；Get the encrypted debugging command;
对所述加密后的调试命令进行解密得到调试命令，所述调试命令用于指示对目标芯片的调试操作；Decrypting the encrypted debug command to obtain a debug command, where the debug command is used to instruct a debug operation on the target chip;
将所述调试命令转换成对应的时序信号；converting the debug command into a corresponding timing signal;
将所述时序信号发送至所述目标芯片，使所述目标芯片按照所述时序信号执行调试操作。The timing signal is sent to the target chip, so that the target chip performs a debugging operation according to the timing signal.
上述方案中，所述获取加密后的调试命令，包括：控制高级精简指令集处理器ARM获取调试命令；In the above scheme, the obtaining the encrypted debugging command includes: controlling the advanced reduced instruction set processor ARM to obtain the debugging command;
相应的，所述对所述加密后的调试命令进行解密得到调试命令，包括：Correspondingly, the decrypting the encrypted debugging command to obtain the debugging command includes:
控制所述ARM对所述加密后的调试命令进行解密得到调试命令；Controlling the ARM to decrypt the encrypted debugging command to obtain a debugging command;
相应的，所述将所述调试命令转换成对应的时序信号，包括：Correspondingly, the converting the debugging command into a corresponding timing signal includes:
控制现场可编程门阵列FPGA将所述调试命令转换成时序信号；Controlling the field programmable gate array FPGA to convert the debug commands into timing signals;
相应的，所述将所述时序信号发送至所述目标芯片，包括：Correspondingly, the sending the timing signal to the target chip includes:
控制所述FPGA将所述时序信号发送至所述目标芯片。The FPGA is controlled to send the timing signal to the target chip.
上述方案中，所述调试命令为联合测试行动组JTAG调试命令；所述时序包括：测试时钟信号，测试模式选择信号、测试数据输入信号和测试数据输出信号；In the above scheme, the debug command is a joint test action group JTAG debug command; the timing sequence includes: a test clock signal, a test mode selection signal, a test data input signal and a test data output signal;
所述将所述调试命令转换成对应的时序信号，包括：将所述JTAG调试命令转换成包括测试时钟信号，测试模式选择信号和测试数据输入信号的JTAG时序信号；The converting the debug command into a corresponding timing signal includes: converting the JTAG debug command into a JTAG timing signal including a test clock signal, a test mode selection signal and a test data input signal;
相应的，在所述将所述时序信号发送至所述目标芯片之后，所述方法还包括：接收所述目标芯片发送的测试数据输出信号。Correspondingly, after the sending the timing signal to the target chip, the method further includes: receiving a test data output signal sent by the target chip.
上述方案中，所述将所述时序信号发送至所述目标芯片，包括：In the above solution, the sending the timing signal to the target chip includes:
将所述时序信号的电平转换成与所述目标芯片适配的电平；converting the level of the timing signal into a level adapted to the target chip;
将电平转换后的所述时序信号输出至所述目标芯片。The level-converted timing signal is output to the target chip.
上述方案中，在所述获取加密后的调试命令之前，所述方法还包括：In the above solution, before obtaining the encrypted debugging command, the method further includes:
为所述目标芯片设置对应的调试命令；其中，所述调试命令包括：命令部分和数据部分；所述命令部分包含N个命令字节，所述数据部分包含M个数据字节，N和M取正整数；所述命令部分用于指示所述目标芯片执行的调试操作，所述数据部分包括向所述目标芯片输入的数据。Set a corresponding debug command for the target chip; wherein, the debug command includes: a command part and a data part; the command part includes N command bytes, and the data part includes M data bytes, N and M A positive integer is taken; the command part is used to instruct the target chip to perform a debug operation, and the data part includes data input to the target chip.
上述方案中，所述命令部分中每一个命令字节包括：位于低四位的命令码和位于高四位的命令码参数，或者位于低四位的命令码和位于高四位的任意值；In the above scheme, each command byte in the command section includes: the command code at the lower four digits and the command code parameter at the upper four digits, or the command code at the lower four digits and any value at the upper four digits;
所述命令码参数是指位于同一字节中的低四位的命令码对应的执行参数，所述执行参数用于具体指示所述目标芯片执行的调试操作。The command code parameter refers to an execution parameter corresponding to the lower four bits of the command code located in the same byte, and the execution parameter is used to specifically indicate the debugging operation performed by the target chip.
本发明实施例中还提供了一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时，实现上述任一项所述的方法的步骤。Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of any of the above methods.
本发明实施例提供的一种芯片调试装置、方法及计算机可读存储介质，该装置包括：命令获取单元和命令处理单元；其中，所述命令获取单元，用于获取加密后的调试命令；对加密后的调试命令进行解密得到调试命令，调试命令用于指示对目标芯片的调试操作；命令获取单元，还用于将调试命令发送至命令处理单元；命令处理单元，用于接收调试命令，并将调试命令转换成对应的时序信号；命令处理单元，还用于将时序信号发送至目标芯片，使目标芯片按照时序信号执行调试操作。采用上述技术实现方案，可以利用两个不同的处理单元来分别实现调试命令的获取和转换，相比于采用单个处理单元提高了调试命令的获取速度和转换速度，从而提高了芯片的调试速度。A chip debugging device, method, and computer-readable storage medium provided by the embodiments of the present invention include: a command obtaining unit and a command processing unit; wherein, the command obtaining unit is used to obtain an encrypted debugging command; The encrypted debug command is decrypted to obtain a debug command, and the debug command is used to instruct the debug operation on the target chip; the command acquisition unit is also used to send the debug command to the command processing unit; the command processing unit is used to receive the debug command, and Convert the debugging command into a corresponding timing signal; the command processing unit is also used for sending the timing signal to the target chip, so that the target chip performs the debugging operation according to the timing signal. By adopting the above technical implementation scheme, two different processing units can be used to realize the acquisition and conversion of debug commands respectively, which improves the acquisition speed and conversion speed of debug commands compared to using a single processing unit, thereby improving the debug speed of the chip.
附图说明Description of drawings
图1为本发明实施例中芯片调试装置的第一组成结构示意图；FIG. 1 is a schematic diagram of a first composition structure of a chip debugging device in an embodiment of the present invention;
图2为本发明实施例中芯片调试装置的第二组成结构示意图；FIG. 2 is a schematic diagram of a second composition structure of a chip debugging device in an embodiment of the present invention;
图3为本发明实施例中目标芯片中JTAG模块的结构示意图；3 is a schematic structural diagram of a JTAG module in a target chip in an embodiment of the present invention;
图4为本发明实施例中目标芯片中TAP控制器的运行流程示意图；4 is a schematic diagram of the operation flow of the TAP controller in the target chip in the embodiment of the present invention;
图5为本发明实施例中芯片调试装置的第三组成结构示意图；5 is a schematic diagram of a third composition structure of a chip debugging device in an embodiment of the present invention;
图6为本发明实施例中芯片调试的方法的流程示意图。FIG. 6 is a schematic flowchart of a method for chip debugging in an embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
实施例一Example 1
本发明实施例提供了一种芯片调试装置，该装置可以实现对目标芯片的调试，例如：对目标芯片进行JTAG调试，该装置可以将自定义的调试命令输出至目标芯片的JTAG接口，目标芯片根据获得的调试命令执行相应的调试操作。An embodiment of the present invention provides a chip debugging device, which can debug a target chip, for example: JTAG debugging is performed on the target chip, the device can output a customized debugging command to the JTAG interface of the target chip, and the target chip can be debugged. Perform corresponding debugging operations according to the obtained debugging commands.
图1为本发明实施例中芯片调试装置的第一组成结构示意图，如图1所示，芯片调试装置10包括：命令获取单元101和命令处理单元102；其中，FIG. 1 is a schematic diagram of the first structure of the chip debugging apparatus in the embodiment of the present invention. As shown in FIG. 1 , the chip debugging apparatus 10 includes: a command obtaining unit 101 and a command processing unit 102; wherein,
命令获取单元101，可以用于获取加密后的调试命令；对加密后的调试命令进行解密得到调试命令，调试命令用于指示对目标芯片的调试操作。The command obtaining unit 101 can be used to obtain an encrypted debugging command; decrypt the encrypted debugging command to obtain a debugging command, and the debugging command is used to instruct a debugging operation on the target chip.
命令获取单元101，还可以用于将调试命令发送至命令处理单元。The command acquisition unit 101 can also be used to send a debugging command to the command processing unit.
命令处理单元102，可以用于接收调试命令，并将调试命令转换成对应的时序信号。The command processing unit 102 may be configured to receive a debug command and convert the debug command into a corresponding timing signal.
命令处理单元102，还可以用于将时序信号发送至目标芯片，使目标芯片按照时序信号执行调试操作。The command processing unit 102 may also be configured to send timing signals to the target chip, so that the target chip performs debugging operations according to the timing signals.
在实际实施时，命令获取单元可以为ARM，命令处理单元可以为FPGA，ARM可以通过先进可扩展接口(Advanced eXtensible Interface，AXI)总线与FPGA进行通信。本发明实施例中，通过ARM与FPGA的结合形成的芯片调试装置，可以实现高速芯片调试，且相比于结构复杂成本较高的高端芯片调试产品，具有结构简单成本较低的优势，能够媲美高端产品的调试性能。In actual implementation, the command acquisition unit may be an ARM, the command processing unit may be an FPGA, and the ARM may communicate with the FPGA through an Advanced eXtensible Interface (AXI) bus. In the embodiment of the present invention, the chip debugging device formed by the combination of ARM and FPGA can realize high-speed chip debugging, and compared with high-end chip debugging products with complex structure and high cost, it has the advantage of simple structure and low cost, and can be comparable to high-end chip debugging products with complex structure and high cost. The debugging performance of high-end products.
在实际实施时，调试命令可以为联合测试行动组JTAG调试命令，命令处理单元将JTAG调试命令转换为遵循IEEE1149.1标准的JTAG时序信号，通过芯片调试装置中的JTAG接口与目标芯片进行通信，其中JTAG接口可以包括以下4个引脚：In actual implementation, the debug command can be a JTAG debug command of the Joint Test Action Group. The command processing unit converts the JTAG debug command into a JTAG timing signal that follows the IEEE1149.1 standard, and communicates with the target chip through the JTAG interface in the chip debug device. The JTAG interface can include the following 4 pins:
测试时钟输入(Test Clock input，TCK)；Test Clock input (TCK);
测试模式选择(Test Mode Select，TMS)，TMS用来设置测试访问口(Test AccessPort，TAP)控制器；Test Mode Select (TMS), TMS is used to set the Test Access Port (TAP) controller;
测试数据输入(Test Data In，TDI)，数据通过TDI输入至TAP控制器；Test data input (Test Data In, TDI), the data is input to the TAP controller through TDI;
测试数据输出(Test Data Output，TDO)，数据通过TDO从TAP控制器输出。Test Data Output (TDO), the data is output from the TAP controller through TDO.
这里，TAP控制器为JTAG内部的一个状态机，TAP控制器的状态机通过TCK和TMS在不同的状态间进行转换，实现数据和命令的输入。Here, the TAP controller is a state machine inside the JTAG, and the state machine of the TAP controller switches between different states through TCK and TMS to realize the input of data and commands.
相应的，时序信号可以包括：测试时钟信号，测试模式选择信号、测试数据输入信号和测试数据输出信号。Correspondingly, the timing signals may include: a test clock signal, a test mode selection signal, a test data input signal and a test data output signal.
示例性的，命令处理单元，具体用于将JTAG调试命令转换成包括测试时钟信号，测试模式选择信号和测试数据输入信号的JTAG时序信号；命令处理单元，还用于接收目标芯片发送的测试数据输出信号。Exemplarily, the command processing unit is specifically configured to convert the JTAG debug command into a JTAG timing signal including a test clock signal, a test mode selection signal and a test data input signal; the command processing unit is further configured to receive test data sent by the target chip output signal.
在实际实施时，装置还可以包括：电平转换单元；电平转换单元，用于将时序信号的电平转换成与目标芯片适配的电平；并将电平转换后的时序信号输出至目标芯片。示例性的，电平转换单元可以为MAX232芯片、MAX485芯片等，也可以根据业务需要选择相应的电平转换芯片，本发明实施例中对于电平转换芯片种类不做具体限制。In actual implementation, the device may further include: a level conversion unit; a level conversion unit for converting the level of the timing signal into a level suitable for the target chip; and outputting the level-converted timing signal to a target chip. Exemplarily, the level conversion unit may be a MAX232 chip, a MAX485 chip, or the like, or a corresponding level conversion chip may be selected according to business needs, and the type of the level conversion chip is not specifically limited in the embodiment of the present invention.
可以理解的是，目标芯片输入信号的电平并没有统一的标准，为了使该装置的适用范围更广，增加的电平转换单元可以将输出的时序信号电平转换成与目标芯片适配的电平，进而扩大芯片的调试范围。It can be understood that there is no uniform standard for the level of the input signal of the target chip. In order to make the device applicable to a wider range, the added level conversion unit can convert the output timing signal level into a level suitable for the target chip. level, thereby expanding the debugging range of the chip.
在实际实施时，装置还可以包括：命令设置单元；命令设置单元，用于为目标芯片设置对应的调试命令。需要说明的是，通过自定义调试命令，可以根据实际业务需求设置对应的调试命令，以完成不同芯片的调试。In actual implementation, the apparatus may further include: a command setting unit; and a command setting unit for setting a corresponding debugging command for the target chip. It should be noted that, by customizing the debugging commands, corresponding debugging commands can be set according to actual business requirements to complete the debugging of different chips.
示例性的，调试命令包括：命令部分和数据部分；命令部分包含N个命令字节，数据部分包含M个数据字节，N和M取正整数；命令部分用于指示目标芯片执行的调试操作，数据部分包括向目标芯片输入的数据。Exemplarily, the debug command includes: a command part and a data part; the command part contains N command bytes, the data part contains M data bytes, and N and M are positive integers; the command part is used to instruct the target chip to perform a debug operation , the data part includes the data input to the target chip.
示例性的，命令部分中每一个命令字节包括：位于低四位的命令码和位于高四位的命令码参数，或者位于低四位的命令码和位于高四位的任意值；命令码参数是指位于同一字节中低四位的命令码对应的执行参数，执行参数用于具体指示目标芯片执行的调试操作。Exemplarily, each command byte in the command part includes: a command code located in the lower four digits and a command code parameter located in the upper four digits, or a command code located in the lower four digits and an arbitrary value located in the upper four digits; the command code The parameter refers to the execution parameter corresponding to the command code in the lower four bits in the same byte, and the execution parameter is used to specifically instruct the debugging operation performed by the target chip.
示例性的，调试命令可以由1个命令字节和M个数据字节组成，M取0至7的整数，自定义的调试命令中一个字节的格式如下：Exemplarily, a debug command may consist of 1 command byte and M data bytes, where M is an integer from 0 to 7, and the format of a byte in a custom debug command is as follows:
其中，CCCC为命令码，PPPP为该字节中命令码对应的命令码参数，如果无参数则为任意值，例如：任意值可以为0000或1111。Among them, CCCC is the command code, PPPP is the command code parameter corresponding to the command code in the byte, if there is no parameter, it is an arbitrary value, for example, the arbitrary value can be 0000 or 1111.
示例性的，按照上述命令格式，自定义以下三种JTAG调试命令，即可完成简单JTAG调试功能，实际应用时，可以根据业务需要对调试命令进行扩展。Exemplarily, according to the above command format, the following three JTAG debugging commands can be customized to complete the simple JTAG debugging function. In practical application, the debugging commands can be extended according to business needs.
(1)设置目标芯片TAP控制器的状态(1) Set the state of the target chip TAP controller
命令字节：Command bytes:
其中，命令码：0001B；Among them, the command code: 0001B;
命令参数：SSSS取值范围为0-15，分别对应16种TAP控制器的状态，SSSS的取值范围用二进制表示为：0000B-1111B。Command parameters: The value range of SSSS is 0-15, corresponding to 16 TAP controller states. The value range of SSSS is expressed in binary as: 0000B-1111B.
(2)设置目标芯片TAP控制器的状态软复位(2) Set the state soft reset of the target chip TAP controller
命令字节：Command bytes:
其中，命令码：0010B；Among them, the command code: 0010B;
命令参数：XXXX为任意值时可以忽略。Command parameter: It can be ignored when XXXX is any value.
(3)输出x个bit数据和读入x个bit数据(3) Output x bits of data and read in x bits of data
命令字节：Command bytes:
数据字节：Data bytes:
其中，命令码：0011B；Among them, the command code: 0011B;
命令参数：T表示最后一个数据位输出后TMS的电平，0表示低电平1表示高电平，T还用于标识最后一个数据位输出后是否结束数据输出，当T为0时标识继续输出，T为1时标识结束输出；Command parameters: T means the level of TMS after the last data bit is output, 0 means low level, 1 means high level, T is also used to mark whether the data output is ended after the last data bit is output, when T is 0, the mark continues Output, when T is 1, it marks the end of output;
命令参数：XXX取值范围为0-7，用于指示数据字节的输出。例如：当XXX为3时(即XXX为0011B)，表示输出数据字节中第0-3位的数据。Command parameter: The value range of XXX is 0-7, which is used to indicate the output of data bytes. For example: when XXX is 3 (that is, XXX is 0011B), it means the data of bits 0-3 in the output data byte.
数据命令：DDDDDDDD表示需要从TDI输出的数据。Data command: DDDDDDDD indicates the data that needs to be output from TDI.
本发明实施例中，数据在没有特殊标注的情况下为十进制数据，由0x打头的数据为十六进制数据，以B结尾的数据为二进制数据。In this embodiment of the present invention, the data is decimal data unless otherwise marked, the data starting with 0x is hexadecimal data, and the data ending with B is binary data.
在实际实施时，命令设置单元的功能也可以通过命令获取单元来实现。In actual implementation, the function of the command setting unit can also be realized by the command acquiring unit.
另一种可选的实施方式是，命令设置单元也可以位于上位机，通过上位机预先设置命令格式，并按照设置的命令格式自定义目标芯片的调试命令。Another optional implementation is that the command setting unit may also be located in the host computer, the command format is preset by the host computer, and the debugging command of the target chip is customized according to the set command format.
在实际应用中，命令获取单元101、命令处理单元102和命令设置单元均可由中央处理器(Central Processing Unit，CPU)、微处理器(Micro Processor Unit，MPU)、数字信号处理器(Digital Signal Processor，DSP)、复杂可编程逻辑器件(ComplexProgrammable Logic Device，CPLD)等实现。In practical applications, the command acquisition unit 101 , the command processing unit 102 and the command setting unit can all be composed of a central processing unit (Central Processing Unit, CPU), a microprocessor (Micro Processor Unit, MPU), a digital signal processor (Digital Signal Processor) , DSP), Complex Programmable Logic Device (Complex Programmable Logic Device, CPLD) etc.
本发明实施例中，芯片调试装置包括：命令获取单元和命令处理单元；其中，命令获取单元，用于获取加密后的调试命令；对加密后的调试命令进行解密得到调试命令，调试命令用于指示对目标芯片的调试操作；命令获取单元，还用于将调试命令发送至命令处理单元；命令处理单元，用于接收调试命令，并将调试命令转换成对应的时序信号；命令处理单元，还用于将时序信号发送至目标芯片，使目标芯片按照时序信号执行调试操作。采用上述技术实现方案，可以利用两个不同的处理单元来分别实现调试命令的获取和转换，相比于采用单个处理单元提高了调试命令的获取速度和转换速度，从而提高了芯片的调试速度。In the embodiment of the present invention, the chip debugging device includes: a command obtaining unit and a command processing unit; wherein, the command obtaining unit is used to obtain an encrypted debugging command; decrypt the encrypted debugging command to obtain a debugging command, and the debugging command is used for Indicates the debug operation on the target chip; the command acquisition unit is also used to send the debug command to the command processing unit; the command processing unit is used to receive the debug command and convert the debug command into a corresponding timing signal; the command processing unit is also used to It is used to send timing signals to the target chip, so that the target chip performs debugging operations according to the timing signals. By adopting the above technical implementation scheme, two different processing units can be used to realize the acquisition and conversion of debug commands respectively, which improves the acquisition speed and conversion speed of debug commands compared to using a single processing unit, thereby improving the debug speed of the chip.
实施例二Embodiment 2
为了能更加体现本发明的目的，在本发明实施例一的基础上，进行进一步的举例说明。In order to better reflect the purpose of the present invention, further examples are provided on the basis of Embodiment 1 of the present invention.
图2为本发明实施例中芯片调试装置的第二组成结构示意图，如图2所示，芯片调试装置20包括：ARM201、FPGA202、电平转换芯片203和总线204。FIG. 2 is a schematic diagram of the second structure of the chip debugging apparatus in the embodiment of the present invention. As shown in FIG.
其中，ARM201用于接收上位机发送的加密后的调试命令，在解密调试命令后，通过总线204将调试命令写入FPGA202中。示例性的，总线204可以为32位的AXI总线，32位AXI总线可以实现ARM201和FPGA202之间调试命令的高速传输。Among them, the ARM201 is used for receiving the encrypted debugging command sent by the upper computer, and after decrypting the debugging command, the debugging command is written into the FPGA202 through the bus 204 . Exemplarily, the bus 204 can be a 32-bit AXI bus, and the 32-bit AXI bus can implement high-speed transmission of debugging commands between the ARM 201 and the FPGA 202 .
在芯片调试开始之前，ARM201还用于设置FPGA202的工作参数，工作参数至少包括FPGA的工作频率、命令输出频率。ARM201具体用于接收上位机发送的参数设置信息，并通过总线204设置FPGA202的工作频率、命令输出频率等工作参数。Before the chip debugging starts, the ARM201 is also used to set the working parameters of the FPGA202, and the working parameters include at least the working frequency of the FPGA and the command output frequency. The ARM 201 is specifically used to receive the parameter setting information sent by the host computer, and set the working parameters such as the working frequency and the command output frequency of the FPGA 202 through the bus 204 .
FPGA202用于将调试命令转换为时序信号，并将时序信号发送至目标芯片21。The FPGA 202 is used to convert the debug commands into timing signals, and send the timing signals to the target chip 21 .
FPGA202具体用于将调试命令转换为包括TCK、TMS和TDI的时序信号，将时序信号通过电平转换芯片203发送至目标芯片21，接收并缓存目标芯片21通过TDO发送的调试结果。The FPGA 202 is specifically configured to convert the debug commands into timing signals including TCK, TMS and TDI, send the timing signals to the target chip 21 through the level conversion chip 203 , and receive and buffer the debugging results sent by the target chip 21 through TDO.
具体的，FPGA202在收到调试命令后解析命令字节，根据命令字节中低四位的命令码，和高四位的命令码参数(也可能不存在命令码参数)对目标芯片进行调试。Specifically, the FPGA 202 parses the command byte after receiving the debug command, and debugs the target chip according to the command code of the lower four bits and the command code parameter of the upper four bits (or there may be no command code parameter) in the command byte.
电平转换芯片203用于将时序信号TCK、TMS和TDI的电平转换为与目标芯片适配的电平，并将转换后的时序信号发送至目标芯片21，将目标芯片21通过TDO发送的调试结果的电平转换为与FPGA202适配的电平，并将转换后的调试结果发送至FPGA202。示例性的，电平转换芯片203可以让芯片调试装置适配工作电压为1.5v-3.3v的目标芯片。The level conversion chip 203 is used to convert the levels of the timing signals TCK, TMS and TDI into levels suitable for the target chip, and send the converted timing signals to the target chip 21, and the target chip 21 sends the signal through TDO. The level of the debug result is converted into a level adapted to the FPGA 202 , and the converted debug result is sent to the FPGA 202 . Exemplarily, the level conversion chip 203 can make the chip debugging apparatus adapt to the target chip whose working voltage is 1.5v-3.3v.
ARM201还用于从FPGA202中读取调试结果，并将调试结果上传至上位机。The ARM201 is also used to read the debugging results from the FPGA202 and upload the debugging results to the upper computer.
本发明实施例中，利用ARM产生的高压缩率的调试命令，结合FPGA快速的数据处理优势对芯片进行调试，比传统的利用单处理器进行芯片调试在处理速度上有很大的提高，且ARM+FPGA结构简单成本较低。In the embodiment of the present invention, the debugging command of high compression rate generated by ARM is used to debug the chip in combination with the advantages of fast data processing of FPGA, which greatly improves the processing speed compared with the traditional chip debugging using a single processor, and ARM+FPGA structure is simple and low cost.
实施例三Embodiment 3
为了能更加体现本发明的目的，在本发明实施例一和实施例二的基础上，通过本发明实施例提供的芯片调试装置对目标芯片进行JTAG调试为例进行进一步的举例说明。In order to better reflect the purpose of the present invention, on the basis of Embodiment 1 and Embodiment 2 of the present invention, the JTAG debugging of the target chip is further illustrated by using the chip debugging apparatus provided by the embodiment of the present invention as an example.
在实际实施时，目标芯片包括JTAG模块，用于实现目标芯片的JTAG调试，只要目标芯片的JTAG模块是遵循IEEE 1149.1标准建立的，本装置均能与目标芯片进行通信并完成目标芯片的JTAG调试。In actual implementation, the target chip includes a JTAG module, which is used to realize JTAG debugging of the target chip. As long as the JTAG module of the target chip is established in accordance with the IEEE 1149.1 standard, the device can communicate with the target chip and complete the JTAG debugging of the target chip. .
图3为本发明实施例中目标芯片中JTAG模块的结构示意图，如图3所示，JTAG模块包括：TAP控制器311、数据寄存器DR312和指令寄存器IR313，其中，数据寄存器DR312中还包括：0#旁路寄存器、1#数据扫描链和2#地址扫描链。由于JTAG模块是遵循IEEE 1149.1标准建立的，故每部分的功能及工作过程在此不再赘述。3 is a schematic structural diagram of a JTAG module in a target chip in an embodiment of the present invention. As shown in FIG. 3, the JTAG module includes: a TAP controller 311, a data register DR312 and an instruction register IR313, wherein the data register DR312 also includes: 0 #Bypass register, 1# data scan chain and 2# address scan chain. Since the JTAG module is established in accordance with the IEEE 1149.1 standard, the function and working process of each part will not be repeated here.
图4为本发明实施例中目标芯片中TAP控制器的运行流程示意图，如图4所示，TAP控制器共包括16种状态，分别为：状态0：Test-Logic Reset，状态1：Run Test/Idle，状态2：Select-DR Scan，状态3：Capture-DR，状态4：Shift-DR，状态5：Exit1-DR，状态6：Pause-DR，状态7：Exit2-DR，状态8：Update-DR，状态9：Select-IR Scan，状态10：Capture-IR，状态11：Shift-IR，状态12：Exit1-IR，状态13：Pause-IR，状态14：Exit2-IR和状态15：Update-IR。通过控制TAP控制器在不同状态的转换便可以实现对目标芯片的调试操作。FIG. 4 is a schematic diagram of the running flow of the TAP controller in the target chip in the embodiment of the present invention. As shown in FIG. 4 , the TAP controller includes 16 states in total, which are: state 0: Test-Logic Reset, state 1: Run Test /Idle, State 2: Select-DR Scan, State 3: Capture-DR, State 4: Shift-DR, State 5: Exit1-DR, State 6: Pause-DR, State 7: Exit2-DR, State 8: Update -DR, State 9: Select-IR Scan, State 10: Capture-IR, State 11: Shift-IR, State 12: Exit1-IR, State 13: Pause-IR, State 14: Exit2-IR and State 15: Update -IR. The debug operation of the target chip can be realized by controlling the transition of the TAP controller in different states.
图4中，利用TMS来指示TAP控制器的状态转换，图中半圆形箭头指示当TMS为0或者1时，TAP控制器保持在该状态；图中直线或折现箭头指示当TMS为0或者1时，TAP控制器从当前状态转换至箭头所指的状态。例如：在状态0：Test-Logic Reset时，当TMS＝1时，TAP控制器保持在状态0；当TMS＝0时，TAP控制器从状态0转换至状态1。在状态2：Select-DR Scan时，当TMS＝1时，TAP控制器从状态2转换至状态9；当TMS＝0时，TAP控制器从状态2转换至状态3。In Figure 4, TMS is used to indicate the state transition of the TAP controller. The semicircular arrow in the figure indicates that when TMS is 0 or 1, the TAP controller remains in this state; the straight line or discounted arrow in the figure indicates that when TMS is 0 or 1, the TAP controller transitions from the current state to the state indicated by the arrow. For example: in state 0: Test-Logic Reset, when TMS=1, the TAP controller remains in state 0; when TMS=0, the TAP controller transitions from state 0 to state 1. In state 2: Select-DR Scan, when TMS=1, the TAP controller transitions from state 2 to state 9; when TMS=0, the TAP controller transitions from state 2 to state 3.
在实际实施时，通过TAP控制器对JTAG模块中指令寄存器的访问流程为：In actual implementation, the access flow to the instruction register in the JTAG module through the TAP controller is as follows:
1、系统上电，TAP控制器进入状态0：Test-Logic Reset；1. When the system is powered on, the TAP controller enters state 0: Test-Logic Reset;
2、TAP控制器依次经过：Run Test/Idle、Select-DR Scan、Select-IR Scan、Capture-IR、Shift-IR、Exit1-IR、Update-IR，最后返回至状态1：Run Test/Idle状态。2. The TAP controller goes through: Run Test/Idle, Select-DR Scan, Select-IR Scan, Capture-IR, Shift-IR, Exit1-IR, Update-IR, and finally returns to state 1: Run Test/Idle state .
通过TAP控制器对JTAG模块中数据寄存器的访问流程为：The access flow to the data register in the JTAG module through the TAP controller is as follows:
1、当前可以访问的数据寄存器由指令寄存器中当前指令决定；1. The currently accessible data register is determined by the current instruction in the instruction register;
2、以状态1：Run Test/Idle为起点，TAP控制器依次经过：Run Test/Idle、Select-DR Scan、Capture-DR、Shift-DR、Exit1-DR、Update-DR，最后返回至状态1：Run Test/Idle。2. Starting from state 1: Run Test/Idle, the TAP controller goes through: Run Test/Idle, Select-DR Scan, Capture-DR, Shift-DR, Exit1-DR, Update-DR, and finally returns to state 1 : Run Test/Idle.
图5为本发明实施例中芯片调试装置的第三组成结构示意图，如图5所示，芯片调试装置50包括：ARM501、FPGA502和电平转换单元503，ARM501通过AXI总线与FPGA502相连，其中，FIG. 5 is a schematic diagram of the third structure of the chip debugging device in the embodiment of the present invention. As shown in FIG. 5 , the chip debugging device 50 includes: an ARM501, an FPGA502, and a level conversion unit 503. The ARM501 is connected to the FPGA502 through an AXI bus, wherein,
FPGA502可以包括：AXI总线矩阵子单元502a、控制子单元502b、命令缓存子单元502c、结果缓存子单元502d、命令处理子单元502e和JTAG接口502f。The FPGA 502 may include: an AXI bus matrix subunit 502a, a control subunit 502b, a command buffering subunit 502c, a result buffering subunit 502d, a command processing subunit 502e, and a JTAG interface 502f.
其中，ARM501与上位机进行通信，用于获取上位机下发的加密后的JTAG调试命令；ARM501通过AXI总线与AXI总线矩阵子单元502a相连，控制子单元502b、命令缓存子单元502c和结果缓存子单元502d一端分别与AXI总线矩阵子单元502a相连，另一端分别与命令处理子单元502e相连；命令处理子单元502e通过JTAG总线与JTAG接口502f相连，JTAG接口502f的四个引脚TCK、TMS、TDI和TDO分别与电平转换单元503相连；电平转换单元503将从JTAG接口502f接收到的TCK、TMS、TDI信号分别发送至目标芯片51的TAP控制器511，并接收来自TAP控制器511发送的调试结果TDO信号。Among them, the ARM501 communicates with the host computer to obtain the encrypted JTAG debugging command issued by the host computer; the ARM501 is connected to the AXI bus matrix subunit 502a through the AXI bus, and the control subunit 502b, the command cache subunit 502c and the result cache are connected One end of the subunit 502d is connected with the AXI bus matrix subunit 502a respectively, and the other end is connected with the command processing subunit 502e respectively; , TDI and TDO are respectively connected with the level conversion unit 503; the level conversion unit 503 sends the TCK, TMS, TDI signals received from the JTAG interface 502f to the TAP controller 511 of the target chip 51 respectively, and receives from the TAP controller Debug result TDO signal sent by 511.
具体的，ARM501通过AXI总线将解密后的JTAG调试命令发送至AXI总线矩阵子单元502a；Specifically, the ARM501 sends the decrypted JTAG debug command to the AXI bus matrix subunit 502a through the AXI bus;
在实际实施时，芯片调试装置对目标芯片进行JTAG调试时的具体实现步骤可以包括以下：In actual implementation, the specific implementation steps when the chip debugging device performs JTAG debugging on the target chip may include the following:
步骤1：ARM501接收上位机发送的加密后JTAG调试命令，并将解密后的所有JTAG调试命令通过AXI总线发送至FPGA502。Step 1: The ARM501 receives the encrypted JTAG debug command sent by the host computer, and sends all the decrypted JTAG debug commands to the FPGA502 through the AXI bus.
步骤2：FPGA502中的AXI总线矩阵子单元502a接收ARM501发送的所有JTAG调试命令。Step 2: The AXI bus matrix subunit 502a in the FPGA 502 receives all the JTAG debugging commands sent by the ARM501.
步骤3：检测控制子单元502b是否空闲，如果空闲，将AXI总线矩阵子单元502a中的部分调试命令缓存至命令缓存子单元502c中，执行步骤4；如果不空闲，继续执行步骤3等待控制子单元502b空闲后再进行调试命令的读取。Step 3: Detect whether the control subunit 502b is idle, if it is idle, cache part of the debugging commands in the AXI bus matrix subunit 502a to the command cache subunit 502c, and execute step 4; if not, continue to execute step 3 and wait for the control subunit. The debug command is read after the unit 502b is idle.
步骤4：控制子单元502b触发命令处理子单元502e工作，使命令处理子单元502e从命令缓存子单元502c中读取调试命令。Step 4: The control subunit 502b triggers the command processing subunit 502e to work, so that the command processing subunit 502e reads the debug command from the command buffer subunit 502c.
步骤5：命令处理子单元502e将每一条JTAG调试命令转化为JTAG时序信号，并通过JTAG接口502f将JTAG时序信号发送至目标芯片51，其中，命令处理子单元502e通过JTAG总线与JTAG接口通信。Step 5: The command processing subunit 502e converts each JTAG debug command into a JTAG timing signal, and sends the JTAG timing signal to the target chip 51 through the JTAG interface 502f, wherein the command processing subunit 502e communicates with the JTAG interface through the JTAG bus.
步骤6：电平转换单元503接收TAP控制器511从TDO引脚发送的调试结果，并将调试结果通过JTAG总线发送至命令处理子单元502e，命令处理子单元502e将调试结果缓存至结果缓存子单元502d中。Step 6: The level conversion unit 503 receives the debug result sent from the TDO pin by the TAP controller 511, and sends the debug result to the command processing subunit 502e through the JTAG bus, and the command processing subunit 502e caches the debug result in the result buffer subunit 502e. in cell 502d.
步骤7：ARM501检测控制子单元502b是否空闲，如果空闲，从结果缓存子单元502d中读取调试结果，并将调试结果发送至上位机；如果不空闲，继续执行步骤7等待控制子单元502b空闲后再进行调试结果的读取。Step 7: ARM501 detects whether the control subunit 502b is idle, if it is idle, reads the debug result from the result cache subunit 502d, and sends the debug result to the host computer; if it is not idle, continue to step 7 and wait for the control subunit 502b to be idle Then read the debugging results.
表1Table 1
在实施例三中，以向目标芯片中写入一个字节数据为例进行进一步的举例说明，例如，向目标芯片51的目的地址0x00001000写入数据0x12345678，目的地址和写入数据的二进制格式分别为：In the third embodiment, writing one byte of data into the target chip is taken as an example for further illustration. For example, to write data 0x12345678 to the destination address 0x00001000 of the target chip 51, the destination address and the binary format of the written data are respectively for:
目的地址：0x00001000＝00000000 00000000 00010000 00000000BDestination address: 0x00001000＝00000000 00000000 00010000 00000000B
写入数据：0x12345678＝00010010 00110100 01010110 01111000BWrite data: 0x12345678=00010010 00110100 01010110 01111000B
按照实施例一中定义的调试命令的格式定义上述调试过程对应的JTAG调试命令，得到25条JTAG调试命令，具体的JTAG调试命令如表1所示。The JTAG debugging commands corresponding to the above debugging process are defined according to the format of the debugging commands defined in the first embodiment, and 25 JTAG debugging commands are obtained. The specific JTAG debugging commands are shown in Table 1.
FPGA502在收到JTAG调试命令后，命令处理子单元502e按照表1中的字节序号依次从命令缓存子单元502c中读取JTAG调试命令，在TCK的驱动下对TMS、TDI进行操作，或者在TCK的驱动下将TDO中的调试结果存入结果缓存子单元502d中，实现与目标芯片51的TAP控制器511的命令交互，执行对目标芯片51的调试操作。After the FPGA 502 receives the JTAG debug command, the command processing subunit 502e reads the JTAG debug command from the command buffer subunit 502c in turn according to the byte sequence numbers in Table 1, and operates on the TMS and TDI under the drive of the TCK, or Driven by the TCK, the debugging results in the TDO are stored in the result cache subunit 502d, so as to realize command interaction with the TAP controller 511 of the target chip 51, and perform debugging operations on the target chip 51.
结合图3所示的JTAG模块结构和图4所示的运行流程，对本发明实施例中每个调试命令的处理过程进行简要说明，具体的命令处理过程如下：With reference to the JTAG module structure shown in FIG. 3 and the operation flow shown in FIG. 4 , the processing process of each debug command in the embodiment of the present invention is briefly described. The specific command processing process is as follows:
第1字节：命令处理子单元502e从命令缓存子单元502c中读取在确定命令字节的低四位命令码为复位命令后，通过JTAG接口502f连续输出5个TMS＝1的信号至TAP控制器511，从图4中可以看到，无论TAP处于哪种状态，在收到5个连续TMS＝1的信号之后TAP控制器都会回到状态0：Test-Logic Reset，之后再输出一个TMS＝0，TAP切换到状态1：RunTest/Idle，如果没有其他操作，TMS始终输出0，TAP保持在状态1：Run Test/Idle，准备进行其他操作。1st byte: The command processing subunit 502e reads from the command buffer subunit 502c. After determining that the lower four-bit command code of the command byte is the reset command, it continuously outputs 5 TMS=1 signals to the TAP through the JTAG interface 502f The controller 511, as can be seen from Figure 4, no matter which state the TAP is in, after receiving 5 consecutive TMS=1 signals, the TAP controller will return to state 0: Test-Logic Reset, and then output a TMS =0, TAP switches to state 1: RunTest/Idle, if there is no other operation, TMS always outputs 0, TAP remains in state 1: Run Test/Idle, ready to perform other operations.
第2字节：命令处理子单元502e在确定该字节的命令码0001B为设置TAP状态命令后，进一步解析命令码参数1011B为状态11：Shift-IR，并判断该命令没有数据字节，于是从TMS输出1100B，根据图4的运行流程，TAP状态机将从状态1切换到状态11，进入指令寄存器IR移位状态。2nd byte: After determining that the command code 0001B of the byte is the command to set the TAP state, the command processing subunit 502e further parses the command code parameter 1011B as state 11: Shift-IR, and judges that the command has no data bytes, so From the TMS output 1100B, according to the operation flow of FIG. 4, the TAP state machine will switch from state 1 to state 11, and enter the instruction register IR shift state.
第3字节：命令处理子单元502e解析命令码0011B为数据输出和读入，解析参数T为1数据输出完成后TMS为高电平，参数CCC取值1，即数据字节0～1位需要输出，于是FPGA读取第4字节的0～1位从TDI输出到IR寄存器；根据TAP状态机的原理，同时会有两个bit的数据从TDO读入到FPGA(无论是否需要这两个bit数据)，FPGA收到数据后会返回给ARM，由ARM侧软件根据功能判断是否需要TDO的数据，如不需要则直接忽略；如果需要则将数据上传至上位机。The third byte: the command processing subunit 502e parses the command code 0011B as data output and read-in, the parsing parameter T is 1 and TMS is high after the data output is completed, and the parameter CCC takes the value of 1, that is, the data bytes are 0 to 1 bits. The output needs to be output, so the FPGA reads the 0~1 bits of the 4th byte and outputs it from the TDI to the IR register; according to the principle of the TAP state machine, two bits of data will be read from the TDO to the FPGA at the same time (whether or not these two bit data), the FPGA will return the data to the ARM after receiving the data, and the ARM side software will judge whether the TDO data is needed according to the function, if not, it will be ignored directly; if necessary, the data will be uploaded to the host computer.
在数据输出结束后，TMS输出参数T为1，TAP状态机从状态11：Shift-IR切换到状态12：Exit-IR，结束输出；TMS再输出10B，TAP切换到状态15：Update-IR，最后回到状态1：RunTest/Idle，在Update-IR时，输出到指令寄存器IR的数据2将生效，指示访问数据寄存器DR中的2#地址扫描链；图3中的数据扫描选择将2#地址扫描链与数据寄存器DR对接，使得接下来对数据寄存器的操作，就是对2#地址扫描链的操作。After the data output ends, the TMS output parameter T is 1, and the TAP state machine switches from state 11: Shift-IR to state 12: Exit-IR, ending the output; TMS outputs 10B again, and TAP switches to state 15: Update-IR, Finally return to state 1: RunTest/Idle, at the time of Update-IR, the data 2 output to the instruction register IR will take effect, indicating access to the 2# address scan chain in the data register DR; the data scan selection in Figure 3 will be 2# The address scan chain is connected to the data register DR, so that the next operation on the data register is the operation on the 2# address scan chain.
第4字节：为数据字节，已经在第3字节处理时使用。The 4th byte: It is the data byte, which has been used when the 3rd byte is processed.
上述对第2字节至第4字节的处理目的是为了实现对2#地址扫描链的选择。The purpose of the above-mentioned processing of the 2nd byte to the 4th byte is to realize the selection of the 2# address scan chain.
第5字节：解析命令码0001B为设置TAP状态，进一步解析命令码参数0100B为4，根据图4的运行流程，TMS输出1100B从状态1：Run Test/Idle切换到状态4：Shift-DR。The 5th byte: Parse the command code 0001B to set the TAP state, and further parse the command code parameter 0100B as 4. According to the running process of Figure 4, the TMS output 1100B switches from state 1: Run Test/Idle to state 4: Shift-DR.
第6字节：解析命令码0011B为数据输出和读入，解析参数T为0数据输出完成后TMS为低电平，参数CCC为7，即数据字节0～7位需要输出，于是FPGA读取下一字节0～7位从TDI输出到DR寄存器，即输出到2#地址扫描链，同时2#地址扫描链会有8个bit从TDO读入，FPGA会把读入数据返回给ARM，由软件决定数据处理。在8个bit输出结束后，TMS输出参数T为0，TAP状态保持在状态4：Shift-DR，继续准备从TDI输出数据。6th byte: The parsing command code 0011B is the data output and read-in, the parsing parameter T is 0 and the TMS is low after the data output is completed, and the parameter CCC is 7, that is, the 0-7 bits of the data byte need to be output, so the FPGA reads Take the 0~7 bits of the next byte and output them from TDI to the DR register, that is, output to the 2# address scan chain. At the same time, the 2# address scan chain will have 8 bits read in from TDO, and the FPGA will return the read data to the ARM , the data processing is determined by the software. After the 8 bits are output, the TMS output parameter T is 0, and the TAP state remains in state 4: Shift-DR, and continues to prepare to output data from TDI.
第7字节：为数据字节，已在第6字节中处理。7th byte: is the data byte, which has been processed in the 6th byte.
第8、9、10、11、12、13字节：均为数据输出字节，可参考第6、7字节的处理，唯一不同的是第12字节命令参数中T为1，标识这个命令执行完后TMS输出1，结束数据输出，TAP切换到状态5：Exit1-DR，至此目的地址0x00001000已经全部输出到数据寄存器DR中，接下来TMS输出10B，TAP切换到状态8：Update-DR，最后回到状态1：Run Test/Idle。在Update-DR时，2#地址扫描链中数据将更新到地址总线，地址总线定位到目标芯片的地址0x00001000。The 8th, 9th, 10th, 11th, 12th, and 13th bytes are all data output bytes. You can refer to the processing of the 6th and 7th bytes. The only difference is that T in the command parameter of the 12th byte is 1, which identifies this After the command is executed, TMS outputs 1, ends the data output, and TAP switches to state 5: Exit1-DR. So far, the destination address 0x00001000 has been output to the data register DR, then TMS outputs 10B, and TAP switches to state 8: Update-DR , and finally back to state 1: Run Test/Idle. During Update-DR, the data in the 2# address scan chain will be updated to the address bus, and the address bus is located to the address 0x00001000 of the target chip.
上述对第5字节至第13字节的处理目的是为了将目的地址输出至2#地址扫描链中，定位目标芯片的地址0x00001000。The purpose of the above processing of the 5th byte to the 13th byte is to output the destination address to the 2# address scan chain and locate the address 0x00001000 of the target chip.
第14、15、16字节：处理方式类似第2、3、4字节，不同的是第16字节数据输出为00000001B，表示向指令寄存器IR中输出的数据为1，操作结束后1#数据扫描链与数据寄存器DR相接，接下来对数据寄存器的操作，就是对数据扫描链的操作。The 14th, 15th, and 16th bytes: The processing method is similar to the 2nd, 3rd, and 4th bytes. The difference is that the data output of the 16th byte is 00000001B, which means that the data output to the instruction register IR is 1, and 1# after the operation is completed. The data scan chain is connected to the data register DR, and the next operation on the data register is the operation on the data scan chain.
第17字节：同第5字节，设置TAP状态到状态4：Shift-DR17th byte: same as 5th byte, set TAP state to state 4: Shift-DR
第18-25字节：操作同第6-13字节，不同的是输出的数据字节，这里将0x12345678输出到数据寄存器DR中的1#数据扫描链，在Update-DR时，1#数据扫描链中的数据0x12345678将更新到数据总线，而此时地址总线正处于0x00001000的存储单元，完成数据写入。Bytes 18-25: The operation is the same as bytes 6-13, the difference is the output data byte. Here, 0x12345678 is output to the 1# data scan chain in the data register DR. During Update-DR, 1# data The data 0x12345678 in the scan chain will be updated to the data bus, and at this time the address bus is in the storage unit of 0x00001000, completing the data writing.
以上便是向地址0x00001000写入数据0x12345678的流程示例，其他操作同该流程类似。The above is an example of the process of writing data 0x12345678 to address 0x00001000, and other operations are similar to this process.
通过上述示例性的调试命令处理过程，可以根据实际业务需求设置对应的调试命令，已完成不同的调试操作。Through the above exemplary debugging command processing process, corresponding debugging commands can be set according to actual business requirements, and different debugging operations have been completed.
实施例四Embodiment 4
基于同一发明构思，本发明实施例还提供了一种芯片调试的方法，图6为本发明实施例中芯片调试的方法的流程示意图，如图6所示，该方法包括：Based on the same inventive concept, an embodiment of the present invention also provides a method for chip debugging. FIG. 6 is a schematic flowchart of the method for chip debugging in an embodiment of the present invention. As shown in FIG. 6 , the method includes:
步骤601：获取加密后的调试命令。Step 601: Obtain an encrypted debugging command.
在实际实施时，在获取加密后的调试命令之前，该方法还包括：为目标芯片设置对应的调试命令；In actual implementation, before obtaining the encrypted debugging command, the method further includes: setting a corresponding debugging command for the target chip;
示例性的，调试命令可以包括：命令部分和数据部分；命令部分包含N个命令字节，数据部分包含M个数据字节，N和M取正整数；命令部分用于指示目标芯片执行的调试操作，数据部分包括向目标芯片输入的数据。Exemplarily, the debug command may include: a command part and a data part; the command part contains N command bytes, the data part contains M data bytes, and N and M are positive integers; the command part is used to instruct the target chip to perform debugging. Operation, the data portion includes data input to the target chip.
具体的，命令部分中每一个命令字节包括：位于低四位的命令码和位于高四位的命令码参数，或者位于低四位的命令码和位于高四位的任意值；命令码参数是指位于同一字节中的低四位的命令码对应的执行参数，执行参数用于具体指示目标芯片执行的调试操作。Specifically, each command byte in the command part includes: the command code located in the lower four digits and the command code parameter located in the upper four digits, or the command code located in the lower four digits and any value located in the upper four digits; the command code parameter It refers to the execution parameter corresponding to the lower four-bit command code located in the same byte, and the execution parameter is used to specifically instruct the debugging operation performed by the target chip.
步骤602：对加密后的调试命令进行解密得到调试命令。Step 602: Decrypt the encrypted debugging command to obtain a debugging command.
这里，调试命令用于指示对目标芯片的调试操作。Here, the debug command is used to instruct a debug operation on the target chip.
步骤603：将调试命令转换成对应的时序信号。Step 603: Convert the debugging command into a corresponding timing signal.
示例性的，调试命令为JTAG调试命令时，时序包括：测试时钟信号，测试模式选择信号、测试数据输入信号和测试数据输出信号；相应的，将JTAG调试命令转换成包括测试时钟信号，测试模式选择信号和测试数据输入信号的JTAG时序信号；Exemplarily, when the debug command is a JTAG debug command, the timing sequence includes: a test clock signal, a test mode selection signal, a test data input signal, and a test data output signal; correspondingly, the JTAG debug command is converted to include a test clock signal, a test mode JTAG timing signal for selection signal and test data input signal;
步骤604：将时序信号发送至目标芯片，使目标芯片按照时序信号执行调试操作。Step 604: Send the timing signal to the target chip, so that the target chip performs debugging operations according to the timing signal.
在实际实施时，将时序信号的电平转换成与目标芯片适配的电平；将电平转换后的时序信号输出至目标芯片。In actual implementation, the level of the timing signal is converted into a level adapted to the target chip; the level-converted timing signal is output to the target chip.
示例性的，当调试命令为JTAG调试命令，在将时序信号发送至目标芯片之后，该方法还包括：接收目标芯片发送的测试数据输出信号。Exemplarily, when the debug command is a JTAG debug command, after the timing signal is sent to the target chip, the method further includes: receiving a test data output signal sent by the target chip.
示例性的，可以控制ARM获取调试命令；并控制ARM对加密后的调试命令进行解密得到调试命令。Exemplarily, the ARM can be controlled to obtain the debugging command; and the ARM can be controlled to decrypt the encrypted debugging command to obtain the debugging command.
示例性的，可以控制FPGA将调试命令转换成时序信号；并控制FPGA将时序信号发送至目标芯片。Exemplarily, the FPGA can be controlled to convert the debug commands into timing signals; and the FPGA can be controlled to send the timing signals to the target chip.
实施例五Embodiment 5
基于同一发明构思，本发明实施例还提供了一种计算机可读存储介质，例如包括计算机程序的存储器，上述计算机程序可由芯片调试装置中的处理器执行，以完成前述一个或者更多个实施例中的方法步骤。Based on the same inventive concept, an embodiment of the present invention further provides a computer-readable storage medium, such as a memory including a computer program, and the computer program can be executed by a processor in a chip debugging device to implement one or more of the foregoing embodiments method steps in .
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.
本发明是参照根据本发明实施例的方法、装置(系统)、和计算机程序产品的流程示意图和/或方框图来描述的。应理解可由计算机程序指令实现流程示意图和/或方框图中的每一流程和/或方框、以及流程示意图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。The present invention is described with reference to schematic flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block in the schematic flow diagrams and/or block diagrams, and combinations of procedures and/or blocks in the schematic flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a process or processes in a flowchart diagram and/or a block or blocks in a block diagram.
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions An apparatus implements the functions specified in a flow or flows of the flowchart diagrams and/or a block or blocks of the block diagrams.
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowchart diagram and/or the block or blocks of the block diagram.
以上，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。The above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710743553.XACN109426594A (en) | 2017-08-25 | 2017-08-25 | A kind of chip debugging apparatus, method and computer readable storage medium |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710743553.XACN109426594A (en) | 2017-08-25 | 2017-08-25 | A kind of chip debugging apparatus, method and computer readable storage medium |
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| CN109426594Atrue CN109426594A (en) | 2019-03-05 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201710743553.XAWithdrawnCN109426594A (en) | 2017-08-25 | 2017-08-25 | A kind of chip debugging apparatus, method and computer readable storage medium |
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| CN (1) | CN109426594A (en) |
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| WW01 | Invention patent application withdrawn after publication | Application publication date:20190305 | |
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