CN109411539B - Semiconductor device, method of manufacturing the same, and electronic apparatus including the same - Google Patents

Abstract

The present disclosure provides a semiconductor device, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. According to an embodiment, a semiconductor device includes: a substrate; a semiconductor nanostructure spaced apart from the substrate and extending laterally over the surface of the substrate; a gate stack formed around an outer periphery of the semiconductor nanostructure. The portion of the gate stack below the semiconductor nanostructure includes a first sidewall and a second sidewall opposite each other, and the portion of the gate stack above the semiconductor nanostructure includes a third sidewall and a fourth sidewall opposite each other. At least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall.

Description

Translated fromChinese

半导体器件及其制造方法及包括该半导体器件的电子设备Semiconductor device, method for manufacturing the same, and electronic equipment including the same

技术领域technical field

本公开涉及半导体领域，具体地，涉及基于半导体纳米结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。The present disclosure relates to the field of semiconductors, and in particular, to semiconductor nanostructure-based semiconductor devices, methods of making the same, and electronic devices including such semiconductor devices.

背景技术Background technique

基于半导体纳米结构如纳米线或纳米片的半导体器件例如金属氧化物半导体场效应晶体管(MOSFET)，尤其是具有四周全环绕栅极(all around wrapped gate，AAWG)的器件，具有良好的短沟道效应，并且使得器件尺寸能够进一步按比例缩小。然而，在制造具有AAWG的半导体器件时，将AAWG的上部与下部对准是非常困难的。此外，在这种器件中，难以对沟道施加强应力以增强器件的性能。Semiconductor devices based on semiconductor nanostructures such as nanowires or nanosheets such as metal oxide semiconductor field effect transistors (MOSFETs), especially devices with an all around wrapped gate (AAWG), have good short channel effect and enable further scaling down of device size. However, when fabricating a semiconductor device with an AAWG, it is very difficult to align the upper part and the lower part of the AAWG. Furthermore, in such devices, it is difficult to apply strong stress to the channel to enhance the performance of the device.

发明内容SUMMARY OF THE INVENTION

有鉴于此，本公开的目的至少部分地在于提供一种具有改进性能的基于半导体纳米结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。In view of this, it is an object of the present disclosure, at least in part, to provide a semiconductor nanostructure-based semiconductor device with improved properties, a method of fabricating the same, and an electronic device including such a semiconductor device.

根据本公开的一个方面，提供了一种半导体器件，包括：衬底；与衬底间隔开、在衬底表面上方横向延伸的半导体纳米结构；以及环绕半导体纳米结构的外周形成的栅堆叠。半导体纳米结构下方的栅堆叠部分包括彼此相对的第一侧壁和第二侧壁，半导体纳米结构上方的栅堆叠部分包括彼此相对的第三侧壁和第四侧壁。第一侧壁的至少一部分与第三侧壁的至少一部分基本共面，和/或第二侧壁的至少一部分与第四侧壁的至少一部分基本共面。According to one aspect of the present disclosure, there is provided a semiconductor device comprising: a substrate; a semiconductor nanostructure spaced from the substrate and extending laterally over a surface of the substrate; and a gate stack formed around a perimeter of the semiconductor nanostructure. The gate stack portion below the semiconductor nanostructure includes first and second sidewalls opposite to each other, and the gate stack portion above the semiconductor nanostructure includes third and fourth sidewalls opposite to each other. At least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall.

根据本公开的另一个方面，提供了一种制造半导体器件的方法，包括：在衬底上形成相对于衬底悬置的预备半导体纳米结构；在衬底上形成预备伪栅层，所述预备伪栅层环绕悬置的预备半导体纳米结构的外周；对预备伪栅层和预备半导体纳米结构进行图案化，形成自对准的伪栅层和半导体纳米结构，伪栅层仍然环绕半导体纳米结构的外周；在伪栅层的侧壁上形成环绕半导体纳米结构的栅侧墙；至少部分地去除伪栅层以在栅侧墙内侧留出环绕半导体纳米结构外周的空间；在所述空间中形成栅堆叠。According to another aspect of the present disclosure, there is provided a method of fabricating a semiconductor device, comprising: forming a preliminary semiconductor nanostructure suspended relative to the substrate on a substrate; forming a preliminary dummy gate layer on the substrate, the preliminary The dummy gate layer surrounds the periphery of the suspended preparatory semiconductor nanostructure; the preparatory dummy gate layer and the preparatory semiconductor nanostructure are patterned to form a self-aligned dummy gate layer and semiconductor nanostructure, and the dummy gate layer still surrounds the semiconducting nanostructure. perimeter; forming gate spacers surrounding the semiconductor nanostructure on sidewalls of the dummy gate layer; at least partially removing the dummy gate layer to leave a space inside the gate spacer surrounding the periphery of the semiconductor nanostructure; forming a gate in the space stack.

根据本公开的另一个方面，提供了一种电子设备，包括至少部分地由前述半导体器件形成的集成电路。According to another aspect of the present disclosure, there is provided an electronic device including an integrated circuit formed at least in part from the aforementioned semiconductor device.

根据本公开的实施例，形成了自对准环绕栅(SWAG)。可以较好地控制SWAG的栅长，这对于大规模制造是有利的。According to an embodiment of the present disclosure, a self-aligned surround gate (SWAG) is formed. The gate length of the SWAG can be better controlled, which is beneficial for large-scale manufacturing.

附图说明Description of drawings

通过以下参照附图对本公开实施例的描述，本公开的上述以及其它目的、特征和优点将更为清楚，在附图中：The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

图1至16(c)是示出了制造根据本公开的实施例的半导体器件的流程中部分阶段的示意图。1 to 16(c) are schematic diagrams showing some stages in a process of fabricating a semiconductor device according to an embodiment of the present disclosure.

贯穿附图，相同或相似的附图标记表示相同或相似的部件。Throughout the drawings, the same or similar reference numbers refer to the same or similar parts.

具体实施方式Detailed ways

以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

根据本公开的实施例，提供了一种基于半导体纳米结构如纳米线或纳米片的半导体器件。半导体纳米结构可以是与衬底间隔开的横向延伸结构。这样，可以绕半导体纳米结构的外周形成四周全环绕栅(AAWG)结构。栅堆叠可以自对准的方式形成。更具体地，半导体纳米结构下方的栅堆叠部分可以包括彼此相对的第一侧壁和第二侧壁，半导体纳米结构上方的栅堆叠部分可以包括彼此相对的第三侧壁和第四侧壁。所谓“自对准”，可以是指第一侧壁的至少一部分与第三侧壁的至少一部分基本共面，和/或第二侧壁的至少一部分与第四侧壁的至少一部分基本共面。例如，第一侧壁和第三侧壁可以构成连续延伸的第一平面，该第一平面环绕半导体纳米结构的一端，和/或第二侧壁和第四侧壁可以构成连续延伸的第二平面，该第二平面环绕半导体纳米结构的另一端。第一平面和第二平面可以基本上彼此平行，且可以沿例如竖直方向(例如，大致垂直于衬底表面的方向)延伸。According to embodiments of the present disclosure, there is provided a semiconductor device based on semiconductor nanostructures such as nanowires or nanosheets. The semiconductor nanostructures may be laterally extending structures spaced apart from the substrate. In this way, a gate all around (AAWG) structure can be formed around the perimeter of the semiconductor nanostructure. The gate stack can be formed in a self-aligned manner. More specifically, the gate stack portion below the semiconductor nanostructure may include first and second sidewalls opposed to each other, and the gate stack portion above the semiconductor nanostructure may include third and fourth sidewalls opposed to each other. By "self-aligned", it may mean that at least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall . For example, the first and third sidewalls can form a continuously extending first plane surrounding one end of the semiconductor nanostructure, and/or the second and fourth sidewalls can form a second continuously extending plane The second plane surrounds the other end of the semiconductor nanostructure. The first and second planes may be substantially parallel to each other, and may extend, for example, in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate).

半导体纳米结构被栅堆叠所包围，从而可以用作器件的沟道。在半导体纳米结构即沟道两端，可以形成源区和漏区。源区和漏区之间可以通过沟道而电连通。源区和漏区可以是掺杂的半导体层，其材料可以与半导体纳米结构的材料相同。源区和漏区可以呈鳍状延伸，其纵向延伸方向可以与半导体纳米结构的纵向延伸方向实质上一致。The semiconductor nanostructure is surrounded by a gate stack, which can serve as a channel for the device. At both ends of the semiconductor nanostructure, ie, the channel, source and drain regions may be formed. The source and drain regions may be in electrical communication through the channel. The source and drain regions may be doped semiconductor layers, which may be of the same material as the semiconductor nanostructures. The source region and the drain region may extend in a fin shape, and the longitudinal extension direction of the source region and the drain region may be substantially the same as the longitudinal extension direction of the semiconductor nanostructure.

源区和漏区各自靠近半导体纳米线结构即沟道一侧的端部可以呈现随着靠近半导体纳米结构而渐缩的形状。在栅堆叠的侧壁上可以形成栅侧墙。源区和漏区各自的渐缩形状的端部可以被栅侧墙环绕。这种结构有利于降低寄生电阻。The ends of the source region and the drain region on one side of the source region and the drain region near the semiconductor nanowire structure, ie, the channel, may exhibit a shape that tapers as they approach the semiconductor nanostructure. Gate spacers may be formed on sidewalls of the gate stack. Ends of the respective tapered shapes of the source and drain regions may be surrounded by gate spacers. This structure is beneficial to reduce parasitic resistance.

对于源区和漏区，可以应用应力工程。例如，可以在源区和漏区的表面上形成应力层。For source and drain regions, stress engineering can be applied. For example, stress layers may be formed on the surfaces of the source and drain regions.

这种半导体纳米结构器件例如可以如下制造。具体地，可以在衬底上形成相对于衬底悬置的预备半导体纳米结构。例如，预备半导体纳米结构可以形成为两端锚定的悬置梁形式。由于悬置形式，可以环绕预备半导体纳米结构的外周形成预备伪栅层。由于预备伪栅层的存在，预备半导体纳米结构可以不再是悬置形式，而是被预备伪栅层所支撑。于是，可以去除梁的锚定部分，而留下梁(随后用作沟道)，以便于随后在其两端形成源区和漏区。也即，可以对预备半导体纳米结构进行构图，留下其一部分(例如，中部)以用作沟道，称作半导体纳米结构。这种构图也可以对预备伪栅层进行，并且以自对准方式进行，从而得到的伪栅层可以自对准于半导体纳米结构。例如，可以通过利用相同掩模来实现自对准的构图。随后，可以通过将伪栅层替换为栅堆叠来形成自对准的栅堆叠。Such a semiconductor nanostructure device can be produced, for example, as follows. Specifically, preliminary semiconductor nanostructures can be formed on the substrate that are suspended relative to the substrate. For example, the preparatory semiconductor nanostructures can be formed in the form of suspended beams anchored at both ends. Due to the suspended form, a preliminary dummy gate layer can be formed around the periphery of the preliminary semiconductor nanostructure. Due to the existence of the preparatory dummy gate layer, the preparatory semiconductor nanostructure can no longer be in a suspended form, but is supported by the preparatory dummy gate layer. Thus, the anchor portion of the beam can be removed, leaving the beam (which is then used as a channel) for subsequent formation of source and drain regions at both ends thereof. That is, a preparatory semiconductor nanostructure can be patterned, leaving a portion (eg, a middle portion) of it to serve as a channel, referred to as a semiconductor nanostructure. This patterning can also be performed on the preparatory dummy gate layer, and in a self-aligned manner, so that the resulting dummy gate layer can be self-aligned to the semiconductor nanostructure. For example, self-aligned patterning can be achieved by utilizing the same mask. Subsequently, a self-aligned gate stack can be formed by replacing the dummy gate layer with a gate stack.

为便于栅堆叠位置的限定，可以在伪栅层的侧壁上形成栅侧墙。为避免在半导体纳米结构的侧壁上形成栅侧墙，可以在半导体纳米结构的端部上进行外延生长，使得端部相对伸出。由于这种突出的端部，可以环绕相对伸出的端部在伪栅层的侧壁上形成栅侧墙，而不会形成在端部的侧壁上。另外，可以去除端部相对于栅侧墙伸出的部分。之后，可以通过去除伪栅层，并在栅侧墙内侧由于伪栅层的去除而留下的空间中形成栅堆叠。伪栅层不必完全去除，只需露出纳米线的外周即可。In order to facilitate the definition of the position of the gate stack, gate spacers may be formed on the sidewalls of the dummy gate layer. To avoid forming gate spacers on the sidewalls of the semiconductor nanostructures, epitaxial growth may be performed on the ends of the semiconductor nanostructures so that the ends protrude relatively. Due to such protruding end portions, gate spacers can be formed on the sidewalls of the dummy gate layer around the oppositely protruding end portions without being formed on the sidewalls of the end portions. In addition, the portion of the end protruding with respect to the gate spacer may be removed. After that, the dummy gate layer can be removed, and a gate stack can be formed in the space left by the removal of the dummy gate layer inside the gate spacer. The dummy gate layer does not have to be completely removed, but only the outer periphery of the nanowire is exposed.

本公开可以各种形式呈现，以下将描述其中一些示例。The present disclosure may be presented in various forms, some examples of which are described below.

如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。As shown in FIG. 1, asubstrate 1001 is provided. Thesubstrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like. In the following description, for the convenience of description, a bulk Si substrate is used as an example for description. Here, a silicon wafer is provided as thesubstrate 1001 .

在衬底1001中，例如可以通过离子注入，形成阱区1001-w。可以根据所要形成的器件类型，选择阱区1001-w的导电类型。例如，如果要形成的器件为p型器件(例如，pMOSFET)，则可以形成n型阱区1001-w。n型阱区1001-w可以通过向衬底1001中注入n型杂质如磷(P)或砷(As)并通过退火来激活注入的杂质而形成。另一方面，如果要形成的器件为n型器件(例如，nMOSFET)，则可以形成p型阱区1001-w。p型阱区1001-w可以通过向衬底1001中注入p型杂质如硼(B)并通过退火来激活注入的杂质而形成。In thesubstrate 1001, a well region 1001-w may be formed, for example, by ion implantation. The conductivity type of the well region 1001-w may be selected according to the type of device to be formed. For example, if the device to be formed is a p-type device (eg, a pMOSFET), an n-type well region 1001-w may be formed. The n-type well region 1001-w may be formed by implanting n-type impurities such as phosphorus (P) or arsenic (As) into thesubstrate 1001 and activating the implanted impurities by annealing. On the other hand, if the device to be formed is an n-type device (eg, an nMOSFET), a p-type well region 1001-w may be formed. The p-type well region 1001-w may be formed by implanting p-type impurities such as boron (B) into thesubstrate 1001 and activating the implanted impurities by annealing.

在衬底1001上，可以通过例如外延生长，依次形成牺牲层1003和预备半导体纳米结构层1005。On thesubstrate 1001, asacrificial layer 1003 and a preparatorysemiconductor nanostructure layer 1005 may be sequentially formed by, for example, epitaxial growth.

牺牲层1003可以具有所需的刻蚀选择性，例如相对于之下的衬底1001以及之上的预备半导体纳米结构层1005的刻蚀选择性，从而可以被选择性刻蚀。另外，考虑预备半导体纳米结构层1005的生长质量，牺牲层1003可以包括半导体材料。牺牲层1003可以具有与之下的衬底1001以及之上的预备半导体纳米结构层1005相同或基本相同的晶体结构。例如，牺牲层1003可以包括SiGe，Ge的原子百分比可以为约10-30％。牺牲层1003的厚度可以根据随后将要形成的环绕栅极的尺寸来确定，例如为约30-60nm。Thesacrificial layer 1003 may have a desired etch selectivity, eg, relative to the etch selectivity of theunderlying substrate 1001 and the preparatorysemiconductor nanostructure layer 1005 above, so that it can be selectively etched. In addition, considering the growth quality of the preparatorysemiconductor nanostructure layer 1005, thesacrificial layer 1003 may include a semiconductor material. Thesacrificial layer 1003 may have the same or substantially the same crystal structure as theunderlying substrate 1001 and the preparatorysemiconductor nanostructure layer 1005 above. For example, thesacrificial layer 1003 may include SiGe, and the atomic percentage of Ge may be about 10-30%. The thickness of thesacrificial layer 1003 can be determined according to the size of the surrounding gate to be formed later, for example, about 30-60 nm.

预备半导体纳米结构层1005可以包括半导体材料例如Si，随后可以形成器件的沟道。可以根据器件的沟道尺寸来确定预备半导体纳米结构层1005的尺寸，特别是其厚度(图中竖直方向上的维度)。例如，预备半导体纳米结构层1005的厚度为约5-15nm。The preparatorysemiconductor nanostructure layer 1005 may comprise a semiconductor material such as Si, and the channel of the device may then be formed. The dimensions of the preparatorysemiconductor nanostructure layer 1005, in particular its thickness (dimension in the vertical direction in the figure), can be determined according to the channel dimensions of the device. For example, the thickness of the preparatorysemiconductor nanostructure layer 1005 is about 5-15 nm.

可以在预备半导体纳米结构层1005中限定所需的沟道形式，例如纳米线或纳米片。这可以通过对预备半导体纳米结构层1005构图来实现。例如，这可以如下进行。The desired channel form, such as nanowires or nanosheets, can be defined in the preparatorysemiconductor nanostructure layer 1005 . This can be achieved by patterning the preparatorysemiconductor nanostructure layer 1005 . For example, this can be done as follows.

如图2所示，可以在预备半导体纳米结构层1005上形成掩模层1007如光刻胶。可以通过光刻将光刻胶1007构图为限定所需的沟道形式。在该示例中，光刻胶1007的中部为线状，以便随后在预备半导体纳米结构层1005中限定纳米线。但是，本公开不限于此。例如，光刻胶可以限定矩形或方形，以便在预备半导体纳米结构层1005中限定纳米片。另外，光刻胶1007的两端覆盖预备半导体纳米结构层1005，以便限定支撑部，以支撑在后继工艺中将与衬底1001相分离的纳米线。As shown in FIG. 2 , amask layer 1007 such as photoresist may be formed on the preparedsemiconductor nanostructure layer 1005 . Thephotoresist 1007 can be patterned by photolithography to define the desired channel form. In this example, the middle portion of thephotoresist 1007 is wire-shaped to subsequently define nanowires in the preparatorysemiconductor nanostructure layer 1005 . However, the present disclosure is not limited thereto. For example, the photoresist may define rectangles or squares to define nanosheets in the preparedsemiconductor nanostructure layer 1005 . In addition, both ends of thephotoresist 1007 are covered with the preparatorysemiconductor nanostructure layer 1005 so as to define support portions to support the nanowires to be separated from thesubstrate 1001 in a subsequent process.

然后，可以将光刻胶1007的图案转移到预备半导体纳米结构层1005中。如图3(a)、3(b)、3(c)和3(d)(图3(a)是俯视图，图3(b)是沿图3(a)中AA′线的截面图，图3(c)是沿图3(a)中B1B1′线的截面图，图3(d)是沿图3(a)中B2B2′线的截面图)所示，可以光刻胶1007作为刻蚀掩模，对预备半导体纳米结构层1005进行选择性刻蚀如反应离子刻蚀(RIE)。RIE可以沿竖直方向(例如，大致垂直于衬底表面的方向)进行。于是，预备半导体纳米结构层1005可以呈现与光刻胶1007基本上相同的图案。另外，可以对牺牲层1003进行选择性刻蚀如RIE。而且，在刻蚀过程中，可以使得在预备半导体纳米结构层1005下方，在牺牲层1003中出现底切，从而可以将预备半导体纳米结构层1005与衬底1001相分离。于是，形成了相对于衬底1001悬置的预备纳米线(预备半导体纳米结构层1005的中部)，该预备纳米线在两端通过牺牲层1003支撑在衬底1001上。之后，可以去除光刻胶1007。Then, the pattern ofphotoresist 1007 can be transferred into the preparatorysemiconductor nanostructure layer 1005 . Figure 3(a), 3(b), 3(c) and 3(d) (Figure 3(a) is a top view, Figure 3(b) is a cross-sectional view along the line AA' in Figure 3(a), Fig. 3(c) is a cross-sectional view along the line B1B1' in Fig. 3(a), and Fig. 3(d) is a cross-sectional view along the line B2B2' in Fig. 3(a)). As shown,photoresist 1007 can be used as the etching An etching mask is used to perform selective etching such as reactive ion etching (RIE) on the preparedsemiconductor nanostructure layer 1005 . RIE can be performed in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate). Thus, the preparatorysemiconductor nanostructure layer 1005 may exhibit substantially the same pattern as thephotoresist 1007 . In addition, thesacrificial layer 1003 may be selectively etched such as RIE. Also, during the etching process, undercuts can be made in thesacrificial layer 1003 under the preparatorysemiconductor nanostructure layer 1005 , so that the preparatorysemiconductor nanostructure layer 1005 can be separated from thesubstrate 1001 . Thus, a preliminary nanowire suspended with respect to the substrate 1001 (the middle of the preliminary semiconductor nanostructure layer 1005 ) is formed, and the preliminary nanowire is supported on thesubstrate 1001 by thesacrificial layers 1003 at both ends. Afterwards, thephotoresist 1007 can be removed.

在以上通过牺牲层来形成悬置结构。由于牺牲层可以通过外延生长来形成，故而其尺寸控制较好。但是，本公开不限于此。本领域存在多种方式来形成悬置结构。例如，可以使衬底1001的表面部分变性从而相对于其下部具备刻蚀选择性，表面的变性部分可以类似于上述系数层1003起作用。The suspension structure is formed above through the sacrificial layer. Since the sacrificial layer can be formed by epitaxial growth, its size is better controlled. However, the present disclosure is not limited thereto. There are various ways in the art to form suspension structures. For example, the surface portion of thesubstrate 1001 can be denatured to have etch selectivity with respect to the lower portion thereof, and the denatured portion of the surface can function similarly to thecoefficient layer 1003 described above.

为形成具有自对准特征的栅堆叠，可以限定栅堆叠的位置。可以利用伪栅结构来占据栅堆叠的位置，在经过一系列处理之后，再将伪栅结构替换为栅堆叠。例如，这可以如下进行。To form a gate stack with self-aligned features, the location of the gate stack can be defined. The position of the gate stack can be occupied by the dummy gate structure, and after a series of processing, the dummy gate structure is replaced with the gate stack. For example, this can be done as follows.

如图4所示，可以在图3(a)、3(b)、3(c)和3(d)所示的结构上，例如通过淀积，形成环绕上述悬置预备纳米线的伪栅层1011。伪栅层1011可以包括提供所需刻蚀选择性的材料，例如氧化物(例如，氧化硅)。在该示例中，伪栅层1011填满了预备纳米线下方、牺牲层1003中的空间，并且还覆盖预备半导体纳米结构层1005的基本上全部顶面。可以对伪栅层1011进行平坦化处理如化学机械抛光(CMP)。As shown in FIG. 4, a dummy gate surrounding the above-mentioned suspended preparatory nanowires may be formed on the structures shown in FIGS. 3(a), 3(b), 3(c) and 3(d), for example, bydeposition Layer 1011. Thedummy gate layer 1011 may include a material that provides the desired etch selectivity, such as an oxide (eg, silicon oxide). In this example, thedummy gate layer 1011 fills the space in thesacrificial layer 1003 under the preparatory nanowire, and also covers substantially all of the top surface of the preparatorysemiconductor nanostructure layer 1005 . Thedummy gate layer 1011 may be planarized, such as chemical mechanical polishing (CMP).

另外，为了保护预备纳米线，在形成伪栅层1011之前，可以先绕预备纳米线的外周形成保护层1009。保护层1009可以包括提供所需刻蚀选择性的材料，例如HfO₂。保护层1009可以为一薄膜，例如大致共形地形成。In addition, in order to protect the preliminary nanowire, before forming thedummy gate layer 1011, aprotective layer 1009 may be formed around the outer periphery of the preliminary nanowire. Theprotective layer 1009 may include a material that provides the desired etch selectivity, such as HfO₂ . Theprotective layer 1009 may be a thin film, eg, formed substantially conformally.

在此，所谓“所需刻蚀选择性”，本领域技术人员可以根据上下文理解其含义。例如，当描述“对某一层进行选择性刻蚀”时，该层相对于暴露于对该层进行刻蚀的刻蚀配方中的其他层可以具有刻蚀选择性。Here, the so-called "required etching selectivity" can be understood by those skilled in the art according to the context. For example, when it is described that "a layer is selectively etched," the layer may have etch selectivity relative to other layers exposed to the etch recipe in which the layer is etched.

可以将伪栅层1011构图为伪栅结构。例如，伪栅结构可以与最终将用作沟道的纳米线相交(例如，各自的纵向延伸方向彼此大致垂直)，以便在纳米线中限定沟道区。Thedummy gate layer 1011 may be patterned into a dummy gate structure. For example, the dummy gate structures may intersect with nanowires that will ultimately serve as channels (eg, with respective longitudinal extensions substantially perpendicular to each other) to define channel regions in the nanowires.

例如，如图5所示，可以在伪栅层1011上形成掩模层1013例如光刻胶。可以通过光刻将光刻胶1013构图为限定所需的栅形式，例如纵向沿与预备纳米线的纵向延伸方向(图5中的水平方向)相交(例如，大致垂直)的方向(图5中的竖直方向)延伸的棒状。For example, as shown in FIG. 5 , amask layer 1013 such as photoresist may be formed on thedummy gate layer 1011 . Thephotoresist 1013 can be patterned by photolithography to define the desired gate form, eg, longitudinally in a direction that intersects (eg, approximately vertical) (eg, substantially vertical) with the longitudinal extension (horizontal direction in FIG. 5 ) of the prepared nanowires. vertical direction) extending rod.

然后，可以将光刻胶1013的图案转移到伪栅层1011中以形成伪栅结构。如图6(a)和6(b)(图6(a)是俯视图，图6(b)是截面图，截取位置为前面示出的AA′线)所示，可以光刻胶1013为刻蚀掩模，对伪栅层1011进行选择性刻蚀如RIE。RIE可以沿竖直方向(例如，大致垂直于衬底表面的方向)进行。于是，伪栅层1011在俯视图中呈现与光刻胶1013基本上相同的棒状，且环绕预备纳米线。Then, the pattern ofphotoresist 1013 may be transferred into thedummy gate layer 1011 to form a dummy gate structure. As shown in FIGS. 6(a) and 6(b) (FIG. 6(a) is a top view, FIG. 6(b) is a cross-sectional view, and the interception position is the line AA' shown earlier), thephotoresist 1013 can be used as the etching An etching mask is used to selectively etch thedummy gate layer 1011 such as RIE. RIE can be performed in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate). Thus, thedummy gate layer 1011 exhibits substantially the same rod shape as thephotoresist 1013 in plan view, and surrounds the preparatory nanowire.

另外，可以依次对保护层1009、预备半导体纳米结构层1005、牺牲层1003进行选择性刻蚀如RIE。RIE同样可以沿竖直方向(例如，大致垂直于衬底表面的方向)进行。于是，预备半导体纳米结构层1005留下的部分形成了纳米线(仍然标注为“1005”)，该纳米线被伪栅层1011所围绕，且由伪栅层1011支撑在衬底1001上。另外，牺牲层1003已被完全去除。之后，可以去除光刻胶1013。In addition, theprotective layer 1009 , the preparatorysemiconductor nanostructure layer 1005 , and thesacrificial layer 1003 may be selectively etched, such as RIE, in sequence. RIE can also be performed in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate). The portion left by the preparatorysemiconductor nanostructure layer 1005 thus forms a nanowire (still labeled "1005") surrounded by and supported on thesubstrate 1001 by thedummy gate layer 1011 . Additionally, thesacrificial layer 1003 has been completely removed. Afterwards, thephotoresist 1013 can be removed.

由于采用同一掩模层1013作为刻蚀掩模进行刻蚀，因此，伪栅层1011中位于纳米线1005上方的部分和位于纳米线1005下方的部分可以自对准。即，上下两部分的至少部分侧壁可以在竖直方向上实质上对齐或者说共面。此外，伪栅层1011可以自对准于纳米线1005(随后将形成沟道)。因此，可以得到自对准环绕栅极(self-aligned wrapped aroundgate，SWAG)结构。由于这种SWAG结构是通过光刻得到的，其尺寸(特别是图中水平方向上的尺寸)可以得到很好地控制，且因此可以很好地控制器件的栅长，这对于大规模制造而言是有利的。Since thesame mask layer 1013 is used as an etching mask for etching, the portion of thedummy gate layer 1011 above thenanowire 1005 and the portion below thenanowire 1005 can be self-aligned. That is, at least part of the side walls of the upper and lower parts may be substantially aligned or coplanar in the vertical direction. In addition, thedummy gate layer 1011 can be self-aligned to the nanowire 1005 (the channel will be formed later). Therefore, a self-aligned wrapped around gate (SWAG) structure can be obtained. Since this SWAG structure is obtained by photolithography, its size (especially the size in the horizontal direction in the figure) can be well controlled, and thus the gate length of the device can be well controlled, which is very important for large-scale manufacturing. Words are beneficial.

通过以上处理，得到了自对准的沟道和(伪)栅结构。接下来，可以在沟道即纳米线1005两端形成源/漏区。例如，源/漏区可以通过在纳米线1005两端形成掺杂半导体材料来形成。为便于源/漏区的形成以及随后伪栅结构的替换，可以在伪栅层1011的侧壁上形成侧墙(spacer)。为了在伪栅层1011的侧壁上形成侧墙而并不在纳米线1005的侧壁上形成侧墙，可以在纳米线1005两端设置横向延伸部分。因为按照侧墙形成工艺，侧墙可以在竖直侧壁上形成，而并不形成在横向表面上。由于纳米线1005两端的横向延伸部分，侧墙可以不形成在纳米线1005的侧壁上。Through the above process, a self-aligned channel and (dummy) gate structure is obtained. Next, source/drain regions may be formed at both ends of the channel, ie, thenanowire 1005 . For example, the source/drain regions may be formed by forming doped semiconductor material across thenanowires 1005 . To facilitate the formation of the source/drain regions and subsequent replacement of the dummy gate structure, spacers may be formed on the sidewalls of thedummy gate layer 1011 . In order to form spacers on the sidewalls of thedummy gate layer 1011 but not on the sidewalls of thenanowires 1005 , laterally extending portions may be provided at both ends of thenanowires 1005 . Because according to the sidewall forming process, the sidewalls can be formed on the vertical sidewalls and not on the lateral surfaces. Due to the laterally extending portions at both ends of thenanowire 1005 , the sidewall spacers may not be formed on the sidewalls of thenanowire 1005 .

例如，如图7所示，可以通过选择性外延生长，从纳米线1005的侧壁生长外延层1015。生长可以纳米线1005(在此为Si)和衬底1001(在此也为Si)的露出表面为种子。外延层1015可以包括与纳米线1005相同的半导体材料，例如Si。当然，本公开不限于此。例如，外延层1015可以包括与纳米线1005不同的半导体材料，例如晶格常数不同的半导体材料以便向纳米线1005中施加应力。外延层1015可以生长一定的厚度，例如约10-30nm。在纳米线1005的两端生长的外延层1015由于其表面取向而可以呈现纺锤状。具体地，外延层1015为朝外侧先扩张然后渐缩的形状。For example, as shown in FIG. 7,epitaxial layers 1015 may be grown from the sidewalls ofnanowires 1005 by selective epitaxial growth. Growth can be seeded by the exposed surfaces of nanowires 1005 (here Si) and substrate 1001 (here also Si).Epitaxial layer 1015 may comprise the same semiconductor material asnanowire 1005, eg, Si. Of course, the present disclosure is not limited thereto. For example,epitaxial layer 1015 may include a different semiconductor material thannanowire 1005 , eg, a semiconductor material with a different lattice constant, in order to apply stress intonanowire 1005 . Theepitaxial layer 1015 may be grown to a certain thickness, eg, about 10-30 nm. Theepitaxial layer 1015 grown on both ends of thenanowire 1005 may exhibit a spindle shape due to its surface orientation. Specifically, theepitaxial layer 1015 has a shape that first expands and then tapers toward the outside.

外延层1015随后可以用来形成延伸区(extension)。为此，可以对外延层1015进行一定导电类型的掺杂。例如，对于n型器件，可以利用n型杂质如P或As进行n型掺杂，而对于p型器件，可以利用p型杂质如B进行p型掺杂。可以在生长外延层1015的同时进行原位掺杂。Epitaxial layer 1015 may then be used to form extensions. To this end, theepitaxial layer 1015 may be doped with a certain conductivity type. For example, for n-type devices, n-type doping can be performed with n-type impurities such as P or As, while for p-type devices, p-type doping can be performed with p-type impurities such as B. In-situ doping can be performed while growing theepitaxial layer 1015 .

接下来，可以进行侧墙形成工艺。Next, a sidewall forming process may be performed.

例如，如图8所示，在图7所示的结构上，通过例如淀积，以大致共形的方式形成侧墙材料层1017。例如，侧墙材料层1017可以包括具有所需刻蚀选择性的材料如氮化物(例如，氮化硅)，厚度为约5-20nm。可以对侧墙材料层1017进行选择性刻蚀如RIE。RIE可以沿着竖直方向(例如，大致垂直于衬底表面的方向)进行，以便去除侧墙材料层1017的横向延伸部分，而留下其竖直延伸部分。纳米线1005两端的外延层1015的上表面上的侧墙材料层1017可以被去除，其竖直侧壁上的侧墙材料层1017由于其高度较低从而甚至可能被完全去除，但是其下表面上的侧墙材料层1017可能留下。可以对外延层1015进行选择性刻蚀如RIE，RIE可以沿着竖直方向(例如，大致垂直于衬底表面的方向)进行。外延层1015靠近纳米线1015端面的部分由于被上方的侧墙材料层1017所遮挡从而可以保留，而外延层1015远离纳米线1015端面的部分由于外露而可以被去除，并因此露出了其下方的侧墙材料层1017。然后，进一步对侧墙材料层1017进行竖直方向的RIE。这样，就得到了如图9所示的侧墙，在此仍然标注为1017。可能仍有部分外延层1015留于衬底1001的表面。For example, as shown in FIG. 8, on the structure shown in FIG. 7, a layer ofspacer material 1017 is formed in a substantially conformal manner, eg, by deposition. For example, thespacer material layer 1017 may include a material with desired etch selectivity, such as nitride (eg, silicon nitride), with a thickness of about 5-20 nm. Thespacer material layer 1017 may be selectively etched such as RIE. RIE may be performed in a vertical direction (eg, a direction substantially perpendicular to the substrate surface) to remove laterally extending portions of the layer ofspacer material 1017, leaving vertically extending portions thereof. Thespacer material layer 1017 on the upper surface of theepitaxial layer 1015 at both ends of thenanowire 1005 can be removed, and thespacer material layer 1017 on its vertical sidewalls may even be completely removed due to its low height, but its lower surface The upper layer ofsidewall material 1017 may remain. Theepitaxial layer 1015 may be selectively etched such as RIE, which may be performed in a vertical direction (eg, a direction substantially perpendicular to the substrate surface). The part of theepitaxial layer 1015 close to the end face of thenanowire 1015 can be retained because it is blocked by the uppersidewall material layer 1017, while the part of theepitaxial layer 1015 far from the end face of thenanowire 1015 can be removed due to being exposed, and thus the underlying layer is exposed.Sidewall material layer 1017. Then, vertical RIE is further performed on thesidewall material layer 1017 . In this way, the side wall as shown in FIG. 9 is obtained, which is still marked as 1017 here. There may still be a portion of theepitaxial layer 1015 left on the surface of thesubstrate 1001 .

按照上述工艺，侧墙1017自对准于伪栅结构，环绕纳米线1005端部的外延层1015。也即，形成了自对准环绕侧墙1017。另外，侧墙1017位于纳米线外延层1015上方的部分和位于外延层1015下方的部分也可以是彼此自对准的。外延层1015可以呈现朝向外侧扩张的形状，且被侧墙1017所环绕，这有助于降低寄生电阻。According to the above process, thesidewall spacers 1017 are self-aligned to the dummy gate structures and surround theepitaxial layers 1015 at the ends of thenanowires 1005 . That is, self-aligned surroundingsidewalls 1017 are formed. In addition, the portion of thespacer 1017 above thenanowire epitaxial layer 1015 and the portion below theepitaxial layer 1015 may also be self-aligned with each other. Theepitaxial layer 1015 may have a shape that expands toward the outside and is surrounded by thespacers 1017, which helps to reduce parasitic resistance.

之后，可以在外延层1015(用作延伸区)的外侧进一步形成源/漏区。这里需要指出的是，延伸区也可以视为源/漏区的一部分。After that, source/drain regions may be further formed on the outside of the epitaxial layer 1015 (serving as extension regions). It should be pointed out here that the extension region can also be regarded as a part of the source/drain region.

例如，如图10(a)和10(b)(图10(a)是俯视图，图10(b)是截面图，截取位置为前面示出的AA′线)所示，可以通过选择性外延生长，从外延层1015的侧壁生长外延层1019。生长可以纳米线1005两端的外延层1015(在此为Si)和衬底1001(在此也为Si)或衬底上1001上留下的外延层1015的露出表面为种子。外延层1019可以包括与纳米线1005相同的半导体材料，例如Si。当然，本公开不限于此。例如，外延层1019可以包括与纳米线1005不同的半导体材料，例如晶格常数不同的半导体材料以便向纳米线1005中施加应力。For example, as shown in Figs. 10(a) and 10(b) (Fig. 10(a) is a top view, Fig. 10(b) is a cross-sectional view, and the interception position is the line AA' shown earlier), selective epitaxy can be achieved by selective epitaxy. Growth,epitaxial layer 1019 is grown from the sidewalls ofepitaxial layer 1015 . Growth can be seeded by the epitaxial layer 1015 (here Si) at both ends of thenanowire 1005 and the substrate 1001 (also Si here) or the exposed surface of theepitaxial layer 1015 left on thesubstrate 1001 .Epitaxial layer 1019 may comprise the same semiconductor material asnanowire 1005, eg, Si. Of course, the present disclosure is not limited thereto. For example,epitaxial layer 1019 may include a different semiconductor material thannanowire 1005 , eg, a semiconductor material with a different lattice constant, in order to apply stress intonanowire 1005 .

可以对外延层1019进行掺杂以形成源/漏区。例如，对于n型器件，可以利用n型杂质如P或As进行n型掺杂，而对于p型器件，可以利用p型杂质如B进行p型掺杂。可以在生长外延层1019的同时进行原位掺杂。Theepitaxial layer 1019 may be doped to form source/drain regions. For example, for n-type devices, n-type doping can be performed with n-type impurities such as P or As, while for p-type devices, p-type doping can be performed with p-type impurities such as B. In situ doping may be performed while growing theepitaxial layer 1019 .

在此，进行较多的生长，获得较大的外延层1019，以便于后继的处理。在该示例中，从纳米线1005两端的外延层1015生长的外延层1019与从衬底1001表面生长的外延层1019可以彼此融合。另外，为便于后继处理，外延层1019的顶面可以低于侧墙1017的顶面。Here, more growth is performed to obtain alarger epitaxial layer 1019 to facilitate subsequent processing. In this example, theepitaxial layer 1019 grown from theepitaxial layer 1015 at both ends of thenanowire 1005 and theepitaxial layer 1019 grown from the surface of thesubstrate 1001 may be fused with each other. In addition, to facilitate subsequent processing, the top surface of theepitaxial layer 1019 may be lower than the top surface of thesidewall spacer 1017 .

至此，已经基本完成了器件的制作。在此，还可以应用应力源/漏技术。So far, the fabrication of the device has been basically completed. Here, stress source/drain techniques can also be applied.

为更好地施加应力，可以将外延层1019构图为鳍状。例如，如图11所示，可以在图10(a)和10(b)所示的结构上形成掩模层1031例如光刻胶。可以通过光刻将光刻胶1031构图为鳍状。在该示例中，鳍状的光刻胶1031的纵向延伸方向可以与纳米线1005的纵向延伸方向(图中水平方向)基本上一致。另外，在俯视图中，光刻胶1031与纳米线1005、纳米线两端的外延层1015重叠。这样，随后通过光刻胶1031限定的源/漏区可以与纳米线1005两端的外延层1015相接。然后，如图12(a)、12(b)和12(c)(图12(a)是俯视图，图12(b)和12(c)是截面图，截取位置分别为前面示出的AA′线和B2B2′线)所示，可以光刻胶1031为刻蚀掩模，对外延层1019进行选择性刻蚀如反应离子刻蚀(RIE)。RIE可以沿竖直方向(例如，大致垂直于衬底表面的方向)进行。于是，外延层1019可以呈现与光刻胶1031基本相同的图案，在此为鳍状。另外，在对外延层1019进行刻蚀时，刻蚀可以没有进行到外延层1019的底面处，从而在衬底1001的表面上仍留有一定厚度的外延层1019，如图12(c)所示。之后，可以去除光刻胶1031。For better stress application, theepitaxial layer 1019 may be patterned into a fin shape. For example, as shown in FIG. 11, amask layer 1031 such as photoresist may be formed on the structure shown in FIGS. 10(a) and 10(b). Thephotoresist 1031 can be patterned into a fin shape by photolithography. In this example, the longitudinal extension direction of the fin-shapedphotoresist 1031 may be substantially the same as the longitudinal extension direction (horizontal direction in the figure) of thenanowires 1005 . In addition, in a top view, thephotoresist 1031 overlaps thenanowire 1005 and theepitaxial layer 1015 at both ends of the nanowire. In this way, the source/drain regions subsequently defined by thephotoresist 1031 can be in contact with theepitaxial layer 1015 at both ends of thenanowire 1005 . Then, as shown in Figures 12(a), 12(b) and 12(c) (Figure 12(a) is a top view, Figures 12(b) and 12(c) are cross-sectional views, and the interception positions are respectively AA shown earlier ' and B2B2'), thephotoresist 1031 can be used as an etching mask to perform selective etching on theepitaxial layer 1019 such as reactive ion etching (RIE). RIE can be performed in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate). Thus, theepitaxial layer 1019 may exhibit substantially the same pattern as thephotoresist 1031, here in the shape of a fin. In addition, when theepitaxial layer 1019 is etched, the etching may not proceed to the bottom surface of theepitaxial layer 1019, so that a certain thickness of theepitaxial layer 1019 is still left on the surface of thesubstrate 1001, as shown in FIG. 12(c). Show. Afterwards, thephotoresist 1031 may be removed.

在外延层1019上可以形成应力层，以向纳米线1005施加应力。例如，如图13(a)、13(b)和13(c)(图13(a)是俯视图，图13(b)和13(c)是截面图，截取位置分别为前面示出的AA′线和B2B2′线)所示，可以通过外延生长，在外延层1019上形成应力层1021。例如，应力层1021可以包括晶格常数与外延层1019不同的半导体材料。对于p型器件，应力层1021可以施加压应力。例如，在外延层1019为Si的情况下，应力层1021可以包括SiGe，Ge的原子百分比可以为约10-70％。另一方面，而对于n型器件，应力层1021可以施加拉应力。例如，在外延层1019为Si的情况下，应力层1021可以包括Si：C，C的原子百分比为约0.3-2％。A stressor layer may be formed on theepitaxial layer 1019 to apply stress to thenanowires 1005 . For example, as shown in Figures 13(a), 13(b) and 13(c) (Figure 13(a) is a top view, Figures 13(b) and 13(c) are cross-sectional views, and the interception positions are respectively AA shown earlier ' line and B2B2' line), thestress layer 1021 may be formed on theepitaxial layer 1019 by epitaxial growth. For example, thestressor layer 1021 may comprise a semiconductor material having a different lattice constant than theepitaxial layer 1019 . For p-type devices, thestressor layer 1021 may apply compressive stress. For example, in the case where theepitaxial layer 1019 is Si, thestressor layer 1021 may include SiGe, and the atomic percentage of Ge may be about 10-70%. On the other hand, for n-type devices, thestressor layer 1021 may apply tensile stress. For example, in the case where theepitaxial layer 1019 is Si, thestressor layer 1021 may include Si:C with an atomic percentage of C of about 0.3-2%.

图13(d)(沿B2B2′线的截面图)示出了生长的应力层1021的另一示例。FIG. 13(d) (a cross-sectional view along the line B2B2') shows another example of thegrown stressor layer 1021 .

可以看到，由于外延层1019形成为鳍状，从而应力层可以绕其顶面和侧壁形成，从而可以更有效地施加应力。为便于后继处理，应力层1021的顶面可以低于侧墙1017的顶面。It can be seen that since theepitaxial layer 1019 is formed in the shape of a fin, a stress layer can be formed around its top surface and side walls, so that stress can be applied more effectively. To facilitate subsequent processing, the top surface of thestress layer 1021 may be lower than the top surface of thesidewall 1017 .

接下来，可以将伪栅结构替换为栅堆叠。Next, the dummy gate structure can be replaced with a gate stack.

例如，如图14(a)和14(b)(图14(a)是俯视图，图14(b)是截面图，截取位置为前面示出的AA′线)所示，可以在图13(a)、13(b)和13(c)(或13(d))所示的结构上，例如通过淀积，形成电介质层1023。电介质层1023可以覆盖外延层1021，以在后继工艺中保护外延层1021。另外，电介质层1023可以占据侧墙1017外侧的空间，以避免栅堆叠形成在侧墙1017外侧。例如，电介质层1023可以包括氮化物(在此由于侧墙1017包括相同的材料，因此将侧墙1017与电介质层1023示出为一体)。淀积的电介质层1023可以超出侧墙1017的顶面，并可以对淀积的电介质层1023进行平坦化处理如CMP，CMP可以停止于侧墙1017，从而露出伪栅层1011。For example, as shown in Figures 14(a) and 14(b) (Figure 14(a) is a top view, Figure 14(b) is a cross-sectional view, and the interception position is the line AA' shown earlier), it can be shown in Figure 13 ( On the structures shown in a), 13(b) and 13(c) (or 13(d)), adielectric layer 1023 is formed, for example, by deposition. Adielectric layer 1023 may cover theepitaxial layer 1021 to protect theepitaxial layer 1021 in subsequent processes. In addition, thedielectric layer 1023 may occupy the space outside thespacer 1017 to prevent the gate stack from being formed outside thespacer 1017 . For example, thedielectric layer 1023 may include nitride (here, thespacer 1017 and thedielectric layer 1023 are shown as one piece since thespacer 1017 includes the same material). The depositeddielectric layer 1023 may extend beyond the top surface of thespacers 1017, and the depositeddielectric layer 1023 may be subjected to a planarization process such as CMP, which may stop at thespacers 1017, thereby exposing thedummy gate layer 1011.

之后，可以去除伪栅层1011，并在由于伪栅层1011的去除而在侧墙内侧留下的空间中形成栅堆叠。如图15(a)和15(b)(图15(a)是俯视图，图15(b)是截面图，截取位置为前面示出的AA′线)所示，可以通过选择性刻蚀如RIE，去除伪栅层1011。在此，为了栅堆叠与衬底1001之间的电隔离，可以在底部(靠近衬底1001一侧)留下一定厚度的伪栅层1011(在此为氧化物)。对于纳米线1005下方的伪栅层1011，可以通过各向同性刻蚀予以去除。类似地，可以通过选择性刻蚀如RIE，去除保护层1009。这样，露出了纳米线1005。然后，如图16(a)、16(b)和16(c)(图16(a)是俯视图，图16(b)和16(c)是截面图，截取位置分别为前面示出的AA′线和B2B2′线)所示，可以在依次淀积栅介质层1025和栅导体层1027。例如，栅介质层1025可以包括高K栅介质如HfO₂；栅导体层1027可以包括金属栅导体。优选地，栅介质层1025可以具有2-5nm的厚度。在形成栅介质层1025之前，还可以形成例如氧化物的界面层(未示出)，氧化物界面层的厚度可以是0.3nm-1nm。另外，在栅介质层1025和栅导体层1027之间还可以存在功函数调节层(未示出)。栅介质层1025可以大致共形的方式形成，栅导体层1027可以填满侧墙内侧的空间。之后，可以对栅导体层1027和栅介质层1025进行平坦化处理例如CMP，CMP可以停止于电介质层1023，从而去除栅导体层1027和栅介质层1025位于侧墙之外的部分。After that, thedummy gate layer 1011 may be removed, and a gate stack may be formed in the space left inside the spacer due to the removal of thedummy gate layer 1011 . As shown in Figures 15(a) and 15(b) (Figure 15(a) is a top view, Figure 15(b) is a cross-sectional view, and the interception position is the line AA' shown earlier), it can be selectively etched such as RIE, thedummy gate layer 1011 is removed. Here, for electrical isolation between the gate stack and thesubstrate 1001, a dummy gate layer 1011 (here, oxide) with a certain thickness may be left at the bottom (the side close to the substrate 1001). Thedummy gate layer 1011 under thenanowire 1005 can be removed by isotropic etching. Similarly, theprotective layer 1009 can be removed by selective etching such as RIE. In this way, thenanowires 1005 are exposed. Then, as shown in Figures 16(a), 16(b) and 16(c) (Figure 16(a) is a top view, Figures 16(b) and 16(c) are cross-sectional views, and the interception positions are respectively AA shown earlier ' line and B2B2' line), agate dielectric layer 1025 and agate conductor layer 1027 may be deposited in sequence. For example, thegate dielectric layer 1025 may include a high-K gate dielectric such as HfO₂ ; thegate conductor layer 1027 may include a metal gate conductor. Preferably, thegate dielectric layer 1025 may have a thickness of 2-5 nm. Before forming thegate dielectric layer 1025, an interface layer such as oxide (not shown) may also be formed, and the thickness of the oxide interface layer may be 0.3 nm-1 nm. In addition, a work function adjustment layer (not shown) may also exist between thegate dielectric layer 1025 and thegate conductor layer 1027 . Thegate dielectric layer 1025 may be formed in a substantially conformal manner, and thegate conductor layer 1027 may fill the space inside the spacer. Afterwards, thegate conductor layer 1027 and thegate dielectric layer 1025 may be planarized, such as CMP, and the CMP may stop at thedielectric layer 1023 to remove the portions of thegate conductor layer 1027 and thegate dielectric layer 1025 outside the spacers.

如图16(a)、16(b)和16(c)所示，根据本实施例的半导体器件可以包括半导体纳米结构1005(在该示例中，为纳米线)以及环绕半导体纳米结构1005的外周形成的栅堆叠。如上所述，由于伪栅层以自对准方式形成，因此占据伪栅层位置的栅堆叠也是自对准的，从而形成了SWAG。As shown in FIGS. 16( a ), 16 ( b ) and 16 ( c ), a semiconductor device according to the present embodiment may include a semiconductor nanostructure 1005 (in this example, a nanowire) and a periphery surrounding thesemiconductor nanostructure 1005 formed gate stack. As described above, since the dummy gate layer is formed in a self-aligned manner, the gate stack occupying the position of the dummy gate layer is also self-aligned, thereby forming a SWAG.

尽管在以上实施例中描述了单根纳米线的器件，但是本公开不限于此。例如，通过在衬底上交替堆叠牺牲层1003和半导体纳米结构层1005。在去除牺牲层1003之后，可以形成中部彼此分离的多个半导体纳米结构层1005并由此可以得到彼此间隔开的多个半导体纳米结构如纳米线或纳米片。可以按照同样的方式来形成伪栅层，伪栅层可以环绕这多个半导体纳米结构。随后，可以同样地将伪栅层替换为栅堆叠。Although a single nanowire device is described in the above embodiments, the present disclosure is not limited thereto. For example, by alternately stackingsacrificial layers 1003 andsemiconductor nanostructure layers 1005 on the substrate. After thesacrificial layer 1003 is removed, a plurality ofsemiconductor nanostructure layers 1005 separated from each other in the middle may be formed and thus a plurality of semiconductor nanostructures such as nanowires or nanosheets spaced apart from each other may be obtained. The dummy gate layer can be formed in the same manner, and the dummy gate layer can surround the plurality of semiconductor nanostructures. Subsequently, the dummy gate layer can likewise be replaced with a gate stack.

根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能、可穿戴设备、移动电源等。The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices, as well as other devices (eg, other forms of transistors, etc.), integrated circuits (ICs) may be formed and electronic devices constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above-described semiconductor device. The electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit. Such electronic devices are, for example, smartphones, computers, tablet computers (PCs), artificial intelligence, wearable devices, power banks, and the like.

在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (20)

1. A semiconductor device, comprising:

a substrate;

a semiconductor nanostructure spaced apart from the substrate and extending laterally over the surface of the substrate;

a gate stack formed around a periphery of the semiconductor nanostructure, wherein a portion of the gate stack below the semiconductor nanostructure includes a first sidewall and a second sidewall opposite each other, and a portion of the gate stack above the semiconductor nanostructure includes a third sidewall and a fourth sidewall opposite each other, wherein at least a portion of the first sidewall is substantially coplanar with at least a portion of the third sidewall, and/or at least a portion of the second sidewall is substantially coplanar with at least a portion of the fourth sidewall;

the semiconductor source region and the semiconductor drain region are respectively positioned at two opposite sides of the semiconductor nano structure, wherein the end part of each semiconductor source region and the end part of each semiconductor drain region close to one side of the nano structure are in a tapered shape along with the approach of the semiconductor nano structure; and

and the grid side wall is formed on the side wall of the grid stack and is a dielectric medium, wherein the grid side wall is separated from the semiconductor source region and the semiconductor drain region through the grid side wall, and the parts of the grid side wall, which are respectively connected with the end parts of the semiconductor source region and the semiconductor drain region, are in an inclined shape, so that the end parts are in a tapered shape.

2. The semiconductor device of claim 1, wherein the first sidewall and the third sidewall of the gate stack constitute a continuously extending first plane surrounding the semiconductor nanostructure and/or the second sidewall and the fourth sidewall of the gate stack constitute a continuously extending second plane surrounding the semiconductor nanostructure.

3. The semiconductor device of claim 2, wherein the first plane and the second plane are substantially parallel to each other.

4. The semiconductor device of claim 2, wherein the first plane and the second plane are both substantially perpendicular to the substrate surface.

5. The semiconductor device of claim 1, wherein the semiconductor source region and the semiconductor drain region are each formed as a fin shape interfacing with the semiconductor nanostructure.

6. The semiconductor device of claim 5, wherein the fin extends along substantially the same longitudinal direction as the semiconductor nanostructure.

7. The semiconductor device of claim 5, wherein the semiconductor source region and the semiconductor drain region are contiguous with the substrate.

8. The semiconductor device of claim 5, wherein the semiconductor source region, the semiconductor drain region, and the semiconductor nanostructure are formed of the same semiconductor material.

9. The semiconductor device of claim 5, further comprising:

and a stress layer formed on the surface of the semiconductor source region and the semiconductor drain region.

10. The semiconductor device of claim 1, further comprising:

an isolation layer between the gate stack and the substrate, wherein the isolation layer is self-aligned to the gate stack.

11. The semiconductor device of claim 1, wherein the semiconductor nanostructure comprises one or more nanowires or one or more nanoplatelets.

12. A method of manufacturing a semiconductor device, comprising:

forming a preliminary semiconductor nanostructure on a substrate suspended relative to the substrate;

forming a preliminary dummy gate layer on a substrate, the preliminary dummy gate layer surrounding an outer periphery of a suspended preliminary semiconductor nanostructure;

patterning the prepared pseudo gate layer and the prepared semiconductor nano structure to form a self-aligned pseudo gate layer and a self-aligned semiconductor nano structure, wherein the pseudo gate layer still surrounds the periphery of the semiconductor nano structure;

carrying out epitaxial growth on the end part of the semiconductor nano structure to form an epitaxial layer which extends out relatively;

forming a gate side wall surrounding the semiconductor nano structure on the side wall of the pseudo gate layer around the epitaxial layer which relatively extends out, wherein the part of the gate side wall connected with the epitaxial layer is in an inclined shape;

removing the part of the epitaxial layer extending out relative to the gate side wall, so that the rest epitaxial layer is surrounded by the gate side wall and is in a shape gradually reduced along with approaching the semiconductor nano structure;

forming a fin-shaped semiconductor source region and a fin-shaped semiconductor drain region on the substrate, wherein the semiconductor source region and the semiconductor drain region are connected with the epitaxial layer and are separated from the pseudo gate layer through the gate side wall;

at least partially removing the pseudo gate layer to leave a space around the periphery of the semiconductor nano structure on the inner side of the gate side wall; and

a gate stack is formed in the space.

13. The method of claim 12, wherein patterning the preliminary dummy gate layer and the preliminary semiconductor nanostructure comprises:

the preliminary dummy gate layer and the preliminary semiconductor nanostructure are patterned using the same mask.

14. The method of claim 13, wherein patterning the preliminary dummy gate layer and the preliminary semiconductor nanostructure comprises:

the anisotropic etching is performed in a direction substantially perpendicular to the substrate surface.

15. The method of claim 12, wherein at least partially removing the dummy gate layer comprises:

removing the upper portion of the dummy gate layer, leaving the lower portion of the dummy gate layer below the semiconductor nanostructure, wherein the top surface of the portion of the dummy gate layer left is lower than the bottom surface of the semiconductor nanostructure.

16. The method of claim 12, further comprising:

and forming stress layers on the surfaces of the semiconductor source region and the semiconductor drain region.

17. The method of claim 12, wherein the semiconductor nanostructure comprises a nanowire or nanoplatelet.

18. An electronic device comprising an integrated circuit formed at least in part by the semiconductor device as claimed in any one of claims 1 to 11.

19. The electronic device of claim 18, further comprising: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.

20. The electronic device of claim 18, comprising a smartphone, a computer, a tablet, an artificial intelligence, a wearable device, or a mobile power source.

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