CN109344094B

Movatterモバイル変換

Info

Publication number: CN109344094B
Application number: CN201811125446.1A
Authority: CN
Inventors: 周玉龙; 刘同强; 邹晓峰; 刘刚
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2018-09-26
Filing date: 2018-09-26
Publication date: 2021-10-29
Anticipated expiration: 2038-09-26
Also published as: CN109344094A

Abstract

Translated fromChinese

本发明公开了一种地址映射关系反馈方法，该方法包括：NANDFlash存储设备接收目标进程发送的目标数据的地址查询请求；读取预设映射表，获得存储地址查询请求对应的地址映射表的目标映射关系；从原始物理地址中读取地址映射表，并判断是否成功读取到目标数据对应的目标地址映射关系；如果读取失败，则从备份物理地址中读取地址映射表，获得目标地址映射关系；将目标地址映射关系反馈至目标进程；其中，目标地址映射关系为目标数据的逻辑地址与物理地址的对应关系。如此，便可提升NAND Flash存储设备的可靠性。本发明还公开了一种地址映射关系反馈装置、设备及可读存储介质，具有相应的技术效果。

The invention discloses an address mapping relationship feedback method. The method includes: a NAND Flash storage device receives an address query request of target data sent by a target process; reads a preset mapping table to obtain a target of the address mapping table corresponding to the storage address query request Mapping relationship; read the address mapping table from the original physical address, and determine whether the target address mapping relationship corresponding to the target data is successfully read; if the read fails, read the address mapping table from the backup physical address to obtain the target address The mapping relationship; the target address mapping relationship is fed back to the target process; wherein, the target address mapping relationship is the corresponding relationship between the logical address and the physical address of the target data. In this way, the reliability of the NAND Flash storage device can be improved. The invention also discloses an address mapping relationship feedback device, equipment and readable storage medium, which have corresponding technical effects.

Description

Address mapping relation feedback method, device and equipment and readable storage medium

Technical Field

The present invention relates to the field of storage technologies, and in particular, to an address mapping relationship feedback method, apparatus, device, and readable storage medium.

Background

The NAND Flash memory in the Solid State Disks (Solid State Disks) has many advantages over the traditional disk, such as low access delay, low energy consumption, low noise, high I/O performance, short addressing time, good stability to temperature and vibration, etc. Due to the above advantages of the solid state disk, and as the Flash storage technology is continuously advanced, the price per byte is continuously reduced, the solid state disk based on the Flash storage is more concerned. However, the Flash memory still has inherent defects to prevent the Flash memory from being widely applied, and the inherent defects of the Flash memory mainly include that the price is still high, the read-write speed is unbalanced, the characteristics of erasing before writing are realized, and the service life is limited by the erasing times.

In order to reduce the influence of the inherent defects on the performance of the Flash memory, the Flash memory needs to be supported by an effective management mode. At present, most Flash memories are managed by FTLs. That is, NAND Flash based storage devices are typically composed of three parts: interface controller, Flash Translation Layer (FTL), NAND flash array. When the Flash memory conversion layer manages the Flash memory, the most basic and key is the address mapping strategy. The address mapping refers to the mapping relation between virtual logical addresses sent from a file system to real physical addresses in a Flash memory.

Address mapping can have a critical impact on FTL and even the entire Flash reliability. In particular, the NAND flash memory has a life limited by the number of times of erasing and is very vulnerable to damage. Once an error occurs in the area of the storage address mapping relationship, the data of the storage device may be lost, and the storage device may not be replied, which may result in low reliability of the storage data of the storage device.

In summary, how to effectively solve the problems of ensuring the reliability of data and the like is a technical problem that needs to be solved urgently by those skilled in the art at present.

Disclosure of Invention

The invention aims to provide an address mapping relation feedback method, device, equipment and readable storage medium, which improve the reliability of data storage of NAND Flash storage equipment by backing up an address mapping table in the NAND Flash storage equipment.

In order to solve the technical problems, the invention provides the following technical scheme:

an address mapping relation feedback method comprises the following steps:

the method comprises the steps that an NAND Flash storage device receives an address query request of target data sent by a target process;

reading a preset mapping table, and obtaining a target mapping relation for storing an address mapping table corresponding to the address query request;

reading the address mapping table from the original physical address, and judging whether a target address mapping relation corresponding to the target data is successfully read or not;

if the reading fails, reading the address mapping table from the backup physical address to obtain the target address mapping relation;

feeding back the target address mapping relation to the target process; the target address mapping relation is a corresponding relation between a logical address and a physical address of the target data.

Preferably, before the receiving an address query request of target data sent by a target process, the method further includes:

the NAND Flash storage device receives a write-in request of an address mapping table; the NAND Flash storage device comprises a first area, a second area and a third area;

determining an original storage address corresponding to the address mapping table in the second area, and determining a backup storage address corresponding to the address mapping table in the third area;

performing data recombination on the address mapping table, the original storage address and the backup storage address to obtain a target address mapping table and a target mapping relation between the original storage address and the backup storage address;

and respectively writing the target address mapping table into the original storage address and the backup storage address, and writing the target mapping relation into the first area.

Preferably, the determining, in the second area, an original storage address corresponding to the address mapping table and determining, in the third area, a backup storage address corresponding to the address mapping table includes:

and determining an original storage address corresponding to the address mapping table in the second area and determining a backup storage address corresponding to the address mapping table in the third area by adopting a wear leveling mechanism.

Preferably, writing the target mapping relationship into the area one includes:

writing the target mapping relation into a preset mapping table in the first area; the storage format of the preset mapping table is ECC + VLD + backup address n + original address n + backup address n-1+ … + backup address 1+ original address 1+ backup address 0+ original address 0; and the VLD is 1, which indicates that the preset mapping table is valid.

Preferably, after reading the address mapping table from the backup physical address and obtaining the target address mapping relationship, the method further includes:

re-determining a target physical address in the second area, and writing the address mapping table into a new target physical address;

and replacing the target mapping relation with the mapping relation between the target physical address and the backup physical address.

Preferably, the method further comprises the following steps:

receiving a write-back operation request of the target mapping relation;

and determining a write-back physical address in the first area, and writing the target mapping relation into the write-back physical address so as to facilitate the NAND-Flash memory array to perform write operation.

Preferably, the method further comprises the following steps:

and receiving an updating request of the address mapping table, and replacing the address mapping table in the original storage address and the backup storage address.

An address mapping relationship feedback device, comprising:

the address query request acquisition module is used for receiving an address query request of target data sent by a target process by the NAND Flash storage device;

a target mapping relation obtaining module, configured to read a preset mapping table and obtain a target mapping relation in which an address mapping table corresponding to the address query request is stored;

a first target address mapping relation reading module, configured to read the address mapping table from the original physical address, and determine whether a target address mapping relation corresponding to the target data is successfully read;

a second target address mapping relation reading module, configured to, if the first target address mapping relation reading module fails to read, read the address mapping table from the backup physical address, to obtain the target address mapping relation;

the target address mapping relation feedback module is used for feeding back the target address mapping relation to the target process; the target address mapping relation is a corresponding relation between a logical address and a physical address of the target data.

An address mapping relationship feedback device, comprising:

a memory for storing a computer program;

and the processor is used for realizing the steps of the address mapping relation feedback method when the computer program is executed.

A readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the above address mapping relation feedback method.

By applying the method provided by the embodiment of the invention, the NAND Flash storage device receives an address query request of target data sent by a target process; reading a preset mapping table, and obtaining a target mapping relation of an address mapping table corresponding to the storage address query request; reading an address mapping table from an original physical address, and judging whether a target address mapping relation corresponding to target data is successfully read or not; if the reading fails, reading an address mapping table from the backup physical address to obtain a target address mapping relation; feeding back the target address mapping relation to a target process; the target address mapping relation is the corresponding relation between the logical address and the physical address of the target data.

After receiving an address query request of target data sent by a target process, the NAND Flash storage device firstly reads a preset mapping table to obtain a target mapping relation of an address mapping table corresponding to the address query request. The target mapping relation is the corresponding relation between the original storage address and the backup storage address of the address mapping table. After the target mapping relation is obtained, firstly, an address mapping table is read from an original storage address, and whether the target address mapping relation corresponding to the target data is successfully read or not is judged. The service life of the NAND flash memory is limited by the erasing times and is easily damaged, so that an address mapping table stored in the NAND memory is easily damaged, and the address mapping relation cannot be read normally. And if the target address mapping relation cannot be successfully read, reading the address mapping table from the backup storage address to obtain the target address mapping relation. After the preset relation of the target address is obtained, the mapping relation of the target address can be fed back to the target process, so that the target process can operate the target data based on the corresponding relation. The target mapping relation is the corresponding relation between the logical address and the physical address of the target data. By backing up the address mapping table, even if the address mapping table stored in the original storage address is damaged, and the target address mapping relation cannot be successfully read, the target address mapping relation of the target data can be read by reading the address mapping table stored in the backup storage address, and returned to the target process. Therefore, the target process can be ensured to obtain the address mapping relation for operating the target data stored in the storage device, namely the data stored in the storage device can still be operated, the data cannot be lost, and the reliability of the NAND Flash storage device can be improved.

Accordingly, embodiments of the present invention further provide an address mapping relation feedback apparatus, a device and a readable storage medium corresponding to the address mapping relation feedback method, which have the above technical effects and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart illustrating an implementation of an address mapping relationship feedback method according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating an address mapping table writing process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating area division of a NAND Flash storage device according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a storage format of a preset mapping table according to an embodiment of the present invention;

FIG. 5 is a block diagram of a write backup mechanism implemented in an embodiment of the present invention;

FIG. 6 is a block diagram of an implementation of a read backup mechanism according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of an address mapping relation feedback apparatus according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of an address mapping relation feedback device in an embodiment of the present invention;

fig. 9 is a schematic structural diagram of an address mapping relation feedback device in an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The first embodiment is as follows:

referring to fig. 1, fig. 1 is a flowchart illustrating an address mapping relationship feedback method according to an embodiment of the present invention, where the method includes the following steps:

s101, the NAND Flash storage device receives an address query request of target data sent by a target process.

The NAND Flash storage device is a storage device comprising an interface controller, a memory translation layer (FTL) and a NAND Flash memory array. During the use process of the NAND Flash storage device, the data reading and writing operations are generally realized by using two addresses, namely a logical address and a physical address. In a computer with address translation, the address (operand) given by an internal instruction is called a logical address and also called a relative address. The actual effective address in the internal memory, i.e. the physical address, is obtained through the calculation or conversion of the addressing mode. When an upper layer application or process needs to operate target data stored in a storage device, the physical address of the target data storage needs to be determined, and then the target data can be really operated.

The target process may specifically perform a process of reading/writing target data, and the address query request sent by the target process may specifically be a physical address corresponding to target data for querying a known logical address. For example, the query request queries a physical address storing target data with logical address a for a request.

S102, reading a preset mapping table, and obtaining a target mapping relation of an address mapping table corresponding to the storage address query request.

After receiving an address query request for reading target data, the preset mapping table can be read to obtain a target mapping relation of the address preset table corresponding to the address query request. The target mapping relation is a corresponding relation between an original storage address and a backup storage address of a storage address preset table, and the preset mapping table stores corresponding relations of a plurality of different address mapping tables. Reading the target mapping relation of the address mapping table corresponding to the address query request, namely obtaining the original storage address and the backup storage address of the address mapping table corresponding to the address query request. In the preset mapping table, the target influence relationship can be determined by judging the type corresponding to the target data inquired by the address inquiry request. For example, according to the cold and hot data, the address mapping relation of the cold data is stored in a cold data address mapping table, and the address mapping relation of the hot data is stored in a hot soymilk address mapping table.

S103, reading the address mapping table from the original physical address, and judging whether the target address mapping relation corresponding to the target data is successfully read.

Specifically, the address mapping table is read from the original physical address, and the logical address in the address mapping table can be determined, that is, whether the currently read logical address is the logical address of the target data is determined, and if yes, the physical address corresponding to the logical address is read, so that the target address mapping relationship of the target data can be obtained. Because NAND Flash is very easy to be damaged, the situation that the address mapping table stored in the original physical address is unreadable or the read logical address is incorrect may occur, and therefore, it is also necessary to determine whether the target address mapping relationship corresponding to the target data is successfully read. The manner of judging whether the reading is successful or not may be to verify the mapping relationship of the read target address, if the verification is successful, the reading is determined to be successful, and if the verification is failed, the reading is determined to be failed. Of course, if the logical address and/or the logical address corresponding to the target data is not found in the address mapping table, the reading is also regarded as a failure.

If the reading is successful, the operation of step S105 may be performed; if the reading fails, the operation of step S104 is performed.

And S104, reading the address mapping table from the backup physical address to obtain a target address mapping relation.

When the target address mapping relation is not read from the original physical address, the target address mapping relation can be read from the backup storage address. It should be noted that, for the same address mapping table, multiple backup physical addresses may exist, that is, the embodiment of the present invention does not limit the backup number of the address mapping table.

And S105, feeding back the target address mapping relation to the target process.

The target address mapping relation is the corresponding relation between the logical address and the physical address of the target data.

After the target address mapping relationship is obtained, the target address mapping relationship can be sent to the target process, so that the target process can obtain the corresponding relationship between the logical address and the physical address of the target data, and the target data is further read or modified based on the physical address.

Preferably, in order to improve the feedback efficiency of the address mapping relationship, after the target address mapping relationship of the target data is read from the backup storage address, the target address mapping relationship may be rewritten into the second area. When writing into the second area, in order to improve the availability of the newly written target address mapping relationship, a target physical address can be determined again in the second area, and the address mapping table is written into the new target physical address; and replacing the target mapping relation with the mapping relation of the target physical address and the backup physical address. Therefore, when the address query request of the target data is received next time, the target storage mapping relation can be obtained in the second area.

Example two:

in order to better understand the technical solution provided by the embodiment of the present invention, the technical solution provided by the embodiment of the present invention is described in detail below by taking the NAND Flash storage device write address mapping table as an example. Similar/identical steps to those of embodiment one may be taken with reference to embodiment one.

Before step S101 is executed, an address mapping table may also be written in the NAND Flash storage device. Referring to fig. 2, fig. 2 is a schematic diagram of an address mapping table writing process according to an embodiment of the present invention, which includes the following specific steps:

s201, the NAND Flash storage device receives a write-in request of the address mapping table.

The NAND Flash storage device comprises a first area, a second area and a third area.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating an area division of a NAND Flash storage device according to an embodiment of the present invention. Dividing the NAND Flash storage device into four areas, wherein the first area stores the corresponding relation between an original storage address and a backup storage address; the original storage address in the second area and the backup storage address in the third area both store an address mapping table; region four stores data. In order to prevent bad blocks from occurring in the memory block, the area one, the area two and the area three can be configured to be larger than the actual requirement.

S202, determining an original storage address corresponding to the address mapping table in the second area, and determining a backup storage address corresponding to the address mapping table in the third area.

After receiving the write request of the address mapping table, a physical address can be determined in the second area, the physical address is the original storage address of the storage address mapping table, meanwhile, one or more physical addresses are determined in the third area, and the physical address in the third area is the backup storage address of the backup address mapping table.

Preferably, in order to improve the service life of the storage device and reduce the occurrence of bad blocks, a wear leveling mechanism may be adopted to determine the original storage address corresponding to the address mapping table in the second area and determine the backup storage address corresponding to the address mapping table in the third area. That is, the physical address may be determined according to a common wear leveling mechanism, such as a cold-hot principle, a least-use principle, and the like, so as to improve the service life of the storage device and avoid a bad block caused by using a certain block at a high frequency.

S203, carrying out data recombination on the address mapping table, the original storage address and the backup storage address to obtain a target address mapping table and a target mapping relation between the original storage address and the backup storage address.

After the original storage address and the backup storage address are determined, data reorganization can be performed on the address mapping table, the original storage address and the backup storage address, namely, data conversion is performed on the address mapping table to obtain a target address mapping table, and a target mapping relation is established between the original storage address and the backup storage address.

S204, writing the target address mapping table into the original storage address and the backup storage address respectively, and writing the target mapping relation into the first area.

After the data conversion is completed, the target address mapping table is respectively written into the original storage address and the backup storage address, and the target mapping relation is written into the first area.

Specifically, when the first region writes the target mapping relationship, the target mapping relationship may be written into a preset mapping table in the first region. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a storage format of a preset mapping table according to an embodiment of the present invention. The storage format of the preset mapping table is ECC + VLD + backup address n + original address n + backup address n-1+ … + backup address 1+ original address 1+ backup address 0+ original address 0; if VLD is 1, the preset mapping table is valid.

Preferably, since the change frequency of the address mapping relationship is high, in order to ensure that the address mapping table is available in term, the embodiment of the present invention further provides two address mapping table updating methods.

Updating the address mapping table by using a write-back mode, specifically comprising:

step one, receiving a write-back operation request of a target mapping relation;

and step two, determining a write-back physical address in the area one, and writing the target mapping relation into the write-back physical address so as to facilitate the NAND-Flash memory array to perform write operation.

For convenience of description, the above two steps will be described in combination.

After receiving the write-back operation request, a write-back physical address can be expected in a region, and then the target mapping relation is written into the write-back physical address, so that the NAND-Flash memory array can perform the write operation.

And updating the address mapping table by using a replacement mode, specifically, receiving an update request of the address mapping table, and replacing the address mapping table in the original storage address and the backup storage address.

The two updating modes can be selected according to actual needs, for example, when the updating content is less, the writing-back mode can be adopted for updating, and when the updating content is more, the overall replacement mode can be adopted for updating.

Example three:

in order to better implement the technical solutions provided by the embodiments of the present invention, those skilled in the art will now describe the technical solutions provided by the embodiments of the present invention in detail with reference to the functional modules shown in fig. 5 and fig. 6.

When writing the address mapping table, in order to ensure the reliability of the address mapping table, the block diagram may be implemented with reference to a write backup mechanism shown in fig. 5, where the specific implementation process includes:

the first step is as follows: if the write address mapping table processing module needs to write the address mapping table, applying an original storage address to the original processing module for storing the original address mapping table; and applying for a backup storage address to the backup processing module for storing the backup address mapping table.

The second step is that: after the original processing module and the backup processing module receive the request, according to the wear leveling mechanism, the original processing module applies for a physical address from the second area, and the backup processing module applies for a physical address from the third area, and provides the original storage address and the backup storage address for the write address mapping table processing module respectively.

The third step: and after the write address mapping table processing module takes the original storage address and the backup storage address, the data, the original storage address and the backup storage address are sent to the data reassembly module together.

The fourth step: and after receiving the data, the data reassembly module sends the assembled data to the write address mapping table module.

The fifth step: and after the writing address mapping table module receives the writing request of the data reassembly module, the original mapping table is written into the second area and the backup mapping table is written into the third area after the original storage address, the backup storage address and the address mapping table data of the address mapping table are obtained.

And a sixth step: and if the writing address mapping module receives the writing request, writing the original address mapping table into the second area and writing the backup address mapping table into the third area. If the original address mapping table and the backup address mapping table are successfully written, the processing module of the write address mapping table is informed, and the next processing operation can be carried out. Meanwhile, the correct original storage address and the correct backup storage address are written into the backup processing module, and the mapping relation between the original storage address and the backup storage address is maintained. If the original address writing fails, reapplying the original storage address to the original processing module until the writing is correct; if the writing of the backup address fails, the backup address is reapplied to the backup processing module until the writing is correct, and if the writing of the backup address and the writing of the backup address are both correct, the processing module is informed of the write address mapping table, and the next processing operation can be carried out. And meanwhile, informing the backup processing module of the correct original storage address and the correct backup storage address which are written finally, and maintaining the mapping relation between the original storage address and the backup storage address.

In reading the address mapping table, in order to ensure the reading reliability of the address mapping table, a read backup implementation block diagram may be given with reference to fig. 6, and the specific implementation includes:

the first step is as follows: after the system is powered on, the backup processing module requests the mapping table of the mapping relationship between the original storage address of the first reading area and the backup address from the address reading mapping table module, and then the mapping table is stored in the backup processing module.

The second step is that: after receiving the read request, the read address mapping module initiates the read request to the NAND Flash memory array, and if the read request is successful, the read address mapping module sends an address mapping table to the read address mapping table processing module; if the reading fails, a physical address is applied to the original processing module again, and a backup storage address is applied to the backup processing module at the same time.

The third step: and after receiving the failure request, the original processing module re-applies for a physical address from the second region according to a wear leveling mechanism and sends the physical address to the address reading mapping table module. After receiving the failure request, the backup processing module provides the backup storage address to the address reading mapping table module.

The fourth step: and the address mapping table reading module reads the backup address mapping table according to the provided backup address.

The fifth step: and after the read address mapping table module takes the replaced original storage address and the backup address, the read address mapping table module requests a mapping table read failure write update request from the write request address mapping table module.

And a sixth step: and after receiving the write updating request of the read failure, the write address mapping table processing module writes the original storage address mapping table into a new replaced original storage address again. And informing the read address mapping table module after the writing is successful. If the writing fails, processing is carried out according to the writing failure operation of the writing address mapping table until the writing succeeds, and the original address which is successfully written is informed to the backup processing module.

The seventh step: and after the address reading mapping table module acquires the replaced address mapping table and writes the successful mark, the address reading mapping table module sends the read address mapping table to the address reading mapping table module according to the backup storage address.

Eighth step: and after the address mapping table is taken by the address mapping table reading module, the address mapping table reading module sends the address mapping table to the requester, and then the next reading operation is processed.

During the mapping table backup operation, referring to fig. 5, the specific implementation process includes:

the first step is as follows: after receiving the write-back operation, the backup processing module writes the mapping relation between the original storage address and the backup storage address stored in the backup processing module into the NAND Flash storage array in sequence, applies for a physical address from the first area according to a wear leveling mechanism, and sends the physical address and the mapping relation to the write address mapping table module.

The second step is that: and after receiving the mapping relation between the written-back physical address and the mapping relation, the writing address mapping table module initiates writing operation to the NAND Flash storage array. If the writing is successful, informing the backup processing module to carry out the next writing operation; and if the writing fails, informing the backup processing module.

The third step: if the backup processing module receives the writing success mark, the next writing operation is carried out until all the mapping relations are written into the NAND Flash storage array; if the write failure mark is received, a physical address is reapplied according to a wear leveling mechanism and sent to the write address mapping table module until the write is successful.

The fourth step: after receiving the new physical address sent by the backup processing module, the write address mapping table module rewrites the mapping relation which has just been written in failure into the new physical address, and if the writing is successful, the write address mapping table module tells the backup processing module to perform the next write operation; if the writing fails, the backup processing module is informed, and the backup processing module processes the writing failure operation request.

Example four:

corresponding to the above method embodiment, the embodiment of the present invention further provides an address mapping relation feedback device, and the address mapping relation feedback device described below and the address mapping relation feedback method described above may be referred to in a corresponding manner.

Referring to fig. 7, the apparatus includes the following modules:

an address queryrequest obtaining module 101, configured to receive an address query request of target data sent by a target process by a NAND Flash storage device;

a target mappingrelationship obtaining module 102, configured to read a preset mapping table and obtain a target mapping relationship of an address mapping table corresponding to the storage address query request;

a first target address mappingrelation reading module 103, configured to read an address mapping table from an original physical address, and determine whether a target address mapping relation corresponding to target data is successfully read;

a second target address mappingrelation reading module 104, configured to, if the first target address mapping relation reading module fails to read, read an address mapping table from the backup physical address, and obtain a target address mapping relation;

a target address mappingrelation feedback module 105, configured to feed back a target address mapping relation to a target process; the target address mapping relation is the corresponding relation between the logical address and the physical address of the target data.

By applying the device provided by the embodiment of the invention, the NAND Flash storage equipment receives an address query request of target data sent by a target process; reading a preset mapping table, and obtaining a target mapping relation of an address mapping table corresponding to the storage address query request; reading an address mapping table from an original physical address, and judging whether a target address mapping relation corresponding to target data is successfully read or not; if the reading fails, reading an address mapping table from the backup physical address to obtain a target address mapping relation; feeding back the target address mapping relation to a target process; the target address mapping relation is the corresponding relation between the logical address and the physical address of the target data.

In one embodiment of the present invention, the method further comprises: the address mapping table writing module is used for writing an address mapping table before receiving an address query request of target data sent by a target process;

the address mapping relation writing module comprises:

a write request receiving unit, configured to receive a write request of an address mapping table by the NAND Flash storage device; the NAND Flash storage device comprises a first area, a second area and a third area;

the storage address determining unit is used for determining an original storage address corresponding to the address mapping table in the second area and determining a backup storage address corresponding to the address mapping table in the third area;

the data recombination unit is used for carrying out data recombination on the address mapping table, the original storage address and the backup storage address to obtain a target address mapping table and a target mapping relation between the original storage address and the backup storage address;

and the data writing unit is used for respectively writing the target address mapping table into the original storage address and the backup storage address and writing the target mapping relation into the first area.

In a specific embodiment of the present invention, the storage address determining unit is specifically configured to determine, by using a wear leveling mechanism, an original storage address corresponding to the address mapping table in the second area, and determine a backup storage address corresponding to the address mapping table in the third area.

In a specific embodiment of the present invention, the data writing unit is specifically configured to write the target mapping relationship into a preset mapping table in the first area; the storage format of the preset mapping table is ECC + VLD + backup address n + original address n + backup address n-1+ … + backup address 1+ original address 1+ backup address 0+ original address 0; VLD ═ 1, indicating that the preset mapping table is valid.

In one embodiment of the present invention, the method further comprises:

a correction and replacement module, configured to read the address mapping table from the backup physical address, obtain a target address mapping relationship, determine a target physical address again in the second area, and write the address mapping table into a new target physical address; and replacing the target mapping relation with the mapping relation of the target physical address and the backup physical address.

In one embodiment of the present invention, the method further comprises:

the write-back updating module is used for receiving a write-back operation request of the target mapping relation; and determining a write-back physical address in the first area, and writing the target mapping relation into the write-back physical address so as to facilitate the write operation of the NAND-Flash memory array.

In one embodiment of the present invention, the method further comprises:

and the replacement updating module is used for receiving an updating request of the address mapping table and replacing the address mapping table in the original storage address and the backup storage address.

Example five:

corresponding to the above method embodiment, an embodiment of the present invention further provides an address mapping relation feedback device, and a device for feeding back an address mapping relation described below and an address mapping relation feedback method described above may be referred to in a corresponding manner.

Referring to fig. 8, the address mapping relation feedback apparatus includes:

a memory D1 for storing computer programs;

and a processor D2, configured to implement the steps of the address mapping relation feedback method of the foregoing method embodiment when executing the computer program.

Specifically, referring to fig. 9, a specific structural diagram of an address mapping relation feedback device provided in this embodiment is shown, where the address mapping relation feedback device may generate a relatively large difference due to different configurations or performances, and may include one or more processors (CPUs) 322 (e.g., one or more processors) and amemory 332, and one or more storage media 330 (e.g., one or more mass storage devices) storing anapplication 342 ordata 344.Memory 332 andstorage media 330 may be, among other things, transient storage or persistent storage. The program stored on thestorage medium 330 may include one or more modules (not shown), each of which may include a series of instructions operating on a data processing device. Still further, thecentral processor 322 may be configured to communicate with thestorage medium 330, and execute a series of instruction operations in thestorage medium 330 on the address mappingrelation feedback device 301.

The address mappingrelation feedback apparatus 301 may also include one ormore power sources 326, one or more wired or wireless network interfaces 350, one or more input-output interfaces 358, and/or one ormore operating systems 341. Such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

The steps in the address mapping relation feedback method described above may be implemented by the structure of an address mapping relation feedback device.

Example six:

corresponding to the above method embodiment, an embodiment of the present invention further provides a readable storage medium, and a readable storage medium described below and an address mapping relation feedback method described above may be referred to in correspondence.

A readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the address mapping relation feedback method of the above-mentioned method embodiment.

The readable storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and various other readable storage media capable of storing program codes.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.